62WV5128ALL

62WV5128ALL ISSI | Alldatasheet

Document overview

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Technical content

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. A 04/30/03 IS62WV5128ALL IS62WV5128BLL ISSI Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. 512K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access time: 55ns, 70ns  CMOS low power operation 36 mW (typical) operating 9 µW (typical) CMOS standby  TTL compatible interface levels  Single power supply 1.65V – 2.2V V DD (IS62WV5128ALL) 2.5V – 3.6V VDD (IS62WV5128BLL)  Fully static operation: no clock or refresh required  Three state outputs  Industrial temperature available

DESCRIPTION

The ISSI IS62WV5128ALL / IS62WV5128BLL are high- speed, 4M bit static RAMs organized as 512K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high- performance and low power consumption devices. When CS1 is HIGH (deselected) the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62WV5128ALL and IS62WV5128BLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I), 32-pin sTSOP (TYPE I), and 32-pin TSOP (Type II). FUNCTIONAL BLOCK DIAGRAM APRIL 2003 A0-A18 CS1 OE WE 512K x 8 MEMORY ARRAYDECODER COLUMN I/O CONTROL CIRCUIT GND VDD I/O DATA CIRCUIT I/O0-I/O7

2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI 32-pin TSOP (TYPE I), (Package Code T) 32-pin sTSOP (TYPE I) (Package Code H) 32-pin TSOP (TYPE II) (Package Code T2) PIN DESCRIPTIONS A0-A18 Address Inputs CS1 Chip Enable 1 Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output NC No Connection VDD Power GND Ground PIN CONFIGURATION A11 A13 WE A18 A15 V DD A17 A16 A14 A12 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A17 A16 A14 A12 I/O0 I/O1 I/O2 GND A15 A18 WE A13 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 VDD

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions V DD Min. Max. Unit VOH Output HIGH Voltage I OH = -0.1 mA 1.65-2.2V 1.4 — V IOH = -1 mA 2.5-3.6V 2.2 — V VOL Output LOW Voltage I OL = 0.1 mA 1.65-2.2V — 0.2 V IOL = 2.1 mA 2.5-3.6V — 0.4 V VIH Input HIGH Voltage 1.65-2.2V 1.4 V DD + 0.2 V 2.5-3.6V 2.2 V DD + 0.3 V VIL(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD , Outputs Disabled –1 1 µA Notes: 1. VIL (min.) = –1.0V for pulse width less than 10 ns. ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND –0.2 to VDD +0.3 V VDD VDD Related to GND –0.2 to V DD +0.3 V TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (V DD ) Range Ambient Temperature IS62WV5128ALL IS62WV5128BLL Commercial 0°C to +70°C 1.65V - 2.2V 2.5V - 3.6V Industrial –40°C to +85°C 1.65V - 2.2V 2.5V - 3.6V

4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI AC TEST LOADS Figure 1 Figure 2 CAPACITANCE (1) Symbol Parameter Cond itions Max. Unit CIN Input Capacitance V IN = 0V 8 pF COUT Input/Output Capacitance V OUT = 0V 10 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter IS62WV5128ALL IS62WV5128BLL (Unit) (Unit) Input Pulse Level 0.4V to V DD -0.2V 0.4V to V DD -0.3V Input Rise and Fall Times 5 ns 5ns Input and Output Timing V REF VREF and Reference Level Output Load See Figures 1 and 2 See Figures 1 and 2 IS62WV5128ALL IS62WV5128BLL R1(Ω) 3070 3070 R2(Ω) 3150 3150 VREF 0.9V 1.5V VTM 1.8V 2.8V 30 pF Including jig and scope OUTPUT VTM 5 pF Including jig and scope OUTPUT VTM

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI POWER SUPPLY CHARACTERISTICS (1) (Over Operating Range) 62WV5128ALL (1.65V - 2.2V) Symbol Parameter Test Conditions Max. Unit 70 ns ICC VDD Dynamic Operating VDD = Max., Com. 25 mA Supply Current I OUT = 0 mA, f = fMAX Ind. 30 ICC1 Operating Supply V DD = Max., CS1 = 0.2VCom. 10 mA Current WE = VDD -0.2V Ind. 10 f=1MHZ ISB1 TTL Standby Current V DD = Max., Com. 0.35 mA (TTL Inputs) V IN = VIH or VIL Ind. 0.35 CS1 = VIH, f = 1 MHZ ISB2 CMOS Standby V DD = Max., Com. 15 µA Current (CMOS Inputs)CS1 ≥ VDD – 0.2V, Ind. 15 VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Note: 1. At f = fMAX , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. POWER SUPPLY CHARACTERISTICS (1) (Over Operating Range) 62WV5128BLL (2.5V - 3.6V) Symbol Parameter Test Conditions Max. Max. Unit 55 ns 70 ns ICC VDD Dynamic Operating VDD = Max., Com. 40 35 mA Supply Current I OUT = 0 mA, f = fMAX Ind. 45 40 ICC1 Operating Supply V DD = Max., CS1 = 0.2VCom. 15 15 mA Current WE = VDD -0.2V Ind. 15 15 f=1MHZ ISB1 TTL Standby Current V DD = Max., Com. 0.35 0.35 mA (TTL Inputs) V IN = VIH or VIL Ind. 0.35 0.35 CS1 = VIH, f = 1 MHZ ISB2 CMOS Standby V DD = Max., Com. 15 15 µA Current (CMOS Inputs)CS1 ≥ VDD – 0.2V, Ind. 15 15 VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Note: 1. At f = fMAX , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI AC WAVEFORMS READ CYCLE NO. 1 (1,2) (Address Controlled) (CS1 = OE = VIL, WE = VIH) DATA VALIDPREVIOUS DATA VALID tAA tOHA tOHA tRC D OUT ADDRESS READ CYCLE SWITCHING CHARACTERISTICS (1) (Over Operating Range) 55 ns 70 ns Symbol Parameter Min. Max. Min. Max. Unit tRC Read Cycle Time 55 — 70 — ns tAA Address Access Time — 55 — 70 ns tOHA Output Hold Time 10 — 10 — ns tACS1 CS1 Access Time — 55 — 70 ns tDOE OE Access Time — 25 — 35 ns tHZOE (2) OE to High-Z Output — 20 — 25 ns tLZOE (2) OE to Low-Z Output 5 — 5 — ns tHZCS1 CS1 to High-Z Output 0 20 0 25 ns tLZCS1 CS1 to Low-Z Output 10 — 10 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to VDD -0.2V/VDD -0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI AC WAVEFORMS READ CYCLE NO. 2 (1,3)(CS1, OE Controlled) Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1= VIL. WE=V IH. 3. Address is valid prior to or coincident with CS1 LOW transition. tRC tOHAtAA tDOE tLZOE tACS1 tLZCS1 tHZOE HIGH-Z DATA VALID tHZCS ADDRESS OE CS1 DOUT

8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI WRITE CYCLE SWITCHING CHARACTERISTICS (1,2) (Over Operating Range) 55 ns 70 ns Symbol Parameter Min. Max. Min. Max. Unit tWC Write Cycle Time 55 — 70 — ns tSCS1 CS1 to Write End 45 — 60 — ns tAW Address Setup Time to Write End 45 — 60 — ns tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWE WE Pulse Width 40 — 50 — ns tSD Data Setup to Write End 25 — 30 — ns tHD Data Hold from Write End 0 — 0 — ns tHZWE (3) WE LOW to High-Z Output — 20 — 20 ns tLZWE (3) WE HIGH to Low-Z Output 5 — 5 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to VDD -0.2V/VDD -0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1 (CS1 Controlled, OE = HIGH or LOW) DATA-IN VALID DATA UNDEFINED tWC tSCS1 tAW tHA tPWE tHZWE HIGH-Z tLZWEtSA tSD tHD ADDRESS CS1 WE DOUT DIN

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) DATA-IN VALID DATA UNDEFINED tWC tSCS1 tAW tHA tPWE tHZWE HIGH-Z tLZWEtSA tSD tHD ADDRESS OE CS1 WE DOUT DIN DATA-IN VALID DATA UNDEFINED tWC tSCS1 tAW tHA tPWE tHZWE HIGH-Z tLZWEtSA tSD tHD ADDRESS OE CS1 WE DOUT DIN

10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR VDD for Data Retention See Data Retention Waveform 1.2 3.6 V IDR Data Retention Current V DD = 1.2V, CS1 ≥ VDD – 0.2V — 15 µA tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns tRDR Recovery Time See Data Retention Waveform t RC —n s DATA RETENTION WAVEFORM ( CS1CS1CS1CS1CS1 Controlled) VDD CS1 ≥ VDD - 0.2V tSDR tRDR VDR CS1 GND Data Retention Mode

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI

ORDERING INFORMATION

IS62WV5128ALL (1.65V - 2.2V) Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package

70 IS62WV5128ALL-70T TSOP, TYPE I

70 IS62WV5128ALL-70T2 TSOP, TYPE II

70 IS62WV5128ALL-70H sTSOP, TYPE I

Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package

70 IS62WV5128ALL-70TI TSOP, TYPE I

70 IS62WV5128ALL-70T2I TSOP, TYPE II

70 IS62WV5128ALL-70HI sTSOP, TYPE I

IS62WV5128BLL (2.5V - 3.6V) Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package

55 IS62WV5128BLL-55T2 TSOP, TYPE II

55 IS62WV5128BLL-55H sTSOP, TYPE I

70 IS62WV5128BLL-70T TSOP, TYPE I

70 IS62WV5128BLL-70T2 TSOP, TYPE II

70 IS62WV5128BLL-70H sTSOP, TYPE I

Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package

55 IS62WV5128BLL-55TI TSOP, TYPE I

55 IS62WV5128BLL-55T2I TSOP, TYPE II

55 IS62WV5128BLL-55HI sTSOP, TYPE I

70 IS62WV5128BLL-70TI TSOP, TYPE I

70 IS62WV5128BLL-70HI sTSOP, TYPE I

Integrated Silicon Solution, Inc. PACKAGING INFORMATION ISSI Plastic STSOP - 32 pins Package Code: H (Type I) Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protru- sions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Plastic STSOP (H - Type I) Millimeters Inches Symbol Min Max Min Max Ref. Std. N 32 A — 1.25 — 0.049 A1 0.05 — 0.002 — A2 0.95 1.05 0.037 0.041 b 0.17 0.23 0.007 0.009 C 0.14 0.16 0.0055 0.0063 D 13.20 13.60 0.520 0.535 D1 11.70 11.90 0.461 0.469 E 7.90 8.10 0.311 0.319 e 0.50 BSC 0.020 BSC L 0.30 0.70 0.012 0.028 S 0.28 Typ. 0.011 Typ. α 0° 5° 0° 5° PK13197H32 Rev. B 04/21/03 SEATING PLANE C D 1 N e S b A E L α

PACKAGING INFORMATION ISSI Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 02/20/03 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Plastic TSOP Package Code: T (Type II) D SEATING PLANE be C

1 N/2

A E L α ZD Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Plastic TSOP (T - Type II) Millimeters Inches Millimeters Inches Millimeters Inches Symbol Min Max Min Max Min Max Min Max Min Max Min Max Ref. Std. No. Leads (N) 32 44 50

Integrated Silicon Solution, Inc. 1 ISSI PACKAGING INFORMATION Plastic TSOP - 32 pins Package Code: T (Type I) D SEATING PLANE Be C N E AS H L α Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Plastic TSOP (T—Type I) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads 32 A — 1.20 — 0.047 A1 0.05 0.25 0.002 0.010 B 0.17 0.23 0.007 0.009 C 0.12 0.17 0.006 0.014 D 7.90 8.10 0.308 0.316 E 18.30 18.50 0.714 0.722 H 19.80 20.20 0.772 0.788 e 0.50 BSC 0.020 BSC L 0.40 0.60 0.016 0.024 α 0° 8° 0° 8° PK13197T32 Rev. B 01/31/97