62LV12816 ISSI | Alldatasheet
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Technical content
Integrated Silicon Solution, Inc. 1 ADVANCE INFORMATION SR002-0C 08/20/98 ISSI
FEATURES
- High-speed access time: 70, 100, and 120 ns
- CMOS low power operation – 120 mW (typical) operating – 6 µW (typical) CMOS standby
- TTL compatible interface levels
- Single 3V ± 10% V CC power supply
- Fully static operation: no clock or refresh required
- Three state outputs
- Data control for upper and lower bytes
- Industrial temperature available
- Available in the 44-pin TSOP (Type II) and 48-pin mini BGA IS62LV12816L 128K x 16 CMOS STATIC RAM
DESCRIPTION
The ISSI IS62LV12816L is a high-speed, 2,097,152-bit static RAM organized as 131,072 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62LV12816L is packaged in the JEDEC standard 44-pin TSOP (Type II) and 48-pin mini BGA. FUNCTIONAL BLOCK DIAGRAM ADVANCE INFORMATION AUGUST 1998 The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc. A0-A16 CE OE WE 128K x 16 MEMORY ARRAYDECODER COLUMN I/O CONTROL CIRCUIT GND VCC I/O DATA CIRCUIT I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte UB LB ISSI
2 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR002-0C 08/20/98 ISSI PIN CONFIGURATIONS 44-Pin TSOP (Type II) TRUTH TABLE I/O PIN Mode WEWEWEWEWE CECECECECE OEOEOEOEOE LBLBLBLBLB UBUBUBUBUB I/O0-I/O7 I/O8-I/O15 Vcc Current Not Selected X H X X X High-Z High-Z I SB 1, ISB 2 Output Disabled H L H X X High-Z High-Z I CC X L X H H High-Z High-Z Read H L L L H D OUT High-Z I CC H L L H L High-Z D OUT HLLLL D OUT D OUT Write L L X L H D IN High-Z I CC L L X H L High-Z D IN LLXLL D IN D IN CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A10 A11 NC PIN DESCRIPTIONS A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vcc Power GND Ground 48-Pin mini BGA 1 2 3 4 5 6 A B C D E F G H LB OE A0 A1 A2 N/C I/O8 UB A3 A4 CE I/O 0 I/O9 I/O10 A5 A6 I/O1 I/O2 GND I/O11 NC A7 I/O3 Vcc Vcc I/O12 NC A16 I/O4 GND I/O14 I/O13 A14 A15 I/O5 I/O6 I/O15 NC A12 A13 WE I/O7 NC A8 A9 A10 A11 NC
Integrated Silicon Solution, Inc. 3 ADVANCE INFORMATION SR002-0C 08/20/98 ISSI POWER SUPPLY CHARACTERISTICS (1) (Over Operating Range) -70 -100 -120 ICC Vcc Dynamic Operating VCC = Max., Com. — 40 — 30 — 20 mA Supply Current I OUT = 0 mA, f = fMAX Ind. — 60 — 50 — 40 (TTL Inputs) V IN = VIH or VIL Ind. — 1.0 — 1.0 — 1.0 CE ≥ VIH , f = 0 ISB 2 CMOS Standby V CC = Max., Com. — 15 — 15 — 15 µA Current (CMOS Inputs)CE ≥ VCC – 0.2V, Ind. — 25 — 25 — 25 VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Note: 1. At f = fMAX , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage V CC = Min., IOH = –1 mA 2.0 — V VOL Output LOW Voltage V CC = Min., IOL = 2.1 mA — 0.4 V VIH Input HIGH Voltage 2.2 V CC + 0.2 V VIL(1) Input LOW Voltage –0.2 0.4 V ILI Input Leakage GND ≤ VIN ≤ VCC –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VCC , Outputs Disabled –1 1 µA Notes: 1. VIL (min.) = –2.0V for pulse width less than 10 ns. ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND –0.5 to Vcc+0.5 V TBIAS Temperature Under Bias –40 to +85 °C VCC Vcc Related to GND –0.3 to +4.0 V TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Ambient Temperature V CC Commercial 0 °C to +70°C 3.0V ± 10% Industrial –40 °C to +85°C 3.0V ± 10%
Integrated Silicon Solution, Inc. 5 ADVANCE INFORMATION SR002-0C 08/20/98 ISSI READ CYCLE SWITCHING CHARACTERISTICS (1) (Over Operating Range) -70 -100 -120 tRC Read Cycle Time 70 — 100 — 120 — ns tAA Address Access Time — 70 — 100 — 120 ns tOHA Output Hold Time 10 — 15 — 15 — ns tACE CE Access Time — 70 — 100 — 120 ns tDOE OE Access Time — 35 — 50 — 60 ns tHZOE (2) OE to High-Z Output — 25 — 30 0 40 ns tLZOE (2) OE to Low-Z Output 5 — 5 — 5 — ns tHZCE (2) CE to High-Z Output 0 25 0 30 0 40 ns tLZCE (2) CE to Low-Z Output 10 — 10 — 10 — ns tBA LB, UB Access Time — 35 — 50 — 60 ns tHZB LB, UB to High-Z Output 0 25 0 35 0 50 ns tLZB LB, UB to Low-Z Output 0 — 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4 to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. DATA VALIDPREVIOUS DATA VALID tAA tOHA tOHA tRC D OUT ADDRESS AC WAVEFORMS READ CYCLE NO. 1 (1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
6 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR002-0C 08/20/98 ISSI WRITE CYCLE SWITCHING CHARACTERISTICS (1,2) (Over Operating Range) -70 -100 -120 tWC Write Cycle Time 70 — 100 — 120 — ns tSCE CE to Write End 65 — 80 — 100 — ns tAW Address Setup Time to Write End 65 — 80 — 100 — ns tHA Address Hold from Write End 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — ns tPWB LB, UB Valid to End of Write 60 — 80 — 100 — ns tPWE WE Pulse Width 60 — 80 — 100 — ns tSD Data Setup to Write End 30 — 40 — 50 — ns tHD Data Hold from Write End 0 — 0 — 0 — ns tHZWE (3) WE LOW to High-Z Output — 30 — 40 — 50 ns tLZWE (3) WE HIGH to Low-Z Output 5 — 5 — 5 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. tRC tOHAtAA tDOE tLZOE tACE tLZCE tHZOE HIGH-Z DATA VALID tHZB ADDRESS OE CE LB, UB D OUT tHZCE tBA tLZB AC WAVEFORMS READ CYCLE NO. 2 (1,3) Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition.
Integrated Silicon Solution, Inc. 7 ADVANCE INFORMATION SR002-0C 08/20/98 ISSI AC WAVEFORMS WRITE CYCLE NO. 1 (1,2) (WE Controlled) Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). UNDEFINED UNDEFINED tWC tSCE tPWB tAW tHA HIGH-ZHIGH-Z tPWE tHD tSA tHZWE ADDRESS CE LB, UB WE WRITE (1) D OUT D IN tLZWE tSD
8 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR002-0C 08/20/98 ISSI DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.3 V IDR Data Retention Current Vcc = 2.0V, CE ≥ Vcc – 0.2V — 15 µA tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns tRDR Recovery Time See Data Retention Waveform tRC —n s DATA RETENTION WAVEFORM (CE Controlled) VCC CE ≥ VCC – 0.2V tSDR tRDR VDR CE GND 2.3V 2.0V Data Retention Mode
Integrated Silicon Solution, Inc. 9 ADVANCE INFORMATION SR002-0C 08/20/98 ISSI Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054 Fax: (408) 588-0806 Toll Free: 1-800-379-4774 email: sales@issi.com http://www.issi.com ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package
70 IS62LV12816L-70T TSOP (Type II)
70 IS62LV12816L-70B Mini BGA
100 IS62LV12816L-100T TSOP (Type II)
100 IS62LV12816L-100B Mini BGA
120 IS62LV12816L-120T TSOP (Type II)
120 IS62LV12816L-120B Mini BGA
Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package