62C256

IS62C256 ISSI | Alldatasheet

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Technical content

Integrated Silicon Solution, Inc. — 1-800-379-4774 1 SR072-1E 05/12/99 ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.

FEATURES

• Access time: 45, 70 ns
• Low active power: 200 mW (typical)
• Low standby power — 250 mW (typical) CMOS standby — 28 mW (typical) TTL standby
• Fully static operation: no clock or refresh required
• TTL compatible inputs and outputs
• Single 5V power supply

DESCRIPTION

The ISSI IS62C256 is a low power, 32,768 word by 8-bit CMOS static RAM. It is fabricated using ISSI's high- performance, low power CMOS technology. When CS is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 mW (typical) at CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Select (CS) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62C256 is pin compatible with other 32K x 8 SRAMs in plastic SOP or TSOP (Type I) package. IS62C256 32K x 8 LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM A0-A14 CS OE WE 32K X 8 MEMORY ARRAYDECODER COLUMN I/O CONTROL CIRCUIT GND VCC I/O DATA CIRCUIT I/O0-I/O7 ISSI

2 Integrated Silicon Solution, Inc. — 1-800-379-4774 SR072-1E 05/12/99 ISSI PIN CONFIGURATION 28-Pin SOP A14 A12 I/O0 I/O1 I/O2 GND VCC WE A13 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 0.5 W IOUT DC Output Current (LOW) 20 mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OE A11 A13 WE VCC A14 A12 A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 PIN CONFIGURATION 28-Pin TSOP PIN DESCRIPTIONS A0-A14 Address Inputs CS Chip Select Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output Vcc Power GND Ground TRUTH TABLE Mode WEWEWEWEWE CSCSCSCSCS OEOEOEOEOE I/O Operation Vcc Current Not Selected X H X High-Z I SB 1, ISB 2 (Power-down) Output Disabled H L H High-Z I CC 1, ICC 2 Read H L L D OUT ICC 1, ICC 2 Write L L X D IN ICC 1, ICC 2

Integrated Silicon Solution, Inc. — 1-800-379-4774 3 SR072-1E 05/12/99 ISSI OPERATING RANGE Range Ambient Temperature V CC Commercial 0 °C to +70°C 5V – 10% Industrial –40 °C to +85°C 5V – 10% CAPACITANCE (1,2) Symbol Parameter Conditions Max. Unit C IN Input Capacitance V IN = 0V 8 pF C OUT Output Capacitance V OUT = 0V 10 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: T A = 25°C, f = 1 MHz, Vcc = 5.0V. POWER SUPPLY CHARACTERISTICS (1) (Over Operating Range) -45 ns -70 ns Symbol Parameter Test Conditions Min. Max. Min. Max. Unit ICC 1 Vcc Operating V CC = Max., CS = VIL Com. — 60 — 60 mA Supply Current I OUT = 0 mA, f = 0 Ind. — 70 — 70 ICC 2 Vcc Dynamic Operating V CC = Max., CS = VIL Com. — 70 — 65 mA Supply Current I OUT = 0 mA, f = fMAX Ind. — 80 — 75 ISB 1 TTL Standby Current V CC = Max., Com. — 5 — 5 mA (TTL Inputs) V IN = VIH or VIL Ind. — 10 — 10 CS ‡ VIH, f = 0 ISB 2 CMOS Standby V CC = Max., Com. — 0.5 — 0.5 mA Current (CMOS Inputs) CS ‡ VCC – 0.2V, Ind. — 1.0 — 1.0 VIN ‡ VCC – 0.2V, or VIN £ 0.2V, f = 0 Note: 1. At f = fMAX , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage V CC = Min., IOH = –1.0 mA 2.4 — V VOL Output LOW Voltage V CC = Min., IOL = 2.1 mA — 0.4 V VIH Input HIGH Voltage 2.2 V CC + 0.5 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND £ VIN £ VCC Com. –2 2 mA Ind. –10 10 ILO Output Leakage GND £ VOUT £ VCC , Com. –2 2 mA Outputs Disabled Ind. –10 10 Note: 1. VIL = –3.0V for pulse width less than 10 ns.

Figure 1. Figure 2.

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1.

1. Tested with the load in Figure 2. Transition is measured –500 mV from steady-state voltage. Not 100% tested.

Integrated Silicon Solution, Inc. — 1-800-379-4774 5 SR072-1E 05/12/99 ISSI DATA VALID READ1.eps PREVIOUS DATA VALID t AA t OHA t OHA t RC D OUT ADDRESS READ CYCLE NO. 2 (1,3) AC WAVEFORMS READ CYCLE NO. 1 (1,2) t RC t OHAt AA t DOE t LZOE t ACS t LZCS t HZOE HIGH-Z DATA VALID ADDRESS OE CS D OUT t HZCS CS_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS = VIL. 3. Address is valid prior to or coincident with CS LOW transitions.

6 Integrated Silicon Solution, Inc. — 1-800-379-4774 SR072-1E 05/12/99 ISSI WRITE CYCLE SWITCHING CHARACTERISTICS (1,3) (Over Operating Range) -45 ns -70ns Symbol Parameter Min. Max. Min. Max. Unit tWC Write Cycle Time 45 — 70 — ns tSCS CS to Write End 35 — 60 — ns tAW Address Setup Time to Write End 25 — 60 — ns tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWE (4) WE Pulse Width 25 — 55 — ns tSD Data Setup to Write End 20 — 30 — ns tHD Data Hold from Write End 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured –500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (CS Controlled, OE is HIGH or LOW) (1 ) DATA UNDEFINED t WC VALID ADDRESS t SCS t PWE1 t PWE2 t AW t HA HIGH-Z t HD t SA t HZWE ADDRESS CS WE D OUT D IN DATA IN VALID t LZWE t SD CS_WR1.eps

Integrated Silicon Solution, Inc. — 1-800-379-4774 7 SR072-1E 05/12/99 ISSI AC WAVEFORMS WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) DATA UNDEFINED LOW t WC VALID ADDRESS t PWE1 t AW t HA HIGH-Z t HD t SA t HZWE ADDRESS CS WE D OUT D IN OE DATA IN VALID t LZWE t SD CS_WR2.eps WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) DATA UNDEFINED t WC VALID ADDRESS LOW LOW t PWE2 t AW t HA HIGH-Z t HD t SA t HZWE ADDRESS CS WE D OUT D IN OE DATA IN VALID t LZWE t SD CS_WR3.eps Notes: 1. The internal write time is defined by the overlap of Cs LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. I/O will assume the High-Z state if OE = VIH.

8 Integrated Silicon Solution, Inc. — 1-800-379-4774 SR072-1E 05/12/99 ISSI

ORDERING INFORMATION

Commerical Range: 0°C to +70°C Speed (ns) Order Part No. Package

45 IS62C256-45T TSOP

70 IS62C256-70T TSOP

Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package

45 IS62C256-45TI TSOP

70 IS62C256-70TI TSOP

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com