61LV256

61LV256 ISSI | Alldatasheet

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Technical content

Integrated Silicon Solution, Inc. 2-1 Rev. F 0296 SR81995LV61 ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1996, Integrated Silicon Solution, Inc.

FEATURES

• High-speed access time: 12, 15, 20, 25 ns
• Automatic power-down when chip is deselected
• CMOS low power operation — 345 mW (max.) operating — 7 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh required
• Three-state outputs

DESCRIPTION

The ISSI IS61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable pro- cess coupled with innovative circuit design techniques, yields access times as fast as 12 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV256 is available in the JEDEC standard 28-pin, 300-mil DIP and SOJ, plus the 450-mil TSOP package. IS61LV256 32K x 8 LOW VOLTAGE CMOS STATIC RAM FEBRUARY 1996 ISSI FUNCTIONAL BLOCK DIAGRAM A0-A14 CE OE WE

256 X 1024

2-2 Integrated Silicon Solution, Inc. Rev. F 0296 SR81995LV61 PIN CONFIGURATION 28-Pin DIP and SOJ OE A11 A13 WE VCC A14 A12 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A12 I/O0 I/O1 I/O2 GND VCC WE A13 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PIN CONFIGURATION 28-Pin TSOP PIN DESCRIPTIONS A0-A14 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output Vcc Power GND Ground TRUTH TABLE Mode WEWEWEWEWE CECECECECE OEOEOEOEOE I/O Operation Vcc Current Not Selected X H X High-Z I SB 1, ISB 2 (Power-down) Output Disabled H L H High-Z I CC 1, ICC 2 Read H L L D OUT ICC 1, ICC 2 Write L L X D IN ICC 1, ICC 2 ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND –0.5 to +4.6 V TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 0.5 W IOUT DC Output Current (LOW) 20 mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Integrated Silicon Solution, Inc. 2-3 Rev. F 0296 SR81995LV61 DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage V CC = Min., IOH = –2.0 mA 2.4 — V VOL Output LOW Voltage V CC = Min., IOL = 4.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 V CC + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VCC Com. –2 2 µA Ind. –5 5 ILO Output Leakage GND ≤ VOUT ≤ VCC , Outputs Disabled Com. –2 2 µA Ind. –5 5 Notes: 1. VIL = –3.0V for pulse width less than 10 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. CAPACITANCE (1,2) Symbol Parameter Conditions Max. Unit C IN Input Capacitance V IN = 0V 6 pF C OUT Output Capacitance V OUT = 0V 5 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: T A = 25°C, f = 1 MHz, Vcc = 3.3V. POWER SUPPLY CHARACTERISTICS (1) (Over Operating Range) -12 ns -15 ns -20 ns -25 ns ICC 1 Vcc Operating V CC = Max., CE = VIL Com. — 50 — 50 — 50 — 50 mA Supply Current I OUT = 0 mA, f = 0 Ind. — — — 60 — 60 — 60 ICC 2 Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 100 — 90 — 80 — 70 mA Supply Current I OUT = 0 mA, f = fMAX Ind. — — — 100 — 90 — 80 ISB 1 TTL Standby Current V CC = Max., Com. — 10 — 10 — 10 — 10 mA (TTL Inputs) V IN = VIH or VIL Ind. — — — 20 — 20 — 20 CE ≥ VIH, f = 0 ISB 2 CMOS Standby V CC = Max., Com. — 2 — 2 — 2 — 2 mA Current (CMOS Inputs) CE ≤ VCC – 0.2V, Ind. — — — 5 — 5 — 5 VIN > VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Notes: 1. At f = fMAX , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. OPERATING RANGE Range Ambient Temperature V CC Commercial 0 °C to +70°C 3.3V +10%, –5% Industrial –40 °C to +85°C 3.3V ± 5%

2-4 Integrated Silicon Solution, Inc. Rev. F 0296 SR81995LV61 AC TEST LOADS 635 Ω 30 pF Including jig and scope 702 Ω OUTPUT 3.3V 635 Ω 5 pF Including jig and scope 702 Ω OUTPUT 3.3V Figure 1a. Figure 1b. AC TEST CONDITIONS Parameter Unit Input Pulse Level 0V to 3.0V Input Rise and Fall Times 3 ns Input and Output Timing 1.5V and Reference Levels Output Load See Figures 1a and 1b READ CYCLE SWITCHING CHARACTERISTICS (1) (Over Operating Range) -12 ns -15 ns -20 ns -25 ns tRC Read Cycle Time 12 — 15 — 20 — 25 — ns tAA Address Access Time — 12 — 15 — 20 — 25 ns tOHA Output Hold Time 2 — 2 — 2 — 2 — ns tACE CE Access Time — 12 — 15 — 20 — 25 ns tDOE OE Access Time — 6 — 7 — 8 — 9 ns tLZOE (2) OE to Low-Z Output 0 — 0 — 0 — 0 — ns tHZOE (2) OE to High-Z Output — 7 — 8 — 9 — 10 ns tLZCE (2) CE to Low-Z Output 3 — 3 — 3 — 3 — ns tHZCE (2) CE to High-Z Output — 5 — 6 — 9 — 10 ns tPU (3) CE to Power-Up 0 — 0 — 0 — 0 — ns tPD (3) CE to Power-Down — 13 — 15 — 18 — 20 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested.

Integrated Silicon Solution, Inc. 2-5 Rev. F 0296 SR81995LV61 DATA VALID tAA tOHA tOHA tRC D OUT ADDRESS 50%50% tRC tOHAtAA tDOE tLZOE tACE tLZCE tHZOE tPD HIGH-Z tPU DATA VALID tHZCE ISB ADDRESS OE CE D OUT SUPPLY CURRENT ICC READ CYCLE NO. 2 (1,3) Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. AC WAVEFORMS READ CYCLE NO. 1 (1,2)

2-6 Integrated Silicon Solution, Inc. Rev. F 0296 SR81995LV61 AC WAVEFORMS WRITE CYCLE NO. 1 (WEWEWEWEWE Controlled)(1,2) DATA-IN VALID DATA UNDEFINED tWC tSCE tAW tHA tPWE tHZWE HIGH-Z tLZWEtSA tSD tHD ADDRESS CE WE D OUT D IN WRITE CYCLE SWITCHING CHARACTERISTICS (1,3) (Over Operating Range) -12 ns -15 ns -20 ns -25 ns tWC Write Cycle Time 12 — 15 — 20 — 25 — ns tSCE CE to Write End 8 — 10 — 13 — 15 — ns tAW Address Setup Time to Write End 8 — 10 — 15 — 20 — ns tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — 0 — ns tPWE (4) WE Pulse Width 8 — 10 — 13 — 15 — ns tSD Data Setup to Write End 6 — 8 — 10 — 12 — ns tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns tHZWE (2) WE LOW to High-Z Output — 6 — 7 — 8 — 10 ns tLZWE (2) WE HIGH to Low-Z Output 0 — 0 — 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH.

Integrated Silicon Solution, Inc. 2-7 Rev. F 0296 SR81995LV61 Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE ≥ VIH. HIGH-ZDATA UNDEFINED DATA-IN VALID tWC tSCEtSA tHA tPWE tAW tHZWE tSD tHD tLZWE ADDRESS D IN CE WE D OUT WRITE CYCLE NO. 2 (CECECECECE Controlled)(1,2)

ORDERING INFORMATION

Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package

12 IS61LV256-12N 300-mil Plastic DIP

12 IS61LV256-12T TSOP - 450 mil

12 IS61LV256-12J 300-mil Plastic SOJ

15 IS61LV256-15N 300-mil Plastic DIP

15 IS61LV256-15T 450-mil TSOP

15 IS61LV256-15J 300-mil Plastic SOJ

20 IS61LV256-20N 300-mil Plastic DIP

20 IS61LV256-20T 450-mil TSOP

20 IS61LV256-20J 300-mil Plastic SOJ

25 IS61LV256-25N 300-mil Plastic DIP

25 IS61LV256-25T 450-mil TSOP

25 IS61LV256-25J 300-mil Plastic SOJ

Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package

12 IS61LV256-12NI 300-mil Plastic DIP

12 IS61LV256-12TI TSOP - 450 mil

12 IS61LV256-12JI 300-mil Plastic SOJ

15 IS61LV256-15NI 300-mil Plastic DIP

15 IS61LV256-15TI 450-mil TSOP

15 IS61LV256-15JI 300-mil Plastic SOJ

20 IS61LV256-20NI 300-mil Plastic DIP

20 IS61LV256-20TI 450-mil TSOP

20 IS61LV256-20JI 300-mil Plastic SOJ

25 IS61LV256-25NI 300-mil Plastic DIP

25 IS61LV256-25TI 450-mil TSOP

25 IS61LV256-25JI 300-mil Plastic SOJ

2-8 Integrated Silicon Solution, Inc. Rev. F 0296 SR81995LV61 Integrated Silicon Solution, Inc.

680 Almanor Avenue

Sunnyvale, CA 94086 Fax: (408) 245-4774 Toll Free: 1-800-379-4774 http://www.issiusa.com ISSI