ICS557-05A ICST | Alldatasheet

Document overview

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Technical content

Features

  • Packaged in 20-pin TSSOP
  • Available in Pb (lead) free package
  • Supports PCI-Express applications
  • Four differential spread spectrum clock outputs
  • Spread spectrum for EMI reduction
  • Uses external 25 MHz clock or crystal input
  • Power down pin turns off chip
  • OE control tri-states outputs
  • Spread and frequency selection via external pins
  • Spread Bypass option available
  • Industrial temperature range available Block Diagram Spread Spectrum/ Output clock selection CLKOUTA CLKOUTA Rr(IREF) PLL Clock Synthesis GND VDD Clock Oscillator SEL[2:0] Spread Spectrum Circuitry CLKOUTB CLKOUTD

25 MHz

Quad Differential PCI-Express Clock Source MDS 557-05A E Revision 011606 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Pin Assignment Spread Spectrum Selection Table GNDODA OE CLKC CLKD GNDXD CLKD IREF CLKB CLKB VDDXD CLKA CLKA PD VDDODA CLKC 20-pin (173 mil) TSSOP Spread% Spread Type Output Frequency (MHz) -0.5 Down 100 -1.0 Down 100 -1.5 Down 100 No Spread Not Applicable 100 -0.5 Down 200 -1.0 Down 200 -1.5 Down 200 No Spread Not Applicable 200

Quad Differential PCI-Express Clock Source MDS 557-05A E Revision 011606 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Pin Descriptions Pin Pin Name Pin Type Pin Description VDDXD Power Connect to +3.3 V digital supply. Input Spread spectrum select pin #0. See table above. Internal pull-up resistor. Input Spread spectrum select pin #1. See table above Internal pull-up resistor. Input Spread spectrum select pin #2. See table above. Internal pull-up resistor. Input Crystal connection. Connect to a fundamental mode crystal or clock input. Output Crystal connection. Connect to a fundamental mode crystal or leave open. PD Input Powers down all PLL’s and tri-states outputs when low. Internal pull-up resistor. OE Input Provides output on, tri-states output (High = enable outputs; Low = disable outputs). Internal pull-up resistor. GND Power Connect to digital ground. IREF Output Precision resistor attached to this pin is connected to the internal current reference. CLKD Output Selectable 100/200 MHz spread spectrum differential Compliment output clock D. CLKD Output Selectable 100/200 MHz spread spectrum differential True output clock D. CLKC Output Selectable 100/200 MHz spread spectrum differential Compliment output clock C. CLKC Output Selectable 100/200 MHz spread spectrum differential True output clock C. VDDODA Power Connect to +3.3 V analog supply. GND Power Connect to analog ground. CLKB Output Selectable 100/200 MHz spread spectrum differential Compliment output clock B. CLKB Output Selectable 100/200 MHz spread spectrum differential True output clock B. CLKA Output Selectable 100/200 MHz spread spectrum differential Compliment output clock A. CLKA Output Selectable 100/200 MHz spread spectrum differential True output clock A.

Quad Differential PCI-Express Clock Source MDS 557-05A E Revision 011606 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS557-05A

Application Information

As with any high-performance mixed-signal IC, the ICS557-05A must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS557-05A. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 µF should be connected between VDD and GND pairs (1,9 and 15,16) as close to the device as possible. On chip capacitors- Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value (in pf) of these crystal caps equal (CL-12)*2 in this equation, CL=crystal load capacitance in pf. For example, for a crystal with a 16 pF load cap, each external crystal cap would be 8 pF. [(16-12)x2]=8. Current Reference Source Rr (Iref) If board target trace impedance (Z) is 50Ω, then Rr = 475Ω (1%), providing IREF of 2.32 mA, output current (IOH) is equal to 6*IREF. Load Resistors RL Since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. Output Termination The PCI-Express differential clock outputs of the ICS557-05A are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-05A can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section.

Quad Differential PCI-Express Clock Source MDS 557-05A E Revision 011606 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Output Structures General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-05A.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. RR 475 6*IREF =2.3 mA IREF See Output Termination Sections - Pages 3 ~ 5 Ω

Quad Differential PCI-Express Clock Source MDS 557-05A E Revision 011606 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS557-05A PCI-Express Layout Guidelines PCI-Express Device Routing Typical PCI-Express (HCSL) Waveform Common Recommendations for Differential Routing Dimension or Value Unit L1 length, Route as non-coupled 50 ohm trace. 0.5 max inch L2 length, Route as non-coupled 50 ohm trace. 0.2 max inch L3 length, Route as non-coupled 50 ohm trace. 0.2 max inch RS ohm RT 49.9 ohm Differential Routing on a Single PCB Dimension or Value Unit L4 length, Route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch L4 length, Route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch Differential Routing to a PCI Express Connector Dimension or Value Unit L4 length, Route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch L4 length, Route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch RS RS RT RT PCI-Express Load or Connector L3’ L1’ L2’ L4’ ICS557-05A Output Clock 0.175 V 0.52 V 0.175 V 0.52 V tOR tOF 500 ps 500 ps 700 mV

Quad Differential PCI-Express Clock Source MDS 557-05A E Revision 011606 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS557-05A LVDS Compatible Layout Guidelines LVDS Device Routing Typical LVDS Waveform LVDS Recommendations for Differential Routing Dimension or Value Unit L1 length, Route as non-coupled 50 ohm trace. 0.5 max inch L2 length, Route as non-coupled 50 ohm trace. 0.2 max inch RP 100 ohm RQ 100 ohm RT 150 ohm L3 length, Route as coupled 50 ohm differential trace. L3 length, Route as coupled 50 ohm differential trace. L2’ L1’ L3’ RQ RP LVDS Device Load ICS557-05A Clock Output RT RT 1150 mV 1250 mV tOR tOF 500 ps 500 ps 1325 mV 1000 mV 1150 mV 1250 mV

Quad Differential PCI-Express Clock Source MDS 557-05A E Revision 011606 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS557-05A. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C 1 Single edge is monotonic when transitioning through region. 2 Inputs with pull-ups/-downs are not included. Item Rating Supply Voltage, VDD, VDDA 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70°C Ambient Operating Temperature (industrial) -40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C ESD Protection (Input) 2000 V min. (HBM) Parameter Symbol Conditions Min. Typ. Max. Units Supply Voltage V 3.135 3.465 Input High Voltage1 VIH 2.0 VDD +0.3 V Input Low Voltage1 VIL VSS-0.3 0.8 V Input Leakage Current2 IIL 0 < Vin < VDD µA Operating Supply Current IDD 50Ω, 2pF load@ 100MHz 105 mA IDDOE OE =Low mA IDDPD No load, PD =Low 500 µA Input Capacitance CIN Input pin capacitance pF Output Capacitance COUT Output pin capacitance pF Pin Inductance LPIN nH Output Resistance Rout CLK outputs 3.0 kΩ Pull-up Resistance RPUP OE, SEL, PD pins 110 kΩ

Quad Differential PCI-Express Clock Source MDS 557-05A E Revision 011606 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85°C 1 Test setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%). 2 Measurement taken from a single-ended waveform. 3 Measurement taken from a differential waveform. 4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. 5 CLKOUT pins are tri-stated when OE is low. asserted. CLKOUT is driven differential when OE is high unless its PD= low. Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency MHz Output Frequency HCSL termination 200 MHz LVDS termination 100 MHz Output High Voltage1,2 VOH 660 700 850 mV Output Low Voltage1,2 VOL -150 mV Crossing Point Voltage1,2 Absolute 250 350 550 mV Crossing Point Voltage1,2,4 Variation over all edges 140 mV Jitter, Cycle-to-Cycle1,3 ps Modulation Frequency Spread spectrum 31.5 kHz Rise Time1,2 tOR From 0.175 V to 0.525 V 175 332 700 ps Fall Time1,2 tOF From 0.525 V to 0.175 V 175 344 700 ps Skew between outputs At crossing point Voltage ps Duty Cycle1,3 Output Enable Time5 All outputs us Output Disable Time5 All outputs us Power-up Time tSTABLE From power-up VDD=3.3 V 3.0 ms Spread Change Time tSPREAD Settling period after spread change 3.0 ms Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air °C/W θJA 1 m/s air flow °C/W θJA 3 m/s air flow °C/W Thermal Resistance Junction to Case θJC °C/W

Quad Differential PCI-Express Clock Source MDS 557-05A E Revision 011606 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS557-05A PCI-Express Layout Guidelines PCI-Express Device Routing Typical PCI-Express (HCSL) Waveform Common Recommendations for Differential Routing Dimension or Value Unit L1 length, Route as non-coupled 50 ohm trace. 0.5 max inch L2 length, Route as non-coupled 50 ohm trace. 0.2 max inch L3 length, Route as non-coupled 50 ohm trace. 0.2 max inch RS ohm RT 49.9 ohm Differential Routing on a Single PCB Dimension or Value Unit L4 length, Route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch L4 length, Route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch Differential Routing to a PCI Express Connector Dimension or Value Unit L4 length, Route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch L4 length, Route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch RS RS RT RT PCI-Express Load or Connector L3’ L1’ L2’ L4’ ICS557-03 Output Clock 0.175 V 0.52 V 0.175 V 0.52 V tOR tOF 500 ps 500 ps 700 mV

Quad Differential PCI-Express Clock Source MDS 557-05A E Revision 011606 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Package Outline and Package Dimensions (20-pin TSSOP, 173 mil Body) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 INDEX AREA 1 2 D E SEATING PLANE A e - C - b aaa C c L *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A 1.20 0.047 0.05 0.15 0.002 0.006 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 D 6.40 6.60 0.252 0.260 E

6.40 BASIC

0.252 BASIC

4.30 4.50 0.169 0.177 e

0.65 Basic

0.0256 Basic

L 0.45 0.75 0.018 0.030 α aaa 0.10 0.004

Quad Differential PCI-Express Clock Source MDS 557-05A E Revision 011606 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS557-05A

Ordering Information

Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature ICS557G-05A ICS557G-05A Tubes 20-pin TSSOP 0 to +70°C ICS557G-05ATR ICS557G-05A Tape and Reel 20-pin TSSOP 0 to +70°C ICS557G-05ALF 557G-05ALF Tubes 20-pin TSSOP 0 to +70°C ICS557G-05ALFTR 557G-05ALF Tape and Reel 20-pin TSSOP 0 to +70°C ICS557GI-05A 557GI-05A Tubes 20-pin TSSOP -40 to +85°C ICS557GI-05ATR 557GI-05A Tape and Reel 20-pin TSSOP -40 to +85°C ICS557GI-05ALF 557GI05ALF Tubes 20-pin TSSOP -40 to +85°C ICS557GI-05ALFTR 557GI05ALF Tape and Reel 20-pin TSSOP -40 to +85°C