ICS556-01 ICST | Alldatasheet

Document overview

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Technical content

Features

  • Packaged in 8-pin TSSOP
  • Requires no external components
  • Low Phase Jitter: <1 ps from 10 kHz to 10 MHz
  • Differential LVDS outputs
  • Operating voltage of 2.5 V.
  • Advanced, low power, sub-micron CMOS process Block Diagram Crystal Oscillator

25 MHz Crystal

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com Broadcom 25 MHz LVDS Clock ICS556-01 Pin Assignment Pin Descriptions External Component Selection The ICS556-01 requires a minimum number of external components for proper operation. A 100Ω termination resistor between CLK and CLK is provided on-chip. Decoupling Capacitors A decoupling capacitor of 0.01µF should be connected between VDD and GND on pins 2 and 3 as close to the ICS556-01 as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. LVDS Driver Termination A general LVDS interface is shown in Figure 2. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. X 2 X 1 V D D G N D C L K I C S 5 5 6 - 0 1

8 P i n ( 1 7 3 m i l ) T S S O P o r S O I C

Crystal connection. VDD Power Power supply. Connect to 2.5 V. GND Power Connect to ground. GND Power Connect to ground. CLK Output Inverting differential clock output. CLK Power Differential clock output. OE Input Output Enable. Internal pull-up resistor. Input Crystal connection. F I G U R E 2 . T Y P I C A L L V D S D R I V E R T E R M I N A T I O N 100 ohm 2.5V 2.5V

100 Ohm Differential Transmission Line

LVDS_Driver

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com Broadcom 25 MHz LVDS Clock ICS556-01 Quartz Crystal The ICS556-01 25 MHz LVDS Clock utilizes an external crystal to generate a low phase noise output. To assure the best system performance and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section shown must be followed. The frequency of oscillation of a quartz crystal is determined by its “cut” and by the load capacitors connected to it. The crystal specified for use with the ICS556-01 is designed to have zero frequency error when the total of on-chip plus stray capacitance is 5 pF. Recommended Crystal Parameters: Initial Accuracy of 25°C±20 ppm Temperature Stability±20 ppm Load Capacitance5 pf Shunt Capacitance, C02 pF Max Equivalent Series Resistance80 Ω Max The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the ICS556-01. There should be no via’s between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal. The value (in pF) of these crystal caps should equal (CL - 12 pF)*2. In this equation, CL =crystal load capacitance in pF. Example: or a crystal with a 16 pF load capacitance, each crystal capacitor would be 8 pF [(16-12) x 2] = 8. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS556-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Soldering Temperature 260°C Parameter Min. Typ. Max. Units Ambient Operating Temperature +70 Power Supply Voltage (measured in respect to GND) +2.375 +2.625 V Reference crystal parameters Refer to page 3

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com Broadcom 25 MHz LVDS Clock ICS556-01 VDD=2.5 V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise Note 1: Outputs terminated with 50Ω to VDD/2 VDD = 2.5 V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 2.375 2.625 V Output High Voltage VOH Note 1 1.375 V Output Low Voltage VOL Note 1 1.125 V Output High Voltage (CMOS Level) VOH IOH = -4 mA VDD-0.4 V Operating Supply Current IDD No load, OE = 1 5.3 mA No load, OE = 0 1.7 mA Parameter Conditions Min. Typ. Max. Units Input Frequency MHz Output Frequency MHz Differential Output Voltages (VOD) 250 350 450 mV ∆ VOD VOD Magnitude Change -40 mV Offset Voltage (VOS) 1.125 1.25 1.375 V ∆ VOS VOS Magnitude Change mV Differential Output Short Circuit Current (IOSD) -3.5 mA Output Short Circuit Current (IOS) -3.5 mA Output Rise Time 20% to 80%, no load 0.8 1.2 ns Output Fall Time 20% to 80%, no load 0.8 1.2 ns Output Clock Duty Cycle Measured at 1.25 V, CL=5 pF Maximum Output Jitter (p-p) CL=5 pF ps Phase Jitter (RMS) Phase Noise integrated from 10 kHz to 10 MHz 1.8 2.5 ps

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com Broadcom 25 MHz LVDS Clock ICS556-01 Parameter Measurement Information 2.5V OUTPUT LOAD AC TEST CIRCUIT LVDS VDD = 2.5V±5% SCOPE 50Ω 50Ω Z = 50Ω Z = 50Ω Qx nQx tPW & tPERIOD nCLK CLK tPERIOD Pulse Width PHASE JITTER nCLK CLK t(φ) tjit(φ) = t(φ) - t(φ)mean = Phase Jitter VOH VOL DIFFERENTIAL INPUT LEVEL VOD Cross Points VDD VOS nCLK CLK GND Clock Outputs 80% 80% 20% 20% tOR tOF OUTPUT RISE/FALL TIME VOD V O S S E T U P LV D S V D D 5 0 Ω o u t D C Inpu t V O S/∆V O S o u t 5 0 Ω VOD SETUP LVDS VDD 100Ω out out DC Input VOD/∆VOD

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com Broadcom 25 MHz LVDS Clock ICS556-01 Package Outline and Package Dimensions (8-pin TSSOP) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping packaging Package Temperature ICS556G-01 556G-01 Tubes 8-pin TSSOP 0 to +70° C ICS556G-01T 556G-01 Tape and Reel 8-pin TSSOP 0 to +70° C INDEX AREA 1 2 D E SEATING PLANE A A A e - C - b aaa C c L Millimeters Inches Symbol Min Max Min Max A 1.20 0.047 0.05 0.15 0.002 0.006 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 C 0.09 0.20 0.0035 0.008 D 2.90 3.10 0.114 0.122 E

6.40 BASIC

0.252 BASIC

4.30 4.50 0.169 0.177 e

0.65 Basic

0.0256 Basic

L 0.45 0.75 0.018 0.030 α aaa 0.10 0.004