ICS544-01 ICST | Alldatasheet

Document overview

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Technical content

Features

  • Packaged in 8-pin SOIC or die
  • Available in Pb-free package
  • ICS’ lowest cost clock divider
  • Easy to use with other generators and buffers
  • Input clock frequency up to 156 MHz
  • Output clock duty cycle of 45/55
  • Output Enable
  • Advanced, low-power CMOS process
  • Operating voltage of 2.25 V to 3.6 V
  • Does not degrade phase noise - no PLL
  • Available in industrial temperature range Block Diagram Divider and Selection Circuitry /32, /64 /256, /512, CLK1 OE GND VDD X1/ICLK 16.777216 MHz clock or crystal input Optional tuning capacitors S1, S0 (1:0)

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS544-01 P R E L I M I N A R Y I N F O R M A T I O N Pin Assignment 8-pin (150 mil) SOIC Clock Divider Table 0 = connect directly to ground 1 = connect directly to VDD Pin Descriptions External Components Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. On chip capacitors- Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value (in pf) of these crystal caps equal (CL-12)*2 in this equation, CL=crystal load capacitance in pf. For example, for a crystal with a 16 pF load cap, each external crystal cap would be 8 pF. [(16-12)x2]=8. Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS544-01 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between VDD and the PCB ground plane. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the X1/ICLK GND VDD OE CLK CLK Input/32 Input/64 Input/256 Input/512 Pin Number Pin Name Pin Type Pin Description X1/ICLK XI Crystal or Clock input. Xo Connect to crystal for crystal input and leave open for clock input. GND Power Connect to ground. Input Select 0 for output clock. Connect to GND or VDD, per divider table above. Internal pull-up resistor. CLK Output Clock output per table above. OE Input Output Enable.Tri-states output clock when low. Also shuts down the oscillator circuit. Internal pull-up resistor. OE=1 normal operation. VDD Power Connect to 2.25 V to 3.6 V. Input Select 1 for output clock. Connect to GND or VDD, per divider table above. Internal pull-up resistor.

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS544-01 P R E L I M I N A R Y I N F O R M A T I O N VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS544-01. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS544-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 +85 Power Supply Voltage (measured in respect to GND) 2.25 3.6 V

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS544-01 P R E L I M I N A R Y I N F O R M A T I O N Unless stated otherwise, VDD = 2.25 V to 3.6 V, CL=15 pf±5%, Ambient Temperature -40°C to +70°C Unless stated otherwise, VDD = 2.25 V to 3.6 V±5%, CL=15 pf±5%, Ambient Temperature -40°C to +70°C Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 2.25 3.6 V Input High Voltage VIH S0, S1, OE, ICLK 0.7VDD V Input Low Voltage VIL S0, S1, OE, ICLK 0.3VDD V Output High Voltage VOH IOH = -2 mA VDD-0.4 VDD-0.15 V Output Low Voltage VOL IOL = 2 mA 0.15 0.4 V Operating Supply Current IDD VDD =2.25 V - 2.75 V 0.3 0.6 mA Operating Supply Current IDD VDD= 2.75 V - 3.6 V 0.5 mA Standby Current ISB OE=0 ua Short Circuit Current IOS ±40 mA Input Capacitance CIN S0, S1, OE pF Nominal Output Impedance ZO at VDD/2 Ω Internal Pull-up Resistor Rpup TBD kΩ Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency, clock input VDD = 3.3 V 156 MHz Output Rise Time tOR 0.1VDD to 0.9VDD 0.2 us Output Fall Time tOF 0.9VDD to 0.1VDD 0.2 us Duty Cycle at VDD/2 49 to 51 Output Enable Delay Time tOE OE going high to CLK output valid us Output Disable Delay Time tOD OE going low to CLK output invalid us Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 150 °C/W θJA 1 m/s air flow 140 °C/W θJA 3 m/s air flow 120 °C/W Thermal Resistance Junction to Case θJC °C/W

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS544-01 P R E L I M I N A R Y I N F O R M A T I O N Marking Diagram (ICS554M-01) Marking Diagram (ICS554MI-01) Marking Diagram (ICS554M-01LF) Marking Diagram (ICS554MI-01LF) Notes: 2. YYWW is the last two digits of the year and week that the part was assembled. 3. “LF” denotes Pb (lead) free package. 4. “I” denotes industrial temperature range. 5. Bottom Marking: (origin) Origin = country of origin if not USA. 554M-01 YYWW 554MI-01 YYWW 554M01LF YYWW 554MI01L YYWW

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS544-01 P R E L I M I N A R Y I N F O R M A T I O N Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 0.10 0.25 .0040 .0098 B 0.33 0.51 .013 .020 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e

1.27 BASIC

0.050 BASIC

H 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 L 0.40 1.27 .016 .050 α

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS544-01 P R E L I M I N A R Y I N F O R M A T I O N

Ordering Information

Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature ICS544M-01 544M-01 Tubes 8-pin SOIC 0 to +70° C ICS544M-01T 544M-01 Tape and Reel 8-pin SOIC 0 to +70° C ICS544MI-01 544MI-01 Tubes 8-pin SOIC -40 to +85° C ICS544MI-01T 544MI-01 Tape and Reel 8-pin SOIC -40 to +85° C ICS544M-01LF 544M01LF Tubes 8-pin SOIC 0 to +70° C ICS544M-01LFT 544M01LF Tape and Reel 8-pin SOIC 0 to +70° C ICS544MI-01LF 544MI01L Tubes 8-pin SOIC -40 to +85° C ICS544MI-01LFT 544MI01L Tape and Reel 8-pin SOIC -40 to +85° C ICS554-01DWF Die on uncut, probed wafers 0 to +70° C ICS554-01DPK Tested die in waffle pack 0 to +70° C