ICS843-75 ICST | Alldatasheet

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www.icst.com/products/hiperclocks.html REV. A JANUARY 9, 2006 Integrated Circuit Systems, Inc. ICS843-75 75MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR GENERAL DESCRIPTION The ICS843-75 is a SAS/SATA Dual Output Oscillator and a member of the HiPerClocksTM family of high performance devices from ICS. The ICS843-75 uses a 25MHz crystal to synthesize 75MHz. The ICS843-75 has excellent jitter performance. The ICS843-75 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.

FEATURES

  • One LVCMOS/LVTTL output, 15Ω output impedence One LVPECL output pair
  • Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal
  • Output frequency: 75MHz
  • Random jitter: 3.07ps (maximum)
  • Deterministic jitter: 0.13ps (maximum)
  • 3.3V operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in both standard and lead-free RoHS-compliant packages HiPerClockS™ ICS ICS843-75 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View VCC XTAL_IN XTAL_OUT VEE nQ1 VCCO BLOCK DIAGRAM PIN ASSIGNMENT Clock Synthesizer XTAL_IN XTAL_OUT 25MHz LVCMOS 75MHz nQ1 LVPECL 75MHz ICS843-75 8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View

TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS

www.icst.com/products/hiperclocks.html REV. A JANUARY 9, 2006 Integrated Circuit Systems, Inc. ICS843-75 75MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = 0°C TO 70°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, VO (LVCMOS) -0.5V to VCCO + 0.5V Outputs, IO (LVPECL) Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA

8 Lead TSSOP

101.7°C/W (0 mps)

8 Lead SOIC

112.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Func- tional operation of product at these conditions or any condi- tions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi- mum rating conditions for extended periods may affect prod- uct reliability. TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = 0°C TO 70°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V H O E T O N e g a tlo V h gi H t u p t u O V V L O E T O N e g a tlo V w o L t u p t u O V h ti w d e t a ni m r e t st u p t u O E T O N Ω V o t O C C n oitc e S n oit a m r o f n I t n e m e r u s a e M r e t e m a r a P e e S ."tiu c ri C ts e T d a o L t u p t u O V TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = 0°C TO 70°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V H O E T O N e g a tlo V h gi H t u p t u O V O C C V O C C V V L O E T O N e g a tlo V w o L t u p t u O V O C C V O C C V V G N I W S g ni w S e g a tlo V t u p t u O k a e P o k a e P V h ti w d e t a ni m r e t st u p t u O E T O N Ω V o t O C C V l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V C C e g a tlo V ylp p u S e vitis o P V V O C C e g a tlo V ylp p u S t u p t u O V I E E t n e rr u C ylp p u S r e w o P A m I C C t n e rr u C ylp p u S r e w o P A m I O C C t n e rr u C ylp p u S t u p t u O A m

TABLE 4. CRYSTAL CHARACTERISTICS (NOTE 1) TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = 0°C TO 70°C

www.icst.com/products/hiperclocks.html REV. A JANUARY 9, 2006 Integrated Circuit Systems, Inc. ICS843-75 75MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR PARAMETER MEASUREMENT INFORMATION LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD LVPECL OUTPUT RISE/FALL TIME 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx LVCMOS 1.65V ± 0.15V -1.65V ± 0.15V Clock Outputs 20% 80% 80% 20% tR tF tPERIOD tPW tPERIOD odc = VCC tPW x 100% GND VCC, VCCO LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD LVCMOS OUTPUT RISE/FALL TIME nQ1 Clock Outputs 20% 80% 80% 20% tR tF VSWING tPW tPERIOD tPW tPERIOD odc = x 100% 3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx nQx LVPECL -1.3V ± 0.3V VEE VCC, VCCO

www.icst.com/products/hiperclocks.html REV. A JANUARY 9, 2006 Integrated Circuit Systems, Inc. ICS843-75 75MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843-75. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843-75 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 110mA = 396mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 396mW + 30mW = 426mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6A. THERMAL RESISTANCE θθθθθJA FOR 8-PIN TSSOP, FORCED CONVECTION θθθθθJA by Velocity (Meters per Second) 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W TABLE 6B. THERMAL RESISTANCE θθθθθJA FOR 8 LEAD SOIC FORCED CONVECTION θθθθθJA by Velocity (Linear Feet per Minute) 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 3. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION

www.icst.com/products/hiperclocks.html REV. A JANUARY 9, 2006 Integrated Circuit Systems, Inc. ICS843-75 75MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR RELIABILITY INFORMATION TRANSISTOR COUNT The transistor count for ICS843-75 is: 2376 TABLE 7A. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θθθθθJA by Velocity (Meters per Second) 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W TABLE 7B. θJAVS. AIR FLOW TABLE 8 LEAD SOIC θθθθθJA by Velocity (Linear Feet per Minute) 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

www.icst.com/products/hiperclocks.html REV. A JANUARY 9, 2006 Integrated Circuit Systems, Inc. ICS843-75 75MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 8A. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MO-153 L O B M Y S s r e t e m illi M m u m i n i M m u m i x a M N A A A b c D E C I S A B E e C I S A B L α a a a PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC TABLE 8B. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MS-012 L O B M Y S s r e t e m illi M M U M I N I M M U M I X A M N A A B C D E e C I S A B H h L α

TABLE 9. ORDERING INFORMATION product for use in life support devices or critical medical instruments. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.