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Features
Attenuation: 0.5 dB steps to 15.5 dB Flexible parallel and serial programming interfaces Latched or direct mode Unique power-up state selection Positive CMOS control logic High attenuation accuracy and linearity over temperature and frequency Very low power consumption Single-supply operation 75Ω impedance Pin compatible with PE430x series Packaged in a 20-lead 4x4 mm QFN Table 1. Electrical Specifications @ +25°C, VDD = 3.0V
- Max input rating in Table 3 & Figures on Pages 4 to 6 for data across frequency
- Note Absolute Maximum in Table 3
Figure 2. Package Type
Table 2. Pin Descriptions exceeding the rate specified in Table 3.
- Latch Enable (LE) has an internal 100 k Ω resistor to VDD
- Connect pin 12 to GND to enable internal negative voltage
- Place a 10 k Ω resistor in series, as close to pin as possible to avoid
Figure 15. Pin Configuration (Top View) devices are immune to latch-up. The PE4307 has a maximum 25 kHz switching rate.
1 N/C No connect
2 RF1 RF port (Note 1)
3 Data Serial interface data input (Note 4)
4 Clock Serial interface clock input
5 LE Latch Enable input (Note 2)
7 N/C No connect
8 PUP2 Power-up selection bit
10 GND Ground connection
11 GND Ground connection
12 V ss/GND Negative supply voltage or GND
13 P/S Parallel/Serial mode select
14 RF2 RF port (Note 1)
15 C8 Attenuation control bit, 8 dB
16 C4 Attenuation control bit, 4 dB
17 C2 Attenuation control bit, 2 dB
19 C1 Attenuation control bit, 1 dB
Table 3. Absolute Maximum Ratings Table 4. Operating Ranges
©2003-2013 Peregrine Semiconductor Corp. All rights reserved. attenuation state, as shown in Table 5. Characteristics), and switching speed (Table 1). Table 5. Truth Table is independent of the state of the LE input. brought LOW, data in the shift register is latched. Table 8 (Serial Interface AC Characteristics). settings to be specified as the power-up state. automatically set to one of two possible values. Truth Table, Parallel Mode). Table 6. Power-Up Truth Table, Parallel
©2003-2013 Peregrine Semiconductor Corp. All rights reserved. Figure 20. Package Drawing
0.90 MAX
0.10 C A B
Document No. 70-0161-05 │ www.psemi.com Page 11 of 11 ©2003-2013 Peregrine Semiconductor Corp. All rights reserved. Advance Information: The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in dev ices or systems int ended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for dam ages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. Sales Contact and Information For Sales and contact information please visit www.psemi.com.