PE4306 PEREGRINE | Alldatasheet

Document overview

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Technical content

Features

  • Attenuation: 1 dB steps to 31 dB
  • Flexible parallel and serial programming interfaces
  • Latched or direct mode
  • Unique power-up state selection
  • Positive CMOS control logic
  • High attenuation accuracy and linearity over temperature and frequency
  • Very low power consumption
  • Single-supply operation
  • 50 Ω impedance
  • Pin compatible with PE430x series
  • Packaged in a 20 Lead 4x4 mm QFN

Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V

  1. See Max input rating in Table 3 & Figures on Pages 2 to 4 for data across frequency.
  2. Note Absolute Maximum in Table 3.

Figure 2. Package Type

Figure 8. Attenuation Error Vs. Attenuation Figure 10. Attenuation Error Vs. Attenuation Figure 9. Attenuation Error Vs. Attenuation Figure 7. Attenuation Error Vs. Frequency

10 MHz @ 25 C

510 MHz @ 25 C

10 MHz @ -40 C

510 MHz @ -40 C

10 MHz @ 85 C

510 MHz @ 85 C

1210 MHZ @ 25 C

1210 MHz @ -40 C

1210 MHz @ 85 C

1010 MHz @ 25 C

1010 MHz @ -40 C

1010 MHz @ 85 C

1510 MHz @ 25 C

2010 MHz @ 25 C

1510 MHz @ -40 C

2010 MHz @ -40 C

1510 MHz @ 85 C

2010 MHz @ 85 C

Figure 12. 1 dB Compression vs. Frequency Figure 13. Input IP3 vs. Frequency Figure 11. Attenuation Error vs. Attenuation

2210 MHz @ 25 C

2510 MHz @ 25 C

2210 MHz @ -40 C

2510 MHz @ -40 C

2210 MHz @ 85 C

2510 MHz @ 85 C

Table 2. Pin Descriptions must be grounded for proper device operation. 2: Latch Enable (LE) has an internal 100 kΩ resistor to VDD. disable internal negative voltage generator.

  1. Place a 10 kΩ resistor in series, as close to pin as possible

Figure 14. Pin Configuration (Top View) vices are immune to latch-up. The PE4306 has a maximum 25 kHz switching rate. dependent upon this condition. 1 C16 Attenuation control bit, 16 dB (Note 4). 3 Data Serial interface data input (Note 4). 4 Clock Serial interface clock input. 5 LE Latch Enable input (Note 2). 7 PUP1 Power-up selection bit. 8 PUP2 Power-up selection bit. 13 P/S Parallel/Serial mode select. 15 C8 Attenuation control bit, 8 dB. 16 C4 Attenuation control bit, 4 dB. 17 C2 Attenuation control bit, 2 dB. 19 C1 Attenuation control bit, 1 dB. 20 N/C No connect. Can be connected to any bias. Table 3. Absolute Maximum Ratings Table 4. Operating Ranges mum for extended periods may reduce reliability.

attenuation state, as shown in Table 5. Characteristics), and switching speed (Table 1). of the device (using hardwire, switches, or jumpers). Table 5. Truth Table is independent of the state of the LE input. brought LOW, data in the shift register is latched. Table 8 (Serial Interface AC Characteristics). Table 6. Power-Up Truth Table, Parallel C1-C16, and PUP1 and PUP2 are not active.

Figure 19. Package Drawing

0.10 C A B

0.20 REF

  1. Dimension applies to metallized terminal and is measured

between 0.25 and 0.30 from terminal tip.

  1. Coplanarity applies to the exposed heat sink slug as well as
  2. Dimensions are in millimeters.

Peregrine Semiconductor Corporation

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