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Technical content

Features

 Single-pin or complementary CMOS logic control inputs  Low insertion loss:  0.35 dB @ 1000 MHz  0.5 dB @ 2000 MHz  Isolation of 30 dB @ 1000 MHz  High ESD tolerance of 2 kV HBM  Typical input 1 dB compression point of +33.5 dBm  1.8V minimum power supply voltage  Ultra-small SC-70 package Figure 2. Package Type SC-70

Notes: 1. Device linearity will begin to degrade below 10 MHz.

  1. The DC transient at the output of any port of the switch w hen the control voltage is switched from Low to High or High to Low in a 50 Ω test

set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.

  1. A tuning capacitor must be added to the application board to optimize the insertion loss and return loss performance. See Figure 6 for

Table 1. Electrical Specifications @ +25°C, VDD = 3V (ZS = ZL = 50 Ω )

2000 MHz

Table 2. Pin Descriptions devices are immune to latch-up. Figure 3. Pin Configuration (Top View)

1 RF1 1 RF Port1

2 GND

3 RF2 1 RF Port2

4 CTRL Switch control input, CMOS logic level.

5 RFC 1 RF Common

6 CTRL or

supply connection is required. on this pin is not required in this mode. Table 4. Absolute Maximum Ratings Table 3. Operating Ranges Figure 4. Maximum Input Power maximum for extended periods may reduce reliability. The PE4259 has a maximum 25 kHz switching rate. desired operating frequency (see Figure 4).

Table 5. Single-pin Control Logic Truth Table Table 6. Complementary-pin Control Logic

transmission line via the top SMA connector, J1. Figure 5. Evaluation Board Layouts

have exactly the same electrical length.

1 K Ohm

5 RFC

6 VDD

Figure 6. Evaluation Board Schematic SOLDER C1 SI DE 1 TO THE RF TRACE CLOSE TO THE J1 PI N. SOLDER C1 SI DE 2 TO C2 SI DE 1. SOLDER C2 SI DE 2 TO GROUND.

  1. ADD TWO 0.5PF CAPS IN SERIES TO BE SHUNTED ON THE J1 SMA INPUT.

Figure 15. Package Drawing Hana - AYT (Thailand) NOTE: 1. ALL DIMENSIONS ARE IN MILLIMETERS.

  1. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND GATE BURR.
  2. ALL SPECIFICATIONS COMPLY TO JEDEC SPEC MO-203 ISSUE A.
  3. DIE IS FACING UP FOR MOLD AND FACING DOWN FOR TRIM/FORM
  4. PACKAGE SUFACE MATTE FINISH VDI 11~13.
  5. THE FOOT LENGTH MEASURING BASED ON GAUGE PLANE METHOD.

Figure 16. Package Drawing Hana - JX (China) Figure 17. Differences Between Hana-AYT and Hana-JX Parts

0.0512 BSC

DIMENSION ARE NOT NECESSARILY EXACTY.

  1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M-1994.
  2. DIMENSION “D” DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR

EXCEED 0.15MM(0.006”) PER END.

  1. THE PACKAGE TOP BE SMALLE R THAN THE PACKAGE BOTTOM.

Table 7. Ordering Information Figure 18. Tape and Reel Specifications Notes: 1. Hana AYT (Thailand) assembly house. Please contact factory for assembly house details.

  1. Hana JX (China) assembly house. Please contact factory for assembly house details.

specifications for product development. Specifications and features may change in any manner without notice. of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. are trademarks of Peregrine Semiconductor Corp. For Sales and contact information please visit www.psemi.com.