41LV16100B ISSI | Alldatasheet

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/14/05 IS41LV16100B ISSI Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

  • TTL compatible inputs and outputs; tristate I/O
  • Refresh Interval: — Auto refresh Mode: 1,024 cycles /16 ms — RAS-Only, CAS-before-RAS (CBR), and Hidden
  • JEDEC standard pinout
  • Single power supply: 3.3V ± 10%
  • Byte Write and Byte Read operation via two CAS
  • Industrial Temperature Range: -40oC to +85oC
  • Lead-free available

DESCRIPTION

The ISSI IS41LV16100B is 1,048,576 x 16-bit high-perfor- mance CMOS Dynamic Random Access Memories. These devices offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 1,024 random ac- cesses within a single row with access cycle time as short as 20 ns per 16-bit word. These features make the IS41LV16100B ideally suited for high-bandwidth graphics, digital signal processing, high- performance computing systems, and peripheral applications. The IS41LV16100B is packaged in a 42-pin 400-mil SOJ and 400-mil 50- (44-) pin TSOP (Type II). 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE KEY TIMING PARAMETERS Parameter -50 -60 Unit Max. RAS Access Time (tRAC) ns Max. CAS Access Time (tCAC) ns Max. Column Address Access Time (tAA) ns Min. EDO Page Mode Cycle Time (tPC) ns Min. Read/Write Cycle Time (tRC) 110 ns PIN CONFIGURATIONS 50(44)-Pin TSOP (Type II) 42-Pin SOJ VDD I/O0 I/O1 I/O2 I/O3 VDD I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC NC VDD GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE GND PIN DESCRIPTIONS A0-A9 Address Inputs I/O0-15 Data Inputs/Outputs WE Write Enable OE Output Enable RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe VDD Power GND Ground NC No Connection APRIL 2005 VDD I/O0 I/O1 I/O2 I/O3 VDD I/O4 I/O5 I/O6 I/O7 NC NC NC WE RAS NC NC VDD GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC NC LCAS UCAS OE GND

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI FUNCTIONAL BLOCK DIAGRAM OE WE LCAS UCAS CAS WE OE DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS MEMORY ARRAY 1,048,576 x 16 ROW DECODER DATA I/O BUFFERS CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC I/O0-I/O15 RAS RAS A0-A9 RAS CLOCK GENERATOR REFRESH COUNTER ADDRESS BUFFERS

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI TRUTH TABLE Function RAS RAS RAS RAS RAS LCAS LCAS LCAS LCAS LCAS UCAS UCAS UCAS UCAS UCAS W E W E W E W E W E OE OE OE OE OE Address tR/tC I/O Standby H H H X X X High-Z Read: Word L L L H L ROW/COL DOUT Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT Upper Byte, High-Z Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z Upper Byte, DOUT Write: Word (Early Write) L L L L X ROW/COL DIN Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN Upper Byte, High-Z Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z Upper Byte, DIN Read-Write(1,2) L L L H→L L→H ROW/COL DOUT, DIN EDO Page-Mode Read(2) 1st Cycle: L H→L H→L H L ROW/COL DOUT 2nd Cycle: L H→L H→L H L NA/COL DOUT Any Cycle: L L→H L→H H L NA/NA DOUT EDO Page-Mode Write(1) 1st Cycle: L H→L H→L L X ROW/COL DIN 2nd Cycle: L H→L H→L L X NA/COL DIN EDO Page-Mode(1,2) 1st Cycle: L H→L H→L H→L L→H ROW/COL DOUT, DIN Read-Write 2nd Cycle: L H→L H→L H→L L→H NA/COL DOUT, DIN Hidden Refresh Read(2) L→H→L L L H L ROW/COL DOUT Write(1,3) L→H→L L L L X ROW/COL DOUT RAS-Only Refresh L H H X X ROW/NA High-Z CBR Refresh(4) H→L L L X X X High-Z Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active (LCAS or UCAS).

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI Functional Description The IS41LV16100B is a CMOS DRAM optimized for high- speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 16 address bits. These are entered ten bits (A0-A9) at time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used to latch the latter nine bits. The IS41LV16100B has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an identical manner to the single CAS input on the other 1M x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 through I/O7 and UCAS controls I/O8 through I/O15. The IS41LV16100B CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41LV16100B both BYTE READ and BYTE WRITE cycle capabilities. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs first. Auto Refresh Cycle To retain data, 1,024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory. 1. By clocking each of the 1,024 row addresses (A0 through A9) with RAS at least once every 128 ms. Any read, write, read- modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-before- RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row ad- dresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Extended Data Out Page Mode EDO page mode operation permits all 1,024 columns within a selected row to be randomly accessed at a high data rate. In EDO page mode read cycle, the data-out is held to the next CAS cycle’s falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. There- fore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter. In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. The EDO page mode allows both read and write opera- tions during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case. Power-On After application of the VDD supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles contain- ing a RAS signal). During power-on, it is recommended that RAS track with VDD or be held at a valid VIH to avoid current surges.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters Rating Unit VT Voltage on Any Pin Relative to GND 3.3V –0.5 to +4.6 V VDD Supply Voltage 3.3V –0.5 to +4.6 V IOUT Output Current mA PD Power Dissipation W TA Commercial Operation Temperature 0 to +70 Industrial Operation Temperature -40 to +85 TSTG Storage Temperature –55 to +125 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol Parameter Min. Typ. Max. Unit VDD Supply Voltage 3.3V 3.0 3.3 3.6 V VIH Input High Voltage 3.3V 2.0 VDD + 0.3 V VIL Input Low Voltage 3.3V –0.3 0.8 V TA Commercial Ambient Temperature Industrial Ambient Temperature –40 CAPACITANCE(1,2) Symbol Parameter Max. Unit CIN1 Input Capacitance: A0-A9 pF CIN2 Input Capacitance: RAS, UCAS, LCAS, WE, OE pF CIO Data Input/Output Capacitance: I/O0-I/O15 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI ELECTRICAL CHARACTERISTICS(1) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter Test Condition Speed Min. Max. Unit IIL Input Leakage Current Any input 0V ≤ VIN ≤ VDD –10 µA Other inputs not under test = 0V IIO Output Leakage Current Output is disabled (Hi-Z) –10 µA 0V ≤ VOUT ≤ VDD VOH Output High Voltage Level IOH = –2.0 mA (3.3V) 2.4 V VOL Output Low Voltage Level IOL = 2.0 mA (3.3V) 0.4 V ICC1 Standby Current: TTL RAS, LCAS, UCAS ≥ VIH Commercial 3.3V mA Industrial 3.3V mA ICC2 Standby Current: CMOS RAS, LCAS, UCAS ≥ VDD – 0.2V 3.3V mA ICC3 Operating Current: RAS, LCAS, UCAS, -50 180 mA Random Read/Write(2,3,4) Address Cycling, tRC = tRC (min.) -60 170 Average Power Supply Current ICC4 Operating Current: RAS = VIL, LCAS, UCAS, -50 180 mA EDO Page Mode(2,3,4) Cycling tPC = tPC (min.) -60 170 Average Power Supply Current ICC5 Refresh Current: RAS Cycling, LCAS, UCAS ≥ VIH -50 180 mA RAS-Only(2,3) tRC = tRC (min.) -60 170 Average Power Supply Current ICC6 Refresh Current: RAS, LCAS, UCAS Cycling -50 180 mA CBR(2,3,5) tRC = tRC (min.) -60 170 Average Power Supply Current Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each EDO page cycle. 5. Enables on-chip refresh and address counters.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -50 -60 Symbol Parameter Min. Max. Min. Max. Units tRC Random READ or WRITE Cycle Time 110 ns tRAC Access Time from RAS(6, 7) ns tCAC Access Time from CAS(6, 8, 15) ns tAA Access Time from Column-Address(6) ns tRAS RAS Pulse Width 10K 10K ns tRP RAS Precharge Time ns tCAS CAS Pulse Width(26) 10K 10K ns tCP CAS Precharge Time(9, 25) ns tCSH CAS Hold Time (21) ns tRCD RAS to CAS Delay Time(10, 20) ns tASR Row-Address Setup Time ns tRAH Row-Address Hold Time ns tASC Column-Address Setup Time(20) ns tCAH Column-Address Hold Time(20) ns tAR Column-Address Hold Time ns (referenced to RAS) tRAD RAS to Column-Address Delay Time(11) ns tRAL Column-Address to RAS Lead Time ns tRPC RAS to CAS Precharge Time ns tRSH RAS Hold Time(27) ns tCLZ CAS to Output in Low-Z(15, 29) ns tCRP CAS to RAS Precharge Time(21) ns tOD Output Disable Time(19, 28, 29) ns tOE/tOEA Output Enable Time(15, 16) ns tOEHC OE HIGH Hold Time from CAS HIGH ns tOEP OE HIGH Pulse Width ns tOES OE LOW to CAS HIGH Setup Time ns tRCS Read Command Setup Time(17, 20) ns tRRH Read Command Hold Time ns (referenced to RAS)(12) tRCH Read Command Hold Time ns (referenced to CAS)(12, 17, 21) tWCH Write Command Hold Time(17, 27) ns tWCR Write Command Hold Time ns (referenced to RAS)(17)

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -50 -60 Symbol Parameter Min. Max. Min. Max. Units tWP Write Command Pulse Width(17) ns tWPZ WE Pulse Widths to Disable Outputs ns tRWL Write Command to RAS Lead Time(17) ns tCWL Write Command to CAS Lead Time(17, 21) ns tWCS Write Command Setup Time(14, 17, 20) ns tDHR Data-in Hold Time (referenced to RAS) ns tOEH OE Hold Time from WE during ns READ-MODIFY-WRITE cycle(18) tDS Data-In Setup Time(15, 22) ns tDH Data-In Hold Time(15, 22) ns tRWC READ-MODIFY-WRITE Cycle Time 110 155 ns tRWD RAS to WE Delay Time during ns READ-MODIFY-WRITE Cycle(14) tCWD CAS to WE Delay Time(14, 20) ns tAWD Column-Address to WE Delay Time(14) ns tPC EDO Page Mode READ or WRITE ns Cycle Time(24) tRASP RAS Pulse Width in EDO Page Mode 100K 100K ns tCPA Access Time from CAS Precharge(15) ns tPRWC EDO Page Mode READ-WRITE ns Cycle Time(24) tCOH Data Output Hold after CAS LOW ns tOFF Output Buffer Turn-Off Delay from ns CAS or RAS(13,15,19, 29) tWHZ Output Disable Delay from WE ns tCLCH Last CAS going LOW to First CAS ns returning HIGH(23) tCSR CAS Setup Time (CBR REFRESH)(30, 20) ns tCHR CAS Hold Time (CBR REFRESH)(30, 21) ns tORD OE Setup Time prior to RAS during ns HIDDEN REFRESH Cycle tREF Auto Refresh Period (1,024 Cycles) ms tT Transition Time (Rise or Fall)(2, 3) ns

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD ≤ tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≤ tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≤ tRWD (MIN), tAWD ≤ tAWD (MIN) and tCWD ≤ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. The first χCAS edge to transition LOW. 21. The last χCAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ- MODIFY-WRITE cycles. 23. Last falling χCAS edge to first rising χCAS edge. 24. Last rising χCAS edge to next cycle’s last rising χCAS edge. 25. Last rising χCAS edge to first falling χCAS edge. 26. Each χCAS must meet minimum pulse width. 27. Last χCAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters. AC TEST CONDITIONS Output load: One TTL Load and 50 pF (VDD = 3.3V ±10%) Input timing reference levels: VIH = 2.0V, VIL = 0.8V (VDD = 3.3V ±10%) Output timing reference levels: VOH = 2.0V, VOL = 0.8V

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI READ CYCLE Note: 1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. tRAS tRC tRP tAR tCAH tASC tRAD tRAL OE I/O WE ADDRESS UCAS/LCAS RAS Row Column Row Open Open Valid Data tCSH tCAS tRSH tCRP tCLCH tRCD tRAH tASR tRRH tRCH tRCS tAA tCAC tOFF(1) tRAC tCLC tOES tOE tOD Don’t Care Undefined

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI EARLY WRITE CYCLE (OE = DON'T CARE) tRAS tRC tRP tAR tCAH tASC tRAD tRAL tACH I/O WE ADDRESS UCAS/LCAS RAS Row Column Row tCSH tCAS tRSH tCRP tCLCH tRCD tRAH tASR tCWL tWCR tWCH tRWL tWP tWCS tDH tDS tDHR Valid Data Don’t Care

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRAS tRWC tRP tAR tCAH tASC tRAD tRAL tACH WE OE ADDRESS UCAS/LCAS RAS Row Column Row tCSH tCAS tRSH tCRP tCLCH tRCD tRAH tASR tRWD tCWL tCWD tRWL tAWD tWP tRCS tCAC tCLZ tDS tDH tOEH tOD tOE tRAC tAA I/O Open Open Valid DOUT Valid DIN Don’t Care Undefined

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI EDO-PAGE-MODE READ CYCLE Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications. tRASP tRP ADDRESS UCAS/LCAS RAS Row Row tCAS, tCLCH tCRP tRCD tCSH tCP tCAS, tCLCH tCAH tCAS, tCLCH tRAL tRSH tCP tCP tPC(1) tASR tRAH tRAD tAR Column Column tCAH tCAH Column tASC tASC OE I/O WE Open Open Valid Data tAA tAA tCPA tCAC tCAC tRAC tCOH tCLZ tOEP tOE tOES tOES tOD tOE tOEHC Valid Data tRCH tRRH tAA tCPA tCAC tOFF tCLZ Valid Data tOD tASC tRCS Don’t Care Undefined

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI EDO-PAGE-MODE EARLY-WRITE CYCLE tRASP tRP ADDRESS UCAS/LCAS RAS Row Row tCAS, tCLCH tCRP tRCD tCSH tCP tCAS, tCLCH tCAH tCAS, tCLCH tRAL tRSH tCP tCP tPC tASR tRAH tRAD tAR tACH Column Column tACH tACH tCAH tCAH Column tASC tASC OE I/O WE Valid Data tASC tWCS tWCH tCWL tWP tRHCP tWCS tWCH tCWL tWP tDS tDH tDHR tWCR tWCS tWCH tCWL tWP Valid Data tDS tDH Valid Data tDS tRWL tDH Don’t Care

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles) Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications. Don’t Care Undefined tRASP tRP ADDRESS UCAS/LCAS RAS Row Row tCRP tRCD tCSH tCP tCAH tCAS, tCLCH tRAL tRSH tCP tCP tRAH tRAD tAR tASR Column Column tCAH tCAH Column tASC tASC tCAS, tCLCH tCAS, tCLCH OE I/O WE tASC tRWD tRCS tCWL tWP tAWD tCWD tDH tDS tCAC tCLZ tAWD tCWD tCWL tWP tAWD tCWD tCWL tRWL tWP Open Open DIN DOUT tOE tOE tOE tOD tOEH tOD tOD tDH tDS tCPA tAA tCAC tCLZ DIN DOUT tDH tDS tCAC tCLZ DIN DOUT tCPA tAA tRAC tAA tPC / tPRWC(1)

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY WRITE) tRASP tRP ADDRESS UCAS/LCAS RAS Row Row tCRP tRCD tPC tCSH tCP tCAH tCAS tRAL tRSH tCP tCP tACH tRAH tRAD tAR tASR Column (A) Column (N) tCAH tCAH Column (B) tASC tASC tCAS tCAS OE I/O WE tASC tCAC tRCH tDH Open Open Valid Data (A) tOE tWCS tCAC tCOH DIN tCPA tWCH tRAC tAA tPC Valid Data (B) tWHZ tDS tRCS tAA Don’t Care

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS RAS RAS RAS RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tAR tCAH tASC tASC tRAD OE I/O WE ADDRESS UCAS/LCAS RAS Row Column Open Open Valid Data tCSH tCAS tCRP tRCD tCP tRAH tASR tRCH tRCS tRCS tAA tCAC tWHZ tRAC tCLZ tCLZ tOE tOD Column tRAS tRC tRP I/O ADDRESS UCAS/LCAS RAS Row Row Open tCRP tRAH tASR tRPC Don’t Care Undefined Don’t Care

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) CBR CBR CBR CBR CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. tRAS tRAS tRP tRP I/O UCAS/LCAS RAS Open tCP tRPC tCSR tCHR tRPC tCSR tCHR tRAS tRAS tRP UCAS/LCAS RAS tCRP tRCD tRSH tCHR tAR tASC tRAD ADDRESS Row Column tRAH tASR tRAL tCAH I/O Open Open Valid Data tAA tCAC tRAC tCLZ tOFF(2) OE tOE tORD tOD Don’t Care Undefined

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 04/13/05 ISSI ORDERING INFORMATION : 3.3V Commercial Range: 0°°°°°C to +70°°°°°C Speed (ns) Order Part No. Package IS41LV16100B-50K 400-mil SOJ IS41LV16100B-50KL 400-mil SOJ, Lead-free IS41LV16100B-50T 400-mil TSOP (Type II) IS41LV16100B-50TL 400-mil TSOP (Type II), Lead-free IS41LV16100B-60K 400-mil SOJ IS41LV16100B-60KL 400-mil SOJ, Lead-free IS41LV16100B-60T 400-mil TSOP (Type II) IS41LV16100B-60TL 400-mil TSOP (Type II), Lead-free Industrial Range: -40°°°°°C to +85°°°°°C Speed (ns) Order Part No. Package IS41LV16100B-50KI 400-mil SOJ IS41LV16100B-50KLI 400-mil SOJ, Lead-free IS41LV16100B-50TI 400-mil TSOP (Type II) IS41LV16100B-50TLI 400-mil TSOP (Type II), Lead-free IS41LV16100B-60KI 400-mil SOJ IS41LV16100B-60KLI 400-mil SOJ, Lead-free IS41LV16100B-60TI 400-mil TSOP (Type II) IS41LV16100B-60TLI 400-mil TSOP (Type II), Lead-free

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 10/29/03 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. 400-mil Plastic SOJ Package Code: K Notes: 1. Controlling dimension: millimeters. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Reference document: JEDEC MS-027. SEATING PLANE N D E B e A C b N/2+1 N/2 Millimeters Inches Millimeters Inches Millimeters Inches Symbol Min Max Min Max Min Max Min Max Min Max Min Max No. Leads (N) A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 — 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 — B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 D 18.29 18.54 0.720 0.730 20.82 21.08 0.820 0.830 23.37 23.62 0.920 0.930 E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 10/29/03 Millimeters Inches Millimeters Inches Millimeters Inches Symbol Min Max Min Max Min Max Min Max Min Max Min Max No. Leads (N) A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 — 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 — B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 D 25.91 26.16 1.020 1.030 27.18 27.43 1.070 1.080 28.45 28.70 1.120 1.130 E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC

Integrated Silicon Solution, Inc. PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II) Plastic TSOP (T - Type II) (MS 25) Millimeters Inches Symbol Min Max Min Max Ref. Std. N A 1.20 0.0472 0.05 0.15 0.002 0.0059 b 0.30 0.51 0.012 0.0201 c 0.12 0.21 0.005 0.0083 D 17.01 17.27 0.670 0.6899 7.49 7.75 0.295 0.3051 e

1.27 BSC

0.050 BSC

E 9.02 9.42 0.462 0.4701 L 0.40 0.60 0.016 0.0236 α PK13197T40 Rev. C 08/013/99 Plastic TSOP (T - Type II) (MS 24) Millimeters Inches Symbol Min Max Min Max Ref. Std. N A 1.20 0.0472 0.05 0.15 0.002 0.0059 b 0.30 0.45 0.012 0.0157 c 0.12 0.21 0.005 0.0083 D 18.31 18.51 0.721 0.7287 10.06 10.26 0.396 0.4040 e

0.80 BSC

0.031 BSC

E 11.56 11.96 0.455 0.4709 L 0.40 0.60 0.016 0.0236 α Plastic TSOP (T - Type II) (MS 24) Millimeters Inches Symbol Min Max Min Max Ref. Std. N A 1.20 0.0472 0.05 0.15 0.002 0.0059 b 0.30 0.45 0.012 0.0157 c 0.12 0.21 0.005 0.0083 D 20.85 21.05 0.821 0.8287 10.06 10.26 0.396 0.4040 e E 11.56 11.96 0.455 0.4709 L 0.40 0.60 0.016 0.0236 α ISSI Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protru- sions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. D SEATING PLANE b e c N/2 N/2+1 N A E L α