41C16257

41C16257 ISSI | Alldatasheet

Document overview

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Technical content

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.

FEATURES

• Fast access and cycle time
• TTL compatible inputs and outputs
• Refresh Interval: 512 cycles/8 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply: -- 5V – 10% (IS41C16257)
• Byte Write and Byte Read operation via two CAS
• Industrial temperature available

DESCRIPTION

The ISSI IS41C16257 and the IS41LV16257 are 262,144 x 16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 512 random accesses within a single row with access cycle time as short as 12 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes these devices ideal for use in 16- and 32-bit wide data bus systems. These features make the IS41C16257 and the IS41LV16257 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C16257 and the IS41LV16257 are packaged in a 40-pin, 400-mil SOJ and TSOP (Type II). IS41C16257 IS41LV16257 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE MAY 1999 Integrated Silicon Solution, Inc. — 1-800-379-4774 1 DR004-1B 05/24/99 KEY TIMING PARAMETERS Parameter -35 -60 Unit Max. RAS Access Time (tRAC )3 5 6 0 n s Max. CAS Access Time (tCAC )1 0 1 5 n s Max. Column Address Access Time (tAA )1 8 3 0 n s Min. Fast Page Mode Cycle Time (tPC )1 2 2 5 n s Min. Read/Write Cycle Time (tRC ) 60 110 ns ISSI

2 Integrated Silicon Solution, Inc. — 1-800-379-4774 DR004-1B 05/24/99 ISSI FUNCTIONAL BLOCK DIAGRAM OE WE LCAS UCAS CAS WE OE DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS MEMORY ARRAY 262,144 x 16 ROW DECODER DATA I/O BUFFERS CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC I/O0-I/O15 RAS RAS A0-A8 RAS CLOCK GENERATOR REFRESH COUNTER ADDRESS BUFFERS VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC VCC GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE GND VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC VCC GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE GND PIN DESCRIPTIONS A0-A8 Address Inputs I/O0-I/O15 Data Inputs/Outputs WE Write Enable OE Output Enable RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe Vcc Power GND Ground NC No Connection 40-Pin SOJ PIN CONFIGURATIONS 40-Pin TSOP (Type II)

Integrated Silicon Solution, Inc. — 1-800-379-4774 3 DR004-1B 05/24/99 ISSI TRUTH TABLE Function RASRASRASRASRAS LCASLCASLCASLCASLCAS UCASUCASUCASUCASUCAS WEWEWEWEWE OEOEOEOEOE Address tR /tC I/O Standby H H H X X X High-Z Read: Word L L L H L ROW/COL D OUT Read: Lower Byte L L H H L ROW/COL Lower Byte, D OUT Upper Byte, High-Z Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z Upper Byte, DOUT Write: Word (Early Write) L L L L X ROW/COL D IN Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, D IN Upper Byte, High-Z Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z Upper Byte, DIN Read-Write(1,2) LL L H fi LL fi H ROW/COL D OUT , DIN Hidden Refresh2) Read Lfi H fi L L L H L ROW/COL D OUT Write Lfi H fi L LLLX R O W / C O L D OUT RAS-Only Refresh L H H X X ROW/NA High-Z CBR Refresh(3) H fi L L L X X X High-Z Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. At least one of the two CAS signals must be active (LCAS or UCAS).

4 Integrated Silicon Solution, Inc. — 1-800-379-4774 DR004-1B 05/24/99 ISSI FUNCTIONAL DESCRIPTION The IS41C16257 and the IS41LV16257 are CMOS DRAMs optimized for high-speed bandwidth, low-power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 18 address bits. These are entered nine bits (A0-A8) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used to latch the latter nine bits. The IS41C16257 and the IS41LV16257 has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generate a CAS signal functioning in an identical manner to the single CAS input on the other 256K x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 - I/O7 and UCAS controls I/O8 - I/O15. The IS41C16257 and the IS41LV16257 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41C16257 both BYTE READ and BYTE WRITE cycle capabilities. Memory Cycle A memory cycle is initiated by bringing RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensure proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum t RAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP , tCP has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR . Data Out becomes valid only when tRAC , tAA , tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. Refresh Cycle To retain data, 512 refresh cycles are required in each 8 ms period. There are two ways to refresh the memory: 1. By clocking each of the 512 row addresses (A0 through A8) with RAS at least once every 8 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the ad- dressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-before- RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Power-On After application of the VCC supply, an initial pause of 200 ms is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges.

Integrated Silicon Solution, Inc. — 1-800-379-4774 5 DR004-1B 05/24/99 ISSI ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameters Rating Unit VT Voltage on Any Pin Relative to GND 5V –1.0 to +7.0 V 3.3V –0.5 t0 +4.6 VCC Supply Voltage 5V –1.0 to +7.0 V 3.3V –0.5 t0 +4.6 IOUT Output Current 50 mA PD Power Dissipation 1 W TA Operation Temperature Com. 0 to 70 °C Ind. –40 to +85 TSTG Storage Temperature –55 to +125 °C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND) Symbol Parameter Voltage Min. Typ. Max. Unit VCC Supply Voltage 5V 4.5 5.0 5.5 V VCC Supply Voltage 3.3V 3.0 3.3 3.6 V VIH Input High Voltage 5V 2.4 — V CC + 1.0 V VIH Input High Voltage 3.3V 2.0 — V CC + 0.3 V VIL Input Low Voltage 5V –1.0 — 0.8 V VIL Input Low Voltage 3.3 –0.3 — 0.8 V TA Ambient Temperature Com. 0 — 70 °C Ind. –40 — 85 CAPACITANCE (1,2) Symbol Parameter Max. Unit C IN1 Input Capacitance: A0-A8 5 pF C IN2 Input Capacitance: RAS, UCAS, LCAS, WE, OE 7p F C IO Data Input/Output Capacitance: I/O0-I/O15 7 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V + 10% or Vcc=3.3V – 10%.

6 Integrated Silicon Solution, Inc. — 1-800-379-4774 DR004-1B 05/24/99 ISSI ELECTRICAL CHARACTERISTICS (1) (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter Test Condition Speed Min. Max. Unit IIL Input Leakage Current Any input 0V < VIN < Vcc –10 10 mA Other inputs not under test = 0V IIO Output Leakage Current Output is disabled (Hi-Z) –10 10 mA 0V < VOUT < Vcc VOH Output High Voltage Level IOH = –2.5 mA 2.4 — V VOL Output Low Voltage Level I OL = 2.1 mA — 0.4 V ICC 1 Stand-by Current: TTL RAS, LCAS, UCAS ‡ VIH Com. 5V — 2 mA Ind. 5V 3 ICC 1 Stand-by Current: TTL RAS, LCAS, UCAS ‡ VIH Com. 3.3V — 1 mA Ind. 3.3V 2 ICC 2 Stand-by Current: CMOS RAS, LCAS, UCAS ‡ VCC – 0.2V 5V — 2 mA ICC 2 Stand-by Current: CMOS RAS, LCAS, UCAS ‡ VCC – 0.2V 3.3V — 1 mA ICC 3 Operating Current: RAS, LCAS, UCAS, -35 — 230 mA Random Read/Write(2,3,4) Address Cycling, tRC = tRC (min.) -60 — 170 Average Power Supply Current ICC 4 Operating Current: RAS = VIL, LCAS, UCAS, -35 — 220 mA Fast Page Mode(2,3,4) Cycling tPC = tPC (min.) -60 — 160 Average Power Supply Current ICC 5 Refresh Current: RAS Cycling, LCAS, UCAS ‡ VIH -35 — 230 mA RAS-Only(2,3) tRC = tRC (min.) -60 — 170 Average Power Supply Current ICC 6 Refresh Current: RAS, LCAS, UCAS Cycling -35 — 230 mA CBR (2,3,5) tRC = tRC (min.) -60 — 170 Average Power Supply Current Notes: 1. An initial pause of 200 ms is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured.The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each fast page cycle. 5. Enables on-chip refresh and address counters.

Integrated Silicon Solution, Inc. — 1-800-379-4774 7 DR004-1B 05/24/99 ISSI AC CHARACTERISTICS (1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -35 -60 Symbol Parameter Min. Max. Min. Max. Units tRC Random READ or WRITE Cycle Time 60 — 110 — ns tRAC Access Time from RAS(6, 7) —3 5 —6 0 n s tCAC Access Time from CAS(6, 8, 15) —1 0 —1 5 n s tAA Access Time from Column-Address(6) —1 8 —3 0 n s tRAS RAS Pulse Width 35 10K 60 10K ns tRP RAS Precharge Time 20 — 40 — ns tCAS CAS Pulse Width(26) 6 10K 10 10K ns tCP CAS Precharge Time(9, 25) 5— 1 0 — n s tCSH CAS Hold Time (21) 35 — 60 — ns tRCD RAS to CAS Delay Time(10, 20) 11 28 20 45 ns tASR Row-Address Setup Time 0 — — 0 — ns tRAH Row-Address Hold Time 6 — 10 — ns tASC Column-Address Setup Time(20) 0— 0— n s tCAH Column-Address Hold Time(20) 6— 1 0 — n s tAR Column-Address Hold Time 30 — 40 — ns (referenced to RAS) tRAD RAS to Column-Address Delay Time(11) 12 20 15 30 ns tRAL Column-Address to RAS Lead Time 18 — 30 — ns tRPC RAS to CAS Precharge Time 0 — 0 — ns tRSH RAS Hold Time(27) 8— 1 5 — n s tCLZ CAS to Output in Low-Z(15, 29) 3— 3— n s tCRP CAS to RAS Precharge Time(21) 5— 5— n s tOD Output Disable Time(19, 28, 29) 31 5 31 5 n s tOE Output Enable Time(15, 16) —1 0 —1 5 n s tOEHC OE HIGH Hold Time from CAS HIGH 10 — 10 — ns tOEP OE HIGH Pulse Width 10 — 10 — ns tOES OE LOW to CAS HIGH Setup Time 5 — 5 — ns tRCS Read Command Setup Time(17, 20) 0— 0— n s tRRH Read Command Hold Time 0 — 0 — ns (referenced to RAS)(12) tRCH Read Command Hold Time 0 — 0 — ns (referenced to CAS)(12, 17, 21) tWCH Write Command Hold Time(17, 27) 5— 1 0 — n s tWCR Write Command Hold Time 30 — 50 — ns (referenced to RAS)(17) tWP Write Command Pulse Width(17) 5— 1 0 — n s tWPZ WE Pulse Widths to Disable Outputs 10 — 10 — ns tRWL Write Command to RAS Lead Time(17) 8— 1 5 — n s tCWL Write Command to CAS Lead Time(17, 21) 8— 1 5 — n s tWCS Write Command Setup Time(14, 17, 20) 0— 0— n s tDHR Data-in Hold Time (referenced to RAS)3 0 — 4 0 — n s (Continued)

8 Integrated Silicon Solution, Inc. — 1-800-379-4774 DR004-1B 05/24/99 ISSI AC CHARACTERISTICS (1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -35 -60 Symbol Parameter Min. Max. Min. Max. Units tACH Column-Address Setup Time to CAS 15 — 15 — ns Precharge during WRITE Cycle tOEH OE Hold Time from WE during 8 — 15 — ns READ-MODIFY-WRITE cycle (18) tDS Data-In Setup Time(15, 22) 0— 0— n s tDH Data-In Hold Time(15, 22) 6— 1 0 — n s tRWC READ-MODIFY-WRITE Cycle Time 80 — 140 — ns tRWD RAS to WE Delay Time during 45 — 80 — ns READ-MODIFY-WRITE Cycle (14) tCWD CAS to WE Delay Time(14, 20) 25 — 36 — ns tAWD Column-Address to WE Delay Time(14) 30 — 49 — ns tPC Fast Page Mode READ or WRITE 12 — 25 — ns Cycle Time(24) tRASP RAS Pulse Width 35 100K 60 100K ns tCPA Access Time from CAS Precharge(15) —2 1 —3 4 n s tPRWC READ-WRITE Cycle Time(24) 40 — 56 — ns tOFF Output Buffer Turn-Off Delay from 3 15 3 15 ns CAS or RAS(13,15,19, 29) tWHZ Output Disable Delay from WE 31 5 31 5 n s tCLCH Last CAS going LOW to First CAS 10 — 10 — ns returning HIGH(23) tCSR CAS Setup Time (CBR REFRESH)(30, 20) 8— 1 0 — n s tCHR CAS Hold Time (CBR REFRESH)(30, 21) 8— 1 0 — n s tORD OE Setup Time prior to RAS during 0 — 0 — ns HIDDEN REFRESH Cycle tREF Refresh Period (512 Cycles) — 8 — 8 ms tT Transition Time (Rise or Fall)(2, 3) 15 0 15 0 n s

Integrated Silicon Solution, Inc. — 1-800-379-4774 9 DR004-1B 05/24/99 ISSI Notes: 1. An initial pause of 200 ms is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD £ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD ‡ tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP . 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC . 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA . 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL . 14. tWCS , tRWD , tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ‡ tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ‡ tRWD (MIN), tAWD ‡ tAWD (MIN) and tCWD ‡ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. The first cCAS edge to transition LOW. 21. The last cCAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ- MODIFY-WRITE cycles. 23. Last falling cCAS edge to first rising cCAS edge. 24. Last rising cCAS edge to next cycle’s last rising cCAS edge. 25. Last rising cCAS edge to first falling cCAS edge. 26. Each cCAS must meet minimum pulse width. 27. Last cCAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters.

10 Integrated Silicon Solution, Inc. — 1-800-379-4774 DR004-1B 05/24/99 ISSI FAST-PAGE-MODE READ CYCLE Note: 1. tOFF is referenced from rising edge of CAS. tRAS tRC tRP tAR tCAHtASC tRAD tRAL OE I/O WE ADDRESS UCAS/LCAS RAS Row Column Row Open Open Valid Data tCSH tCAS tRSH tCRP tCLCHtRCD tRAHtASR tRRH tRCHtRCS tAA tCAC tOFF (1) tRAC tCLC tOES tOE tOD Don't Care

Integrated Silicon Solution, Inc. — 1-800-379-4774 11 DR004-1B 05/24/99 ISSI FAST PAGE MODE READ-MODIFY-WRITE CYCLE Don't Care OUT tAR tRWD tAWD I/O0-I/O15 WE OE ADDRESS UCAS/LCAS RAS Row Column Column Column tAR tCSH tCAS tCAS tCAS tRASP tRSHtPRWC tRCD tCWD tCWD tCWD tCRP tASR tRAD tRCS tASC tASC tASC tRAL tCAH tCP tCP tRP tCAH tAWD tAWD tCAC tAA tDH tCLZ tRAC tDH tDH tOEA tCLZ tCAC tOEA tCAC tOEA OUTOUT IN IN IN tOEZ tOEZ tOED tOED tDS tOEZ tOED tDStCLZ tAAtAA tWP tRAH tWP tWP tCWL tCWL tCWL tRWL tCPWD tCPWD tCAH tCRP tDS

12 Integrated Silicon Solution, Inc. — 1-800-379-4774 DR004-1B 05/24/99 ISSI FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE) tRAS tRC tRP tAR tCAHtASC tRAD tRAL tACH I/O WE ADDRESS UCAS/LCAS RAS Row Column Row tCSH tCAS tRSH tCRP tCLCHtRCD tRAHtASR tCWL tWCR tWCH tRWL tWP tWCS tDHtDS tDHR Valid Data Don't Care

Integrated Silicon Solution, Inc. — 1-800-379-4774 13 DR004-1B 05/24/99 ISSI FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRAS tRWC tRP tAR tCAHtASC tRAD tRAL tACH WE OE ADDRESS UCAS/LCAS RAS Row Column Row tCSH tCAS tRSH tCRP tCLCHtRCD tRAHtASR tRWD tCWL tCWD tRWL tAWD tWP tRCS tCAC tCLZ tDS tDH tOEHtODtOE tRAC tAA I/O Open Open Valid DOUT Valid DIN Don't Care

14 Integrated Silicon Solution, Inc. — 1-800-379-4774 DR004-1B 05/24/99 ISSI FAST PAGE MODE EARLY WRITE CYCLE Don't Care tAR I/O0-I/O15 WE OE ADDRESS UCAS/LCAS RAS Row Column Column Column tAR tCWL tWCR tDHR tCSH tCAS tCAS tCAS tRASP tRSH tRHCP tPC tRCDtCRP tASR tWCS tDS tRAD tASC tASC tASC tRAL tCAH tWCH tDH tDS tDStDH tDH tCP tCP tRP tCAH tRAH tCAH tCRP tCWL tWCS tWCStWCH tWP tWP tCWL tWCH tWP Valid DIN Valid DINValid DIN

Integrated Silicon Solution, Inc. — 1-800-379-4774 15 DR004-1B 05/24/99 ISSI AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RASRASRASRASRAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tAR tCAH tASCtASC tRAD OE I/O WE ADDRESS UCAS/LCAS RAS Row Column Open Open Valid Data tCSH tCAStCRP tRCD tCP tRAHtASR tRCH tRCStRCS tAA tCAC tWHZ tRAC tCLZtCLZ tOE tOD Column tRAS tRC tRP I/O ADDRESS UCAS/LCAS RAS Row Row Open tCRP tRAHtASR tRPC Don't Care Don't Care

16 Integrated Silicon Solution, Inc. — 1-800-379-4774 DR004-1B 05/24/99 ISSI HIDDEN REFRESH CYCLE (1) (WE = HIGH; OE = LOW) CBRCBRCBRCBRCBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. tRAS tRAStRP tRP I/O UCAS/LCAS RAS Open tCP tRPC tCSR tCHR tRPC tCSR tCHR tRAS tRAStRP UCAS/LCAS RAS tCRP tRCD tRSH tCHR tAR tASC tRAD ADDRESS Row Column tRAHtASR tRAL tCAH I/O Open Open Valid Data tAA tCAC tRAC tCLZ tOFF (2) OE tOE tORD tOD Don't Care

Integrated Silicon Solution, Inc. — 1-800-379-4774 17 DR004-1B 05/24/99 ISSI

ORDERING INFORMATION

Commercial Range: 0°C to 70°C Speed (ns) Order Part No. Package

35 IS41C16257-35K 400-mil SOJ

IS41C16257-35T 400-mil TSOP (Type II)

60 IS41C16257-60K 400-mil SOJ

IS41C16257-60T 400-mil TSOP (Type II) Industrial Range: –40°C to 85°C Speed (ns) Order Part No. Package

35 IS41C16257-35KI 400-mil SOJ

IS41C16257-35TI 400-mil TSOP (Type II)

60 IS41C16257-60KI 400-mil SOJ

IS41C16257-60TI 400-mil TSOP (Type II) ISSI Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com Commercial Range: 0°C to 70°C Speed (ns) Order Part No. Package

35 IS41LV16257-35K 400-mil SOJ

IS41LV16257-35T 400-mil TSOP (Type II)

60 IS41LV16257-60K 400-mil SOJ

IS41LV16257-60T 400-mil TSOP (Type II) Industrial Range: –40°C to 85°C Speed (ns) Order Part No. Package

35 IS41LV16257-35KI 400-mil SOJ

IS41LV16257-35TI 400-mil TSOP (Type II)

60 IS41LV16257-60KI 400-mil SOJ

IS41LV16257-60TI 400-mil TSOP (Type II)