PE3342 PEREGRINE | Alldatasheet
Document overview
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Technical content
Features
- Field-programmable EEPROM for self- starting applications
- Standard 2700 MHz operation,
3000 MHz speed-grade option
- ÷10/11 dual modulus prescaler
- Internal phase detector
- Serial programmable
- Low power — 20 mA at 3 V
- Ultra-low phase noise
- Available in 24-lead TSSOP or 20-lead 4x4 mm QFN package Enhancement Register (8-bit) Fin Fin Prescaler ÷10/11 M Counter ÷2 to ÷512 Serial Interface Mux R Counter ÷1 to ÷64 fr Phase Detector S_WR PD_U PD_D VPP EELoad EESel FSel Clock Data LD Cext Primary Register (20-bit) EE Register (20-bit) Transfer Logic EEPROM ENH E_WR Secondary Register (20-bit)
Document No. 70-0091-03 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Dout Output Data out function. Dout is defined with the Enhancement Register and enabled with ENH. VDD (Note 1) Same as pin 1. PD_D Output Phase detector output. PD_D pulses negatively when fp leads fc. PD_U Output Phase detector output. PD_U pulses negatively when fc leads fp. EESel Input Control line for Frequency Register selection, EE Register parallel loading, and EEPROM programming. Internal 70 kΩ pull-up resistor. GND (Note 2) Ground. fr Input Reference frequency input. Table 3. DC Electrical Specifications
Description
Notes 1: VDD pins 1, 11, and 19 (TSSOP) or pins 6, 14 and 19 (QFN), are connected by diodes and must be supplied with the same positive voltage level. 2: Ground connections are made through the exposed solder pad. The solder pad must be soldered to the ground plane for proper operation . Table 2. Absolute Maximum Ratings Table 4. ESD Ratings exceeding the specified rating in Table 4. devices are immune to latch-up. may cause permanent device damage. limits in the DC and AC Characteristics table. extended periods may affect device reliability.
©2005 Peregrine Semiconductor Corp. All rights reserved. Table 5. DC Characteristics
©2005 Peregrine Semiconductor Corp. All rights reserved. Table 6. AC Characteristics
100 Hz Offset
Rise and fall times of the VPP programming voltage pulse must be greater than 1 µs. Ordering Information, for ordering details. frequency limit exists when operated in this mode. phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. Note 6: Parameter is guaranteed through characterization only and is not tested.
©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0091-03 │UltraCMOS™ RFIC Solutions Functional Description The PE3342 consists of a dual modulus prescaler, three programmable counters, a phase detector and control logic with EEPROM memory (see Figure 1). The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the state of the internal modulus select logic. The R and M counters divide the reference and prescaler outputs by integer values stored in one of three selectable registers. The modulus select logic uses the 4-bit A counter. The phase-frequency detector generates up and down frequency control signals and are also used to enable a lock detect circuit. Frequency control data is loaded into the device via the Serial Data Port, and can be placed in three separate frequency registers. One of these registers (EE register) is used to load from and write to the non-volatile 20-bit EEPROM. Various operational and test modes are available through the enhancement register, which is only accessible through the Serial Data Port (it cannot be loaded from the EEPROM). Main Counter Chain The main counter chain divides the RF input frequency, Fin, by an integer derived from the user-defined values in the M and A counters. It operates in two modes: High Frequency Mode Setting PB (prescaler bypass) LOW enables the ÷10/11 prescaler, providing operation to 2.7 GHz. In this mode, the output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation: fp = Fin / [10 x (M + 1) + A] (1) where 0 ≤ A ≤ 15 and A ≤ M + 1; 1 ≤ M ≤ 511 When the loop is locked, Fin is related to the reference frequency, fr, by the following equation: Fin = [10 x (M + 1) + A] x (fr / (R+1)) (2) where 0 ≤ A ≤ 15 and A ≤ M + 1; 1 ≤ M ≤ 511 A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. Programming the M counter with the minimum value of 1 will result in a minimum M counter divide ratio of 2. Programming the M and A counters with their maximum values provides a divide ratio of 5135. Prescaler Bypass Mode Setting the PB bit of a frequency register HIGH allows Fin to bypass the ÷10/11 prescaler. In this mode, the prescaler and A counter are powered down, and the input VCO frequency is divided by the M counter directly. The following equation relates Fin to the reference frequency fr: Fin = (M + 1) x (fr / (R+1)) (3) where 1 ≤ M ≤ 511 Reference Counter The reference counter chain divides the reference frequency, fr, down to the phase detector comparison frequency, fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation: fc = fr / (R + 1) (4) where 0 ≤ R ≤ 63 Note that programming R with 0 will pass the reference frequency, fr, directly to the phase detector. Phase Detector The phase detector is triggered by rising edges from the main counter (fp) and the reference counter (fc). It has two outputs, PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses LOW. If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses LOW. The width of either pulse is directly proportional to the phase offset between the fp and fc signals.
©2005 Peregrine Semiconductor Corp. All rights reserved. this output will be HIGH with narrow pulses LOW. provides integration of this signal. register, the Primary register, and the EE register. to select one of these destinations. the timing requirements for this process . Table 7. Serial Interface Figure 4. Serial Interface Timing Diagram
©2005 Peregrine Semiconductor Corp. All rights reserved. selected to control the PLL as shown in Table 9. load of data into the Secondary Register. The Secondary Register is a parallel-load register. selected to control the PLL as shown in Table 9. data from the EEPROM for controlling the PLL. settings required to enable this mode. Table 8. Primary / Secondary / EE Register Bit Assignments Table 9. Frequency Register Selection Table 10. EE Register Load from EEPROM
Document No. 70-0091-03 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Enhancement Register The Enhancement Register is a buffered serial shift register, loaded from the Serial Data Port. It activates special test and operating modes in the PLL. The bit assignments for these modes are shown in Table 11. The functions of these Enhancement Register bits are shown in Table 12. A function becomes active when its corresponding bit is set HIGH. Note that bits 1, 2, 5, and 6 direct various data to the Dout pin, and for valid operation no more than one should be set HIGH simultaneously . The Enhancement Register is buffered to prevent inadvertent control changes during serial loading. Data that has been loaded into the register is cap- tured in the buffer and made available to the PLL on the falling edge of E_WR. A separate control line is provided to enable and disable the Enhancement mode. Functions are enabled by taking the ENH control line LOW. Note: The enhancement register bit values are unknown during power up. To avoid enabling the enhancement mode during power up, set the Enh pin high (“1”) until the enhancement register bit values are programmed to a known state. Table 11. Enhancement Register Bit Assignments Table 12. Enhancement Register Functions Allows the contents of the EE Register to be serially shifted out Dout, LSB (B0) first. Data is shifted on rising edge of Clock. Bit 2 fp output Provides the M counter output at Dout. Bit 3 Power down Powers down all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming. Bit 5 MSEL output Provides the internal dual modulus prescaler modulus select (MSEL) at Dout. Bit 6 fc output Provides the R counter output at Dout. Bit 7 Reserved Program to 0
©2005 Peregrine Semiconductor Corp. All rights reserved. Figure 8. Details of EE register contents loaded from EEPROM and then shifted out Serially through Dout pin - The procedure is performed twice. access EE Register Output Bit Function. clocking the contents of the EEPROM register out.
19 Clock pulses are enough for the 20-bit EE
Note: ENH/ ( Pin 3 in TSSOP or Pin 20 in QFN) is at low (0) for this process.
Document No. 70-0091-03 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Evaluation and Programming Kit Support To provide easy evaluation of the PE3342 and to also enable programming of small evaluation quantities, Peregrine has developed complete evaluation kits and programming kits for the PE3342 EEPROM PLLs. Evaluation Kits The evaluation kits consist of an evaluation board and support software enabling the user to evaluate the full functionality of the part. The EEPROM can be loaded with user specified values and then placed in a self start-up mode. Please refer to Table 14, Ordering Information, for the specific order codes. Programming Kits The programming kits consist of a programming board and support software that enables the user to program small quantities of devices for prototype evaluation and for small pre-production runs. Please refer to Table 14, Ordering Information, for the specific order codes Large production quantities can be special programmed at Peregrine for an additional charge. Please contact Peregrine Sales for pricing and leadtime at sales@psemi.com.
Application Information
The PE3342 has been designed to allow a self- starting PLL synthesizer to be built, removing the need to have a micro-controller or other programming source load data into the device on power-up. It can be used as a remotely controllable PLL as well, since the EEPROM circuitry has been added to a complete PLL core (PE3339). The PE3342’s EEPROM can be programmed in- circuit, or prior to assembly using a socketed fixture. It can be reprogrammed a minimum of 100 times, but is not designed to support constant reprogramming of the EEPROM by an application . Self-Starting Mode In self-starting applications, the EE Register is used to control the device and must be selected per Table 9. Additionally, the contents of the EEPROM must be copied to the EE Register per Table 10, and device power must be stable for this transfer to be reliably accomplished. These requirements can be met by connecting a capacitor of 50pF-10uF (evaluation design uses 3.3uF) from the EESel pin to ground. The delay of the rising edge on EESel, created by the RC time constant of its 70k ohm internal pull-up resistor and the external capacitor, will allow device power to stabilize first, ensuring proper data transfer. This edge is adaptable by capacitor value selection. The Vcc applied to the IC must be settled first.
©2005 Peregrine Semiconductor Corp. All rights reserved. Figure 9. Package Drawing
1.10 MAX
0.30 MAX
1.0 REF
©2005 Peregrine Semiconductor Corp. All rights reserved. Figure 10. Package Drawing
0.50 TYP
2.00 TYP
0.20 REF
- COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL
- DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.25 AND 0.30 FROM TERMINAL TIP.
©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0091-03 │UltraCMOS™ RFIC Solutions Table 14. Ordering Information 2000 units / T&R 3342-03 PE3342 PE3342-20QFN4x4-92A 20-lead QFN 91 units / Tube 624 units / Tray 3342-04 PE3342 PE3342-20QFN4x4-3000C 20-lead QFN 3000 units / T&R 3342-31 PE3342 PE3342-24TSSOP-62A (3GHz grade) 24-lead TSSOP 62 units / Tube 3342-32 PE3342 PE3342-24TSSOP-2000C (3GHz grade) 24-lead TSSOP 2000 units / T&R 3342-33 PE3342 PE3342-20QFN4x4-92A (3GHz grade) 20-lead QFN 91 units / Tube 624 units / Tray 3342-34 PE3342 PE3342-20QFN4x4-3000C (3GHz grade) 20-lead QFN 3000 units / T&R 3342-00 PE3342-EK PE3342-24TSSOP-EK (TSSOP) Evaluation Kit 1 / Box 3342-05 PE3342-EK PE3342-20QFN4x4-EK (QFN) Evaluation Kit 1 / Box 3342-06 PE3342-PK PE3342-24TSSOP-PK (TSSOP) Programming Kit 1 / Box 3342-07 PE3342-PK PE3342-20QFN4x4-PK (QFN) Programming Kit 1 / Box 3342-54 PE3342 PE3342G-20QFN4x4-3000C Green 20-lead QFN 3000 units / T&R 3342-53 PE3342 PE3342G-20QFN4x4-92A Green 20-lead QFN 91 units / Tube 624 units / Tray
Document No. 70-0091-03 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Sales Offices The Americas Peregrine Semiconductor Corporation
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