3340-00

PE3340 PEREGRINE | Alldatasheet

Document overview

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• PDF pages: 12

Technical content

Features

• 3.0 GHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector
• Serial programmable
• Low power ⎯ 20 mA at 3 V
• Ultra-low phase noise
• Available in 20-lead TSSOP Peregrine’s PE3340 is a high performance integer-N PLL capable of frequency synthesis up to 3.0 GHz. The superior phase noise performance of the PE3340 makes it ideal for applications such as wireless local loop basestations, LMDS systems and other demanding terrestrial systems. The PE3340 features a 10/11 dual modulus prescaler, counters and a phase comparator as shown in Figure 1. Counter values are programmable through a three wire serial interface. Fabricated in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS technology, the PE3340 offers excellent RF performance with the economy and integration of conventional CMOS. Fin Fin Prescaler Main Counter Secon- dary 20-bit Latch Primary 20-bit Latch R Counter fr Phase Detector Sdata PD_U PD_D

Copyright © Peregrine Semiconductor Corp. 2004 File No. 70/0040~02A| UTSi ® CMOS RFIC SOLUTIONS Page 2 of 12 Figure 2. Pin Configuration Table 1. Pin Descriptions

Description

(Note 1) Enh Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 kΩ pull-up resistor. S_WR Input Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are transferred to the secondary register on S_WR rising edge. Sdata Input Binary serial data input. Input data entered MSB first. Sclk Input Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. GND Ground. FSELS Input Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters. Internal 70 kΩ pull-down resistor. E_WR Input Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. Internal 70 kΩ pull-down resistor. VDD (Note 1) Same as pin 1. Fin Input Prescaler input from the VCO. Max frequency input is 3.0 GHz. Fin Input Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected in series with a 50 Ω resistor to the ground plane. GND Ground. Cext Output Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. LD Output Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (“0”). Dout Output Data out function, Dout, enabled in enhancement mode. VDD (Note 1) Same as pin 1. VDD Enh S_WR Sdata Sclk GND FSELS E_WR VDD Fin Fin GND Cext LD Dout VDD PD_D PD_U GND fr

PEREGRINE SEMICONDUCTOR CORP. ® | http://www.psemi.com Copyright © Peregrine Semiconductor Corp. 2004 Page 3 of 12 Pin No. Pin Name Type PD_D Output PD_D pulses down when fp leads fc. PD_U Output PD_U pulses down when fc leads fp. GND Ground. fr Input Reference frequency input. Note 1: VDD pins 1, 9, and 16 are connected by diodes and must be supplied with the same positive voltage level. Table 2. Absolute Maximum Ratings Table 3. Operating Ratings Table 4. ESD Ratings rating specified in Table 4. devices are immune to latch-up.

Table 5. DC Characteristics

Table 6. AC Characteristics

100 Hz Offset

noise performance, the reference input falling edge rate should be faster than 80mV/ns. Parameter is guaranteed through characterization only and is not tested.

11, depending on the value of the modulus select. (“A”) is used in the modulus select logic. the internal registers via the three wire serial bus. Figure 3. Functional Block Diagram

derived from the values in the “M” and “A” counters. it will cycle from 0 to 9 between increments in M. counter divide ratio of “2”. Figure 4. Data are transferred to the counters as register contents are utilized.

Table 7. Primary Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. Table 8. Enhancement Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge. Figure 4. Serial Interface Mode Timing Diagram

PEREGRINE SEMICONDUCTOR CORP. ® | http://www.psemi.com Copyright © Peregrine Semiconductor Corp. 2004 Page 9 of 12 Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality Reserved Bit 1 Reserved Bit 2 fp output Drives the M counter output onto the Dout output. Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 fc output Drives the reference counter output onto the Dout output Bit 7 Reserved Program to 0 Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, namely PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “low”. If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses “low”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The phase detector gain is equal to 2.70 V / 2 π, which numerically yields 0.43 V / Radian. PD_U and PD_D drive an active loop filter which controls the VCO tune voltage. PD_U pulses result in an increase in VCO frequency and PD_D results in a decrease in VCO frequency, for a positive Kv VCO. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2 kohm resistor. Connecting Cext to an external shunt capacitor provides low pass filtering of this signal. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D.

1.10 MAX

0.30 MAX

1.0 REF

Figure 5. Package Drawing

PEREGRINE SEMICONDUCTOR CORP. ® | http://www.psemi.com Copyright © Peregrine Semiconductor Corp. 2004 Page 11 of 12 Table 10. Ordering Information 2000 units / T&R 3340-00 PE3340EK PE3340-20TSSOP-EVAL KIT 20-lead TSSOP 1 / Box

Copyright © Peregrine Semiconductor Corp. 2004 File No. 70/0040~02A| UTSi ® CMOS RFIC SOLUTIONS Page 12 of 12 Sales Offices United States Peregrine Semiconductor Corp.

9450 Carroll Park Drive

San Diego, CA 92121 Tel 1-858-731-9400 Fax 1-858-731-9499 Japan Peregrine Semiconductor K.K. 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches France For a list of representatives in your area, please refer to our Web site at: http://www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp., and UTSi are registered trademarks of Peregrine Semiconductor Corporation. Copyright © 2004 Peregrine Semiconductor Corp. All rights reserved.