3336-00

PE3336 PEREGRINE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 15

Technical content

Features

• 3000 MHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector
• Serial, parallel or hardwired programmable
• Pin compatible with PE3236
• Ultra-low phase noise
• Available in 44-lead PLCC and 7x7 mm 48-lead QFN package

Figure 1. Block Diagram

Document No. 70-0033-02 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. S_WR Serial Input Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are transferred to the secondary register on S_WR or Hop_WR rising edge. Parallel Input Parallel data bus bit4 Direct Input M Counter bit4 Sdata Serial Input Binary serial data input. Input data entered MSB first. Parallel Input Parallel data bus bit5. Direct Input M Counter bit5. Sclk Serial Input Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. Parallel Input Parallel data bus bit6. Direct Input M Counter bit6. FSELS Serial Input Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters while in Serial Interface Mode. Parallel Input Parallel data bus bit7 (MSB). Pre_en Direct Input Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. GND ALL Ground. FSELP Parallel Input Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for programming of internal counters while in Parallel Interface Mode. Direct Input A Counter bit0 (LSB). E_WR Serial Input Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. Parallel Input Enhancement register write. D[7:0] are latched into the enhancement register on the rising edge of E_WR. Direct Input A Counter bit1. M2_WR Parallel Input M2 write. D[3:0] are latched into the primary register (R[5:4], M [8:7]) on the rising edge of M2_WR. Direct Input A Counter bit2. Smode Serial, Parallel Input Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0, Smode=0). Direct Input A Counter bit3 (MSB). Bmode ALL Input Selects direct interface mode (Bmode=1). 17,18 VDD ALL (Note 1) Same as pin 1. M1_WR Parallel Input M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of M1_WR. A_WR Parallel Input A write. D[7:0] are latched into the primary register (R[3:0], A [3:0]) on the rising edge of A_WR. Hop_WR Serial, Parallel Input Hop write. The contents of the primary register are latched into the secondary register on the rising edge of Hop_WR. Fin ALL Input Prescaler input from the VCO. 3.0 GHz max frequency. Pin No. (44-lead PLCC) Pin No. (48-lead QFN) Pin Name Interface Mode Type

Description

Table 1. Pin Descriptions (continued)

©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0033-02 │UltraCMOS™ RFIC Solutions Table 1. Pin Descriptions Figure 2. Pin Configurations (Top View) (Note 1) Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended. Direct Input R Counter bit0 (LSB). Direct Input R Counter bit1. Direct Input R Counter bit2. Direct Input R Counter bit3. GND ALL (Note 1) Ground. Parallel Input Parallel data bus bit0 (LSB). Direct Input M Counter bit0 (LSB). Parallel Input Parallel data bus bit1. Direct Input M Counter bit1. Parallel Input Parallel data bus bit2. Direct Input M Counter bit2. Parallel Input Parallel data bus bit3. Direct Input M Counter bit3. VDD ALL (Note 1) Same as pin 1. VDD ALL (Note 1) Same as pin 1. D0, M0 D1, M1 D2, M2 D3, M3 VDD VDD S_WR, D4, M4 Sdata, D5, M5 Sclk, D6, M6 FSELS, D7, Pre_en GND GND fp VDD_fp Dout VDD Cext VDD PD_D PD_U VDD_fc fc Fin Fin Hop_WR A_WR M1_WR VDD Bmode Smode, A3 M2_WR, A2 E_WR, A1 FSELP, A0 GND VDD Enh LD fr GND GND

Document No. 70-0033-02 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Fin ALL Input Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected in series with a 50 Ω resistor directly to the ground plane. GND ALL Ground. fp ALL Output Monitor pin for main divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 31. VDD-fp ALL (Note 1) VDD for fp. Can be left floating or connected to GND to disable the fp output. Dout Serial, Parallel Output Data Out. The MSEL signal and the raw prescaler output are available on Dout through enhancement register programming. VDD ALL (Note 1) Same as pin 1. Cext ALL Output Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. VDD ALL (Note 1) Same as pin 1. PD_D ALL Output PD_D is pulse down when fp leads fc. PD_U ALL PD_U is pulse down when fc leads fp. VDD-fc ALL (Note 1) VDD for fc can be left floating or connected to GND to disable the fc output. fc ALL Output Monitor pin for reference divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 38. 31,37 GND ALL Ground. 38,39 GND ALL Ground. fr ALL Input Reference frequency input. LD ALL Output Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (“0”). Enh Serial, Parallel Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional. N/A NC ALL No connection. Pin No. (44-lead PLCC) Pin No. (48-lead QFN) Pin Name Interface Mode Type Note 1: All VDD pins are connected by diodes and must be supplied with the same positive voltage level. All digital input pins have 70 kΩ pull-down resistors to ground.

©2005 Peregrine Semiconductor Corp. All rights reserved. Table 2. Absolute Maximum Ratings Table 4. ESD Ratings exceeding the specified rating in Table 4. devices are immune to latch-up. Table 3. Operating Ratings Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified

©2005 Peregrine Semiconductor Corp. All rights reserved. Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Parameter is guaranteed through characterization only and is not tested. noise amplifier to square up the edges is recommended at lower input frequencies.

©2005 Peregrine Semiconductor Corp. All rights reserved. generates up and down frequency control signals. Figure 3. Functional Block Diagram

©2005 Peregrine Semiconductor Corp. All rights reserved. and powers down the prescaler. a minimum M Counter divide ratio of “2”. and M8 are internally forced low. R5 are internally forced low (“0”). Bmode input “low” and the Smode input “low”. secondary register contents are utilized. Figure 4. This data provides control bits as Bmode input “low” and the Smode input “high”. as shown in Table 7 on page 10. secondary register contents are utilized.

©2005 Peregrine Semiconductor Corp. All rights reserved. register on the rising edge of Sclk, MSB (B0) first.

1. After the falling edge of E_WR, the data provide

R4 and R5 are internally forced low (“0”). Table 7. Primary Register Programming Table 8. Enhancement Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

Document No. 70-0033-02 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. PD_U and PD_D drive an active loop filter which controls the VCO tune voltage. PD_U pulses result in an increase in VCO frequency; PD_D pulses result in a decrease in VCO frequency (for a positive Kv VCO). A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2 kohm resistor. Connecting Cext to an external shunt capacitor provides low pass filtering of this signal. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality Reserved Bit 1 Reserved Bit 2 Reserved Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming as directed by the Bmode and Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 Prescaler output Drives the raw internal prescaler output onto the Dout output. Bit 7 fp, fc OE fp, fc outputs disabled. Program to 0 Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “low”. If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses “low”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The phase detector gain is equal to 2.7 V / 2 π, which numerically yields 0.43 V / radian.

©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0033-02 │UltraCMOS™ RFIC Solutions Handling Requirements All surface mount products which do not meet Level 1 moisture sensitivity requirements are processed through dry bake and pack procedure. The necessary data is recorded on the caution label of each shipment. Both packages for the PE3335 are moisture sensitivity Level 3. Level 3 Caution Label The caution label should contain the following information for Level 3 devices: 1. Calculated shelf life in sealed bag: 12 months at <40 °C and <90% relative humidity (RH) 2. Peak package body temperature is 225 °C. 3. After bag is opened, devices that will be subjected to reflow solder or other high temperature process must a) Be mounted within 168 hours of factory conditions <30 °C/60% RH, or b) Be stored at <10% RH 4. Devices require bake, before mounting, if: a) Humidity Indicator Card is > 10% when read at 23 ± 5 °C b) 3a or 3b are not met 5. If baking is required, devices may be baked for 48 hours at 125 +5/-0 °C Note: If device containers cannot be subjected to high temperature or shorter bake times are desired, reference IPC/JEDEC-J-STD-033 for bake procedure. Level and Body temperature defined by: IPC/JEDEC-J-STD-020 For Dry Bake Procedures, see: IPC/JEDEC-J-STD-033 Operator must observe ESD precautions per ESD Control Procedure and Parts Handling and shipping Procedure.

©2005 Peregrine Semiconductor Corp. All rights reserved. Figure 6. Package Drawing

1. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL
2. DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED

BETWEEN 0.25 AND 0.30 FROM TERMINAL TIP.

0.20 REF

0.50 TYP

5.50 TYP

2.75 TYP

©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0033-02 │UltraCMOS™ RFIC Solutions Figure 7. Package Drawing Table 10. Ordering Information 500 units / T&R 3336-23 PE3336 PE3336-48QFN 7x7 mm-52A 48-lead QFN 52 units / Tube 3336-24 PE3336 PE3336-48QFN 7x7 mm-2000C 48-lead QFN 2000 units / T&R 3336-00 PE3336EK PE3336-44PLCC-EVAL KIT Evaluation Kit 1 / Box 3336-01 PE3336EK PE3336-48QFN 7x7 mm-EK Evaluation Kit 1 / Box DETAIL SURFACE R0.025 0.610 ±0.020 A 0.020 MIN. MOUNT POINT DIMENSIONS ARE IN INCHES TOLERANCES ARE ± 0.004 SEE DETAIL A 0.070 0.070 *EJECT PIN POSITION 0.010 0.004 0.180 MAX. Ø0.040 50X 45°

0.010 X 45°

0.027 (WIDTH OF LEAD SLOT) BOTTOM VIEW PIN 1

0.045 X 45°

0.653±0.003 0.050 0.653±0.003 0.050 0.690±0.005 0.690±0.005

Document No. 70-0033-02 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Sales Offices The Americas Peregrine Semiconductor Corporation

9450 Carroll Park Drive

San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 North Asia Pacific Peregrine Semiconductor K.K. 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Peregrine Semiconductor, Korea #B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si, Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. South Asia Pacific Peregrine Semiconductor, China Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Space and Defense Products Americas: Tel: 505-881-0438 Fax: 505-881-0443 Europe, Asia Pacific:

180 Rue Jean de Guiramand

13852 Aix-En-Provence cedex 3, France

Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227