PE3291 PEREGRINE | Alldatasheet

Document overview

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Technical content

Features

  • Ultra-Low Power via FlexiPower variable supply voltages
  • Modulo-32 fractional-N main counters
  • On-board fractional spur compensation: No tuning required, stable over temperature
  • Improved phase noise compared to integer-N architectures Figure 1: FlexiPower technology enables the prescaler to operate at voltages down to 0.8 volts. This significantly reduces the total power. PE3291 Low Speed Counters Phase Comparator and Charge pump Ref. Input To Loop Filter

3 Volts

0.8 3 Volts Regulator

Applications

  • CDMA handsets
  • CDMA base stations
  • Analog Cordless phones
  • One and two way pagers

©2005 Peregrine Semiconductor Corp. All rights reserved. with no degradation in phase noise performance. multiples of the step size away from center tone. their ability to reduce these spurious sidebands. over the full commercial temperature range. Figure 4. PE3291 Block Diagram

©2005 Peregrine Semiconductor Corp. All rights reserved. Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Table 2. Absolute Maximum Ratings Table 4. ESD Ratings specified rating in Table 4. devices are immune to latch-up. Table 3. Operating Ratings

3 V supply current when VDD1

2 PLL’s enabled

1 PLL enabled

externally supplied. When VDD1 and VDD2 are internally generated, pins 7 and 14 should be left floating.

©2005 Peregrine Semiconductor Corp. All rights reserved. Table 5. DC Characteristics (continued): VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Output current magnitude variation vs. Figure 5. Prescaler Current vs. FlexiPower Voltage (VDD1 and VDD2 externally supplied) Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified

©2005 Peregrine Semiconductor Corp. All rights reserved. Table 6. AC Characteristics (continued): VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Figure 6. PLL Maximum Frequency vs. FlexiPower Voltage

©2005 Peregrine Semiconductor Corp. All rights reserved. supporting counters, and a fractional accumulator. the PE3291 automatically reduces the fraction. Figure 7. Functional Block Diagram

©2005 Peregrine Semiconductor Corp. All rights reserved. Table 7. Register Set Figure 8. Serial Interface Mode Timing Diagram

©2005 Peregrine Semiconductor Corp. All rights reserved.

  1. For example, to program the PLL1 (RF)

Table 8. For normal operation, S16 of address Table 8. PE3291 Counter Programming Example operation are shown on Table 9. The truth table for the foLD output is shown in Table 10. Table 9. PE3291 Program Modes the foLD output, causing fr (pin 8) and foLD (pin 10) to become high impedance. The Serial Control Interface remains active at all times. presumes the use of a passive loop filter. If an inverting active loop filter is used the relationship is also inverted. Figure 9. VCO Characteristics

  • When VCO1 (RF) slope is positive like (1), C11 should be set HIGH.
  • When VCO1 (RF) slope is negative like (2), C11 should be set LOW.
  • When VCO2 (IF) slope is positive like (1), C21 should be set HIGH.
  • When VCO2 (IF) slope is negative like (2), C21 should be set LOW.

©2005 Peregrine Semiconductor Corp. All rights reserved. Table 10. foLD Programming Truth Table supply pins should be left grounded. Table 11. FlexiPower Voltage Regulation Programming Note: 1. When the foLD is disabled the output is a CMOS LOW.

  1. Lock detect indicates when the VCO frequency is in “lock”. When PLL1 is in lock and PLL1 lock detect is selected, the foLD pin will be HIGH

PLL1 / PLL2 lock detect is selected the foLD pin will be HIGH with narrow pulses LOW only when both PLL1 and PLL2 are in lock.

  1. The counter reset state when activated resets all counters. Upon removal of the reset, counters M, A, and F resume counting in close

©2005 Peregrine Semiconductor Corp. All rights reserved. to sink current. If C11 = LOW, UP1 and DOWN1 are interchanged. to sink current. If C21 = LOW, UP2 and DOWN2 are interchanged. Figure 10. Phase Comparator Timing Diagram Note 1: fc1(2), fp1(2), and LD1(2) are accessible via the foLD pin per programming in Table 11.

©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0009-04 │UltraCMOS™ RFIC Solutions Loop Filter Second/Third Order Loops Choosing the optimum loop filter for a design encompasses many trade offs. The rule of thumb for choosing the loop filter bandwidth is 10 percent of the step size. A second order loop (C1 C2 R2 and C4 C5 R5 in Figure 11 omitting C3 R3 C6 and R6) will provide the least amount of components and the fastest lock times. If lock time is an issue, one might try opening up the loop filter, although if it is too wide, instability will dominate and worsen lock time. If lock time is not an issue, a narrower second order filter will minimize residual FM without requiring additional components. Third Order loop filters (C1 C2 R2 C3 R3 and C4 C5 R5 C6 R6 in Figure 11) provide a good compromise between lock time and residual FM. We have found using a third order loop with 20 dB of rejection at the step size will halve the Residual FM as measured with a similar second order loop, with minimum effect on lock time. Loop Filter Bandwidth Design Considerations As part of the spur compensation circuitry, the PE329x series PLLs contain capacitors to ground internal to the charge pump. PLL1 contains a 50 pF capacitor and PLL2 contains a 100 pF capacitor. To ensure accurate loop filter calculations, it is critical that the calculated value of the first shunt capacitor (C1 & C4 in Figure 11) be at least 100 pF for PLL1 and 200 pF for PLL2. With this requirement satisfied, the remaining loop components can be calculated. For a stable loop, it is also important that the loop bandwidth be less than or equal to one tenth of the step size. Digital Control Lines Control Line Noise We have noticed frequency jitter during programming when a low impedance, such as a capacitor to ground, is placed next to any control line pin (clock, data, and load enable). The use of a 51 k ohm resistor in series with the control line will eliminate the problem with no effect to programming time. Enable Line Voltage The PE329x series PLLs use a level sensitive load enable. Therefore the digital controller must provide an active low to the part at all times except when the data is to be loaded into the shift register. If the PLL controller does not hold the voltage low, a high impedance resistor to ground should be added to the enable line to ensure stable operation.

5 Volt Operation:

The PE329x series PLLs are not capable of accepting control voltages greater than 3.3 volts. Interface to 5 volt controllers requires the addition of resistor dividers to comply with the 3.3 volt maximum operation voltage.

©2005 Peregrine Semiconductor Corp. All rights reserved. Figure 11. Application Example 100 pF, and C4 must be greater than or equal to 200 pF.

©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0009-04 │UltraCMOS™ RFIC Solutions Figure 12. Package Drawing

1.0 REF

0.65 BSC

6.4 BSC

Table 12. Ordering Information

Description

2000 unit / T&R 3291-00 PE3291EK PE3291-20TSSOP-Eval Kit Evaluation Kit 1 / Box 6.40 SIDE VIEW R 0.90 MIN 0.60 +.15 -.10 R 0.90 MIN 12o REF 12o REF 0.20 0.25 GAGE PLANE

1.10 MAX

0.30 MAX

0.10 C B A 0.10 C 0.10±0.05 - C - 0.65BSC 4.40±0.10 .20 C B A - A - - B - TOP VIEW 1.00 1.00 3.20 0.90±0.05 6.50±0.10 Ø1.00±0.10 0.325

Document No. 70-0009-04 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Sales Offices The Americas Peregrine Semiconductor Corporation

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San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 North Asia Pacific Peregrine Semiconductor K.K. 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Peregrine Semiconductor, Korea #B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si, Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. South Asia Pacific Peregrine Semiconductor, China Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Space and Defense Products Americas: Tel: 505-881-0438 Fax: 505-881-0443 Europe, Asia Pacific:

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