PE3239 PEREGRINE | Alldatasheet

Document overview

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Technical content

Features

  • 2.2 GHz operation
  • ÷10/11 dual modulus prescaler
  • Internal phase detector with charge pump
  • Serial programmable
  • Low power— 20 mA at 3 V
  • Ultra-low phase noise
  • Available in 20-lead TSSOP

Figure 1. Block Diagram

Document No. 70-0047-02 │www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Table 1. Pin Descriptions (continued) Charge pump current is sourced when fc leads fp and sinked when fc lags fp.

Description

Note 1: VDD pins 1, 9, and 16 are connected by diodes and must be supplied with the same positive voltage level. Table 2. Absolute Maximum Ratings Table 3. Operating Ratings Table 4. ESD Ratings exceeding the specified rating in Table 4. devices are immune to latch-up.

©2006 Peregrine Semiconductor Corp. All rights reserved. Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified

©2006 Peregrine Semiconductor Corp. All rights reserved. Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. Parameter is guaranteed through characterization only and is not tested.

100 Hz Offset

©2006 Peregrine Semiconductor Corp. All rights reserved. phase detector, charge pump and control logic. internal registers via the three wire serial bus. Figure 6. Functional Block Diagram

©2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0047-02 │UltraCMOS™ RFIC Solutions Main Counter Chain Normal Operating Mode Setting the Pre_en control bit “low” enables the ÷10/11 prescaler. The main counter chain then divides the RF input frequency (Fin) by an integer derived from the values in the “M” and “A” counters. In this mode, the output from the main counter chain (fp) is related to the VCO frequency (Fin) by the following equation: fp = Fin / [10 x (M + 1) + A] (1) where A ≤ M + 1, 1 ≤ M ≤ 511 When the loop is locked, Fin is related to the reference frequency (fr) by the following equation: Fin = [10 x (M + 1) + A] x (fr / (R+1)) (2) where A ≤ M + 1, 1 ≤ M ≤ 511 A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. The A counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in M. Programming the M counter with the minimum allowed value of “1” will result in a minimum M counter divide ratio of “2”. Prescaler Bypass Mode Setting the frequency control register bit Pre_en “high” allows Fin to bypass the ÷10/11 prescaler. In this mode, the prescaler and A counter are powered down, and the input VCO frequency is divided by the M counter directly. The following equation relates Fin to the reference frequency fr: Fin = (M + 1) x (fr / (R+1)) (3) where 1 ≤ M ≤ 511 Reference Counter The reference counter chain divides the reference frequency fr down to the phase detector comparison frequency fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation: fc = fr / (R + 1) (4) where 0 ≤ R ≤ 63 Note that programming R with “0” will pass the reference frequency (fr) directly to the phase detector. Register Programming Serial Interface Mode While the E_WR input is “low” and the S_WR input is “low”, serial input data (Sdata input), B0 to B19, are clocked serially into the primary register on the rising edge of Sclk, MSB (B0) first. The contents from the primary register are transferred into the secondary register on the rising edge of either S_WR according to the timing diagrams shown in Figure 7. Data are transferred to the counters as shown in Table 7 on page 9. The double buffering provided by the primary and secondary registers allows for “ping-pong” counter control using the FSELS input. When FSELS is “high”, the primary register contents set the counter inputs. When FSELS is “low”, the secondary register contents are utilized. While the E_WR input is “high” and the S_WR input is “low”, serial input data (Sdata input), B0 to B7, are clocked serially into the enhancement register on the rising edge of Sclk, MSB (B0) first. The enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially entered data performed on the falling edge of E_WR according to the timing diagram shown in Figure 7. After the falling edge of E_WR, the data provide control bits as shown in Table 8 on page 9 will have their bit functionality enabled by asserting the Enh input “low”.

©2006 Peregrine Semiconductor Corp. All rights reserved. Table 7. Primary Register Programming Table 8. Enhancement Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge. Figure 7. Serial Interface Mode Timing Diagram

©2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0047-02 │UltraCMOS™ RFIC Solutions CP. The current pulses from pin CP are low pass filtered externally and then connected to the VCO tune voltage. PD_U pulses result in a current source, which increases the VCO frequency and PD_D results in a current sink, which decreases VCO frequency when using a positive Kv VCO. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2 kohm resistor. Connecting Cext to an external shunt capacitor provides low pass filtering of this signal. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality two input signals, fp and fc. Reserved Bit 1 Reserved Bit 2 fp output Drives the M counter output onto the Dout output. Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 fc output Drives the reference counter output onto the Dout output Bit 7 Reserved** Figure 8. Typical PE3239 Loop Filter Application Example

Document No. 70-0047-02 │www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Figure 9. Package Drawing Table 10. Ordering Information

1.10 MAX

0.30 MAX

1.0 REF

2000 units / T&R 3239-00 PE3239EK PE3239-20TSSOP-EVAL KIT Evaluation Board 1 / Box

©2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0047-02 │UltraCMOS™ RFIC Solutions Sales Offices The Americas Peregrine Semiconductor Corporation

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San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 North Asia Pacific Peregrine Semiconductor K.K. 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Peregrine Semiconductor, Korea #B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. South Asia Pacific Peregrine Semiconductor, China Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Space and Defense Products Americas: Tel: 505-881-0438 Fax: 505-881-0443 Europe, Asia Pacific:

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