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ICS85301 ICST | Alldatasheet

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www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER GENERAL DESCRIPTION The ICS85301 is a high performance 2:1 Differ- ential-to-LVPECL Multiplexer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85301 can also per- form differential translation because the differ- ential inputs accept LVPECL, CML as well as LVDS levels. The ICS85301 is packaged in a small 3mm x 3mm

16 VFQFN package, making it ideal for use on space con-

strained boards.

FEATURES

• 2:1 LVPECL MUX
• One LVPECL output
• Two differential clock inputs can accept: LVPECL, LVDS, CML
• Maximum input/output frequency: 3GHz
• Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLK0, nPCLK0
• Propagation delay: 490ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Additive phase jitter, RMS: 0.009ps (typical)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT HiPerClockS™ ICS ICS85301 16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View PCLK0 nPCLK0 PCLK1 nPCLK1 VEE Q nQ VEE VBB CLK_SEL nc VCC nc VEE VEE VCC 5 6 7 8 16 15 14 13 PCLK0 nPCLK0 PCLK1 nPCLK1 CLK_SEL VBB Q nQ PCLK0 nPCLK0 PCLK1 nPCLK1 VBB CLK_SEL nc VCC nc VEE VEE VCC VEE Q nQ VEE ICS85301 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View

TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS TABLE 3. CONTROL INPUT FUNCTION TABLE

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V ± 5% OR 2.5V ± 5%, TA = -40°C TO 85°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V ± 5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V H I e g a tlo V h gi H t u p n I L E S K L C V C C V V L I e g a tlo V w o L t u p n I L E S K L C V I H I t n e rr u C h gi H t u p n I L E S K L C V C C V N I V r o V A µ I L I t n e rr u C w o L t u p n I L E S K L C V C C V V r o V N I V A µ h ti w d e t a ni m r e t st u p t u O E T O N Ω V o t C C ."tiu c ri C ts e T d a o L t u p t u O n oit a m r o f n I t n e m e r u s a e M r e t e m a r a P e e S l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V C C e g a tlo V ylp p u S e vitis o P V I E E t n e rr u C ylp p u S r e w o P A m ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA

16 VFQFN

51.5°C/W (0 lfpm)

16 TSSOP

89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V ± 5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U V C C e g a tlo V ylp p u S e vitis o P V I E E t n e rr u C ylp p u S r e w o P A m TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V ± 5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U I H I t n e rr u C h gi H t u p n I K L C P n K L C P K L C P n K L C P V C C V N I A µ I L I t n e rr u C w o L t u p n I K L C P K L C P V C C V V N I V A µ K L C P n K L C P n V C C V V N I V A µ V P P e g a tlo V t u p n I k a e P o k a e P V m V R M C E T O N e g a tlo V t u p n I e d o M n o m m o C V V H O E T O N e g a tlo V h gi H t u p t u O V V L O E T O N e g a tlo V w o L t u p t u O V V B B e g a tlo V s ai B V V s a d e nif e d si e g a tlo v e d o m n o m m o C E T O N H I . s n oit a cilp p a d e d n e elg nis r o F E T O N V si x K L C P n K L C P r o f e g a tlo v t u p ni m u m ix a m e h t C C V h ti w d e t a ni m r e t st u p t u O E T O N Ω V o t C C V

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U f X A M y c n e u q e r F t u p t u O z H G t D P E T O N ale D n oit a g a p o r P s p t p p k s E T O N w e k S tr a P o t-tr a P s p t )i( k s w e k S t u p n I s p t tij S M R e ttiJ e s a h P e vitid d A r e ff u B n oitc e s r e ttiJ e s a h P e vitid d A o t r e f e r e g n a R n oit a r g e t n z H M z H M z H K s p tR t F e m i T lla F e si R t u p t u O o t s p c d o elc y C yt u D t u p t u O X U M L O S I n oit alo sI X U M f = z H M m B d f t a d e r u s a e m s r e t e m a r a p ll A d e t o n e si w r e h t o s s eln u z H G nio p g nis s o r c t u p t u o lait n e r e ffid e h t o t t nio p g nis s o r c t u p nilait n e r e ffid e h t m o rf d e r u s a e M E T O N d n a s e g a tlo v ylp p u s e m a s e h t t a g nit a r e p o s e civ e d t n e r e ffid n o st u p t u o n e e w t e b w e k s s a d e nif e D E T O N d e r u s a e m e r a st u p t u o e h t e civ e d h c a e n o st u p nif o e p yt e m a s e h t g nis U n oitid n o c d a olla u q e h ti w .st nio p s s o r c lait n e r e ffid e h t t a d r a d n a t S C E D E J h ti w e c n a d r o c c a ni d e nif e d si r e t e m a r a p sih T E T O N TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U f X A M y c n e u q e r F t u p t u O z H G t D P E T O N ale D n oit a g a p o r P s p t p p k s E T O N w e k S tr a P o t-tr a P s p t )i( k s w e k S t u p n I s p t tij S M R e ttiJ e s a h P e vitid d A r e ff u B n oitc e s r e ttiJ e s a h P e vitid d A o t r e f e r e g n a R n oit a r g e t n z H M z H M z H K s p tR t F e m i T lla F e si R t u p t u O o t s p c d o elc y C yt u D t u p t u O X U M L O S I n oit alo sI X U M z H M f m B d e v o b a A elb a T e e s e t o n r o F TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = 2.5V ± 5%, TA = -40°C TO 85°C l o b m y S r e t e m a r a P s n o iti d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s ti n U I H I h gi H t u p n I t n e rr u C K L C P n K L C P K L C P n K L C P V C C V N I V A µ I L I t n e rr u C w o L t u p n I K L C P K L C P V C C V V N I V A µ K L C P n K L C P n V C C V V N I V A µ V P P e g a tlo V t u p n I k a e P o k a e P V m V R M C E T O N e g a tlo V t u p n I e d o M n o m m o C V V H O E T O N e g a tlo V h gi H t u p t u O V V L O E T O N e g a tlo V w o L t u p t u O V V B B e g a tlo V s ai B V V s a d e nif e d si e g a tlo v e d o m n o m m o C E T O N H I . s n oit a cilp p a d e d n e elg nis r o F E T O N V si x K L C P n K L C P r o f e g a tlo v t u p ni m u m ix a m e h t C C V h ti w d e t a ni m r e t st u p t u O E T O N Ω V o t C C V

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER ADDITIVE PHASE JITTER Additive Phase Jitter 3.3V or 2.5V @ 622MHz (12KHz to 20MHz) = 0.009ps typical -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10k 100k 10M 100M The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fun- damental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- the 1Hz band to the power in the fundamental. When the re- quired offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the funda- mental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER PARAMETER MEASUREMENT INFORMATION PART-TO-PART SKEW PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 2.5V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL 3.3V OUTPUT LOAD AC TEST CIRCUIT VCMR Cross Points VPP VEE nPCLK0, nPCLK1 nPCLK0, nPCLK1 VCC tPD Q nQ tsk(pp) PART 1 PART 2 Q0x Qy nQx nQy PCLK0, PCLK1 nPCLK0, nPCLK1 Q nQ tPW tPERIOD tPW tPERIOD odc = x 100% SCOPE Qx nQx LVPECL -1.3V ± 0.165V VCC VEE SCOPE Qx nQx LVPECL -0.5V ± 0.125V VCC VEE

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER Clock Outputs 20% 80% 80% 20% tR tF VOD OUTPUT RISE/FALL TIME INPUT SKEW tPD2 tPD1 tsk(i) = |tPD1 - tPD2| tsk(i) Q nQ PCLK0 nPCLK0 PCLK1 nPCLK1

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER θθθθθJA at 0 Air Flow (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 51.5°C/W TABLE 6A. THERMAL RESISTANCE θθθθθJA FOR 16-PIN VFQFN, FORCED CONVECTION POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85301. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85301 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 26mA = 90.09mW Power (outputs)MAX = 27.83mW/Loaded Output pair Total Power_MAX (3.465, with all outputs switching) = 90.09mW + 27.83mW = 117.92mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6B. THERMAL RESISTANCE θθθθθJA FOR FOR 16 LEAD TSSOP θθθθθJA by Velocity (Linear Feet per Minute) 200 500 Single-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 118.2°C/W 106.8°C/W Multi-Layer PCB, JEDEC Standard Test Boards 89.0°C/W 81.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER RELIABILITY INFORMATION TRANSISTOR COUNT The transistor count for ICS85301 is: 137 TABLE 7A. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN θθθθθJA at 0 Air Flow (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 51.5°C/W TABLE 7B. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θθθθθJA by Velocity (Linear Feet per Minute) 200 500 Single-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 118.2°C/W 106.8°C/W Multi-Layer PCB, JEDEC Standard Test Boards 89.0°C/W 81.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN TABLE 8A. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MO-220 N O I T A I R A V C E D E J S R E T E M I L L I M N I S N O I S N E M I D L L A L O B M Y S M U M I N I M M U M I X A M N A A A e c n e r e f e R b e C I S A B ND NE D D E E L

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 8B. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MO-153 L O B M Y S s r e t e m illi M m u m i n i M m u m i x a M N A A A b c D E C I S A B E e C I S A B L α a a a

for use in life support devices or critical medical instruments. TABLE 9. ORDERING INFORMATION The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER T E E H S Y R O T S I H N O I S I V E R v e R e l b a T e g a P e g n a h C f o n o it p ir c s e D e t a D A T n u o c d e tc e rr o c elb a T n oit a m r o f n I g nir e d r O A e e h s a t a d e h t t u o h g u o r h t e g a k c a p P O S S T d a e L d e d d A A T d e d d A ni P t u p n I d e s u n U r o f s n oit a d n e m m o c e R F L G A S C I o t g nik r a m e e rf- d a el d e d d a elb a T n oit a m r o f n I g nir e d r O e b m u n tr a p