Z16C30_08 ZILOG | Alldatasheet
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Copyright ©2008 by Zilog®, Inc. All rights reserved. www.zilog.com
DS007902-0708 P R E L I M I N A R Y DO NOT USE IN LIFE SUPPORT LIFE SUPPORT POLICY ZILOG'S PRODUCTS ARE NOT AUTHORIZED FO R USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT TH E EXPRESS PRIOR WRITTEN APPROV AL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. A critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2008 by Zilog, Inc. All rights reserved. Information in this pu blication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG , INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. Warning:
Revision History
Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. Date Revision Level Description Page No July 2008 02 Updated as per latest template and style guide. All Jan 2000 01 Original issue
DS007902-0708 P R E L I M I N A R Y Table of Contents Z16C30 Product Specification iv Table of Contents
DS007902-0708 P R E L I M I N A R Y Architectural Overview Z16C30 Product Specification Architectural Overview
Features
The key features of Zilog’s Z16C30 device include:
- Two Independent 0-to-10 Mbps Full-Duplex Channels, each with Two Baud Rate Gener- ators and One digital phase-locked loop (DPLL) for Clock Recovery
- 32-byte Data FIFO’s for each Receiver and Transmitter
- 110 ns Bus Cycle Time, 16-bit Data Bus Bandwidth
- Multi-Protocol Operation under Program Control with Independent Mode Selection for Receiver and Transmitter
- Async Mode with 1 to 8 Bits/Character, 1/16 to 2 Stop Bits/Character in 1/16-bit Incre- ments, Programmable Clock Factor, Break Detect and Generation, Odd, Even, Mark, Space or no Parity and Framing Error Detection, Supports One Address/Data Bit and MIL STD 1553B Protocols
- Byte Oriented Synchronous Mode with One to Eight Bits/Character, Programmable Idle Line Condition, Optional Receive Sync Stripping; Optional Preamble Transmission, 16- or 32-bit CRC, and Transmit-to-Receive Slaving (for X.21)
- Bisync Mode with 2- to 16-bit Programmable Sync Character, Programmable Idle Line Condition, Optional Receive Sync Stripping, Optional Preamble Transmission, 16- or 32- bit CRC
- Transparent Bisync Mode with EBCDIC or ASCII Character Code, Automatic CRC Han- dling, Programmable Idle Line Condition, Optional Preamble Transmission, Automatic Recognition of DLE, SYN, SOH, ITX, ETX, ETB, EOT, ENQ, and ITB
- External Character Sync Mode for Receive
- HDLC/SDLC Mode with Eight-Bit Address Compare, Extended Address Field Option, 16- or 32-bit CRC, Programmable Idle Line Condition, Optional Preamble Transmission and Loop Mode
- DMA Interface with Separate Request and Acknowledge for Each Receiver and Transmit- ter
- Channel Load Command for DMA Controlled Initialization
- Flexible Bus Interface for Direct Connection to Most Microprocessors, User Programma- ble for 8 or 16 Bits Wide, Directly Supports 680X0 Family or 8X86 Family Bus Interfaces
- Low Power CMOS
- 68-Pin PLCC/100-Pin VQFP Packages
DS007902-0708 P R E L I M I N A R Y Architectural Overview Z16C30 Product Specification General Description Zilog’s Z16C30 USC Universal Serial Controller is a dual-channel multi-protocol data communications peripheral designed for use with any conventional multiplexed or non- multiplexed bus. The USC functions as a serial-to-parallel, parallel-to-serial converter/ controller and may be software configured to satisfy a wide variety of serial communica- tions applications. The device contains a variety of new, sophisticated internal functions including two baud rate generators per channel, one digital phase-locked loop (DPLL) per channel, character counters for both receive and transmit in each channel and 32-byte data FIFO’s for each receiver and transmitter (Figure 1 on page 3). Zilog now offers a high speed version of the USC with improved bus bandwidth. CPU bus accesses have been shortened from 160 ns per access to 110 ns per access. The USC has a transmit and receive clock range of up to 10 MHz (20 MHz when using the DPLL, BRG , or CTR) and data transfer rates as high as 10 Mbits/sec full duplex. The USC handles asynchronous formats, synchronous byte-oriented formats such as BISYNC, and synchronous bit-oriented formats such as HDLC. This device supports vir- tually any serial data transfer application. The device can generate and check CRC in any synchronous mode and can be pro- grammed to check data integrity in various modes. The USC also has facilities for modem controls in both channels. In applications where these controls are not needed, the modem controls may be used for general-purpose I/O (GPIO). The same is true for most of the other pins in each channel. Interrupts are supported with a daisy-chain hierarchy, with the two channels having com- pletely separate interrupt structures. High-speed data transfers through DMA are supported by a Request/Acknowledge signal pair for each receiver and transmitter. The device supports automatic status transfer through DMA and also allows device initialization under DMA control. When written to, all reserved bits must be programmed to 0. To aid in efficiently programming the USC, support tools are available. The Technical Manual describes in detail all features presented in this Product Specification and gives programming sequence hints. The Programmer’s Assistant is a MS-DOS disk-based pro- gramming initialization tool to be used in conjunction with the Technical Manual. There are also available assorted application notes and development boards to assist in the hard- ware/software development. All Signals with an overline, are active Low. For example: B/W, in which WORD is active Low, and B/W, in which BYTE is active Low. Power connections follow these conventional descriptions: Note:
Table 1. Power connection conventions Figure 1. Z16C30 Block Diagram
Figure 2. Z16C30 Pin Functions
Figure 3. Z16C30 68-Pin PLCC Pin Assignments
pins for CPU handshake, and 14 pins for power and ground. Register (BCR) and external connections to the AD bus control selection of the bus type. BCR bit 2 to 0 and tying AD15–AD8 to VSS. Figure 4. 100-Pin VQFP Pin Assignments
DS007902-0708 P R E L I M I N A R Y Pin Description Z16C30 Product Specification The 8-bit bus with separate address is selected by setting BCR bit 2 to 0 and, during the BCR write, forcing AD15 to a 1 and forcing AD14–AD8 to 0. The multiplexed bus is selected for the USC if there is an Address Strobe prior to or during the transaction which writes the BCR. If no Address Strobe is present prior to or during the transaction which writes the BCR, a nonmultiplexed bus is selected (see Figure 29 on page 49). Pin Functions RESET Reset (input, active Low)— This signal resets the device to a known state. The first write to the USC after a reset accesses the BCR to select additional bus options for the device. AS Address Strobe (input, active Low)— This signal is used in the multiplexed bus modes to latch the address on the AD lines. The AS signal is not used in the nonmulti- plexed bus modes and should be tied to VDD. DS Data Strobe (input, active Low)— This signal strobes data out of the device during a read and may strobe an interrupt vector out of the device during an interrupt acknowledge cycle. DS also strobes data into the device on the state of R/W. RD Read Strobe (input, active Low)— This signal strobes data out of the device during a read and may strobe an interrupt vector out of the device during an interrupt acknowledge cycle. WR Write Strobe (input, active Low)— This signal strobes data into the device during a write. R/W Read/Write (input)— This signal determines the direction of data transfer for a read or write cycle in conjunction with DS. CS Chip Select (input, active Low)— This signal selects the device for access and must be asserted for read and write cycles, but is ignored during interrupt acknowledge and fly- by DMA transfers. In the case of a multiplexed bus interface, CS is latched by the rising edge of AS. A/B Channel A/Channel B Select (input)— This signal selects between the two channels in the device. High selects channel A and Low selects channel B. This signal is sampled and the result is latched during the BCR (Bus Configuration Register) write. It programs the sense of the WAIT /RDY signal appropriate for different bus interfaces. D/C Data/Control Select (input)— This signal, when High, provides for direct access to the RDR and TDR. In the case of a multiplexed bus interface, D/C High overrides the address provided to the device. SITACK Status Interrupt Acknowledge (input, active Low)— This signal is a status sig- nal that indicates that an interrupt acknowledge cycle is in progress. The device is capable of returning an interrupt vector that may be encoded with the type of interrupt pending during this acknowledge cycle. This signal is compatible with 680X0 family microproces- sors.
DS007902-0708 P R E L I M I N A R Y Pin Description Z16C30 Product Specification PITACK Pulsed Interrupt Acknowledge (input, active Low)— This signal is a strobe signal that indicates that an interrupt acknowledge cycle is in progress. The device is capa- ble of returning an interrupt vector that may be encoded with the type of interrupt pending during this acknowledge cycle. PITACK may be programmed to accept a single pulse or double pulse acknowledge type. This programming is done in the BCR. With the double pulse type selected, the first PITACK is recognized but no action takes place. The interrupt vector is returned on the second pulse if the no vector option is not selected. The double pulse type is compatible with 8X86 family microprocessors. WAIT/RDY Wait/Data Ready (output, active Low)— This signal serves to indicate when the data is available during a read cycle, when the device is ready to receive data during a write cycle, and when a valid vector is available during an interrupt acknowledge cycle. It may be programmed to function either as a Wait signal or a Ready signal using the state of the A/B pin during the BCR write. When A/B is High during the BCR write, this signal functions as a wait output and thus supports the READY function of 8X86 family micro- processors. When A/B is Low during the BCR write, this signal functions as a ready out- put and thus supports the DTACK function of 680X0 family microprocessors. AD15–AD0 Address/Data Bus (bidirectional, active High, tri-state)— The AD signals carry addresses to, and data to and from, the device. When the 16-bit nonmultiplexed bus is selected, AD15–AD0 carry data to and from the device. Addresses are provided using a pointer within the device that is loaded with the desired register address. When selecting the 8-bit nonmultiplexed bus (without separate address) only AD7–AD0 are used to trans- fer data. The pointer is used for addressing, with AD15–AD8 unused. When selecting the 8-bit nonmultiplexed bus (with separate address), AD7–AD0 are used to transfer data with AD15–AD8 used as address bus. When the 16-bit multiplexed bus is selected, addresses are latched from AD7–AD0 and data transfers are sixteen bits wide. When selecting the 8- bit multiplexed bus (without separate address) only AD7–AD0 are used to transfer addresses and data, with AD15–AD8 unused. When the 8-bit multiplexed bus with sepa- rate address is selected, only AD7–AD0 are used to transfer data, while AD15–AD8 are used as an address bus. INTA, INTB Interrupt Request (outputs, active Low)— These signals indicate that the channel has an interrupt condition pending and is requesting service. These outputs are NOT open-drain. IEIA, IEIB Interrupt Enable In (inputs, active High)— The IEI signal for each channel is used with the accompanying IEO signal to form an interrupt daisy chain. An active IEI indicates that no device having higher priority is requesting or servicing an interrupt. IEOA, IEOB Interrupt Enable Out (outputs, active High)— The IEO signal for each channel is used with the accompanying IEI signal to form an interrupt daisy chain. IEO is Low if IEI is Low, an interrupt is under service in the channel, or an interrupt is pending during an interrupt acknowledge cycle. TxACKA, TxACKB Transmit Acknowledge (inputs or outputs, active Low)— The pri- mary function of these signals is to perform fly-by DMA transfers to the transmit FIFOs. They may also be used as bit inputs or outputs.
DS007902-0708 P R E L I M I N A R Y Pin Description Z16C30 Product Specification RxACKA, RxACKB Receive Acknowledge (inputs or outputs, active Low)— The pri- mary function of these signals is to perform fly-by DMA transfers from the receive FIFOs. They may also be used as bit inputs or outputs. TxDA, TxDB Transmit Data (outputs, active High, tri-state)— These signals carry the serial transmit data for each channel. RxDA, RxDB Receive Data (inputs, active High)— These signals carry the serial receive data for each channel. TxCA, TxCB Transmit Clock (inputs or outputs, active Low)— These signals are used as clock inputs for any of the functional blocks within the device. They may also be used as outputs for various transmitter signals or internal clock signals. RxCA, RxCB Receive Clock (inputs or outputs, active Low)— These signals are used as clock inputs for any of the functional blocks within the device. They may also be used as outputs for various receiver signals or internal clock signals. TxREQA, TxREQB Transmit Request (inputs or outputs, active Low)— The primary function of these signals is to request DMA transfers to the transmit FIFOs. They may also be used as simple inputs or outputs. RxREQA, RxREQB Receive Request (inputs or outputs, active Low)— The primary function of these signals is to request DMA transfers from the receive FIFOs. They may also be used as simple inputs or outputs. CTSA, CTSB Clear To Send (inputs or outputs, active Low)— These signals are used as enables for the respective transmitters. They may also be programmed to generate inter- rupts on either transition or used as simple inputs or outputs. DCDA, DCDB Data Carrier Detect (inputs or outputs, active Low)— These signals are used as enables for the respective receivers. They may also be programmed to generate interrupts on either transition or used as simple inputs or outputs.
Electrical Characteristics
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Standard Test Conditions The DC Characteristics and Capacitance section below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive cur- rent flows into the referenced pin (Figure 5 on page 11). Standard conditions are as fol- lows:
- GND = 0 V
- TA as specified in Ordering Information on page 97
Table 2. Absolute Maximum Ratings *Voltage on all pins with respect to GND.†See Ordering Information on page 97.
Figure 5. Test Load Diagram Table 3. Capacitance COUT Output Capacitance 15 pF Returned to Ground. Note: f = 1 MHz over specified temperature range.
Table 4. Z16C30 DC Characteristics Note: VCC= 5 V ±10% unless otherwise specified, over specified temperature range. Table 5. Z16C30 AC Characteristics
1 Tcyc Bus Cycle Time 110 ns
2 TwASl AS
3 TwASh AS High Width 60 ns
4 TwDSl DS Low Width 60 ns
5 TwDSh DS High Width 50 ns
6 TdAS(DS) AS Rise to DS Fall Delay
7 TdDS(AS) DS Rise to AS Fall Delay
8 TdDS(DRa) DS Fall to Data Active Delay 0 ns
9 TdDS(DRv) DS Fall to Data Valid Delay 60 ns
10 TdDS(DRn) DS Rise to Data Not Valid
11 TdDS(DRz) DS Rise to Data Float Delay 20 ns
12 TsCS(AS) CS to AS Rise Setup Time 15 ns
13 ThCS(AS) CS to AS Rise Hold Time 5 ns
14 TsADD(AS) Direct Address to AS Rise
15 ThADD(AS) Direct Address to AS Rise
16 TsSIA(AS) SITACK to AS Rise Setup
17 ThSIA(AS) SITACK to AS Rise Hold
18 TsAD(AS) Address to AS Rise Setup
19 ThAD(AS) Address to AS Rise Hold
20 TsRW(DS) R/W to DS Fall Setup Time 0 ns
21 ThRW(DS) R/W to DS Fall Hold Time 25 ns
22 TsDSf(RRQ) DS Fall to RxREQ Inactive
23 TdDSr(RRQ) DS Rise to RxREQ Active
24 TsDW(DS) Write Data to DS Rise Setup
25 ThDW(DS) Write Data to DS Rise Hold
26 TdDSf(TRQ) DS Fall to TxREQ Inactive
27 TdDSr(TRQ) DS Rise to TxREQ Active
28 TwRDl RD Low Width 60 ns
29 TwRDh RD High Width 50 ns
30 TdAS(RD) AS Rise to RD Fall Delay
31 TdRD(AS) RD Rise to AS Fall Delay
32 TdRD(DRa) RD Fall to Data Active Delay 0 ns
33 TdRD(DRv) RD Fall to Data Valid Delay 60 ns
34 TdRD(DRn) RD Rise to Data Not Valid
Table 5. Z16C30 AC Characteristics (Continued)
35 TdRD(DRz) RD Rise to Data Float Delay 20 ns
36 TdRDf(RRQ) RD Fall to RxREQ Inactive
37 TdRDr(RRQ) RD Rise to RxREQ Active
38 TwWRl WR Low Width 60 ns
39 TwWRh WR High Width 50 ns
40 TdAS(WR) AS Rise to WR Fall Delay
41 TdWR(AS) WR Rise to AS Fall Delay
42 TsDW(WR) Write Data to WR Rise Setup
43 ThDW(WR) Write Data to WR Rise Hold
44 TdWRf(TRQ) WR Fall to TxREQ Inactive
45 TdWRr(TRQ) WR Rise to TxREQ Active
46 TsCS(DS) CS to DS Fall Setup Time 0 ns 2
47 ThCS(DS) CS to DS Fall Hold Time 25 ns 2
48 TsADD(DS) Direct Address to DS Fall
49 ThADD(DS) Direct Address to DS Fall
50 TsSIA(DS) SITACK to DS Fall Setup
51 ThSIA(DS) SITACK to DS Fall Hold Time 25 ns 2
52 TsCS(RD) CS to RD Fall Setup Time 0 ns 2
53 ThCS(RD) CS to RD Fall Hold Time 25 ns 2
54 TsADD(RD) Direct Address to RD Fall
55 ThADD(RD) Direct Address to RD Fall
56 TsSIA(RD) SITACK to RD Fall Setup
57 ThSIA(RD) SITACK to RD Fall Hold Time 25 ns 2
58 TsCS(WR) CS to WR Fall Setup Time 0 ns 2
59 ThCS(WR) CS to WR Fall Hold Time 25 ns 2
60 TsADD(WR) Direct Address to WR Fall
61 ThADD(WR) Direct Address to WR Fall
62 TsSIA(WR) SITACK to WR Fall Setup
63 ThSIA(WR) SITACK to WR Fall Hold
64 TwRAKl RxACK Low Width 60 ns
65 TwRAKh RxACK High Width 50 ns
66 TdRAK(DRa) RxACK Fall to Data Active
67 TdRAK(DRv) RxACK Fall to Data Valid
68 TdRAK(DRn) RxACK Rise to Data Not
69 TdRAK(DRz) RxACK Rise to Data Float
70 TdRAKf(RRQ) RxACK Fall to RxREQ
71 TdRAKr(RRQ) RxACK Rise to RxREQ
72 TwTAKl TxACK Low Width 60 ns
73 TwTAKh TxACK High Width 50 ns
74 TsDW(TAK) Write Data to TxACK Rise
75 ThDW(TAK) Write Data to TxACK Rise
76 TdTAKf(TRQ) TxACK Fall to TxREQ
77 TdTAKr(TRQ) TxACK Rise to TxREQ Active
78 TdDSf(RDY) DS Fall (INTACK) to RDY Fall
79 TdRDY(DRv) RDY Fall to Data Valid Delay 40 ns
80 TdDSr(RDY) DS Rise to RDY Rise Delay 40 ns
81 TsIEI(DSI) IEI to DS Fall (INTACK)
82 ThIEI(DSI) IEI to DS Rise (INTACK) Hold
83 TdIEI(IEO) IEI to IEO Delay 30 ns
84 TdAS(IEO) AS Rise (Intack) to IEO Delay 60 ns
85 TdDSI(INT) DS Fall (INTACK) to INT
87 TdDSI(Wr) DS Fall (INTACK) to WAIT
88 TdW(DRv) WAIT Rise to Data Valid
89 TdRDf(RDY) RD Fall (INTACK) to RDY
90 TdRDr(RDY) RD Rise to RDY Rise Delay 40 ns
91 TsIEI(RDI) IEI to RD Fall (INTACK)
92 ThIEI(RDI) IEI to RD Rise (INTACK) Hold
93 TdRDI(INT) RD Fall (INTACK) to INT
94 TdRDI(Wf) RD Fall (INTACK) to WAIT
95 TdRDI(Wr) RD Fall (INTACK) to WAIT
96 TwPIAl PITACK Low Width 60 ns
97 TwPIAh PITACK High Width 50 ns
98 TdAS(PIA) AS Rise to PITACK Fall
99 TdPIA(AS) PITACK Rise to AS Fall
100 TdPIA(DRa) PITACK Fall to Data Active
101 TdPIA(DRn) PITACK Rise to Data Not
102 TdPIA(DRz) PITACK Rise to Data Float
103 TsIEI(PIA) IEI to PITACK Fall Setup
104 ThIEI(PIA) IEI to PITACK Rise Hold
105 TdPIA(IEO) PITACK Fall to IEO Delay 60 ns
106 TdPIA(INT) PITACK Fall to INT Inactive
107 TdPIAf(RDY) PITACK Fall to RDY Fall
108 TdPIAr(RDY) PITACK Rise to RDY Rise
109 TdPIA(Wf) PITACK Fall to WAIT Fall
110 TdPIA(Wr) PITAC K Fall to WAIT Rise
111 TdSIA(INT) SITACK Fall to IEO Inactive
112 TwSTBh Strobe High Width 50 ns 3
113 TwRESl RESET Low Width 170 ns
114 TwRESh RESET High Width 60 ns
115 Tdres(STB) RESET Rise to STB Fall 60 ns 3
116 TdDSf(RDY) DS Fall to RDY Fall Delay 50 ns
117 TdWRf(RDY) WR Fall to RDY Fall Delay 50 ns
118 TdWRr(RDY) WR Rise to RDY Rise Delay 40 ns
119 TdRDf(RDY) RD Fall to RDY Fall Delay 50 ns
120 TdRAKf(RDY) RxACK Fall to RDY Fall
121 TdRAKr(RDY) RxACK Rise to RDY Rise
122 TdTAKf(RDY) TxACK Fall to RDY Fall
sary setup hold and delay times.
123 TdTAKr(RDY) TxACK Rise to RDY Rise
- Direct address is any of A/B, D/C, or AD15–AD8 used as an address bus.
- The parameter applies only when AS is not present.
- Strobe (STB) is any of DS, RD, WR, PITACK, RxACK or TxACK.
- Parameter applies only if read empties the receive FIFO.
- Parameter applies only if write fills the transmit FIFO.
- For extended temperature part TdDSI(Wf) max = 220 ns.
- For extended temperature part TdDSF(TRQ) max = 75 ns.
Figure 6. Reset Timing
Figure 9. DMA Write Cycle
Figure 10. Multiplexed DS Read Cycle
Figure 11. Multiplexed DS Write Cycle
Figure 12. Multiplexed RD Read Cycle
Figure 13. Multiplexed WR Write Cycle
Figure 14. Nonmultiplexed DS Read Cycle
Figure 15. Nonmultiplexed DS Write Cycle
Figure 16. Nonmultiplexed RD Read Cycle
Figure 17. Nonmultiplexed WR Write Cycle
Figure 18. Multiplexed DS Interrupt Acknowledged Cycle
Figure 19. Multiplexed RD Interrupt Acknowledge Cycle
Figure 20. Multiplexed Pulsed Interrupt Acknowledge Cycle
Figure 21. Nonmultiplexed DS Interrupt Acknowledge Cycle
Figure 22. Nonmultiplexed RD Interrupt Acknowledge Cycle
Figure 23. Nonmultiplexed Pulsed Interrupt Acknowledge Cycle
Figure 24. Multiplexed Double-Pulse Intack Cycle
Figure 25. Nonmultiplexed Double-Pulse Intack Cycle
Table 6 lists Z16C30 General Timing. Table 6. Z16C30 General Timing
1 TsRxD(RxCr) RxD to RxC Rise Setup Time (x1 Mode) 0 ns 1
2 ThRxD(RxCr) RxD to RxC Rise Hold Time (x1 Mode) 40 ns 1
3 TsRxd(RxCf) RxD to RxC Fall Setup Time (x1 Mode) 0 ns 1,3
4 ThRxD(RxCf) RxD to RxC Fall Hold Time (x1 Mode) 40 ns 1,3
5 TsSy(RxC) DCD as SYNC to RxC Rise Setup Time 0 ns 1
6 ThSy(RxC) DCD as SYNC to RxC Rise Hold Time (x1
8 TdTxCr(TxD) TxC Rise to TxD Delay 50 ns 2,3
9 TwRxCh RxC High Width 40 ns 1
11 TcRxC RxC Cycle Time 100 ns 1
12 TwTxCh TxC High Width 40 ns 2
13 TwTxCl TxC Low Width 40 ns 2
14 TcTxC TxC Cycle Time 100 ns 2
15 TwExT DCD or CTS Pulse Width 70 ns
16 TWSY DCD as SYNC Input Pulse Width 70 ns
17 TwCLKh CLK High Width 20 ns 4
18 TwCLKI CLK High Width 20 ns 4
19 TcCLK CLK Cycle Time 50 ns 4
- RxC is RxC or TxC, whichever is supplying the receive clock.
- TxC is TxC or RxC, whichever is supplying the transmit clock.
- Parameter applies only to FM encoding/decoding.
is RxC or TxC, when supplying DPLL, BRG, or CTR clock.
Figure 26. Z16C30 System Timing Note: CLK is RxC or TxC when supplying DPLL, BRG, or CTR clock.
Table 7. Z16C30 System Timing
1 TdRxC(REQ) RxC Rise to RxREQ Valid Delay 100 ns 1
2 TdRxC(RxC) TxC Rise to RxC as Receiver Output Valid Delay 100 ns 1
3 TdRxC(INT) RxC Rise to INT Valid Delay 100 ns 1
4 TdTxC(REQ) TxC Fall to TxREQ Valid Delay 100 ns 2
5 TdTxC(TxC) RxC Fall to TxC as Transmitter Output Valid
6 TdTxC(INT) TxC Fall to INT Valid Delay 100 ns 2
7 TdEXT(INT) CTS , DCD, TxREQ, RxREQ transition to INT
- RxC is RxC or TxC, whichever is supplying the receive clock.
- TxC is TxC or RxC, whichever is supplying the transmit clock.
Figure 27. Bus Configuration Register
DS007902-0708 P R E L I M I N A R Y Functional Description Z16C30 Product Specification Functional Description The functional capabilities of the USC are described from two different points of view: as a data communications device, it transmits and receives data in a wide variety of data communications protocols; as a microprocessor peripheral, the USC offers such features as read/write registers, a flexible bus interface, DMA interface support, and vectored inter- rupts. Data Communications Capabilities The USC provides two independent full-duplex channels programmable for use in any common data communication protocol. The receiver and transmitter modes are com- pletely independent, as are the two channels. Each receiver and transmitter is supported by a 32-byte deep FIFO and a 16-bit message length counter. All modes allow optional even, odd, mark or space parity. Synchronous modes allow the choice of two 16-bit or one 32-bit CRC polynomial. Selection of from one to eight bits-per-character is available in both receiver and transmitter, independently. Error and status conditions are carried with the data in the receive and transmit FIFOs to greatly reduce the CPU overhead required to send or receive a message. Specific, appropriately timed interrupts are available to signal such conditions as overrun, parity error, framing error, end-of-frame, idle line received, sync acquired, transmit underrun, CRC sent, closing sync/flag sent, abort sent, idle line sent, and preamble sent. In addition, several useful internal signals such as receive FIFO load, received sync, transmit FIFO read and transmission complete may be sent to pins for use by external circuitry. Asynchronous Mode— The receiver and transmitter can handle data at a rate of 1/16, 1/ 32, or 1/64 the clock rate. The receiver rejects start bits less than one-half a bit time and will not erroneously assemble characters following a framing error. The transmitter is capable of sending one, two, or anywhere in the range of 1/16 to two stop bits per charac- ter in 1/16 bit increments. External Sync Mode— The receiver is synchronized to the receive data stream by an externally-supplied signal on a pin for custom protocol applications. Isochronous Mode— Both transmitter and receiver may operate on start-stop (async) data using a 1x clock. The transmitter can send one or two stop bits. Asynchronous With Code Violations— This is similar to Isochronous mode except that the start bit is replaced by a three bit-time code violation pattern as in MIL-STD 1553B. The transmitter can send zero, one or two stop bits. Monosync Mode— In this mode, a single character is used for synchronization. The sync character can be either eight bits long with an arbitrary data character length, or pro- grammed to match the data character length. The receiver is capable of automatically stripping sync characters from the received data stream. The transmitter may be pro-
DS007902-0708 P R E L I M I N A R Y Functional Description Z16C30 Product Specification grammed to automatically send CRC on either an underrun or at the end of a programmed message length. Bisync Mode— This mode is identical to monosync mode except that character synchroni- zation requires two successive characters for synchronization. The two characters need not be identical. HDLC Mode— In this mode, the receiver recognizes flags, performs optional address matching, accommodates extended address fields, 8- or 16-bit control fields and logical control fields, performs zero deletion and CRC checking. The receiver is capable of receiving shared-zero flags, recognizes the abort sequence and can receive arbitrary length messages. The transmitter automatically sends opening and closing flags, performs zero insertion and can be programmed to send an abort, an extended abort, a flag or CRC, and a flag on transmit underrun. The transmitter can also automatically send the closing flag with optional CRC at the end of a programmed message length. Shared-zero flags are selected in the transmitter and a separate character length may be programmed for the last character in the frame. Bisync Transparent Mode— In this mode, the synchronization pattern is DLE–SYN, pro- grammable selected from either ASCII or EBCDIC encoding. The receiver recognizes control character sequences and automatically handles CRC calculation without CPU intervention. The transmitter can be programmed to send either SYN, DLE–SYN, CRC– SYN, or CRC–DLE–SYN upon underrun and can automatically send the closing DLE– SYN with optional CRC at the end of a programmed message length. NBIP Mode— This mode is identical to async except that the receiver checks for the status of an additional address/data bit between the parity bit and the stop bit. The value of this bit is FIFO’ed along with the data. This bit is automatically inserted in the transmitter with the value that is FIFO’ed with the transmit data. 802.3 Mode— This mode implements the data format of IEEE 802.3 with 16-bit address compare. In this mode, DCD and CTS are used to implement the carrier sense and colli- sion detect interactions with the receiver and transmitter. Slaved Monosync Mode— This mode is available only in the transmitter and allows the transmitter (operating as though it were in monosync mode) to send data that is byte-syn- chronous to the data being received by the receiver. HDLC Loop Mode— This mode is also available only in the transmitter and allows the USC to be used in an HDLC loop configuration. In this mode, the receiver is programmed to operate in HDLC mode so that the transmitter echoes received messages. Upon receipt of a particular bit pattern (actually a sequence of seven consecutive ones) the transmitter breaks the loop and inserts its own frame(s). Data Encoding The USC may be programmed to encode and decode the serial data in any of eight differ- ent ways as displayed in Figure 28 on page 44. The transmitter encoding method is selected independently of the receiver decoding method.
DS007902-0708 P R E L I M I N A R Y Functional Description Z16C30 Product Specification NRZ— In NRZ, a 1 is represented by a High level for the duration of the bit cell and a 0 is represented by a Low level for the duration of the bit cell. NRZB— Data is inverted from NRZ. NRZI-Mark— In NRZI-Mark, a 1 is represented by a transition at the beginning of the bit cell. That is, the level present in the preceding bit cell is reversed. A 0 is represented by the absence of a transition at the beginning of the bit cell. NRZI-Space— In NRZI-Space, a 1 is represented by the absence of a transition at the beginning of the bit cell. That is, the level present in the preceding bit cell is maintained. A 0 is represented by a transition at the beginning of the bit cell. Biphase-Mark— In Biphase-Mark, a 1 is represented by a transition at the beginning of the bit cell and another transition at the center of the bit cell. A 0 is represented by a transition at the beginning of the bit cell only. Biphase-Space— In Biphase-Space, a 1 is represented by a transition at the beginning of the bit cell only. A 0 is represented by a transition at the beginning of the bit cell and another transition at the center of the bit cell. Biphase-Level— In Biphase-Level, a 1 is represented by a High during the first half of the bit cell and a Low during the second half of the bit cell. A 0 is represented by a Low dur- ing the first half of the bit cell and a High during the second half of the bit cell.
Figure 28. Data Encoding
DS007902-0708 P R E L I M I N A R Y Functional Description Z16C30 Product Specification ically loaded into a four-deep FIFO. This allows DMA transfer of data to proceed without CPU intervention at the end of a received message, as the values in the FIFO allow the CPU to determine message boundaries in memory. Similarly, the transmit character counter is loaded either under software control or automatically at the beginning of a transmit message. The counter is decremented with each write to the transmit FIFO. When the counter has decremented to 0, and that byte is sent, the transmitter automatically termi- nates the message in the appropriate fashion (usually CRC and the closing flag or sync character) without requiring CPU intervention. Baud Rate Generators Each channel in the USC contains two baud rate generators. Each generator consists of a 16-bit time constant register and a 16-bit down counter. In operation, the counter decre- ments with each baud rate generator clock, with the time constant automatically reloaded when the count reaches zero. The output of the baud rate generator toggles when the counter reaches a count of one-half of the time constant and again when the counter reaches zero.A new time constant may be written at any time but the new value will not take effect until the next load of the counter. The outputs of both baud rate generators are sent to the clock multiplexer for use internally or externally. The baud rate generator out- put frequency is related to the baud rate generator input clock frequency by the following equation: Output frequency = Input frequency/(time constant + 1) This allows an output frequency in the range of 1 to 1/65536 of the input frequency, inclu- sive. Digital Phase-Locked Loop Each channel in the USC contains a Digital Phase-Locked Loop (DPLL) to recover clock information from a data stream with NRZI or Biphase encoding. The DPLL is driven by a clock that is nominally 8, 16 or 32 times the receive data rate. The DPLL uses this clock, along the data stream, to construct a clock for the data. This clock may then be routed to the receiver, transmitter, or both, or to a pin for use externally. In all modes, the DPLL counts the input clock to create nominal bit times. As the clock is counted, the DPLL watches the incoming data stream for transitions. Whenever a transition is detected, the DPLL makes a count adjustment (during the next counting cycle), to produce an output clock which tracks the incoming bit cells. The DPLL provides properly phased transmit and receive clocks to the clock multiplexer. Counters Each channel contains two 5-bit counters, which are programmed to divide an input clock by 4, 8, 16, or 32. The inputs of these two counters are sent to the clock multiplexer. The counters are used as prescalers for the baud rate generators, or to provide a stable transmit clock from a common source when the DPLL is providing the receive clock.
DS007902-0708 P R E L I M I N A R Y Functional Description Z16C30 Product Specification Clock Multiplexer The clock multiplexer in each channel selects the clock source for the various blocks in the channel and selects an internal clock signal to potentially be sent to either the RxC or TxC pin. Test Modes The USC can be programmed for local loopback or auto echo operation. In local loopback, the output of the transmitter is internally routed to the input of the receiver. This allows testing of the USC data paths without any external logic. Auto echo connects the RxD pin directly to the TxD pin. This is useful for testing serial links external to the USC. I/O Interface Capabilities The USC offers the choice of polling, interrupt (vectored or nonvectored) and block trans- fer modes to transfer data, status and control information to and from the CPU. Polling All interrupts are disabled. The registers in the USC are automatically updated to reflect current status. The CPU polls the Daisy Chain Control Register (DCCR) to determine sta- tus changes and then reads the appropriate status register to find and respond to the change in status. USC status bits are grouped according to function to simplify this software action. Interrupt When a USC responds to an interrupt acknowledge from the CPU, an interrupt vector may be placed on the data bus. This vector is held in the Interrupt Vector Register (IVR). To speed interrupt response time, the USC modifies three bits in this vector to indicate which type of interrupt is being requested. Each of the six sources of interrupts in each channel of the USC (Receive Status, Receive Data, Transmit Status, Transmit Data, I/O Status, and Device Status) has three bits associ- ated with the interrupt source: Interrupt Pending (IP), Interrupt-Under-Service (IUS), and Interrupt Enable (IE). If the IE bit for a given source is set, that source can request inter- rupts. Note that individual sources within the six groups also have interrupt enable bits which are set for the particular source. In addition, there is a Master Interrupt Enable (MIE) bit in each channel which globally enables or disables interrupts within the channel. The other two bits are related to the interrupt priority chain. A channel in the USC may request an interrupt only when no higher priority interrupt source is requesting one, e.g., when IEI is High for the channel. In this case the channel activates the INT signal. The CPU then responds with an interrupt acknowledge cycle, and the interrupting channel places a vector on the data bus.
DS007902-0708 P R E L I M I N A R Y Functional Description Z16C30 Product Specification In the USC, the IP bit signals that an interrupt request is being serviced. If an IUS is set, all interrupt sources of lower priority within the channel and external to the channel are pre- vented from requesting interrupts. The internal interrupt sources are inhibited by the state of the internal daisy chain, while lower priority devices are inhibited by the IEO output of the channel being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an interrupt acknowledge cycle if there are no higher priority devices requesting interrupts. There are six sources of interrupt in each channel: Receive Status, Receive Data, Transmit Status, Transmit Data, I/O Status, and Device Status, prioritized in that order within the channel. There are six sources of Receive Status interrupt, each individually enabled: exited hunt, idle line, break/abort, code violation/end-of-transmission/end-of-frame, parity error, and overrun error. The Receive Data interrupt is generated whenever the receive FIFO fills with data beyond the level programmed in the Receive Interrupt Control Regis- ter (RICR). There are six sources of Transmit Status interrupt, each individually enabled: preamble sent, idle line sent, abort sent, end-of-frame/end-of-transmission sent, CRC sent, and underrun error. The Transmit Data interrupt is generated whenever the transmit FIFO empties below the level programmed in the Transmit Interrupt Control Register (TICR). The I/O Status interrupt serves to report transitions on any of six pins. Interrupts are gener- ated on either or both edges with separate selection and enables for each pin. The pins pro- grammed to generate I/O Status interrupts are RxC, TxC, RxREQ, TxREQ, DCD, and CTS. These interrupts are independent of the programmed function of the pins. The Device Status interrupt has four separately enabled sources: receive character count FIFO overflow, DPLL sync acquired, BRG1 zero count, and BRGO zero count. Block Transfer Mode The USC accommodates block transfers through DMA through the RxREQ, TxREQ, RxACK, and TxACK pins. The RxREQ signal is activated when the fill level of the receive FIFO exceeds the value programmed in the RICR. The DMA may respond with either a normal bus transaction or by activating the RxACK pin to read the data directly (fly-by transfer). The TxREQ signal is activated when the empty level of the transmit FIFO falls below the value programmed in the TICR. The DMA may respond either with a normal bus transaction or by activating the TxACK pin to write the data directly (fly-by transfer). The RxACK and TxACK pin functions for this mode are controlled by the Hard- ware Configuration Register (HCR). Then using the RxACK and TxACK pins to transfer data, no chip select is necessary; these are dedicated strobes for the appropriate FIFO. Programming The registers in each USC channel are programmed by the system to configure the chan- nels. Before this can occur, however, the system must program the bus interface by writing to the Bus Configuration Register (BCR). The BCR has no specific address and is only
because the first write after a hardware reset is automatically programmed for the BCR. AD6–AD0 or AD7–AD1. This is controlled by the Shift Right/Shift Left bit in the BCR. the address pointer in the Channel Command/Address Register (CCAR) in each channel.
- The Channel Reset bit in the CCAR places the channel in the reset state. To exit this
of all zeros must be written to the lower byte of the CCAR (8-bit bus).
- After reset, the transmit and receive clocks are not connected. The first thing that
Register (CMCR) to select a clock source for the receiver and transmitter. registers are displayed in Figure 29. Table 8. Multiplexed Bus Address Assignments
Figure 29. BCR Reset Sequence and Bit Assignments and including the BCR write, chooses a multiplexed type of bus.
Table 9. Register Address List
00000 CCAR Channel Command/Address
00001 CMR Channel Mode Register
00010 CCSR Channel Command/Status Register
00011 CCR Channel Control Register
00110 TMDR Test Mode Data Register
00111 TMCR Test Mode Control Register
01000 CMCR Clock Mode Control Register
01001 HCR Hardware Configuration Register
01010 IVR Interrupt Vector Register
01011 IOCR I/O Control Register
01100 ICR Interrupt Control Register
01101 DCCR Daisy-Chain Control Register
01110 MISR Misc Interrupt Status Register
01111 SICR Status Interrupt Control Register
10001 RMR Receive Mode Register
10010 RCSR Receive Command/Status Register
10011 RICR Receive Interrupt Control Register
10100 RSR Receive Sync Register
10101 RCLR Receive Count Limit Register
10110 RCCR Receive Character Count Register
10111 TC0R Time Constant 0 Register
11001 TMR Transmit Mode Register
11010 TCSR Transmit Command/Status Register
11011 TICR Transmit Inte rrupt Control Register
11100 TSR Transmit Sync Register
11101 TCLR Transmit Count Limit Register
11110 TCCR Transmit Character Count Register
11111 TC1R Time Constant 1 Register
Figure 30. Channel Command/Address Register
Figure 31. Channel Mode Register
Figure 32. Channel Mode Register, Asynchronous Mode
11 R e s e r v e d
00 O n e S t o p B i t
Figure 35. Channel Mode Register, Asynchronous Mode with
0000 A s y n c h r o n o u s w i t h C V Transmitter
Figure 36. Channel Mode Register, Monosync Mode
Figure 37. Channel Mode Register, Bisync Mode
Figure 38. Channel Mode Register, HDLC Mode
0110 H D L C
00 A b o r t
10 F l a g
00 D i s a b l e d
Figure 39. Channel Mode Register, Transparent Bisync Mode
0111 T r a n s p a r e n t B i s y n c
00 S Y N
Figure 40. Channel Mode Register, NBIP Mode
1000 N B I P
Figure 41. Channel Mode Register, 802.3 Mode
Figure 42. Channel Mode Register, Slaved Monosync Mode
Figure 43. Channel Mode Register, HDLC Loop Mode
Figure 44. Channel Command/Status Register
Figure 45. Channel Control Register Figure 46. Primary Reserved Register
00 N o S t a t u s B l o c k
Figure 49. Test Mode Control Register
00010 C R C B y t e 0
00011 C R C B y t e 1
01000 D P L L S t a t u s
01010 C R C B y t e 2
01011 C R C B y t e 3
Figure 50. Clock Mode Control Register
000 D i s a b l e d
110 C T R 0 O u t p u t
00 C T R 0 O u t p u t
01 C T R 1 O u t p u t
11 T x C P i n
01 D i s a b l e d
Figure 51. Hardware Configuration Register
01 N R Z / N R Z I
Figure 52. Interrupt Vector Register
000 N o n e
Figure 53. I/O Control Register
000 I n p u t P i n
111 D P L L O u t p u t
10 O u t p u t 0
11 O u t p u t 1
Figure 54. Interrupt Control Register
000 A l l
001 A l l
10 R e s e t I E
11 S e t I E
Figure 55. Daisy-Chain Control Register
10 R e s e t I P
11 S e t I P
10 R e s e t I U S
11 S e t I U S
Figure 56. Miscellaneous Interrupt Status Register
Figure 57. Status Interrupt Control Register
01 B o t h E d g e s
Figure 58. Receive Data Register
Figure 59. Receive Mode Register
00 E v e n
01 O d d
11 M a r k
000 N R Z
Figure 60. Receive Command Status Register
0000 N u l l C o m m a n d
0001 R e s e r v e d
0100 R e s e r v e d
1000 R e s e r v e d
1001 R e s e r v e d
1010 R e s e r v e d
1011 R e s e r v e d
1100 R e s e r v e d
1101 R e s e r v e d
1110 R e s e r v e d
1111 R e s e r v e d
Figure 61. Receive Interrupt Control Register
Figure 62. Receive Sync Register
Figure 63. Receive Count Limit Register
Figure 64. Receive Character Count Register
Figure 65. Time Constant 0 Register
Figure 66. Transmit Data Register
Figure 67. Transmit Mode Register
Figure 68. Transmit Command/Status Register
0010 P r e s e t C R C
1001 Send Abort
1010 Reserved
1011 Reserved
1100 Reset DLE Inhibit
1101 Set DLE Inhibit
1110 Reset EOF/EOM
1111 Set EOT/EOM
Figure 69. Transmit Interrupt Control Register
Figure 70. Transmit Sync Register
Figure 71. Transmit Count Limit Register
Figure 72. Transmit Character Count Register
Figure 73. Time Constant 1 Register
Figure 74. Receive Status Block Register
Figure 75. Transmit Status Block Register
Figure 76. Bus Configuration Register *Must be programmed as zero.
Ordering Information
Order the Z16C30 Series from Zilog®, using the following part numbers. For more infor- mation on ordering, consult your local Zilog sales office. The Zilog website (www.zilog.com) lists all regional offices and provides additional Z16C30 product infor- mation. For fast results, contact your local Zilog® sales office for assistance in ordering the part desired. Codes Z16C30 (10 MHz) 68-Pin PLCC Z16C3010VSC Z 16C30 10 V S C Environmental Flow C= Plastic Standard Flow Temperature Range S = 0 °C to 70 °C (Standard) Package V= Plastic Leaded Chip Carrier Speed 10= 10 MHz Product Number 16C30 Zilog ® Prefix
DS007902-0708 P R E L I M I N A R Y Customer Support Z16C30 Product Specification Customer Support For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at http://support.zilog.com.