25X10BVNIG

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Publication Release Date: August 20,, 2009 - 1 - P r e l i m i n a r y - - R e v i s i o n B 1M-BIT, 2M-BIT AND 4M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI

• 2 - Table of Contents 9.1

ication Release Date: August 20, 2009 - 3 - P r e l i m i n a r y - - R e v i s i o n B

9.2.9 Fast Read Dual Output (3Bh)

11.1

• 4 - 1. GENERAL DESCRIPTION The W25X10BV (1M-bit), W25X20BV (2M-bit) and t he W25X40BV (4M-bit) Serial Flash memories provides a storage solution for systems with limit ed space, pins and power. The 25X series offers flexibility and performance well beyond ordinary Seri al Flash devices. They are ideal for code download applications as well as storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space-saving packages. The W25X10BV/20BV/40BV arrays are organized into 512/1,024/2,048 programmable pages of 256- bytes each. Up to 256 bytes can be programmed at a time using the Page Program instruction. Pages can be erased in groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (block erase) or the entire chip (chip erase). T he W25X10BV/20BV/40BV has 32/64/128 erasable sectors and 2/4/8 erasable 64KB blocks respectively. The sma ll 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25X10BV/20BV/40BV supports the standard Serial Peripheral Interface (SPI), and a high performance dual output as well as Dual I/O SPI: Serial Clock, Chip Select, Serial Data DI (I/O0), DO (I/O1). SPI clock frequencies of up to 104MHz ar e supported allowing equivalent clock rates of 208MHz when using the Fast Read Dual Output inst ruction. These transfer rates are comparable to those of 8 and 16-bit Parallel Flash memories. A Hold pin, Write Protect pin and programmable wr ite protect, with top or bottom array control features, provide further control flexibility. Additionally, the devic e supports JEDEC standard manufacturer and device identification. 2. FEATURES  Family of Serial Flash Memories – W25X10BV: 1M-bit/128K-byte (131,072) – W25X20BV: 2M-bit/256K-byte (262,144) – W25X40BV: 4M-bit/512K-byte (524,288) – 256-bytes per programmable page – Unif orm 4KB Sectors, 32KB & 64KB Blocks  SPI with Single / Dual Outputs / Dual I/O – Clock, Chip Select, Data I/O, Data Out – Optional Hold function for SPI flexibility  Data Transfer up to 208M-bits / second – Clock operation to 104MHz – Fast Read Dual Output instruction – Auto-increment Read capability  Efficient “Continuous Read Mode” – Low Instruction overhead – Continuous Read – As few as 8 clocks to address memory – Allows true XIP (execute in place) operation  Softw are and Hardware Write Protection – Write-Protect all or portion of memory – Enable/Disable protection with /WP pin – Top or bottom array protection  Flexible Architecture w ith 4KB sectors – Sector Erase (4K-bytes) – Block Erase (32K and 64K-byte) – Page program up to 256 bytes <1ms More than 100,000 erase/write cycles – More than 20-year retention  Low Power Consumption, Wide Temperature Range – Single 2.7 to 3.6V supply – 4mA active current, 1µA Power-down (typ) – -40° to +85°C operating range  Space Efficient Packaging – 8-pin SOIC 150-mil – 8-pin SOIC 208-mil – 8-pad WSON 6x5-mm – 8-pin PDIP 300-mil

• 6 - 5. PIN CONFIGURATION PDIP 300-MIL Figure 1c. W25X40BV Pin Assignments, 8-pin PDIP (Package Code DA) 6. PIN DESCRIPTION SOIC 150 / 208-MIL, PDIP 300-MIL, WSON 6X5-MM PIN NO. PIN NAME I/O FUNCTION 1 /CS I Chip Select Input

2 DO (IO1) O Data Input / Output

3 /WP I Write Protect Input

4 GND Ground

5 DIO (IO0) I/O Data Input / Output

6 CLK I Serial Clock Input

8 VCC Power Supply

Publication Release Date: August 20, 2009 - 7 - P r e l i m i n a r y - - R e v i s i o n B

6.1 Package Types

W25X10BV/20BV/40BV are offered in an 8-pin pl astic 150-mil width SOIC (package code SN) and 6x5-mm WSON (package code ZP), see figures 1a and 1b, respectively. The W25X40BV is offered in the 208-mil width SOIC (package code SS) and the 300-mil 8-pin PDIP (package code DA), see figure 1c. Package diagrams and dimensions are illustrated at the end of this datasheet.

6.2 Chip Select (/CS)

The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices power consumption will be at standby levels unless an in ternal erase, program or status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new inst ruction will be accepted. The /CS input must track the VCC supply level at power-up (see “Write Protection” and Figure 25). If needed a pull-up resister on /CS can be used to accomplish this.

6.3 Serial Data Input, Output and IOs (DI, DO, IO0 and IO1)

The W25X10BV/20BV/40BV supports standard SPI and Dual SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK ) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.

6.4 Write Protect (/WP)

The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Pr otect (BP2, BP1, and BP0) bits and Status Register Protect (SRP) bit, a portion or the entire memory array can be hardware protected. The /WP pin is active low.

6.5 HOLD (/HOLD)

The Hold (/HOLD) pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DIO and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. (“See Hold function”)

6.6 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. (“See SPI Operations”)

• Block 0 (64KB) • 000000h 0000FFh 03FF00h 03FFFFh
• Block 3 (64KB) • 030000h 0300FFh 04FF00h 04FFFFh
• Block 4 (64KB) • 040000h 0400FFh 07FF00h 07FFFFh
• Block 7 (64KB) • 070000h 0700FFh Column Decode And 256-Byte Page Buffer Beginning Page Address Ending Page Address W25X40BV SPI Command & Control Logic Byte Address Latch / Counter Status Register Write Control Logic Page Address Latch / Counter DO (IO1) DIO (IO0) /CS CLK /HOLD /WP High Voltage Generators xx0F00h xx0FFFh
• Sector 0 (4KB) • xx0000h xx00FFh xx1F00h xx1FFFh
• Sector 1 (4KB) • xx1000h xx10FFh xx2F00h xx2FFFh
• Sector 2 (4KB) • xx2000h xx20FFh xxDF00h xxDFFFh
• Sector 13 (4KB) • xxD000h xxD0FFh xxEF00h xxEFFFh
• Sector 14 (4KB) • xxE000h xxE0FFh xxFF00h xxFFFFh
• Sector 15 (4KB) • xxF000h xxF0FFh Block Segmentation Data Write Protect Logic and Row Decode 01FF00h 01FFFFh
• Block 1 (64KB) • 010000h 0100FFh W25X20BV W25X10BV

Figure 2. W25X10BV/20BV/40BV Block Diagram

Publication Release Date: August 20, 2009 - 9 - P r e l i m i n a r y - - R e v i s i o n B 8. FUNCTIONAL DESCRIPTION

8.1 SPI OPERATIONS

8.1.1 Standard SPI Instructions

The W25X10BV/20BV/40BV are accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions , addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge CLK. SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3 the CL K signal is normally high on the falling and rising edges of /CS..

8.1.2 Dual SPI Instructions

The W25X10BV/20BV/40BV supports Dual SPI operat ion when using the “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading c ode to RAM upon power-up (code-shadowing) or for executing non-speed-critical code dire ctly from the SPI bus (XIP). W hen using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.

8.1.3 Hold Function

The /HOLD signal allows the W25X10BV/20BV/40BV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if t he CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (D O) is high impedance, and Serial Data Input/Output (DIO) and Serial Clock (CLK) are ignor ed. The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device.

• 10 -

8.2 WRITE PROTECTION

Applications that use non-volatile memory must ta ke into consideration the possibility of noise and other adverse system conditions that may compromi se data integrity. To address this concern the W25X10BV/20BV/40BV provides several means to protect data from inadvertent writes.

8.2.1 Write Protect Features

 Device resets when VCC is below threshold.  Time delay write disable after Power-up.  Write enable/disable instructions.  Automatic write disable after program and erase.  Software write protection using Status Register.  Hardware write protection using Status Register and /WP pin.  Write Protection using Power-down instruction. Upon power-up or at power-down the W25X10BV/20 BV/40BV will maintain a reset condition while VCC is below the threshold value of V WI, (See Power-up Timing and Voltage Levels and Figure 25). While reset, all operations are disabled and no instru ctions are recognized. During power-up and after the VCC voltage exceeds V WI, all program and erase related instructions are further disabled for a time delay of t PUW. This includes the Write Enable, Page Progr am, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If needed a pull- up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Chip Erase or Write Stat us Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WE L) is automatically cleared to a write-disabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP) and Block Pr otect (TB, BP2, BP1, and BP0) bits. These Status Register bits allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to t he Status Register can be enabled or disabled under hardware control. See Status Register for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction.

Publication Release Date: August 20, 2009 - 1 1 - P r e l i m i n a r y - - R e v i s i o n B 9. CONTROL AND STATUS REGISTERS The Read Status Register instruction can be used to provide status on the av ailability of the Flash memory array, if the device is write enabled or dis abled, and the state of writ e protection. The Write Status Register instruction can be used to configure the device write protection features. See Figure 3.

9.1 STATUS REGISTER

9.1.1 BUSY

BUSY is a read only bit in the status register (S0) t hat is set to a 1 state w hen the device is executing a Page Program, Sector Erase, Block Erase, Chip Er ase or Write Status Register instruction. During this time the device will ignore further instructions except for the Read Status Register instruction (see tW, t PP, t SE, t BE, and t CE in AC Characteristics). When the progr am, erase or write status register instruction has completed, the BUSY bit will be clear ed to a 0 state indicating the device is ready for further instructions.

9.1.2 Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a Write Enable Instruction. The WE L status bit is cleared to a 0 w hen the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.

9.1.3 Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, and BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see t W in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Regi ster Memory Protection table). The factory default setting for the Block Protec tion Bits is 0, none of the array protected. The Block Protect bits can not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low.

9.1.4 Top/Bottom Block Protect (TB)

The Top/Bottom bit (TB) controls if the Block Pr otect Bits (BP2, BP1, BP0 ) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The TB bit is non-volatile and the factory default setti ng is TB=0. The TB bit can be set with the Write Status Register Instruction provided that the Write Enable instruction has been issued. The TB bit can not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low.

9.1.5 Reserved Bits

Status register bit location S6 is reserved for fu ture use. Current devices will read 0 for this bit location. It is recommended to mask out the reserved bit when testing the Status Register. Doing this will ensure compatibility with future devices.

9.1.6 Status Register Protect (SRP)

/WP pin is high the Write Status Register instruction is allowed. Figure 3. Status Register Bit Locations

Publication Release Date: August 20, 2009 - 1 3 - P r e l i m i n a r y - - R e v i s i o n B

9.1.7 Status Register Memory Protection

STATUS REGISTER(1) W25X40BV (4M-BIT) MEMORY PROTECTION TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION x 0 0 0 NONE NONE NONE NONE 0 0 0 1 7 070000h - 07FFFFh 64KB Upper 1/8 0 0 1 0 6 and 7 060000h - 07FFFFh 128KB Upper 1/4 0 0 1 1 4 thru 7 040000h - 07FFFFh 256KB Upper 1/2 1 0 0 1 0 000000h - 00FFFFh 64KB Lower 1/8 1 0 1 0 0 and 1 000000h - 01FFFFh 128KB Lower 1/4 1 0 1 1 0 thru 3 000000h - 03FFFFh 256KB Lower 1/2 x 1 x x 0 thru 7 000000h - 07FFFFh 512KB ALL STATUS REGISTER(1) W25X20BV (2M-BIT) MEMORY PROTECTION TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION x x 0 0 NONE NONE NONE NONE 0 x 0 1 3 030000h - 03FFFFh 64KB Upper 1/4 0 x 1 0 2 and 3 020000h - 03FFFFh 128KB Upper 1/2 1 x 0 1 0 000000h - 00FFFFh 64KB Lower 1/4 1 x 1 0 0 and 1 000000h - 01FFFFh 128KB Lower 1/2 x x 1 1 0 thru 3 000000h - 03FFFFh 256KB ALL STATUS REGISTER(1) W25X10BV (1M-BIT) MEMORY PROTECTION TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION x x 0 0 NONE NONE NONE NONE 0 x 0 1 1 010000h - 01FFFFh 64KB Upper 1/2 1 x 0 1 0 000000h - 00FFFFh 64KB Lower 1/2 x x 1 x 0 and 1 000000h - 01FFFFh 128KB ALL Note: 1. x = don’t care

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9.2 INSTRUCTIONS

The instruction set of the W25X10BV/20BV/40BV consis ts of nineteen basic instructions that are fully controlled through the SPI bus (see Instruction Set t able). Instructions are initiated with the falling edge of Chip Select (/CS). The firs t byte of data clocked into the DI O input provides the instruction code. Data on the DIO input is sampled on the rising edge of clock with most significant bit (MSB) first. Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some ca ses, a combination. Inst ructions are completed with the rising edge of edge /CS. Clock relative ti ming diagrams for each instruction are included in figures 4 through 24. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a full 8-bits have been clocked) otherwise the instructi on will be terminated. This feature further protects the device from inadvertent writes . Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all inst ructions except for Read Status Register will be ignored until the program or erase cycle has completed.

9.2.1 Manufacturer and Device Identification

MANUFACTURER ID (M7-M0) Winbond Serial Flash EFh Device ID (ID7-ID0) (ID15-ID0) Instruction ABh, 90h, 92h 9Fh W25X10BV 10h 3011h W25X20BV 11h 3012h W25X40BV 12h 3013h

Publication Release Date: August 20, 2009 - 1 5 - P r e l i m i n a r y - - R e v i s i o n B

9.2.2 Instruction Set (1)

BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 N-BYTES Write Enable 06h Write Disable 04h Read Status Register 05h (S7–S0) (1) (2) Write Status Register 01h S7–S0 Read Data 03h A23–A16 A15–A8 A7–A0 (D7–D0) (Next byte) continuous Fast Read 0Bh A23–A16 A15–A8 A7–A0 dummy (D7–D0) (Next Byte) continuous Fast Read Dual Output 3Bh A23–A16 A15–A8 A7–A0 dummy (D7-D0, …) (5) (one byte per 4 clocks, continuous) Fast Read Dual I/O BBh A23-A8 (6) A7-A0, M7- (6) (D7-D0, …) (5) Page Program 02h A23–A16 A15–A8 A7–A0 (D7–D0) (Next byte) Up to 256 bytes Sector Erase (4KB) 20h A23–A16 A15–A8 A7–A0 Block Erase (32KB) 52h A23–A16 A15–A8 A7–A0 Block Erase (64KB) D8h A23–A16 A15–A8 A7–A0 Chip Erase C7h/60h Power-down B9h Release Power- down / Device ID ABh dummy dummy dummy (ID7-ID0) (4) Manufacturer/ Device ID (3) 90h dummy dummy 00h (M7-M0) (ID7-ID0) Manufacturer/Device ID by Dual I/O 92h A23-A8 A7-A0, M[7:0] (MF[7:0], ID[7:0]) JEDEC ID 9Fh (M7-M0) Manufacturer (ID15-ID8) Memory Type (ID7-ID0) Capacity Read Unique ID 4Bh dummy dummy dummy dummy (ID63-ID0) Read Unique ID Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the device on the DO pin. 2. The Status Register contents will repeat continuously until /CS terminates the instruction. 3. See Manufacturer and Device Identification table for Device ID information. 4. The Device ID will repeat continuously until /CS terminates the instruction. 5. Dual Output and Dual I/O data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 6. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1

9.2.3 Write Enable (06h)

Figure 4. Write Enable Instruction Sequence Diagram

9.2.4 Write Disable (04h)

Figure 5. Write Disable Instruction Sequence Diagram

9.2.5 Read Status Register (05h)

continuously, as shown in Figure 6. The instruction is completed by driving /CS high. Figure 6. Read Status Register Instruction Sequence Diagram

9.2.6 Write Status Register (01h)

Status Register instruction. cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. high the Write Status Register instruction is allowed. Figure 7. Write Status Register Instruction Sequence Diagram

9.2.7 Read Data (03h)

R (see AC Electrical Characteristics). Figure 8. Read Data Instruction Sequence Diagram

9.2.8 Fast Read (0Bh)

data value on the DIO pin is a “don’t care”. Figure 9. Fast Read Instruction Sequence Diagram

applications that cache code-segments to RAM for execution. Figure 10. Fast Read Dual Output Instruction Sequence Diagram

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9.2.10 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Out put (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per cl ock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. Fast Read Dual I/O with “Continuous Read Mode” The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 11a. The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the firs t byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), t hen the next Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require t he BBh instruction code, as shown in figure 11b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (See 9.2.12 for detail descriptions). Figure 11a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4  10)

Publication Release Date: August 20, 2009 - 2 3 - P r e l i m i n a r y - - R e v i s i o n B Figure 11b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10)

9.2.11 Continuous Read Mode Bits (M7-0)

allow true XIP (execute in place) to be performed on serial flash devices. accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be used.

9.2.12 Continuous Read Mode Reset (FFFFh)

Continuous Read Mode and return to normal SPI operation, as shown in figure 12. Figure 12. Continuous Read Mode Reset for Fast Read Dual I/O SPI instructions to be recognized.

9.2.13 Page Program (02h)

length of the instruction while data is being sent to the device. wrap to the beginning of the page and overwrite previously sent data. Figure 13. Page Program Instruction Sequence Diagram

9.2.14 Sector Erase (20h)

2). The Sector Erase instruction sequence is shown in figure 14. BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 14. Sector Erase Instruction Sequence Diagram

pin low and shifting the instruction code “52h” followed a 24-bit block address (A23-A0) (see Figure 2). The Block Erase instruction sequence is shown in figure 15. BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 15. 32KB Block Erase Instruction Sequence Diagram

9.2.16 Block Erase (D8h)

2). The Block Erase instruction sequence is shown in figure 16. and BP0) bits (see Status Register Memory Protection table). Figure 16. Block Erase Instruction Sequence Diagram

9.2.17 Chip Erase (C7h or 60h)

Figure 17. Chip Erase Instruction Sequence Diagram

9.2.18 Power-down (B9h)

“B9h” as shown in figure 18. the normal operation with the standby current of ICC1. Figure 18. Deep Power-down Instruction Sequence Diagram

9.2.19 Release Power-down / Device ID (ABh)

instructions will be accepted. The /CS pin must remain high during the tRES1 time duration. device will resume normal operation and other instructions will be accepted. Figure 19. Release Power-down Instruction Sequence

Figure 20. Release Power-down / Device ID Instruction Sequence Diagram

9.2.20 Read Manufacturer / Device ID (90h)

Device ID instruction that provides both JEDEC assigned manufacturer ID and the specific device ID. continuously, alternating from one to the other. The instruction is completed by driving /CS high. Figure 21. Read Manufacturer / Device ID Diagram

9.2.21 Read Manufacturer / Device ID Dual I/O (92h)

bits per clock on the falling edge of CLK with most si gnificant bits (MSB) first as shown in figure 22. alternating from one to the other. The instruction is completed by driving /CS high. Figure 22. Read Manufacturer / Device ID Dual I/O Diagram The “Continuous Read Mode” bits M7-0 must be set to Fxh to be compatible with Fast Read Dual I/O instruction.

9.2.22 Read Unique ID Number (4Bh)

clocks. After which, the 64-bit ID is shifted out on the falling edge of CLK as shown in figure 23. Figure 23. Read Unique ID Number Instruction Sequence

9.2.23 JEDEC ID (9Fh)

standard for SPI compatible serial memories that was adopted in 2003. Device Identification table. Figure 24. Read JEDEC ID

Publication Release Date: August 20, 2009 - 3 7 - P r e l i m i n a r y - - R e v i s i o n B 10. ELECTRICAL CHARACTERISTICS(1)

10.1 Absolute Maximum Ratings (2)

PARAMETERS SYMBOL CONDITIONS RANGE UNIT Supply Voltage VCC –0.6 to +4.0 V Voltage Applied to Any Pin VIO Relative to Ground –0.6 to VCC +0.4 V Transient Voltage on any Pin VIOT <20nS Transient Relative to Ground –2.0V to VCC+2.0V V Storage Temperature TSTG –65 to +150 °C Lead Temperature TLEAD See Note (3) °C Electrostatic Discharge Voltage VESD Human Body Model(4) –2000 to +2000 V Notes: 1. Specification for W25X10BV/20BV/40BV are prelim inary. See preliminary designation at the end of this document. 2. This device has been designed and tested for t he specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maxi mum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage. 3. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU. 4. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).

10.2 Operating Ranges

SPEC PARAMETER SYMBOL CONDITIONS MIN MAX UNIT Supply Voltage(1) VCC FR = 80MHz, fR = 50MHz FR = 104MHz, fR = 50MHz 2.7 3.0 3.6 3.6 V Ambient Temperature, Operating T A Industrial Commericial –40 +85 +70 °C Note: 1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming (erase/write) voltage.

10.3 Power-up Timing and Write Inhibit Threshold

1. These parameters are characterized only.

Figure 25. Power-up Timing and Voltage Levels

Publication Release Date: August 20, 2009 - 3 9 - P r e l i m i n a r y - - R e v i s i o n B

10.4 DC Electrical Characteristics

SPEC PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Input Capacitance CIN(1) V IN = 0V(2) 6 pF Output Capacitance Cout(1) V OUT = 0V(2) 8 pF Input Leakage ILI ±2 µA I/O Leakage ILO ±2 µA Standby Current ICC1 /CS = VCC, VIN = GND or VCC 25 50 µA Power-down Current ICC2 /CS = VCC, VIN = GND or VCC 1 5 µA Current Read Data / Dual Output 1MHz (2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 4/5 6/7.5 mA Current Read Data / Dual Output 33MHz (2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 6/7 9/10 mA Current Read Data / Dual Output 80MHz (2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 10/11 15/16.5 mA Current Write Status Register I CC4 /CS = VCC 8 12 mA Current Page Program ICC5 /CS = VCC 20 25 mA Current Sector/Block Erase I CC6 /CS = VCC 20 25 mA Current Chip Erase ICC7 /CS = VCC 20 25 mA Input Low Voltage VIL –0.5 VCCx0.3 V Input High Voltage VIH VCCx0.7 VCC+0.4 V Output Low Voltage VOL I OL = 1.6 mA 0.4 V Output High Voltage VOH I OH = –100 µA VCC–0.2 V Notes: 1. Tested on sample basis and specified through design and characterization data. TA=25°C, VCC=3V. 2. Checker Board Pattern.

10.5 AC Measurement Conditions

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 26. AC Measurement I/O Waveform

Publication Release Date: August 20, 2009 - 4 1 - P r e l i m i n a r y - - R e v i s i o n B

10.6 AC Electrical Characteristics

Clock frequency for all instructions, except Read Data (03h) 2.7V-3.6V VCC & Industrial Temperature F R f c D.C. 80 MHz Clock frequency for all instructions, except Read Data (03h) 3.0V-3.6V VCC & Commercial Temperature F R f c D.C. 104 MHz Clock freq. Read Data instruction 03h fR D.C. 50 MHz Clock High, Low Time, for Fast Read (0Bh, 3Bh) / other instructions except Read Data (03h) tCLH, tCLL(1) 4 ns Clock High, Low Time for Read Data (03h) instruction t CRLH, tCRLL(1) 8 ns Clock Rise Time peak to peak tCLCH(2) 0.1 V/ns Clock Fall Time peak to peak tCHCL(2) 0.1 V/ns /CS Active Setup Time relative to CLK tSLCH t CSS 5 ns /CS Not Active Hold Time relative to CLK tCHSL 5 ns Data In Setup Time tDVCH t DSU 2 ns Data In Hold Time tCHDX t DH 5 ns /CS Active Hold Time relative to CLK tCHSH 5 ns /CS Not Active Setup Time relative to CLK tSHCH 5 ns /CS Deselect Time (for Array ReadArray Read / Erase or Program  Read Status Register) tSHSL t CSH 10/50 ns Output Disable Time tSHQZ(2) t DIS 7 ns Clock Low to Output Valid tCLQV t V 7 ns Output Hold Time tCLQX t HO 0 ns Continued – next page

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10.7 AC Electrical Characteristics (cont’d)

/HOLD Active Setup Time relative to CLK t HLCH 5 ns /HOLD Active Hold Time relative to CLK t CHHH 5 ns /HOLD Not Active Setup Time relative to CLK t HHCH 5 ns /HOLD Not Active Hold Time relative to CLK t CHHL 5 ns /HOLD to Output Low-Z t HHQX(2) t LZ 7 ns /HOLD to Output High-Z t HLQZ(2) t HZ 12 ns Write Protect Setup Time Before /CS Low tWHSL(3) 20 ns Write Protect Hold Time After /CS High tSHWL(3) 100 ns /CS High to Power-down Mode tDP(2) 3 µs /CS High to Standby Mode without Electronic Signature Read tRES1(2) 3 µs /CS High to Standby Mode with Electronic Signature Read t RES2(2) 1.8 µs Write Status Register Time tW 10 15 ms Byte Program Time (First Byte) (4) tBP1 30 50 µs Additional Byte Program Time (After First Byte) (4) t BP2 2.5 12 µs Page Program Time tPP 0.7 3 ms Sector Erase Time (4KB) tSE 30 200 ms Block Erase Time (32KB) tBE1 120 800 ms Block Erase Time (64KB) tBE2 150 1,000 ms Chip Erase Time W25X10BV / W25X20BV Chip Erase Time W25X40BV tCE 0.5 s Notes: 1. Clock high + Clock low must be less than or equal to 1/f C. 2. Value guaranteed by design and/or characte rization, not 100% tested in production. 3. Only applicable as a constraint for a Write Stat us Register instruction when SRP is set to 1. 4. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes programmed.

Publication Release Date: August 20, 2009 - 4 3 - P r e l i m i n a r y - - R e v i s i o n B

10.8 Serial Output Timing

10.9 Input Timing

10.10 Hold Timing

• 44 - 11. PACKAGE SPECIFICATION 11.1 8-Pin SOIC 150-mil (Package Code SN) L O c D A e b SEATING PLANE Y 0.25 GAUGE PLANE E HE 8 5 MILLIMETERS INCHES SYMBOL Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.008 0.010 E(3) 3.80 4.00 0.150 0.157 D(3) 4.80 5.00 0.188 0.196 e(2) 1.27 BSC 0.050 BSC HE 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050  0° 10° 0° 10° Notes: 1. Controlling dimensions: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches

Publication Release Date: August 20, 2009 - 4 5 - P r e l i m i n a r y - - R e v i s i o n B 11.2 8-Pin SOIC 208-mil (Package Code SS) θ MILLIMETERS INCHES SYMBOL MIN NOM MAX MIN NOM MAX e 1.27 BSC 0.050 BSC θ 0° - 8° 0° - 8° Notes: 1. Controlling dimensions: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches.

• 46 - 11.3 8-Pin PDIP 300-mil (Package Code DA) Seating Plane e A c E Base Plane1A L A S D B 8 5 1 4 α Millimeters Inches Symbol Min Typ. Max Min Typ. Max D - 9.14 9.65 - 0.360 0.380 α 0 - 15 0 - 15

Publication Release Date: August 20, 2009 - 4 7 - P r e l i m i n a r y - - R e v i s i o n B 11.4 8-Contact 6x5mm WSON (Package Code ZP) MILLIMETERS INCHES SYMBOL MIN TYP. MAX MIN TYP. MAX E(2) 1.27 BSC 0.0500 BSC y 0.00 - 0.75 0.0000 - 0.0029

• 48 - 8-Pad WSON 6x5mm Cont’d. MILLIMETERS INCHES SYMBOL MIN TYP. MAX MIN TYP MAX SOLDER PATTERN M 3.40 0. 38 13 N 4.30 0. 92 16 P 6.00 0. 60 23 Q 0.50 0. 96 01 R 0.75 0. 55 02 Notes: 1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.

Publication Release Date: August 20, 2009 - 4 9 - P r e l i m i n a r y - - R e v i s i o n B 12. ORDERING INFORMATION(1) W 25X xxB V xx(2) I = Industrial (-40°C to +85°C) SS = 8 pin SOIC 208-mil DA = 8-pin PDIP 300mil SN = 8-pin SOIC 150-mil ZP = 8-pad WSON 6x5mm V = 2.7V to 3.6V 40 = 4M-bit 20 = 2M-bit 10 = 1M-bit 25X = spiFlash Serial Flash Memory with 4KB sectors, Dual Outputs W = Winbond G = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) Notes: 1a. Standard bulk shipments are in Tube (shape E). Please s pecify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 1b. The “W” prefix is not included on the part marking. 2. Only the 2 nd letter is used for the part marking, package type ZP is not used for the part marking.

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12.1 Valid Part Numbers and Top Side Marking

The following table provides the valid part numbers for the W25X10BV/20BV/40BV SpiFlash Memories. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 12-digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 10-digit number. PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING 1M-bit W25X10BVSNIG 25X10BVNIG 2M-bit W25X20BVSNIG 25X20BVNIG SN SOIC-8 150mil 4M-bit W25X40BVSNIG 25X40BVNIG SS SOIC-8 208mil 4M-bit W25X40BVSSIG 25X40BVSIG 1M-bit W25X10BVZPIG 25X10BVIG 2M-bit W25X20BVZPIG 25X20BVIG ZP(1) WSON-8 6x5mm 4M-bit W25X40BVZPIG 25X40BVIG DA PDIP-8 300mil 4M-bit W25X40BVDAIG 25X40BVAIG Notes: 1. For WSON packages, the package type ZP is not used in the top side marking.

Publication Release Date: August 20, 2009 - 5 1 - P r e l i m i n a r y - - R e v i s i o n B

REVISION HISTORY

VERSION DATE PAGE DESCRIPTION A 07/10/09 All New create preliminary. B 08/07/09 44~48 Update Package Diagrams UID Waveform Correction Preliminary Designation The “Preliminary” designation on a Winbond datasheet indicates that the product is not fully characterized. The specifications ar e subject to change and are not guaranteed. Winbond or an authorized sales representative should be consulted for current information before using this product. Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Important Notice Winbond products are not designed, intended, authoriz ed or warranted for use as components in systems or equipment intended for surg ical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instrument s, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or seve re property or environmental damage could occur. Winbond customers using or selling these products for us e in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Information in this document is provided solely in connection with Winbond products. Winbond reserves the right to make changes, corrections, m odifications or improvements to this document and the products and services described herein at any time, without notice.