25Q64FVIQ

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 89

Technical content

Publication Release Date:October 07, 2013 - 1 - Revision L 3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

• 2 - Table of Contents

Publication Release Date: October 07, 2013 - 3 - Revision L

• 4 -

Publication Release Date: October 07, 2013 - 5 - Revision L 1. GENERAL DESCRIPTION The W25Q64FV (64M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25 Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from D ual/Quad SPI (XIP) and storing voice, text and data. The device operate s on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power -down. All devices are of fered in space - saving packages. The W25Q64FV array is organized into 32,768 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 ( 4KB sector erase), groups of 128 (32KB block erase), groups of 256 ( 64KB block erase) or th e entire chip (chip erase). The W25Q64FV has 2,048 erasable sectors and 128 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25Q64FV support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2 - clocks instruction cycle Quad Peripheral Interface (QPI) : Serial Clock, Chip Select, Serial Data I/O 0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outperform standard Asynchronous 8 and 16 -bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protect ion, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification, a 64-bit Unique Serial Number and four 256-bytes Security Registers. 2. FEATURES  Family of SpiFlash Memories – W25Q64FV: 64M-bit / 8M-byte (8,388,608) – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 – QPI: CLK, /CS, IO0, IO1, IO2, IO3  Highest Performance Serial Flash – 104MHz Standard/Dual/Quad SPI clocks – 208/416MHz equivalent Dual/Quad SPI – 50MB/S continuous data transfer rate – More than 100,000 erase/program cycles – More than 20-year data retention  Efficient “Continuous Read” and QPI Mode – Continuous Read with 8/16/32/64-Byte Wrap – As few as 8 clocks to address memory – Quad Peripheral Interface (QPI) reduces instruction overhead – Allows true XIP (execute in place) operation – Outperforms X16 Parallel Flash  Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply – 4mA active current, <1µA Power-down (typ.) – -40°C to +85°C operating range  Flexible Architecture with 4KB sectors – Uniform Sector Erase (4K-bytes) – Uniform Block Erase (32K and 64K-bytes) – Program 1 to 256 byte per programmable page – Erase/Program Suspend & Resume  Advanced Security Features – Software and Hardware Write-Protect – Top/Bottom, 4KB complement array protection – Power Supply Lock-Down and OTP protection – 64-Bit Unique ID for each device – Discoverable Parameters (SFDP) Register – 3X256-Bytes Security Registers with OTP locks – Volatile & Non-volatile Status Register Bits  Space Efficient Packaging – 8-pin SOIC/VSOP 208-mil – 8-pad WSON 6x5-mm/8x6-mm – 16-pin SOIC 300-mil – 8-pin PDIP 300-mil – 24-ball TFBGA 8x6-mm – Contact Winbond for KGD and other options

• 6 - 3. PACKAGE TYPES AND PIN CONFIGURATIONS W25Q64FV is offered in an 8 -pin SOIC 208 -mil (package code SS), an 8-pin VSOP 208 -mil (package code ST), an 8 -pad WSON 6x5-mm or 8x6 -mm (package code ZP & ZE), an 8 -pin PDIP 300-mil (package code DA), a 16-pin SOIC 300-mil (package code SF) and a 24-ball (5x5-1 or 6x4 balls) 8x6-mm TFBGA (package code TB & TC) as shown in Figure 1a -e respectively. Package diagrams and dimensions are illustrated at the end of this datasheet.

3.1 Pin Configuration SOIC / VSOP 208-mil

/CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) DI (IO0) CLK Top View Figure 1a. W25Q64FV Pin Assignments, 8-pin SOIC / VSOP 208-mil (Package Code SS / ST)

3.2 Pad Configuration WSON 6x5-mm / 8X6-mm

/CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) DI (IO0) CLK Top View Figure 1b. W25Q64FV Pad Assignments, 8-pad WSON 6x5-mm / 8x6-mm (Package Code ZP / ZE)

Publication Release Date: October 07, 2013 - 7 - Revision L

3.3 Pin Configuration PDIP 300-mil

/CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) DI (IO0) CLK Top View Figure 1c. W25Q64FV Pin Assignments, 8-pin PDIP 300-mil (Package Code DA)

3.4 Pin Description SOIC/VSOP 208-mil, WSON 6x5/8x6-mm and PDIP 300-mil

PIN NO. PIN NAME I/O FUNCTION 1 /CS I Chip Select Input

2 DO (IO1) I/O Data Output (Data Input Output 1)*1

3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)*2

4 GND Ground

5 DI (IO0) I/O Data Input (Data Input Output 0)*1

6 CLK I Serial Clock Input

7 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2

8 VCC Power Supply

*1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions

• 8 -

3.5 Pin Configuration SOIC 300-mil

/CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) DI (IO0) CLK Top View NC NC NC NC NC NC NC NC5 Figure 1d. W25Q64FV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)

3.6 Pin Description SOIC 300-mil

PIN NO. PIN NAME I/O FUNCTION 1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2

2 VCC Power Supply

3 N/C No Connect

4 N/C No Connect

5 N/C No Connect

6 N/C No Connect

8 DO (IO1) I/O Data Output (Data Input Output 1)*1

9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2

10 GND Ground

11 N/C No Connect

12 N/C No Connect

13 N/C No Connect

14 N/C No Connect

15 DI (IO0) I/O Data Input (Data Input Output 0)*1

16 CLK I Serial Clock Input

*1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions

Publication Release Date: October 07, 2013 - 9 - Revision L

3.7 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)

/HOLD(IO3)DI(IO0)DO(IO1) /WP (IO2) D2 D3 D4 NC NCNCNC E2 E3 E4 NC NCNCNC F2 F3 F4 NC NCNCNC A2 A3 A4 NC VCCGNDCLK B2 B3 B4 NC NC/CS C2 C3 C4 NC Top View Package Code TC /HOLD(IO3)DI(IO0)DO(IO1) /WP (IO2) D2 D3 D4 NC NCNCNC E2 E3 E4 NC NCNCNC A2 A3 A4 NC VCCGNDCLK B2 B3 B4 NC NC/CS C2 C3 C4 NC Top View Package Code TB NC NC NC NC Figure 1e. W25Q64FV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB / TC)

3.8 Ball Description TFBGA 8x6-mm

BALL NO. PIN NAME I/O FUNCTION B2 CLK I Serial Clock Input B3 GND Ground B4 VCC Power Supply C2 /CS I Chip Select Input C4 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2 D2 DO (IO1) I/O Data Output (Data Input Output 1)*1 D3 DI (IO0) I/O Data Input (Data Input Output 0)*1 D4 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2 Multiple NC No Connect *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions

• 10 -

3.9 Pin Descriptions

3.10 Chip Select (/CS)

The SPI Chip Select ( /CS) pin enables and disables device operation. When /CS is high, the device is deselected and the Serial Data Output (DO, or IO0, IO1, I O2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low , the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up and power-down (see “Write Protection” and figure 43). If needed a pull-up resister on /CS can be used to accomplish this.

3.11 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)

The W25Q64FV supports standard SPI, Dual SPI, Quad SPI and QPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual/Quad SPI and QPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device o n the falling edge of CLK. Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

3.12 Write Protect (/WP)

The Write Protect ( /WP) pin can be use d to prevent the Status Register s from being written. Used in conjunction with the Status Register’s Block Protect ( CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array c an be hardware protected. The /WP pin is active low. However, when the QE bit of Status Register -2 is set for Quad I/O, the /WP pin function is not available since this pin is used for IO2. See figure 1a, 1b and 1 c for the pin configuration of Quad I/O operation.

3.13 HOLD (/HOLD)

The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register -2 is set for Quad I/O, the /HOLD pin function is not avail able since this pin is used for IO3. See figure 1a, 1b and 1c for the pin configuration of Quad I/O operation.

3.14 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input an d output operations. ("See SPI Operations")

Figure 2. W25Q64FV Serial Flash Memory Block Diagram

• Sector 0 (4KB) • xx0000h xx00FFh xx1F00h xx1FFFh
• Sector 1 (4KB) • xx1000h xx10FFh xx2F00h xx2FFFh
• Sector 2 (4KB) • xx2000h xx20FFh xxDF00h xxDFFFh
• Sector 13 (4KB) • xxD000h xxD0FFh xxEF00h xxEFFFh
• Sector 14 (4KB) • xxE000h xxE0FFh xxFF00h xxFFFFh
• Sector 15 (4KB) • xxF000h xxF0FFh Block Segmentation Data Security Register 1 - 3 Write Protect Logic and Row Decode 000000h 0000FFh SFDP Register 00FF00h 00FFFFh
• Block 0 (64KB) • 000000h 0000FFh 1FFF00h 1FFFFFh
• Block 31 (64KB) • 1F0000h 1F00FFh 20FF00h 20FFFFh
• Block 32 (64KB) • 200000h 2000FFh 3FFF00h 3FFFFFh
• Block 63 (64KB) • 3F0000h 3F00FFh 40FF00h 40FFFFh
• Block 64 (64KB) • 400000h 4000FFh 7FFF00h 7FFFFFh
• Block 127 (64KB) • 7F0000h 7F00FFh

5.1 SPI/QPI OPERATIONS

Figure 3. W25Q64FV Serial Flash Memory Operation Diagram

5.1.1 Standard SPI Instructions

DO output pin is used to read data or status from the device on the falling edge of CLK. rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.

5.1.2 Dual SPI Instructions

become bidirectional I/O pins: IO0 and IO1.

Publication Release Date: October 07, 2013 - 13 - Revision L

5.1.3 Quad SPI Instructions

The W25Q64FV supports Quad SPI operation when using instructions such as “Fast Read Quad Output (6Bh)”, “ Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O (E3h)”. These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a signific ant improvement in continuous and random access transfer rates allowing fast code -shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1 , and the /WP and /HOLD pin s become IO2 and IO3 respectively. Quad SPI instructions require the non - volatile Quad Enable bit (QE) in Status Register-2 to be set.

5.1.4 QPI Instructions

The W25Q64FV supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enable QPI (38h)” instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks are required. This can significantly reduce the SPI instruction overhead and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given time. “Enable QPI (38h)” and “Disable QPI (FFh)” instructions are used to switch between these two modes. Upon power-up or after a software reset using “Reset (99h)” instruction, the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. See Figure 3 for the device operation modes.

5.1.5 Hold Function

For Standard SPI and Dual SPI operations, t he /HOLD signal allows the W25Q64FV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in case s where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instr uction and the data in the buffer so programming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation, not during Quad SPI or QPI. To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high i mpedance, and Serial Data Input (DI ) and Serial Clock (CLK) are ignored. The Chip Select ( /CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device.

• 14 -

5.2 WRITE PROTECTION

Applications that use non -volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern , the W25Q64FV provides several means to protect the data from inadvertent writes.

5.2.1 Write Protect Features

 Device resets when VCC is below threshold  Time delay write disable after Power-up  Write enable/disable instructions and automatic write disable after erase or program  Software and Hardware (/WP pin) write protection using Status Register  Write Protection using Power-down instruction  Lock Down write protection for Status Register until the next power-up  One Time Program (OTP) write protection for array and Security Registers using Status Register* * Note: This feature is available upon special order. Please contact Winbond for details. Upon power-up or at power-down, the W25Q64FV will maintain a reset condition while VCC is below the threshold value of V WI, (See Power -up Timing and Voltage Levels and Figure 43). While reset, all operations are disabled and no instructions are recognized. During power -up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page Pr ogram, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached , and it must also track the VCC supply level at power - down to prevent adverse command sequence . If needed a pull -up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write -disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write - disabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP 0, SRP1) and Block Protect ( CMP, SEC, TB, BP2, BP1 and BP0) bits. These settings allow a portion as small as a 4KB sector or the entire memory array to be configured as read only. Used in conjunction with the Write Protect ( /WP) pin, changes to the Status Register can be enabled or disabled under hardware control . See Status Register section for further information. Additionally, the Power -down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction.

Publication Release Date: October 07, 2013 - 15 - Revision L 6. STATUS REGISTERS AND INSTRUCTIONS The Read Status Register -1 and Status Register -2 instructions can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting and Security Register OTP lock. Write access to the Status Register is controlled by the state of the non- volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI operations, the /WP pin.

6.1 STATUS REGISTERS

6.1.1 BUSY

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see t W, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status /security register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.

6.1.2 Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the statu s register (S1) that is set to 1 after executing a Write Enable Instruction. Th e WEL status bit is cleared to 0 when the device is write disabled. A writ e disable state occurs upon power -up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register , Erase Security Register and Program Security Register.

6.1.3 Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruc tion (see t W in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected.

6.1.4 Top/Bottom Block Protect (TB)

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The f actory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits.

6.1.5 Sector/Block Protect (SEC)

The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0.

• 16 -

6.1.6 Complement Protect (CMP)

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection s et by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not; when CMP=1, the top 4KB sector will become unprotected while the rest of the array become read-only. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0.

6.1.7 Status Register Protect (SRP1, SRP0)

The Status Register Protect bits (SRP1 and SRP0 ) are non-volatile read/write bits in the status register (S8 and S7). The SR P bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. SRP1 SRP0 /WP Status Register Description 0 0 X Software Protection /WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default] 0 1 0 Hardware Protected When /WP pin is low the Status Register locked and can not be written to. 0 1 1 Hardware Unprotected When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. 1 0 X Power Supply Lock-Down Status Register is protected and can not be written to again until the next power-down, power-up cycle.(1) 1 1 X One Time Program(2) Status Register is permanently protected and can not be written to. Note: 1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available upon special order. Please contact Winbond for details.

6.1.8 Erase/Program Suspend Status (SUS)

The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle.

6.1.9 Security Register Lock Bits (LB3, LB2, LB1)

The Security Register Lock Bits (LB3, LB2, LB1 ) are non-volatile One Time Program (OTP) bits in Sta tus Register (S13, S12, S11 ) that provide the write protect control and stat us to the Security Registers . The default state of LB3 -0 is 0, Security Registers are unlocked. LB3 -1 can be set to 1 individually using the Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the corresponding 256-Byte Security Register will become read-only permanently.

Publication Release Date: October 07, 2013 - 17 - Revision L

6.1.10 Quad Enable (QE)

The Quad Enable (QE) bit is a non -volatile read/write bit in the status register (S9) that allows Quad SPI and QPI operation. When the QE bit is set to a 0 state (factory default for part number with ordering options “IG” and “IF”), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1(factory default for Quad Enabled part numbers with ordering option “IQ”) , the Quad IO2 and I O3 pins are enabled , and /WP and /HOLD functions are disabled. QE bit is required to be set to a 1 before issuing an “Enable QPI (38h)” to switch the device from Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI mode, QE bit will remain to be 1. A “Write S tatus Register” command in QPI mode cannot change QE bit from a “1” to a “0”. WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during standard SPI or Dual SPI operation, the QE bit should never be set to a 1. S7 S6 S5 S4 S3 S2 S1 S0 SRP0 SEC TB BP2 BP1 BP0 WEL BUSY STATUS REGISTER PROTECT 0 (non-volatile) SECTOR PROTECT (non-volatile) TOP/BOTTOM PROTECT (non-volatile) BLOCK PROTECT BITS (non-volatile) WRITE ENABLE LATCH ERASE/WRITE IN PROGRESS S7 S6 S5 S4 S3 S2 S1 S0 SRP0 SEC TB BP2 BP1 BP0 WEL BUSY STATUS REGISTER PROTECT 0 (non-volatile) SECTOR PROTECT (non-volatile) TOP/BOTTOM PROTECT (non-volatile) BLOCK PROTECT BITS (non-volatile) WRITE ENABLE LATCH ERASE/WRITE IN PROGRESS Figure 4a. Status Register-1 S15 S14 S13 S12 S11 S10 S9 S8 SUS CMP LB3 LB2 LB1 (R) QE SRP1 SUSPEND STATUS COMPLEMENT PROTECT (non-volatile) SECURITY REGISTER LOCK BITS (non-volatile OTP) QUAD ENABLE (non-volatile) STATUS REGISTER PROTECT 1 (non-volatile) RESERVED S15 S14 S13 S12 S11 S10 S9 S8 SUS CMP LB3 LB2 LB1 (R) QE SRP1 SUSPEND STATUS COMPLEMENT PROTECT (non-volatile) SECURITY REGISTER LOCK BITS (non-volatile OTP) QUAD ENABLE (non-volatile) STATUS REGISTER PROTECT 1 (non-volatile) RESERVED Figure 4b. Status Register-2

• 18 -

6.1.11 W25Q64FV Status Register Memory Protection (CMP = 0)

STATUS REGISTER(1) W25Q64FV (64M-BIT) MEMORY PROTECTION(3) SEC TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED DENSITY PROTECTED PORTION(2) X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 126 and 127 7E0000h – 7FFFFFh 128KB Upper 1/64 0 0 0 1 0 124 thru 127 7C0000h – 7FFFFFh 256KB Upper 1/32 0 0 0 1 1 120 thru 127 780000h – 7FFFFFh 512KB Upper 1/16 0 0 1 0 0 112 thru 127 700000h – 7FFFFFh 1MB Upper 1/8 0 0 1 0 1 96 thru 127 600000h – 7FFFFFh 2MB Upper 1/4 0 0 1 1 0 64 thru 127 400000h – 7FFFFFh 4MB Upper 1/2 0 1 0 0 1 0 and 1 000000h – 01FFFFh 128KB Lower 1/64 0 1 0 1 0 0 thru 3 000000h – 03FFFFh 256KB Lower 1/32 0 1 0 1 1 0 thru 7 000000h – 07FFFFh 512KB Lower 1/16 0 1 1 0 0 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/8 0 1 1 0 1 0 thru 31 000000h – 1FFFFFh 2MB Lower 1/4 0 1 1 1 0 0 thru 63 000000h – 3FFFFFh 4MB Lower 1/2 X X 1 1 1 0 thru 127 000000h – 7FFFFFh 8MB ALL 1 0 0 0 1 127 7FF000h – 7FFFFFh 4KB U – 1/2048 1 0 0 1 0 127 7FE000h – 7FFFFFh 8KB U – 1/1024 1 0 0 1 1 127 7FC000h – 7FFFFFh 16KB U – 1/512 1 0 1 0 X 127 7F8000h – 7FFFFFh 32KB U – 1/256 1 1 0 0 1 0 000000h – 000FFFh 4KB L – 1/2048 1 1 0 1 0 0 000000h – 001FFFh 8KB L – 1/1024 1 1 0 1 1 0 000000h – 003FFFh 16KB L – 1/512 1 1 1 0 X 0 000000h – 007FFFh 32KB L – 1/256 Note: 1. X = don’t care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains p rotected data portion, this command will be ignored.

Publication Release Date: October 07, 2013 - 19 - Revision L

6.1.12 W25Q64FV Status Register Memory Protection (CMP = 1)

STATUS REGISTER(1) W25Q64FV (64M-BIT) MEMORY PROTECTION(3) SEC TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED DENSITY PROTECTED PORTION(2) X X 0 0 0 0 thru 127 000000h – 7FFFFFh 8MB ALL 0 0 0 0 1 0 thru 125 000000h – 7DFFFFh 8,064KB Lower 63/64 0 0 0 1 0 0 thru 123 000000h – 7BFFFFh 7,936KB Lower 31/32 0 0 0 1 1 0 thru 119 000000h – 77FFFFh 7,680KB Lower 15/16 0 0 1 0 0 0 thru 111 000000h – 6FFFFFh 7MB Lower 7/8 0 0 1 0 1 0 thru 95 000000h – 5FFFFFh 5MB Lower 3/4 0 0 1 1 0 0 thru 63 000000h – 3FFFFFh 4MB Lower 1/2 0 1 0 0 1 2 thru 127 020000h – 7FFFFFh 8,064KB Upper 63/64 0 1 0 1 0 4 thru 127 040000h – 7FFFFFh 7,936KB Upper 31/32 0 1 0 1 1 8 thru 127 080000h – 7FFFFFh 7,680KB Upper 15/16 0 1 1 0 0 16 thru 127 100000h – 7FFFFFh 7MB Upper 7/8 0 1 1 0 1 32 thru 127 200000h – 7FFFFFh 5MB Upper 3/4 0 1 1 1 0 64 thru 127 400000h – 7FFFFFh 4MB Upper 1/2 X X 1 1 1 NONE NONE NONE NONE 1 0 0 0 1 0 thru 127 000000h – 7FEFFFh 8,188KB L – 2047/2048 1 0 0 1 0 0 thru 127 000000h – 7FDFFFh 8,184KB L – 1023/1024 1 0 0 1 1 0 thru 127 000000h – 7FBFFFh 8,176KB L – 511/512 1 0 1 0 X 0 thru 127 000000h – 7F7FFFh 8,160KB L – 255/256 1 1 0 0 1 0 thru 127 001000h – 7FFFFFh 8,188KB L – 2047/2048 1 1 0 1 0 0 thru 127 002000h – 7FFFFFh 8,184KB L – 1023/1024 1 1 0 1 1 0 thru 127 004000h – 7FFFFFh 8,176KB L – 511/512 1 1 1 0 X 0 thru 127 008000h – 7FFFFFh 8,160KB L – 255/256 Note: 1. X = don’t care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.

• 20 -

6.2 INSTRUCTIONS

The Standard/Dual/Quad SPI instruction set of the W25Q64FV consists of thirty six basic instructions that are fully controlled through the SPI bus (see Instruction Set table 1-3). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clo cked into the DI input provides the i nstruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. The QPI instruction set of the W 25Q64FV consists of twenty four basic instructions that are fully controlled through the SPI bus (see Instruction Set table 4). Instructio ns are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked through IO[3:0] pins provides the instruction code. Data on all four IO pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI instructions, addresses, data and dummy bytes are using all four IO pins to transfer every byte of data with every two serial clocks (CLK). Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in figures 5 through 42. All read instructions can be completed after an y clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary ( /CS driven high after a full 8 -bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed.

6.2.1 Manufacturer and Device Identification

MANUFACTURER ID (MF7 - MF0) Winbond Serial Flash EFh Device ID (ID7 - ID0) (ID15 - ID0) Instruction ABh, 90h, 92h, 94h 9Fh W25Q64FV (SPI) 16h 4017h W25Q64FV (QPI) 16h 6017h

Publication Release Date: October 07, 2013 - 21 - Revision L

6.2.2 Instruction Set Table 1 (Standard SPI Instructions)(1)

INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Write Enable 06h Volatile SR Write Enable 50h Write Disable 04h Read Status Register-1 05h (S7-S0) (2) Read Status Register-2 35h (S15-S8) (2) Write Status Register 01h (S7-S0) (S15-S8) Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0 (3) Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0 Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0 Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0 Chip Erase C7h/60h Erase / Program Suspend 75h Erase / Program Resume 7Ah Power-down B9h Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0) Release Powerdown / ID (4) ABh dummy dummy dummy (ID7-ID0) (2) Manufacturer/Device ID (4) 90h dummy dummy 00h (MF7-MF0) (ID7-ID0) JEDEC ID (4) 9Fh (MF7-MF0) Manufacturer (ID15-ID8) Memory Type (ID7-ID0) Capacity Read Unique ID 4Bh dummy dummy dummy dummy (UID63-UID0) Read SFDP Register 5Ah 00h 00h A7–A0 dummy (D7-0) Erase Security Registers (5) 44h A23-A16 A15-A8 A7-A0 Program Security Registers (5) 42h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0 (3) Read Security Registers (5) 48h A23-A16 A15-A8 A7-A0 dummy (D7-D0) Enable QPI 38h Enable Reset 66h Reset 99h

• 22 -

6.2.3 Instruction Set Table 2 (Dual SPI Instructions)

INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …) (7) Fast Read Dual I/O BBh A23-A8 (6) A7-A0, M7-M0 (6) (D7-D0, …) (7) Manufacturer/Device ID by Dual I/O (4) 92h A23-A8 (6) A7-A0, M7-M0 (6) (MF7-MF0, ID7-ID0)

6.2.4 Instruction Set Table 3 (Quad SPI Instructions)

INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Quad Page Program 32h A23-A16 A15-A8 A7-A0 D7-D0, … (9) D7-D0, … (3) Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …) (9) Fast Read Quad I/O EBh A23-A0, M7-M0 (8) (xxxx, D7-D0) (10) (D7-D0, …) (9) Word Read Quad I/O (12) E7h A23-A0, M7-M0 (8) (xx, D7-D0) (11) (D7-D0, …) (9) Octal Word Read Quad I/O (13) E3h A23-A0, M7-M0 (8) (D7-D0, …) (9) Set Burst with Wrap 77h xxxxxx, W6-W4 (8) Manufacture/Device ID by Quad I/O (4) 94h A23-A0, M7-M0 (8) xxxx, (MF7-MF0, ID7-ID0) (MF7-MF0, ID7-ID0, …)

Publication Release Date: October 07, 2013 - 23 - Revision L

6.2.5 Instruction Set Table 4 (QPI Instructions)(14)

INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Write Enable 06h Volatile SR Write Enable 50h Write Disable 04h Read Status Register-1 05h (S7-S0) (2) Read Status Register-2 35h (S15-S8) (2) Write Status Register 01h (S7-S0) (S15-S8) Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 (9) D7-D0 (3) Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0 Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0 Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0 Chip Erase C7h/60h Erase / Program Suspend 75h Erase / Program Resume 7Ah Power-down B9h Set Read Parameters C0h P7-P0 Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (15) (D7-D0) Burst Read with Wrap (16) 0Ch A23-A16 A15-A8 A7-A0 dummy (15) (D7-D0) Fast Read Quad I/O EBh A23-A16 A15-A8 A7-A0 M7-M0 (15) (D7-D0) Release Powerdown / ID (4) ABh dummy dummy dummy (ID7-ID0) (2) Manufacturer/Device ID (4) 90h dummy dummy 00h (MF7-MF0) (ID7-ID0) JEDEC ID (4) 9Fh (MF7-MF0) Manufacturer (ID15-ID8) Memory Type (ID7-ID0) Capacity Disable QPI FFh Enable Reset 66h Reset 99h

• 24 - Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data output from the device on either 1, 2 or 4 IO pins. 2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction. 3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. 4. See Manufacturer and Device Identification table for device ID information. 5. Security Register Address: Security Register 1: A23 -16 = 00h; A15 -8 = 10h; A7 -0 = byte address Security Register 2: A23 -16 = 00h; A15 -8 = 20h; A7 -0 = byte address Security Register 3: A23 -16 = 00h; A15 -8 = 30h; A7 -0 = byte address 6. Dual SPI address input format: IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 7. Dual SPI data output format: IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 8. Quad SPI address input format: Set Burst with Wrap input format: IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO2 = x, x, x, x, x, x, W6, x IO3 = A23, A19, A15, A11, A7, A3, M7, M3 IO3 = x, x, x, x, x, x, x, x 9. Quad SPI data input/output format: 10. Fast Read Quad I/O data output format: IO0 = (x, x, x, x, D4, D0, D4, D0) IO1 = (x, x, x, x, D5, D1, D5, D1) IO2 = (x, x, x, x, D6, D2, D6, D2) IO3 = (x, x, x, x, D7, D3, D7, D3) 11. Word Read Quad I/O data output format: IO0 = (x, x, D4, D0, D4, D0, D4, D0) IO1 = (x, x, D5, D1, D5, D1, D5, D1) IO2 = (x, x, D6, D2, D6, D2, D6, D2) IO3 = (x, x, D7, D3, D7, D3, D7, D3) 12. For Word Read Quad I/O, the lowest address bit must be 0. (A0 = 0) 13. For Octal Word Read Quad I/O, the lowest four address bits must be 0. (A3, A2, A1, A0 = 0) 14. QPI Command, Address, Data input/output format: CLK # 0 1 2 3 4 5 6 7 8 9 10 11 IO0 = C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0 IO1 = C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1 IO2 = C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2 IO3 = C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3 15. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is controlled by read parameter P7 – P4. 16. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 – P0.

6.2.6 Write Enable (06h)

1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block

pin on the rising edge of CLK, and then driving /CS high. Figure 5. Write Enable Instruction for SPI Mode (left) or QPI Mode (right)

6.2.7 Write Enable for Volatile Status Register (50h)

valid for the Write Status Register instruction to change the volatile Status Register bit values. Figure 6. Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI Mode (right)

6.2.8 Write Disable (04h)

Program, Sector Erase, Block Erase, Chip Erase and Reset instructions. Figure 7. Write Disable Instruction for SPI Mode (left) or QPI Mode (right)

6.2.9 Read Status Register-1 (05h) and Read Status Register-2 (35h)

SRP1, QE, LB3-0, CMP and SUS bits (see Status Register section earlier in this datasheet). continuously, as shown in Figure 8. The instruction is completed by driving /CS high.

Publication Release Date: October 07, 2013 - 27 - Revision L /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 05h or 35h 2 3 4 5 4 0 4 0 5 1 6 2 7 3 5 1 6 2 7 3 SR1 or SR2 out SR1 or SR2 out Instruction Figure 8b. Read Status Register Instruction (QPI Mode)

6.2.10 Write Status Register (01h)

The Write Status Register instruction allows the Status Register to be written. Only non -volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register -1) and CMP, LB3, L B2, LB1, QE, SRP1 (bits 14 thru 8 of Status Register -2) can be written to. All other Status Register bit locations are read -only and will not be affected by the Write Status Register instruction. LB3 -0 are non - volatile OTP bits, once it is set to 1, it can not be cleared to 0. The Status Register bits are shown in Figure 4a and 4b, and described in 7.1. To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been executed for the device to accept the Write Status Register instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction code “01h”, and then writing the status register data byte as illustrated in figure 9. To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have been executed prior to the Write Status Register instruction (Status Reg ister bit WEL remains 0). However, SRP1 and LB3, LB2, LB1 can not be changed from “1” to “0” because of the OTP protection for these bits. Upon power off or the execution of a “Reset (99h)” instruction , the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will be restored. To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Registe r instruction will not be executed. If /CS is driven high after the eighth clock (compatible with the 25X series) the CMP, QE and SRP1 bits will be cleared to 0. During non-volatile Status Register write operation (06h combined with 01h), after /CS is driv en high, the self-timed Write Status Register cycle will commence for a time duration of t W (See AC Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to check the status of th e BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle

6.2.11 Read Data (03h)

the clock continues. The instruction is completed by driving /CS high. (see AC Electrical Characteristics). The Read Data (03h) instruction is only supported in Standard SPI mode. Figure 10. Read Data Instruction (SPI Mode only)

• 30 -

6.2.12 Fast Read (0Bh)

The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible freq uency of F R (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24 -bit address as shown in figure 11. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. Du ring the dummy clocks the data value on the DO pin is a “don’t care”. /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (0Bh) High Impedance 8 9 10 28 29 30 31 24-Bit Address 23 22 21 3 2 1 0 Data Out 1 /CS CLK DI (IO0) DO (IO1) 32 33 34 35 36 37 38 39 Dummy Clocks High Impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 Data Out 2 7 6 5 4 3 2 1 0 4331 = MSB* Figure 11a. Fast Read Instruction (SPI Mode)

Publication Release Date: October 07, 2013 - 31 - Revision L Fast Read (0Bh) in QPI Mode The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number of dummy clo cks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide range applications with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the n umber of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 2. /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 0Bh 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Dummy* Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 IOs switch from Input to Output * "Set Read Parameters" instruction (C0h) can set the number of dummy clocks. Instruction Figure 11b. Fast Read Instruction (QPI Mode)

6.2.13 Fast Read Dual Output (3Bh)

Figure 12. Fast Read Dual Output Instruction (SPI Mode only)

6.2.14 Fast Read Quad Output (6Bh)

at four times the rate of standard SPI devices. be high-impedance prior to the falling edge of the first data out clock. Figure 13. Fast Read Quad Output Instruction (SPI Mode only)

• 34 -

6.2.15 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23 -0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. Fast Read Dual I/O with “Continuous Read Mode” The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” b its (M7-0) after the input Address bits (A23 -0), as shown in Figure 14a. The upper nibble of the (M7 -4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3 -0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require the BBh instruction code, as shown in Figure 14b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediatel y entered after /CS is asserted low. If the “Continuous Read Mode” bits M5 -4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFFFh on IO0 for the next instruction (16 clocks), to ensure M4 = 1 and return the device to normal operation. /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (BBh) 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 /CS CLK DI (IO0) DO (IO1) 32 33 34 35 36 37 38 39 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * IOs switch from Input to Output 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 16 17 18 20 21 2219 23 A23-16 A15-8 A7-0 M7-0 Byte 1 Byte 2 Byte 3 Byte 4 = MSB* * Figure 14a. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4  10, SPI Mode only)

Publication Release Date: October 07, 2013 - 35 - Revision L /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 /CS CLK DI (IO0) DO (IO1) 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * IOs switch from Input to Output 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 A23-16 A15-8 A7-0 M7-0 Byte 1 Byte 2 Byte 3 Byte 4 0 1 2 3 4 5 6 7 16 17 18 20 21 2219 23 = MSB* Figure 14b. Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)

• 36 -

6.2.16 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output th rough four pins IO 0, IO1, IO2 and IO3 and four Dummy clocks are required in SPI mode prior to the data output . The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction. Fast Read Quad I/O with “Continuous Read Mode” The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7 -0) after the input Address bits (A23 -0), as shown in Figure 15a. The upper nibble of the (M7 -4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3 -0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the EBh instruction code, as shown in Figure 15b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5 -4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensu re M4 = 1 and return the device to normal operation. Figure 15a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-410, SPI Mode) M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output Byte 3 15 16 17 18 19 20 21 22 23 Dummy DummyInstruction (EBh)

Publication Release Date: October 07, 2013 - 37 - Revision L M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output Byte 3 Dummy Dummy Figure 15b. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode) Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Fast Read Quad I/O instruction can also be used to access a specific portio n within a page by issuing a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h) command can either enable or disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the data being acce ssed can be limited to either a 8, 16, 32 or 64 -byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 -byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 -byte) of data without issuing multiple read commands. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6 -4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wra p around section within a page. See 7.2.19 for detail descriptions.

• 38 - Fast Read Quad I/O (EBh) in QPI Mode The Fast Read Quad I/O instruction is also supported in QPI mode , as shown in Figure 15c . When QPI mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide range applications with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 2. In QPI mode, the “Continuous Read Mode” bits M7 -0 are also considered as dummy clocks. In the default setting, the dat a output will follow the Continuous Read Mode bits immediately. “Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please refer to the description on previous pages. “Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch) instruction must be used. Please refer to 7.2.39 for details. Figure 15c. Fast Read Quad I/O Instruction (Initial instruction or previous M5-410, QPI Mode) M7-0* /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 EBh 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output * "Set Read Parameters" instruction (C0h) can set the number of dummy clocks. Byte 3 Instruction

Publication Release Date: October 07, 2013 - 39 - Revision L

6.2.17 Word Read Quad I/O (E7h)

The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clock are required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word Read Quad I/O Instruction. Word Read Quad I/O with “Continuous Read Mode” The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bit s (M7-0) after the input Address bits (A23 -0), as shown in Figure 16a. The upper nibble of the (M7 -4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bit s of the (M3 -0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised a nd then lowered) does not require the E7h instruction code, as shown in Figure 16b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5 -4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation. Figure 16a. Word Read Quad I/O Instruction (Initial instruction or previous M5-4  10, SPI Mode only) M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output Byte 3 15 16 17 18 19 20 21 DummyInstruction (E7h)

• 40 - M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 4 0 5 1 6 2 7 3 A15-8 A7-0 4 0 5 1 6 2 7 3 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 IOs switch from Input to Output Byte 3 8 9 10 11 12 13 Dummy Figure 16b. Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only) Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Word Read Quad I/O instruction can also be used to access a specific por tion within a page by issuing a “Set Burst with Wrap” (77h) command prior to E7h. The “Set Burst with Wrap” (77h) command can either enable or disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is enabled, the data being a ccessed can be limited to either a 8, 16, 32 or 64 -byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 -byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32 /64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6 -4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. See 7.2.19 for detail descriptions.

Publication Release Date: October 07, 2013 - 41 - Revision L

6.2.18 Octal Word Read Quad I/O (E3h)

The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution (XIP). The Quad Enable bit (QE) of Status Register -2 must be se t to enable the Octal Wo rd Read Quad I/O Instruction. Octal Word Read Quad I/O with “Continuous Read Mode” The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7 -0) after the input Address bits (A23 -0), as shown in Figure 17a. The upper nibble of the (M7 -4) controls the length of the next Octal Word Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3 -0) are don’t care (“x”). However, the IO pins should be high -impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E 3h instruction code, as shown in Figure 17b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5 -4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation. M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output Byte 3 15 16 17 18 19 20 21 Instruction (E3h) 4 0 5 1 6 2 7 3 Byte 4 Figure 17a. Octal Word Read Quad I/O Instruction (Initial instruction or previous M5-4  10, SPI Mode only)

• 42 - M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 4 0 5 1 6 2 7 3 A15-8 A7-0 4 0 5 1 6 2 7 3 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 IOs switch from Input to Output Byte 3 8 9 10 11 12 13 4 0 5 1 6 2 7 3 Byte 4 Figure 17b. Octal Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)

6.2.19 Set Burst with Wrap (77h)

instruction sequence is shown in Figure 18. Wrap bit W7 and the lower nibble W3-0 are not used. Figure 18. Set Burst with Wrap Instruction (SPI Mode only)

• 44 -

6.2.20 Page Program (02h)

The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL = 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24 -bit address (A23 -A0) and at l east one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program instruction sequence is shown in Figure 19. If an entire 256 byte page is to be programmed, the last address byte (the 8 le ast significant address bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) ca n be programmed without having any effect on other bytes within the same page. One condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven high, the self -timed Page Program instruction will commence for a time duration of tpp (See AC Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits. /CS CLK DI (IO0) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (02h) 8 9 10 28 29 30 39 24-Bit Address 23 22 21 3 2 1 /CS CLK DI (IO0) 40 41 42 43 44 45 46 47 Data Byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 5139 32 33 34 35 36 37 38 Data Byte 1 7 6 5 4 3 2 1 Mode 0 Mode 3 Data Byte 3 2073 2074 2075 2076 2077 2078 2079 Data Byte 256 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 = MSB* Figure 19a. Page Program Instruction (SPI Mode)

Publication Release Date: October 07, 2013 - 45 - Revision L /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 02h Instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte1 Byte 2 Byte 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 Byte 255 Byte 256 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 Mode 0 Mode 3 516 517 518 519 Figure 19b. Page Program Instruction (QPI Mode)

6.2.21 Quad Input Page Program (32h)

improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. since the inherent page program time is much greater than the time it take to clock-in the data. instruction sequence is shown in Figure 20. Figure 20. Quad Input Page Program Instruction (SPI Mode only)

Publication Release Date: October 07, 2013 - 47 - Revision L

6.2.22 Sector Erase (20h)

The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before th e device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “20h” followed a 24 -bit sector address (A23 -A0) (see Figure 2). The Sector Erase instruction sequence is shown in Figure 21a & 21b. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Sector Erase instruction will not be executed. After /CS is driven high, the self -timed Sector Erase instruction will commence for a time duration of t SE (See AC Characteristics). While the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sec tor Erase instruction will not be executed if the addressed page is protected by the Block Protect ( CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (20h) High Impedance 8 9 29 30 31 24-Bit Address 23 22 2 1 0 Mode 0 Mode 3 = MSB* Figure 21a. Sector Erase Instruction (SPI Mode) /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 20h Instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 4 0 5 1 6 2 7 3 A15-8 A7-0 Mode 0 Mode 3 Figure 21b. Sector Erase Instruction (QPI Mode)

6.2.25 Chip Erase (C7h / 60h)

instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 24. Figure 24. Chip Erase Instruction for SPI Mode (left) or QPI Mode (right)

Publication Release Date: October 07, 2013 - 51 - Revision L

6.2.26 Erase / Program Suspend (75h)

The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase operation or a Page Program ope ration and then read from or program/erase data to, any other sectors or blocks. The Erase/Program Suspend instruction sequence is shown in Figure 25a & 25b. The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Register instruction (01h) and Program inst ructions (02h, 32h, 42h) are not allowed during Program Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation. The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation is on -going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by the device. A maximum of time of “tSUS” (See AC Characteristics) is required to suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within “t SUS” and the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase/Program Suspend. For a previously resumed Erase/Program operation, it is also required that the Suspend instruction “75h” is not issued earlier than a minimum of time of “t SUS” following the preceding Resume instruction “7Ah”. Unexpected power off during the Erase/Program suspend state will reset the device and release the suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was being suspended may become corrupted. It is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state. /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (75h) High Impedance Mode 0 Mode 3 tSUS Accept instructions Figure 25a. Erase/Program Suspend Instruction (SPI Mode)

• 52 - /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 75h Instruction Mode 0 Mode 3 tSUS Accept instructions Figure 25b. Erase/Program Suspend Instruction (QPI Mode)

Publication Release Date: October 07, 2013 - 53 - Revision L

6.2.27 Erase / Program Resume (7Ah)

The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by t he device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the era se operation or the page will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction “7Ah” will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 26a & 26b. Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of “tSUS” following a previous Resume instruction. /CS CLK DI (IO0) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (7Ah) Mode 0 Mode 3 Resume previously suspended Program or Erase Figure 26a. Erase/Program Resume Instruction (SPI Mode) /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 7Ah Instruction Mode 0 Mode 3 Resume previously suspended Program or Erase Figure 26b. Erase/Program Resume Instruction (QPI Mode)

• 54 -

6.2.28 Power-down (B9h)

Although the standby current during normal operation is relatively low, standby current can b e further reduced with the Power -down instruction. The lower power consumption makes the Power -down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 27a & 27b. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power -down instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of t DP (See AC Characteristics). While in the power -down state only the Release from Power - down / Device ID instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always pow ers-up in the normal operation with the standby current of ICC1. /CS CLK DI (IO0) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (B9h) Mode 0 Mode 3 tDP Power-down currentStand-by current Figure 27a. Deep Power-down Instruction (SPI Mode) /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 B9h Instruction Mode 0 Mode 3 tDP Power-down currentStand-by current Figure 27b. Deep Power-down Instruction (QPI Mode)

Publication Release Date: October 07, 2013 - 55 - Revision L

6.2.29 Release Power-down / Device ID (ABh)

The Release from Power -down / Device ID instruction is a multi -purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To release the device from the power -down state, the instruction is issued by driving the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in Figure 28a & 28b . Release from power-down will take the time duration of t RES1 (See AC Characteristics) before the devic e will resume normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the power -down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code “ABh” followed by 3 -dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 28. The Device ID values for the W25Q64FV is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. When used to release the device from the power -down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 28c & 28d , except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instructions will be accept ed. If the Release from Power -down / Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle. /CS CLK DI (IO0) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (ABh) Mode 0 Mode 3 tRES1 Power-down current Stand-by current Figure 28a. Release Power-down Instruction (SPI Mode)

• 56 - /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 ABh Instruction Mode 0 Mode 3 tRES1 Power-down current Stand-by current Figure 28b. Release Power-down Instruction (QPI Mode) tRES2 /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (ABh) High Impedance 8 9 29 30 31

3 Dummy Bytes

Power-down current Stand-by current= MSB* Figure 28c. Release Power-down / Device ID Instruction (SPI Mode) Power-down current Stand-by current Device ID /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 ABh 2 3 4 5 X X X X X X X X 6 7 8 4 0 5 1 6 2 7 3 IOs switch from Input to Output Instruction tRES2 Mode 0 Mode 3 X X X X X X X X X X X X X X X X Figure 28d. Release Power-down / Device ID Instruction (QPI Mode)

6.2.30 Read Manufacturer / Device ID (90h)

ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. table. The instruction is completed by driving /CS high. Figure 29. Read Manufacturer / Device ID Instruction (SPI Mode)

6.2.31 Read Manufacturer / Device ID Dual I/O (92h)

The Read Manufactur er / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. 24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock . Figure 30. Read Manufacturer / Device ID Dual I/O Instruction (SPI Mode only) The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction.

6.2.32 Read Manufacturer / Device ID Quad I/O (94h)

The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction. the other. The instruction is completed by driving /CS high. Figure 31. Read Manufacturer / Device ID Quad I/O Instruction (SPI Mode only) The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Quad I/O instruction.

6.2.33 Read Unique ID Number (4Bh)

bit ID is shifted out on the falling edge of CLK as shown in Figure 32. Figure 32. Read Unique ID Number Instruction (SPI Mode only)

Publication Release Date: October 07, 2013 - 61 - Revision L

6.2.34 Read JEDEC ID (9Fh)

For compatibility reasons, the W25Q64FV provides several instructions to electronically determine the identity of the de vice. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15 -ID8) and Capacity (ID7 -ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 33a & 33b . For memory type and capacity values refer to Manufacturer and Device Identification table. /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (9Fh) High Impedance 8 9 10 12 13 14 15 Capacity ID7-0 /CS CLK DI (IO0) DO (IO1) 16 17 18 19 20 21 22 23 Manufacturer ID (EFh) 24 25 26 28 29 30 7 6 5 4 3 2 1 0 2715 Mode 0 Mode 3 7 6 5 4 3 2 1 0 Memory Type ID15-8 = MSB* Figure 33a. Read JEDEC ID Instruction (SPI Mode) /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 9Fh 2 3 4 5 12 8 13 9 14 10 15 11 EFh 4 0 5 1 6 2 7 3 ID15-8 ID7-0 IOs switch from Input to Output Instruction Mode 0 Mode 3 Figure 33b. Read JEDEC ID Instruction (QPI Mode)

6.2.35 Read SFDP Register (5Ah)

code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet. Application Note for SFDP Definition table. Note: 1. A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register. Figure 34. Read SFDP Register Instruction Sequence Diagram (SPI Mode only)

6.2.36 Erase Security Registers (44h)

important information separately from the main memory array. instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the four security registers. after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed. register will be ignored (See 11.1.9 for detail descriptions). Figure 35. Erase Security Registers Instruction (SPI Mode only)

6.2.37 Program Security Registers (42h)

Figure 36. Program Security Registers Instruction (SPI Mode only)

6.2.38 Read Security Registers (48h)

maximum of FR (see AC Electrical Characteristics). Figure 37. Read Security Registers Instruction (SPI Mode only)

6.2.39 Set Read Parameters (C0h)

with Wrap (0Ch)” instruction. to any 0Bh, EBh or 0Ch instructions. Figure 38. Set Read Parameters Instruction (QPI Mode only)

6.2.40 Burst Read with Wrap (0Ch)

“Wrap Length” once the ending boundary is reached. set the number of dummy clocks. Figure 39. Burst Read with Wrap Instruction (QPI Mode only)

6.2.41 Enable QPI (38h)

instruction is the only way to switch the device from SPI mode to QPI mode. (QE) bit in Status Register 2 must be set to 1 first, and an “Enable QPI (38h)” instruction must be issued . See Instruction Set Table 4 for all the commands supported in QPI mode. Suspend status, and the Wrap Length setting will remain unchanged. Figure 40. Enable QPI Instruction (SPI Mode only)

6.2.42 Disable QPI (FFh)

Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. Figure 41. Disable QPI Instruction (QPI Mode only)

• 70 -

6.2.43 Enable Reset (66h) and Reset (99h)

Because of the small package and the limitation on the number of pins, t he W 25Q64FV provide a software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going internal operations will be terminated and the device will return to its default power -on state and lose all the current volatile settings, such as Volatile Status Register bits, Write E nable Latch (WEL) status, Program/Erase Suspend status, Read parameter setting (P7-P0), Continuous Read Mode bit setting (M7-M0) and Wrap Bit setting (W6-W4). “Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode. To avoid accidental reset, both instructions must be issued in sequence. Any other commands other than “Reset (99h)” after the “Enable Reset (66h)” command will disable the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset command is accepted by the device, the device will take approximately tRST=30us to reset. During this period, no command will be accepted. Data corruption may happen if there is an on -going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (99h) Mode 0 Mode 3 /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (66h) High Impedance Figure 42a. Enable Reset and Reset Instruction Sequence (SPI Mode) Mode 0 Mode 3 0 1 99h Instruction Mode 0 Mode 3 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 66h Instruction Figure 42b. Enable Reset and Reset Instruction Sequence (QPI Mode)

Publication Release Date: October 07, 2013 - 71 - Revision L 7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings (1)(2)

PARAMETERS SYMBOL CONDITIONS RANGE UNIT Supply Voltage VCC –0.6 to 4.6V V Voltage Applied to Any Pin VIO Relative to Ground –0.6 to VCC+0.4 V Transient Voltage on any Pin VIOT <20nS Transient Relative to Ground –2.0V to VCC+2.0V V Storage Temperature TSTG –65 to +150 °C Lead Temperature TLEAD See Note °C Electrostatic Discharge Voltage VESD(3) Human Body Model –2000 to +2000 V Notes: 1.This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage. 2.JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms). 3.Compliant with JEDEC Standard J -STD-20C for small body Sn -Pb or Pb -free (Green) assembly and the European direc tive on restrictions on hazardous substances (RoHS) 2002/95/EU.

7.2 Operating Ranges

PARAMETER SYMBOL CONDITIONS SPEC UNIT MIN MAX Supply Voltage(1) VCC FR = 104MHz, fR = 50MHz FR = 80MHz, fR = 33MHz 3.0 2.7 3.6 3.0 V Ambient Temperature, Operating TA Industrial –40 +85 °C Note: 1.VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming (erase/write) voltage.

• 72 -

7.3 Power-up Power-down Timing and Requirements(1)

VCC (min) to /CS Low tVSL 20 µs Time Delay Before Write Instruction tPUW 5 ms Write Inhibit Threshold Voltage VWI 1.0 2.0 V Note: 1. These parameters are characterized only. VCC tVSL Read Instructions Allowed Device is fully Accessible tPUW /CS must track VCC Program, Erase and Write Instructions are ignored Reset State VCC (max) VCC (min) VWI Time Figure 43a. Power-up Timing and Voltage Levels VCC Time /CS must track VCC during VCC Ramp Up/Down /CS Figure 43b. Power-up, Power-Down Requirement

Publication Release Date: October 07, 2013 - 73 - Revision L

7.4 DC Electrical Characteristics

PARAMETER SYMBOL CONDITIONS SPEC UNIT MIN TYP MAX Input Capacitance CIN(1) VIN = 0V 6 pF Output Capacitance Cout(1) VOUT = 0V 8 pF Input Leakage ILI ±2 µA I/O Leakage ILO ±2 µA Standby Current ICC1 /CS = VCC, VIN = GND or VCC 10 50 µA Power-down Current ICC2 /CS = VCC, VIN = GND or VCC 1 25 µA Current Read Data / Dual /Quad 50MHz ICC3(2) C = 0.1 VCC / 0.9 VCC DO = Open 15 mA Current Read Data / Dual /Quad 80MHz ICC3(2) C = 0.1 VCC / 0.9 VCC DO = Open 18 mA Current Read Data / Dual Output Read/Quad Output Read 104MHz ICC3(2) C = 0.1 VCC / 0.9 VCC DO = Open 20 mA Current Write Status Register ICC4 /CS = VCC 8 12 mA Current Page Program ICC5 /CS = VCC 20 25 mA Current Sector/Block Erase ICC6 /CS = VCC 20 25 mA Current Chip Erase ICC7 /CS = VCC 20 25 mA Input Low Voltage VIL –0.5 VCC x 0.3 V Input High Voltage VIH VCC x 0.7 VCC + 0.4 V Output Low Voltage VOL IOL = 100 µA 0.2 V Output High Voltage VOH IOH = –100 µA VCC – 0.2 V Notes: 1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.0V. 2. Checker Board Pattern.

7.5 AC Measurement Conditions(1)

1. Output Hi-Z is defined as the point where data out is no longer driven.

0.9 VCC

0.1 VCC

0.5 VCC

Figure 44. AC Measurement I/O Waveform

Publication Release Date: October 07, 2013 - 75 - Revision L

7.6 AC Electrical Characteristics

Clock frequency for all other instructions 3.0-3.6V, except Read data instructions (03h) FR fC1 D.C. 104 MHz Clock frequency for all other instructions 2.7-3.0V, except Read data instructions (03h) FR fC1 D.C. 80 MHz Clock frequency for SPI Read data instructions(03h) 3.0-3.6V fR fC2 D.C. 50 MHz Clock frequency for SPI Read data instructions (03h) 2.7-3.0V fR fC2 D.C. 33 MHz Clock High, Low Time for all instructions except for Read Data (03h) tCLH, tCLL(1) 4 ns Clock High, Low Time for Read Data (03h) instruction tCRLH, tCRLL(1) 6 ns Clock Rise Time peak to peak tCLCH(2) 0.1 V/ns Clock Fall Time peak to peak tCHCL(2) 0.1 V/ns /CS Active Setup Time relative to CLK tSLCH tCSS 5 ns /CS Not Active Hold Time relative to CLK tCHSL 5 ns Data In Setup Time tDVCH tDSU 2 ns Data In Hold Time tCHDX tDH 3 ns /CS Active Hold Time relative to CLK tCHSH 5 ns /CS Not Active Setup Time relative to CLK tSHCH 5 ns /CS Deselect Time (for Erase or Program  Read Status Registers) tSHSL tCSH 50 ns Output Disable Time tSHQZ(2) tDIS 7 ns Clock Low to Output Valid tCLQV tV 7 ns Output Hold Time tCLQX tHO 0 ns /HOLD Active Setup Time relative to CLK tHLCH 5 ns /HOLD Active Hold Time relative to CLK tCHHH 5 ns /HOLD Not Active Setup Time relative to CLK tHHCH 5 ns Continued – next page

• 76 - DESCRIPTION SYMBOL ALT SPEC UNIT MIN TYP MAX /HOLD Not Active Hold Time relative to CLK tCHHL 5 ns /HOLD to Output Low-Z tHHQX(2) tLZ 7 ns /HOLD to Output High-Z tHLQZ(2) tHZ 12 ns Write Protect Setup Time Before /CS Low tWHSL(3) 20 ns Write Protect Hold Time After /CS High tSHWL(3) 100 ns /CS High to Power-down Mode tDP(2) 3 µs /CS High to Standby Mode without Electronic Signature Read tRES1(2) 3 µs /CS High to Standby Mode with Electronic Signature Read tRES2(2) 3 µs /CS High to next Instruction after Suspend tSUS(2) 20 µs /CS High to next Instruction after Reset tRST(2) 30 µs Write Status Register Time tW 15 20 ms Byte Program Time (First Byte) tBP1(4) 20 50 µs Additional Byte Program Time (After First Byte) tBP2(4) 2.5 10 µs Page Program Time tPP 0.7 3 ms Sector Erase Time (4KB) W25Q64FVxxIG tSE 400 ms W25Q64FVxxIQ & W25Q64FVxxIF 45 Block Erase Time (32KB) tBE1 120 1,600 ms Block Erase Time (64KB) tBE2 150 2,000 ms Chip Erase Time tCE 20 100 s Notes: 1. Clock high + Clock low must be less than or equal to 1/fC. 2. Value guaranteed by design and/or characterization, not 100% tested in production. 3. Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1). 4. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes programmed. 5. 4-bytes address alignment for QPI/Quad Read

Publication Release Date: October 07, 2013 - 77 - Revision L

7.7 Serial Output Timing

/CS CLK IO output tCLQX tCLQV tCLQX tCLQV tSHQZtCLL LSB OUT tCLH MSB OUT

7.8 Serial Input Timing

/CS CLK IO input tCHSL MSB IN tSLCH tDVCH tCHDX tSHCHtCHSH tCLCH tCHCL LSB IN tSHSL 7.9 /HOLD Timing /CS CLK IO output /HOLD tCHHL tHLCH tCHHH tHHCH tHLQZ tHHQX IO input 7.10 /WP Timing /CS CLK /WP tWHSL tSHWL IO input Write Status Register is allowed Write Status Register is not allowed

• 78 - 8. PACKAGE SPECIFICATION 8.1 8-Pin SOIC 208-mil (Package Code SS) θ Symbol Millimeters Inches Min Nom Max Min Nom Max e 1.27 BSC 0.050 BSC

Publication Release Date: October 07, 2013 - 79 - Revision L 8.2 8-Pin VSOP 208-mil (Package Code ST) θ θ Symbol Millimeters Inches Min Nom Max Min Nom Max c 0.127 REF 0.005 REF θ 0° ― 8° 0° ― 8°

• 80 - 8.3 8-Pin PDIP 300-mil (Package Code DA) Symbol Millimeters Inches Min Nom Max Min Nom Max E 7.62 BSC 0.300 BSC d p w

Publication Release Date: October 07, 2013 - 81 - Revision L 8.4 8-Pad WSON 6x5-mm (Package Code ZP) Symbol Millimeters Inches Min Nom Max Min Nom Max e 1.27 BSC 0.050 BSC Note: 1.The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.

• 82 - 8.5 8-Pad WSON 8x6-mm (Package Code ZE) Symbol Millimeters Inches Min Nom Max Min Nom Max Note: The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.

Publication Release Date: October 07, 2013 - 83 - Revision L 8.6 16-Pin SOIC 300-mil (Package Code SF) Symbol Millimeters Inches Min Nom Max Min Nom Max e 1.27 BSC 0.050 BSC

• 84 - 8.7 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 ball array) Symbol Millimeters Inches Min Nom Max Min Nom Max D1 4.00 BSC 0.157 BSC E1 4.00 BSC 0.157 BSC SE 1.00 TYP 0.039 TYP SD 1.00 TYP 0.039 TYP e 1.00 BSC 0.039 BSC Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm

Publication Release Date: October 07, 2013 - 85 - Revision L 8.8 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array) Symbol Millimeters Inches Min Nom Max Min Nom Max D1 5.00 BSC 0.197 BSC E1 3.00 BSC 0.118 BSC e 1.00 BSC 0.039 BSC Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm

• 86 -

8.9 Ordering Information

Notes: 1. The “W” prefix is not included on the part marking. 2. Only the 2nd letter is used for the part marking; WSON package type ZP and ZE are not used for the part marking. 3. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 4. For shipments with OTP feature enabled, please contact Winbond. W(1) 25Q 64F V xx(2) W = Winbond 25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 64F = 64M -bit V = 2.7V to 3.6V I = Industrial ( -40°C to +85°C) (3,4) G = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) F = Green Package with Fast Sector Erase time (tSE) Q = Green Package with QE=1 in Status Register-2 SS = 8 -pin SOIC 208-mil ZP = 8 -pad WSON 6x5mm DA = 8 -pin PDIP 300-mil SF = 16 -pin SOIC 300-mil ZE = 8 -pad WSON 8x6mm ST = 8 -pin VSOP 208-mil TC = 24 -ball TFBGA 8x6mm (6x4 ball array) TB = 24 -ball TFBGA 8x6mm (5x5-1 ball array)

Publication Release Date: October 07, 2013 - 87 - Revision L

8.10 Valid Part Numbers and Top Side Marking

The following table provides the valid part numbers for the W25Q64FV SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 1 2- digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 10-digit number. PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING SS SOIC-8 208mil 64M-bit W25Q64FVSSIG W25Q64FVSSIQ W25Q64FVSSIF 25Q64FVSIG 25Q64FVSIQ 25Q64FVSIF ST VSOP-8 208mil 64M-bit W25Q64FVSTIG W25Q64FVSTIF 25Q64FVTIG 25Q64FVTIF SF SOIC-16 300mil 64M-bit W25Q64FVSFIG W25Q64FVSFIQ W25Q64FVSFIF 25Q64FVFIG 25Q64FVFIQ 25Q64FVFIF DA PDIP-8 300mil 64M-bit W25Q64FVDAIG W25Q64FVDAIQ W25Q64FVDAIF 25Q64FVAIG 25Q64FVAIQ 25Q64FVAIF ZP(1) WSON-8 6x5mm 64M-bit W25Q64FVZPIG W25Q64FVZPIQ W25Q64FVZPIF 25Q64FVIG 25Q64FVIQ 25Q64FVIF ZE(1) WSON-8 8x6mm 64M-bit W25Q64FVZEIG W25Q64FVZEIF 25Q64FVIG 25Q64FVIF TB TFBGA-24 8x6mm (5x5 Ball Array) 64M-bit W25Q64FVTBIG W25Q64FVTBIF 25Q64FVBIG 25Q64FVBIF TC TFBGA-24 8x6mm (6x4 Ball Array) 64M-bit W25Q64FVTCIG W25Q64FVTCIF 25Q64FVCIG 25Q64FVCIF Note: 1.For WSON packages, the package type ZP and ZE is not used in the top side marking.

• 88 - 9. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A 03/29/2011 All New Create Preliminary B 08/10/2011 60-62 5-9, 81, 85-87 Updated SFDP to JESD216 Added PDIP, TFBGA package types C 11/02/2011 All Removed preliminary designator D 04/13/2012 9, 79, 84, 86-87 Referred to SFDP definition application note Updated clock high/low time for Read Data Updated Erase Time Updated WSON metal pad size Added TFBGA 5x5, VSOP packages, Q order option E 07/13/2012 10, 14, 72 Added power-down requirement Updated PDIP part number F 10/15/2012 Updated power-up timing parameters Updated PDIP dimensions Updated ordering part number G 03/15/2013 76 86,87 Added tSE of W25Q64FVxxIF Added W25Q64FVxxIF into order information H 04/11/2013 76 Moidfied tSE of W25Q64FVxxIQ & IF I 04/25/2013 81,82 Added Quad Enable default description Modified Supply Voltage Updated note for metal pad for WSON, USON J 05/30/2013 5,10,88-90 Added WLBGA package type K 06/10/2013 89 Added WLBGA “TOP SIDE MARKING” K1 09/10/2013 89 Added WLBGA for W25Q64FVBYIQ L 10/07/2013 59,60 76-77 5,17,76,86-87 Modified the description of 92h and 94h Modified DC Electrical Characteristics Modified AC Electrical Characteristics Removed the W25Q64FVxxIP & WLBGA package

Publication Release Date: October 07, 2013 - 89 - Revision L Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Information in this document is provided solely in connection with Winbond products. Winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice.