25Q16DVAIG

W25Q16DV WINBOND | Alldatasheet

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Technical content

Publication Release Date: May 23, 2016 - 1 - Revision K 3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

• 2 - Table of Contents

Publication Release Date: May 23, 2016 - 3 - Revision K

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Publication Release Date: May 23, 2016 - 5 - Revision K 1. GENERAL DESCRIPTION The W25Q16DV (16M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from D ual/Quad SPI (XIP) and storing voice, text and data. The device operate s on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. The W25Q16DV array is organized into 8,192 programmable pages of 256 -bytes each. Up to 256 bytes can be programmed at a time. Pag es can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 ( 64KB block erase) or the entire chip (chip erase). The W25Q16DV has 512 erasable sectors and 32 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25Q16DV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O 0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD) . SPI clock frequencies of up to 104MHz are suppo rted allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16 -bit Parallel Flash memorie s. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protect ion, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number. 2. FEATURES  Family of SpiFlash Memories – W25Q16DV: 16M-bit / 2M-byte (2,097,152) – 256-byte per programmable page – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3  Highest Performance Serial Flash – 104MHz Dual SPI / Quad SPI clocks – 208/416MHz equivalent Dual/Quad SPI – 52MB/S continuous data transfer rate – Up to 8X that of ordinary Serial Flash – More than 100,000 erase/program cycles – More than 20-year data retention  Efficient “Continuous Read Mode” – Low Instruction overhead – Continuous Read with 8/16/32/64-Byte Wrap – As few as 8 clocks to address memory – Allows true XIP (execute in place) operation – Outperforms X16 Parallel Flash  Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply – 4mA active current, <1µA Power-down (typ.) – -40° C to +85° C operating range  Flexible Architecture with 4KB sectors – Uniform Sector/Block Erase (4/32/64K-bytes) – Program one to 256 bytes – Erase/Program Suspend & Resume  Advanced Security & Identification Features – Software and Hardware Write-Protect – Top/Bottom, 4KB complement array protection – Power Supply Lock-Down and OTP protection – 64-Bit Unique ID for each device – Discoverable Parameters (SFDP) Register – 3X256-Byte Security Registers with OTP locks – Volatile & Non-volatile Status Register Bits  Space Efficient Packaging(1) – 8-pin SOIC 150/208-mil – 8-pad WSON 6x5-mm – 8-pad USON 4X3mm / 4X4mm – 8-pin PDIP 300-mil – 8-ball WLCSP – 16-pin SOIC 300-mil – 24-ball TFBGA 8x6-mm (6x4/5x5 ball array) – Contact Winbond for KGD and other options Note 1. Some package types are special orders, please contact Winbond for ordering information .

• 6 - 3. PACKAGE TYPES AND PIN CONFIGURATIONS W25Q16DV is offered in an 8 -pin SOIC 150 -mil or 208 -mil (package code SN & SS), an 8-pad WSON 6x5-mm (package code ZP) , an 8-pad USON 4x3-mm (package code UU), an 8-pad USON 4x4-mm (package code UZ), an 8-pin PDIP 300-mil (package code DA), a 16-pin SOIC 300-mil (package code SF) and a 24-ball 8x6-mm TFBGA ( 5x5 ball array - package code TB, 6x4 ball array – package code TC) as shown in Figure 1a -f respectively. Package diagrams and dimensions are illustrated at the end of this datasheet.

3.1 Pin Configuration SOIC 150 / 208-mil

/CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) DI (IO0) CLK Top View Figure 1a. W25Q16DV Pin Assignments, 8-pin SOIC 150 / 208-mil (Package Code SN, SS, SV, ST)

3.2 Pad Configuration WSON 6x5-mm / USON 4X3-mm / USON 4X4-mm

/CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) DI (IO0) CLK Top View Figure 1b. W25Q16DV Pad Assignments, 8-pad WSON 6x5-mm / USON 4x3-mm (Package Code ZP,UU,UZ)

Publication Release Date: May 23, 2016 - 7 - Revision K

3.3 Pin Configuration PDIP 300-mil

/CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) DI (IO0) CLK Top View Figure 1c. W25Q16DV Pin Assignments, 8-pin PDIP (Package Code DA)

3.4 Pin Description SOIC 150/208-mil, WSON 6x5-mm / USON 4x3-mm / PDIP 300-mil

PIN NO. PIN NAME I/O FUNCTION 1 /CS I Chip Select Input

2 DO (IO1) I/O Data Output (Data Input Output 1)*1

3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)*2

4 GND Ground

5 DI (IO0) I/O Data Input (Data Input Output 0)*1

6 CLK I Serial Clock Input

7 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2

8 VCC Power Supply

*1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions

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3.5 Ball Configuration WLCSP

DI(IO0) /CS VCC DO(IO1) /HOLD(IO3) /WP(IO2) CLK Top View GND DI(IO0) /CS VCC DO(IO1) /HOLD(IO3) /WP(IO2) CLK Bottom View Figure 1f. W25Q16DV Ball Assignments, 8-ball WLCSP (Package Code BY)

3.6 Ball Description WLCSP

BALL NO. PIN NAME I/O FUNCTION A1 VCC Power Supply A2 /CS I Chip Select Input B1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2 B2 DO (IO1) I/O Data Output (Data Input Output 1)*1 C1 CLK I Serial Clock Input C2 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2 D1 DI (IO0) I/O Data Input (Data Input Output 0)*1 D2 GND Ground *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions

Publication Release Date: May 23, 2016 - 9 - Revision K

3.7 Pin Configuration SOIC 300-mil

/CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) DI (IO0) CLK Top View NC NC NC NC NC NC NC NC5 Figure 1d. W25Q16DV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)

3.8 Pin Description SOIC 300-mil

PIN NO. PIN NAME I/O FUNCTION 1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2

2 VCC Power Supply

3 N/C No Connect

4 N/C No Connect

5 N/C No Connect

6 N/C No Connect

8 DO (IO1) I/O Data Output (Data Input Output 1)*1

9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2

10 GND Ground

11 N/C No Connect

12 N/C No Connect

13 N/C No Connect

14 N/C No Connect

15 DI (IO0) I/O Data Input (Data Input Output 0)*1

16 CLK I Serial Clock Input

*1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions

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3.9 Ball Configuration TFBGA 8x6-mm

/HOLD(IO3)DI(IO0)DO(IO1) /WP (IO2) D2 D3 D4 NC NCNCNC E2 E3 E4 NC NCNCNC F2 F3 F4 NC NCNCNC A2 A3 A4 NC VCCGNDCLK B2 B3 B4 NC NC/CS C2 C3 C4 NC Top View Package Code TC /HOLD(IO3)DI(IO0)DO(IO1) /WP (IO2) D2 D3 D4 NC NCNCNC E2 E3 E4 NC NCNCNC A2 A3 A4 NC VCCGNDCLK B2 B3 B4 NC NC/CS C2 C3 C4 NC Top View Package Code TB NC NC NC NC Figure 1e. W25Q16DV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB or TC)

3.10 Ball Description TFBGA 8x6-mm

BALL NO. PIN NAME I/O FUNCTION B2 CLK I Serial Clock Input B3 GND Ground B4 VCC Power Supply C2 /CS I Chip Select Input C4 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2 D2 DO (IO1) I/O Data Output (Data Input Output 1)*1 D3 DI (IO0) I/O Data Input (Data Input Output 0)*1 D4 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2 Multiple NC No Connect *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions

Publication Release Date: May 23, 2016 - 11 - Revision K 4. PIN DESCRIPTIONS

4.1 Chip Select (/CS)

The SPI Chip Select ( /CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, I O3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up and power-down (see “Write Protection” and figure 39). If needed a pull-up resister on /CS can be used to accomplish this.

4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)

The W25Q16DV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual and Quad SPI instruction s use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on th e falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register -2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

4.3 Write Protect (/WP)

The Write Protect ( /WP) pin can be used to preven t the Status Register from being written. Used in conjunction with the Status Register’s Block Protect ( CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register -2 is set for Quad I/O, the /WP pin function is not available since this pin is used for IO2. See figure 1a-e for the pin configuration of Quad I/O operation.

4.4 HOLD (/HOLD)

The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operati on can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register -2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See figure 1a-e for the pin configuration of Quad I/O operation.

4.5 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input an d output operations. ("See SPI Operations")

Figure 2. W25Q16DV Serial Flash Memory Block Diagram

• Sector 0 (4KB) • xx0000h xx00FFh xx1F00h xx1FFFh
• Sector 1 (4KB) • xx1000h xx10FFh xx2F00h xx2FFFh
• Sector 2 (4KB) • xx2000h xx20FFh xxDF00h xxDFFFh
• Sector 13 (4KB) • xxD000h xxD0FFh xxEF00h xxEFFFh
• Sector 14 (4KB) • xxE000h xxE0FFh xxFF00h xxFFFFh
• Sector 15 (4KB) • xxF000h xxF0FFh Block Segmentation Data Security Register 1 - 3 Write Protect Logic and Row Decode 00FF00h 00FFFFh
• Block 0 (64KB) • 000000h 0000FFh 07FF00h 07FFFFh
• Block 7 (64KB) • 070000h 0700FFh 08FF00h 08FFFFh
• Block 8 (64KB) • 080000h 0800FFh 0FFF00h 0FFFFFh
• Block 15 (64KB) • 0F0000h 0F00FFh 10FF00h 10FFFFh
• Block 16 (64KB) • 100000h 1000FFh 1FFF00h 1FFFFFh
• Block 31 (64KB) • 1F0000h 1F00FFh 000000h 0000FFh SFDP Register

Publication Release Date: May 23, 2016 - 13 - Revision K 6. FUNCTIONAL DESCRIPTION

6.1 SPI OPERATIONS

6.1.1 Standard SPI Instructions

The W25Q16DV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select ( /CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge CLK. SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the S erial Flash. For Mode 0 , the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.

6.1.2 Dual SPI Instructions

The W25Q16DV supports Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power -up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP) . When using Dual SPI instructions , the DI and DO pins become bidirectional I/O pins: IO0 and IO1.

6.1.3 Quad SPI Instructions

The W25Q16DV supports Quad SPI operation whe n using the “ Fast Read Quad Output (6Bh)”, “ Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O (E3h)” instructions. These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code -shadowing to RAM or execution directly from the SPI bus (XIP) . When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1 , and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non -volatile Quad Enable bit (QE) in Status Register-2 to be set.

6.1.4 Hold Function

For Standard SPI and Dual SPI operations, t he /HOLD signal allows the W25Q16DV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devic es. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation, not during Quad SPI. To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK sign al is already low. If the CLK is not already low the /HOLD

• 14 - condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high impedance, a nd Serial Data Input (DI ) and Serial Clock (CLK) are ignored. The Chip Select ( /CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device.

6.2 WRITE PROTECTION

Applications that use non -volatile memory must take into consideration the pos sibility of noise and other adverse system conditions that may compromise data integrity. To address this concern , the W25Q16DV provides several means to protect the data from inadvertent writes.

6.2.1 Write Protect Features

 Device resets when VCC is below threshold  Time delay write disable after Power-up  Write enable/disable instructions and automatic write disable after erase or program  Software and Hardware (/WP pin) write protection using Status Register  Write Protection using Power-down instruction  Lock Down write protection until next power-up  One Time Program (OTP) write protection* * Note: This feature is available upon special order. Please contact Winbond for details. Upon power-up or at power-down, the W25Q16DV will maintain a reset condition while VCC is below the threshold value of V WI, (See Power -up Timing and Voltage Levels and Figure 39). While reset, all operations are disabled and no instructions are recognized. During power -up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of t PUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin ( /CS) must track the VCC supply le vel at power-up until the VCC-min level and t VSL time delay is reached , and it must also track the VCC supply level at power - down to prevent adverse command sequence . If needed a pull -up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write -disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instructio n will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write - disabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0) bits. These settings allow a portion as small as 4KB sector or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register section for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instruction s are ignored except for the Release Power-down instruction.

Publication Release Date: May 23, 2016 - 15 - Revision K 7. STATUS REGISTERS AND INSTRUCTIONS The Read Status Register -1 and Status Register -2 instructions can be used to provide status on the availability of the Flash memory array, if the device is writ e enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status and Erase/Program Suspend status . The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting and Security Register OTP lock. Write access to the Status Register is controlled by the state of the non- volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI operations, the /WP pin.

7.1 STATUS REGISTERS

7.1.1 BUSY Status (BUSY)

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Registe r instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see t W, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status /security register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.

7.1.2 Write Enable Latch Status (WEL)

Write Enable Latch (WEL) is a read only bit in the statu s register (S1) that is set to 1 after executing a Write Enable Instruction. Th e WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power -up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register , Erase Security Register and Program Security Register.

7.1.3 Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see t W in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (se e Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected.

7.1.4 Top/Bottom Block Protect Bit (TB)

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, B P0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The f actory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits.

7.1.5 Sector/Block Protect Bit (SEC)

The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0.

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7.1.6 Complement Protect Bit (CMP)

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not; when CMP=1, the top 4KB sector will become unprotected while the rest of the array become read -only. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0.

7.1.7 Status Register Protect Bits (SRP1, SRP0)

The Status Register Protect bits (SRP1 and SRP0 ) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. SRP1 SRP0 /WP Status Register Description 0 0 X Software Protection /WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default] 0 1 0 Hardware Protected When /WP pin is low the Status Register locked and can not be written to. 0 1 1 Hardware Unprotected When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. 1 0 X Power Supply Lock-Down Status Register is protected and can not be written to again until the next power-down, power-up cycle.(1) 1 1 X One Time Program(2) Status Register is permanently protected and can not be written to. Notes: 1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available upon special order. Please contact Winbond for details.

7.1.8 Erase/Program Suspend Status (SUS)

The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 af ter executing a Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle.

7.1.9 Security Register Lock Bits (LB3, LB2, LB1)

The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11) that provide the write protect control and status to the Security Registers . The default state of LB[3:1] is 0, Security Registers are unlocked. LB [3:1] can be set to 1 individually using the Write Status Register instruction. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the corresponding 256-Byte Security Register will become read-only permanently.

Publication Release Date: May 23, 2016 - 17 - Revision K

7.1.10 Quad Enable Bit (QE)

The Quad Enable (QE) bit is a no n-volatile read/write bit in the status register (S9) that allows Quad SPI operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1 , the Quad IO2 and I O3 pins are enabled , and /WP an d /HOLD functions are disabled. WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during standard SPI or Dual SPI operation, the QE bit should never be set to a 1. S7 S6 S5 S4 S3 S2 S1 S0 SRP0 SEC TB BP2 BP1 BP0 WEL BUSY STATUS REGISTER PROTECT 0 (non-volatile) SECTOR PROTECT (non-volatile) TOP/BOTTOM PROTECT (non-volatile) BLOCK PROTECT BITS (non-volatile) WRITE ENABLE LATCH ERASE/WRITE IN PROGRESS S7 S6 S5 S4 S3 S2 S1 S0 SRP0 SEC TB BP2 BP1 BP0 WEL BUSY STATUS REGISTER PROTECT 0 (non-volatile) SECTOR PROTECT (non-volatile) TOP/BOTTOM PROTECT (non-volatile) BLOCK PROTECT BITS (non-volatile) WRITE ENABLE LATCH ERASE/WRITE IN PROGRESS Figure 3a. Status Register-1 S15 S14 S13 S12 S11 S10 S9 S8 SUS CMP LB3 LB2 LB1 (R) QE SRP1 SUSPEND STATUS COMPLEMENT PROTECT (non-volatile) SECURITY REGISTER LOCK BITS (non-volatile OTP) QUAD ENABLE (non-volatile) STATUS REGISTER PROTECT 1 (non-volatile) RESERVED S15 S14 S13 S12 S11 S10 S9 S8 SUS CMP LB3 LB2 LB1 (R) QE SRP1 SUSPEND STATUS COMPLEMENT PROTECT (non-volatile) SECURITY REGISTER LOCK BITS (non-volatile OTP) QUAD ENABLE (non-volatile) STATUS REGISTER PROTECT 1 (non-volatile) RESERVED Figure 3b. Status Register-2

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7.1.11 Status Register Memory Protection (CMP = 0)

STATUS REGISTER(1) W25Q16DV (16M-BIT) MEMORY PROTECTION(3) SEC TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED DENSITY PROTECTED PORTION(2) X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 31 1F0000h – 1FFFFFh 64KB Upper 1/32 0 0 0 1 0 30 and 31 1E0000h – 1FFFFFh 128KB Upper 1/16 0 0 0 1 1 28 thru 31 1C0000h – 1FFFFFh 256KB Upper 1/8 0 0 1 0 0 24 thru 31 180000h – 1FFFFFh 512KB Upper 1/4 0 0 1 0 1 16 thru 31 100000h – 1FFFFFh 1MB Upper 1/2 0 1 0 0 1 0 000000h – 00FFFFh 64KB Lower 1/32 0 1 0 1 0 0 and 1 000000h – 01FFFFh 128KB Lower 1/16 0 1 0 1 1 0 thru 3 000000h – 03FFFFh 256KB Lower 1/8 0 1 1 0 0 0 thru 7 000000h – 07FFFFh 512KB Lower 1/4 0 1 1 0 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/2 X X 1 1 X 0 thru 31 000000h – 1FFFFFh 2MB ALL 1 0 0 0 1 31 1FF000h – 1FFFFFh 4KB U – 1/512 1 0 0 1 0 31 1FE000h – 1FFFFFh 8KB U – 1/256 1 0 0 1 1 31 1FC000h – 1FFFFFh 16KB U – 1/128 1 0 1 0 X 31 1F8000h – 1FFFFFh 32KB U – 1/64 1 1 0 0 1 0 000000h – 000FFFh 4KB L – 1/512 1 1 0 1 0 0 000000h – 001FFFh 8KB L – 1/256 1 1 0 1 1 0 000000h – 003FFFh 16KB L – 1/128 1 1 1 0 X 0 000000h – 007FFFh 32KB L – 1/64 Notes: 1. X = don’t care 2. L = Lower; U = Upper 3. If any Erase or Pro gram command specifies a memory region that contains protected data portion, this command will be ignored.

Publication Release Date: May 23, 2016 - 19 - Revision K

7.1.12 Status Register Memory Protection (CMP = 1)

STATUS REGISTER(1) W25Q16DV (16M-BIT) MEMORY PROTECTION(3) SEC TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED DENSITY PROTECTED PORTION(2) X X 0 0 0 0 thru 31 000000h – 1FFFFFh ALL ALL 0 0 0 0 1 0 thru 30 000000h – 1EFFFFh 1,984KB Lower 31/32 0 0 0 1 0 0 thru 29 000000h – 1DFFFFh 1,920KB Lower 15/16 0 0 0 1 1 0 thru 27 000000h – 1BFFFFh 1,792KB Lower 7/8 0 0 1 0 0 0 thru 23 000000h – 17FFFFh 1,536KB Lower 3/4 0 0 1 0 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/2 0 1 0 0 1 1 thru 31 010000h – 1FFFFFh 1,984KB Upper 31/32 0 1 0 1 0 2 and 31 020000h – 1FFFFFh 1,920KB Upper 15/16 0 1 0 1 1 4 thru 31 040000h – 1FFFFFh 1,792KB Upper 7/8 0 1 1 0 0 8 thru 31 080000h – 1FFFFFh 1,536KB Upper 3/4 0 1 1 0 1 16 thru 31 100000h – 1FFFFFh 1MB Upper 1/2 X X 1 1 X NONE NONE NONE NONE 1 0 0 0 1 0 thru 31 000000h – 1FEFFFh 2,044KB L – 511/512 1 0 0 1 0 0 thru 31 000000h – 1FDFFFh 2,040KB L – 255/256 1 0 0 1 1 0 thru 31 000000h – 1FBFFFh 2,032KB L – 127/128 1 0 1 0 X 0 thru 31 000000h – 1F7FFFh 2,016KB L – 63/64 1 1 0 0 1 0 thru 31 001000h – 1FFFFFh 2,044KB U – 511/512 1 1 0 1 0 0 thru 31 002000h – 1FFFFFh 2,040KB U – 255/256 1 1 0 1 1 0 thru 31 004000h – 1FFFFFh 2,032KB U – 127/128 1 1 1 0 X 0 thru 31 008000h – 1FFFFFh 2,016KB U – 63/64 Notes: 1. X = don’t care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.

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7.2 INSTRUCTIONS

The instruction set of the W25Q16DV consists of thirty five basic instructions that are fully controlled through the SPI bus (see Instruction Set table 1-3). Instructions are ini tiated with the falling edge of Chip Select (/CS). The first byte of data clo cked into the DI input provides the i nstruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each instru ction are included in figures 4 through 37. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary ( /CS driven high after a full 8 -bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Regis ter will be ignored until the program or erase cycle has completed.

7.2.1 Manufacturer and Device Identification

MANUFACTURER ID (MF7-MF0) Winbond Serial Flash EFh Device ID (ID7-ID0) (ID15-ID0) Instruction ABh, 90h 9Fh W25Q16DV 14h 4015h

Publication Release Date: May 23, 2016 - 21 - Revision K

7.2.2 Instruction Set Table 1 (Erase, Program Instructions)(1)

(CODE) BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Write Enable 06h Write Enable for Volatile Status Register 50h Write Disable 04h Read Status Register-1 05h (S7–S0) (2) Read Status Register-2 35h (S15-S8) (2) Write Status Register 01h (S7–S0) (S15-S8) Page Program 02h A23–A16 A15–A8 A7–A0 (D7–D0) Quad Page Program 32h A23–A16 A15–A8 A7–A0 (D7–D0, …)(3) Sector Erase (4KB) 20h A23–A16 A15–A8 A7–A0 Block Erase (32KB) 52h A23–A16 A15–A8 A7–A0 Block Erase (64KB) D8h A23–A16 A15–A8 A7–A0 Chip Erase C7h/60h Erase / Program Suspend 75h Erase / Program Resume 7Ah Power-down B9h Continuous Read Mode Reset (4) FFh FFh Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from the device on the DO pin. 2. The Status Register contents will repeat continuously until /CS terminates the instruction. 3. Quad Page Program Input Data: IO0 = (D4, D0, ……) IO1 = (D5, D1, ……) IO2 = (D6, D2, ……) IO3 = (D7, D3, ……) 4. This instruction is recommended when using the Dual or Quad “Continuous Read Mode” feature. See section

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7.2.3 Instruction Set Table 2 (Read Instructions)

(CODE) BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0) Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …)(1) Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …)(3) Fast Read Dual I/O BBh A23-A8(2) A7-A0, M7-M0(2) (D7-D0, …)(1) Fast Read Quad I/O EBh A23-A0, M7-M0(4) (x,x,x,x, D7-D0, Word Read Quad I/O(7) E7h A23-A0, M7-M0(4) (x,x, D7-D0, …)(6) (D7-D0, …)(3) Octal Word Read Quad I/O(8) E3h A23-A0, M7-M0(4) (D7-D0, …)(3) Set Burst with Wrap 77h xxxxxx, W6-W4(4) Notes: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data 4. Quad Input Address Set Burst with Wrap Input IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO2 = x, x, x, x, x, x, W6, x IO3 = A23, A19, A15, A11, A7, A3, M7, M3 IO3 = x, x, x, x, x, x, x, x 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0, …..) IO1 = (x, x, x, x, D5, D1, …..) IO2 = (x, x, x, x, D6, D2, …..) IO3 = (x, x, x, x, D7, D3, …..) 6. Word Read Quad I/O Data 7. The lowest address bit must be 0. ( A0 = 0 ) 8. The lowest 4 address bits must be 0. ( A0, A1, A2, A3 = 0 )

Publication Release Date: May 23, 2016 - 23 - Revision K

7.2.4 Instruction Set Table 3 (ID, Security Instructions)

(CODE) BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Release Power down / Device ID ABh dummy dummy dummy (ID7-ID0)(1) Manufacturer/ Device ID(2) 90h dummy dummy 00h (MF7-MF0) (ID7-ID0) Manufacturer/Device ID by Dual I/O 92h A23-A8 A7-A0, M[7:0] (MF[7:0], ID[7:0]) Manufacture/Device ID by Quad I/O 94h A23-A0, M[7:0] xxxx, (MF[7:0], ID[7:0]) (MF[7:0], ID[7:0], …) JEDEC ID 9Fh (MF7-MF0) Manufacturer (ID15-ID8) Memory Type (ID7-ID0) Capacity Read Unique ID 4Bh dummy dummy dummy dummy (ID63-ID0) Read SFDP Register 5Ah 00h 00h A7–A0 dummy (D7-0) Erase Security Registers(3) 44h A23–A16 A15–A8 A7–A0 Program Security Registers(3) 42h A23–A16 A15–A8 A7–A0 (D7-0) (D7-0) Read Security Registers(3) 48h A23–A16 A15–A8 A7–A0 dummy (D7-0) Enable Reset 66h Reset 99h Notes: 1. The Device ID will repeat continuously until /CS terminates the instruction. 2. See Manufacturer and Device Identification table for Device ID information. 3. Security Register Address: Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address

7.2.5 Write Enable (06h)

1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block

pin on the rising edge of CLK, and then driving /CS high. Figure 4. Write Enable Instruction Sequence Diagram

7.2.6 Write Enable for Volatile Status Register (50h)

valid for the Write Status Register instruction to change the volatile Status Register bit values. Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram

7.2.7 Write Disable (04h)

Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 6. Write Disable Instruction Sequence Diagram

7.2.8 Read Status Register-1 (05h) and Read Status Register-2 (35h)

SRP1, QE, LB[3:1], CMP and SUS bits (see Status Register section earlier in this datasheet). continuously, as shown in Figure 7. The instruction is completed by driving /CS high. Figure 7. Read Status Register Instruction Sequence Diagram

7.2.9 Write Status Register (01h)

Figure 3 and described in 7.1. code “01h”, and then writing the status register data byte as illustrated in Figure 8. have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). Register bit values will be restored when power on again.

self-timed Write Status Register cycle will commence for a time duration of t W (See AC Characteristics). Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period. Figure 8. Write Status Register Instruction Sequence Diagram

7.2.10 Read Data (03h)

the clock continues. The instruction is completed by driving /CS high. (see AC Electrical Characteristics). Figure 9. Read Data Instruction Sequence Diagram

7.2.11 Fast Read (0Bh)

on the DO pin is a “don’t care”. Figure 10. Fast Read Instruction Sequence Diagram

7.2.12 Fast Read Dual Output (3Bh)

Figure 11. Fast Read Dual Output Instruction Sequence Diagram

7.2.13 Fast Read Quad Output (6Bh)

at four times the rate of standard SPI devices. high-impedance prior to the falling edge of the first data out clock. Figure 12. Fast Read Quad Output Instruction Sequence Diagram

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7.2.14 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23 -0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. Fast Read Dual I/O with “Continuous Read Mode” The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7 -0) after the input Address bits (A23 -0), as shown in Figure 13a. The upper nibble of the (M7 -4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3 -0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require the BBh instruction code, as shown in Figure 13b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M7 -0) before issuing normal instructions (See 7.2.20 for detail descriptions). /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (BBh) 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 /CS CLK DI (IO0) DO (IO1) 32 33 34 35 36 37 38 39 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * IOs switch from Input to Output 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 16 17 18 20 21 2219 23 A23-16 A15-8 A7-0 M7-0 Byte 1 Byte 2 Byte 3 Byte 4 = MSB* * Figure 13a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4  10)

Publication Release Date: May 23, 2016 - 33 - Revision K /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 /CS CLK DI (IO0) DO (IO1) 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * IOs switch from Input to Output 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 A23-16 A15-8 A7-0 M7-0 Byte 1 Byte 2 Byte 3 Byte 4 0 1 2 3 4 5 6 7 16 17 18 20 21 2219 23 = MSB* Figure 13b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10)

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7.2.15 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO 0, IO1, IO2 and IO3 and four Dummy clock are required prior to the data output . The Quad I/O dramatically reduces instruction ov erhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction. Fast Read Quad I/O with “Continuous Read Mode” The Fast Read Q uad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7 -0) after the input Address bits (A23 -0), as shown in Figure 14a. The upper nibble of the (M7 -4) controls the length of the next Fast Read Quad I /O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3 -0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the EBh instruction code, as shown in Figure 14b. This reduces the instruction sequence by eight clocks and allows t he Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5 -4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M7 -0) before issuing normal instructions (See 7.2.20 for detail descriptions). Figure 14a. Fast Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4  10) M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output Byte 3 15 16 17 18 19 20 21 22 23 Dummy DummyInstruction (EBh)

Publication Release Date: May 23, 2016 - 35 - Revision K M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output Byte 3 Dummy Dummy Figure 14b. Fast Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” command prior to EBh. The “Set Burst with Wrap” command can either enable or disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64 -byte section of a 256 -byte page. The output data starts at the initial address specified in the instruction, once it reaches the end ing boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 -byte) of data without issuing multiple read commands. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6 -4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. See 7.2.18 for detail descriptions.

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7.2.16 Word Read Quad I/O (E7h)

The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) i nstruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clocks are required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word Read Quad I/O Instruction. Word Read Quad I/O with “Continuous Read Mode” The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7 -0) after the input Address bits (A23 -0), as shown in Figure 15a. The upper nibble of the (M7 -4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3 -0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E7h instruction code, as shown in Figure 15b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Co ntinuous Read Mode” bits M5 -4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can also be used to re set (M7-0) before issuing normal instructions (See 7.2.20 for detail descriptions). Figure 15a. Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4  10) M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output Byte 3 15 16 17 18 19 20 21 DummyInstruction (E7h)

Publication Release Date: May 23, 2016 - 37 - Revision K M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 4 0 5 1 6 2 7 3 A15-8 A7-0 4 0 5 1 6 2 7 3 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 IOs switch from Input to Output Byte 3 8 9 10 11 12 13 Dummy Figure 15b. Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Word Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” command prior to E7h. The “Set Burst with Wrap” command can either enable or disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64 -byte section of a 256 -byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 -byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 -byte) of data without issuing multiple read commands. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6 -4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. See 7.2.18 for detail descriptions.

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7.2.17 Octal Word Read Quad I/O (E3h)

The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution (XIP). The Quad Enable bit (QE) of Status Register -2 must be set to enable the Octal Word Read Quad I/O Instruction. Octal Word Read Quad I/O with “Continuous Read Mode” The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7 -0) after the input Address bits (A23 -0), as s hown in Figure 16a. The upper nibble of the (M7 -4) controls the length of the next Octal Word Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3 -0) are don’t care (“x”). However , the IO pins should be high -impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E3h inst ruction code, as shown in Figure 16b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5 -4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M7 -0) before issuing normal instructions (See 7.2.20 for detail descriptions). M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output Byte 3 15 16 17 18 19 20 21 Instruction (E3h) 4 0 5 1 6 2 7 3 Byte 4 Figure 16a. Octal Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4  10)

Publication Release Date: May 23, 2016 - 39 - Revision K M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 4 0 5 1 6 2 7 3 A15-8 A7-0 4 0 5 1 6 2 7 3 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 IOs switch from Input to Output Byte 3 8 9 10 11 12 13 4 0 5 1 6 2 7 3 Byte 4 Figure 16b. Octal Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10)

7.2.18 Set Burst with Wrap (77h)

Read Quad I/O” instructions to access a fixed length of 8/16/32/64 -byte section within a 256 -byte page. instruction sequence is shown in Figure 17. Wrap bit W7 and the lower nibble W3-0 are not used. Figure 17. Set Burst with Wrap Instruction Sequence

7.2.19 Continuous Read Mode Bits (M7-0)

to be performed on serial flash devices.

7.2.20 Continuous Read Mode Reset (FFh or FFFFh)

Continuous Read Mode and return to normal SPI operation, as shown in Figure 18. Figure 18. Continuous Read Mode Reset for Fast Read Dual/Quad I/O Continuous Read Mode and allow Standard SPI instructions to be recognized. needed to shift in instruction “FFFFh”.

7.2.21 Page Program (02h)

while data is being sent to the device. The Page Program instruction sequence is shown in Figure 19. page and overwrite previously sent data. the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits. Figure 19. Page Program Instruction Sequence Diagram

7.2.22 Quad Input Page Program (32h)

improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. the inherent page program time is much greater than the time it take to clock-in the data. sequence is shown in Figure 20. Figure 20. Quad Input Page Program Instruction Sequence Diagram

7.2.23 Sector Erase (20h)

Sector Erase instruction sequence is shown in Figure 21. BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 21. Sector Erase Instruction Sequence Diagram

Erase instruction sequence is shown in Figure 22. bits (see Status Register Memory Protection table). Figure 22. 32KB Block Erase Instruction Sequence Diagram

Erase instruction sequence is shown in Figure 23. bits (see Status Register Memory Protection table). Figure 23. 64KB Block Erase Instruction Sequence Diagram

7.2.26 Chip Erase (C7h / 60h)

instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 24. Figure 24. Chip Erase Instruction Sequence Diagram

7.2.27 Erase / Program Suspend (75h)

blocks. The Erase/Program Suspend instruction sequence is shown in Figure 25. Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation. same address location, to avoid the potention data corruption. Figure 25. Erase/Program Suspend Instruction Sequence

7.2.28 Erase / Program Resume (7Ah)

will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 26. issued within a minimum of time of “tSUS” following a previous Resume instruction. Figure 26. Erase/Program Resume Instruction Sequence

7.2.29 Power-down (B9h)

instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). Figure 27. Deep Power-down Instruction Sequence Diagram

Publication Release Date: May 23, 2016 - 51 - Revision K

7.2.30 Release Power-down / Device ID (ABh)

The Release from Power -down / Device ID instruction is a multi -purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To release the device from the power -down state, the instruction is issued by driving the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in Figure 28a. Release from power-down will take the time duration of t RES1 (See AC Characteristics) before the device will resume normal operation and other instructions are accepted. The /CS pin must remain high during the t RES1 time duration. When used only to obtain the Device ID while not in the power -down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code “ABh” followed by 3 -dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 28a. The Device ID values for the W25Q16DV is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. When used to release the device from the power -down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 28b, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instructions will be accepted. If the Release from Power -down / Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle. /CS CLK DI (IO0) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (ABh) Mode 0 Mode 3 tRES1 Power-down current Stand-by current Figure 28a. Release Power-down Instruction Sequence

• 52 - tRES2 /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (ABh) High Impedance 8 9 29 30 31

3 Dummy Bytes

Power-down current Stand-by current= MSB* Figure 28b. Release Power-down / Device ID Instruction Sequence Diagram

7.2.31 Read Manufacturer / Device ID (90h)

ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. instruction is completed by driving /CS high. Figure 29. Read Manufacturer / Device ID Diagram

7.2.32 Read Manufacturer / Device ID Dual I/O (92h)

The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. Figure 30. The Device ID values for the W25Q16DV is listed in Manufacturer and Device Identification instruction is completed by driving /CS high. Figure 30. Read Manufacturer / Device ID Dual I/O Diagram The “Continuous Read Mode” bits M7-0 must be set to Fxh to be compatible with Fast Read Dual I/O instruction.

7.2.33 Read Manufacturer / Device ID Quad I/O (94h)

The Read Manufacturer / Device ID Quad I/O instruction is simi lar to the Fast Read Quad I/O instruction. alternating from one to the other. The instruction is completed by driving /CS high. Figure 31. Read Manufacturer / Device ID Quad I/O Diagram The “Continuous Read Mode” bits M7-0 must be set to Fxh to be compatible with Fast Read Quad I/O instruction.

7.2.34 Read Unique ID Number (4Bh)

bit ID is shifted out on the falling edge of CLK as shown in Figure 32. Figure 32. Read Unique ID Number Instruction Sequence

7.2.35 Read JEDEC ID (9Fh)

values refer to Manufacturer and Device Identification table. Figure 33. Read JEDEC ID Instruction Sequence

7.2.36 Read SFDP Register (5Ah)

and beyond) support the SFDP feature as specified in the applicable datasheet. Application Note for SFDP Definition table. Note: 1. A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256 -Byte SFDP Register. Figure 34. Read SFDP Register Instruction Sequence Diagram

7.2.37 Erase Security Registers (44h)

important information separately from the main memory array. instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the three security registers. after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed. ignored (See 7.1.9 for detail descriptions). Figure 35. Erase Security Registers Instruction Sequence

7.2.38 Program Security Registers (42h)

byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. the instruction code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. Figure 36. Program Security Registers Instruction Sequence

7.2.39 Read Security Registers (48h)

maximum of FR (see AC Electrical Characteristics). Figure 37. Read Security Registers Instruction Sequence

7.2.40 Enable Reset (66h) and Reset (99h)

setting (M7-M0) and Wrap Bit setting (W6-W4). “Enable Reset (66h)” and “Reset (99h)” instructions must be issued in sequence to avoid accidental reset. tRST=30us to reset. During this period, no command will be accepted. the SUS bit in Status Register before issuing the Reset command sequence. Figure 38. Enable Reset and Reset Instruction Sequence

Publication Release Date: May 23, 2016 - 63 - Revision K 8. ELECTRICAL CHARACTERISTICS

8.1 Absolute Maximum Ratings (1)

PARAMETERS SYMBOL CONDITIONS RANGE UNIT Supply Voltage VCC –0.6 to +4.6 V Voltage Applied to Any Pin VIO Relative to Ground –0.6 to VCC+0.4 V Transient Voltage on any Pin VIOT <20nS Transient Relative to Ground –2.0V to VCC+2.0V V Storage Temperature TSTG –65 to +150 °C Lead Temperature TLEAD See Note (2) °C Electrostatic Discharge Voltage VESD Human Body Model(3) –2000 to +2000 V Notes: 1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage. 2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU. 3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).

8.2 Operating Ranges

PARAMETER SYMBOL CONDITIONS SPEC UNIT MIN MAX Supply Voltage VCC FR = 80MHz, fR = 50MHz FR = 104MHz, fR = 50MHz 2.7 3.0 3.0 3.6 V Ambient Temperature, Operating TA Industrial -40 +85 °C

• 64 -

8.3 Power-Up Power-Down Timing and Requirements

VCC (min) to /CS Low tVSL(1) 20 µs Time Delay Before Write Instruction tPUW(1) 5 ms Write Inhibit Threshold Voltage VWI(1) 1.0 2.0 V Note: 1. These parameters are characterized only. VCC tVSL Read Instructions Allowed Device is fully Accessible tPUW /CS must track VCC Program, Erase and Write Instructions are ignored Reset State VCC (max) VCC (min) VWI Time Figure 39a. Power-up Timing and Voltage Levels VCC Time /CS must track VCC during VCC Ramp Up/Down /CS Figure 39b. Power-up, Power-Down Requirement

Publication Release Date: May 23, 2016 - 65 - Revision K

8.4 DC Electrical Characteristics

PARAMETER SYMBOL CONDITIONS SPEC UNIT MIN TYP MAX Input Capacitance CIN(1) VIN = 0V(1) 6 pF Output Capacitance Cout(1) VOUT = 0V(1) 8 pF Input Leakage ILI ±2 µA I/O Leakage ILO ±2 µA Standby Current ICC1 /CS = VCC, VIN = GND or VCC 10 50 µA Power-down Current ICC2 /CS = VCC, VIN = GND or VCC 1 5 µA Current Read Data Normal Read 50MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 8 10 mA Current Read Data / Dual Output Read/Quad Output Read 80MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 12 18 mA Current Write Status Register ICC4 /CS = VCC 20 25 mA Current Page Program ICC5 /CS = VCC 20 25 mA Current Sector/Block Erase ICC6 /CS = VCC 20 25 mA Current Chip Erase ICC7 /CS = VCC 20 25 mA Input Low Voltage VIL VCC x 0.3 V Input High Voltage VIH VCC x 0.7 V Output Low Voltage VOL IOL = 100 µA 0.2 V Output High Voltage VOH IOH = –100 µA VCC – 0.2 V Notes: 1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3V. 2. Checker Board Pattern.

8.5 AC Measurement Conditions

1. Output Hi-Z is defined as the point where data out is no longer driven.

0.9 VCC

0.1 VCC

0.5 VCC

Figure 40. AC Measurement I/O Waveform

Publication Release Date: May 23, 2016 - 67 - Revision K

8.6 AC Electrical Characteristics

Clock frequency for all instructions, except Read Data (03h) 2.7-3.0V / 3.0-3.6V & Industrial Temperature FR fC D.C. 80/104 MHz Clock freq. Read Data instruction (03h) fR D.C. 50 MHz Clock High, Low Time except Read Data (03h) tCLH, tCLL(1) 4 ns Clock High, Low Time for Read Data (03h) instruction tCRLH, tCRLL(1) 8 ns Clock Rise Time peak to peak tCLCH(2) 0.1 V/ns Clock Fall Time peak to peak tCHCL(2) 0.1 V/ns /CS Active Setup Time relative to CLK tSLCH tCSS 3 ns /CS Not Active Hold Time relative to CLK tCHSL 3 ns Data In Setup Time tDVCH tDSU 2 ns Data In Hold Time tCHDX tDH 3 ns /CS Active Hold Time relative to CLK tCHSH 3 ns /CS Not Active Setup Time relative to CLK tSHCH 3 ns /CS Deselect Time (for Array Read  Array Read) tSHSL1 tCSH 10 ns /CS Deselect Time (for Erase/Program  Read SR) Volatile Status Register Write Time tSHSL2 tCSH 50 ns Output Disable Time tSHQZ(2) tDIS 7 ns Clock Low to Output Valid 2.7-3.0V / 3.0-3.6V tCLQV1 tV1 7 / 6 ns Clock Low to Output Valid (for Read ID instructions) Output Hold Time tCLQX tHO 0 ns /HOLD Active Setup Time relative to CLK tHLCH 3 ns Continued – next page

• 68 -

8.7 AC Electrical Characteristics (cont’d)

/HOLD Active Hold Time relative to CLK tCHHH 3 ns /HOLD Not Active Setup Time relative to CLK tHHCH 3 ns /HOLD Not Active Hold Time relative to CLK tCHHL 3 ns /HOLD to Output Low-Z tHHQX(2) tLZ 7 ns /HOLD to Output High-Z tHLQZ(2) tHZ 12 ns Write Protect Setup Time Before /CS Low tWHSL(3) 20 ns Write Protect Hold Time After /CS High tSHWL(3) 100 ns /CS High to Power-down Mode tDP(2) 3 µs /CS High to Standby Mode without Electronic Signature Read tRES1(2) 3 µs /CS High to Standby Mode with Electronic Signature Read tRES2(2) 1.8 µs /CS High to next Instruction after Suspend tSUS(2) 20 µs Write Status Register Time tW 10 15 ms Byte Program Time (First Byte) (4) tBP1 20 50 µs Additional Byte Program Time (After First Byte) (4) tBP2 2.5 10 µs Page Program Time tPP 0.7 3 ms Sector Erase Time (4KB) tSE 60 200/400(5) ms Block Erase Time (32KB) tBE1 150 800 ms Block Erase Time (64KB) tBE2 180 1,000 ms Chip Erase Time tCE 3 10 s Notes: 1. Clock high + Clock low must be less than or equal to 1/fC. 2. Value guaranteed by design and/or characterization, not 100% tested in production. 3. Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1). 4. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes programmed. 5. Max Value tSE with <50K cycles is 200ms and >50K & <100K cycles is 400ms.

Publication Release Date: May 23, 2016 - 69 - Revision K

8.8 Serial Output Timing

/CS CLK IO output tCLQX tCLQV tCLQX tCLQV tSHQZtCLL LSB OUT tCLH MSB OUT

8.9 Serial Input Timing

/CS CLK IO input tCHSL MSB IN tSLCH tDVCH tCHDX tSHCHtCHSH tCLCH tCHCL LSB IN tSHSL 8.10 /HOLD Timing /CS CLK IO output /HOLD tCHHL tHLCH tCHHH tHHCH tHLQZ tHHQX IO input 8.11 /WP Timing /CS CLK /WP tWHSL tSHWL IO input Write Status Register is allowed Write Status Register is not allowed

• 70 - 9. PACKAGE SPECIFICATION 9.1 8-Pin SOIC 150-mil (Package Code SN) L θ c D A e b SEATING PLANE Y 0.25 GAUGE PLANE E HE L θ c D A e bbb SEATING PLANE Y 0.25 GAUGE PLANE E HEE HE SYMBOL MILLIMETERS INCHES Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.008 0.010 E(3) 3.80 4.00 0.150 0.157 D(3) 4.80 5.00 0.188 0.196 e(2) 1.27 BSC 0.050 BSC HE 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 θ 0° 10° 0° 10° Notes: 1. Controlling dimensions: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches.

Publication Release Date: May 23, 2016 - 71 - Revision K 9.2 8-Pin SOIC 208-mil (Package Code SS) θ GAUGE PLANE θ GAUGE PLANE SYMBOL MILLIMETERS INCHES Min Nom Max Min Nom Max e(2) 1.27 BSC. 0.050 BSC. Notes: 1. Controlling dimensions: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches.

• 72 - 9.3 8-Pin PDIP 300-mil (Package Code DA) SYMBOL MILLIMETERS INCHES Min Nom Max Min Nom Max E 7.62 BSC. 0.300 BSC.

Publication Release Date: May 23, 2016 - 73 - Revision K 9.4 8-Pad WSON 6x5mm (Package Code ZP) SYMBOL MILLIMETERS INCHES Min Nom Max Min Nom Max e (2) 1.27 BSC. 0.050 BSC. Notes: 1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.

• 74 - 9.5 8-Pad USON 4x3-mm (Package Code UU) Symbol Millimeters Inches Min Nom Max Min Nom Max e 0.80 BSC 0.031 BSC Note:The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be left floating or connected to t he device ground (GND pin). Avoid placement of expo sed PCB vias under the pad.

Publication Release Date: May 23, 2016 - 75 - Revision K 9.6 8-Pad USON 4x4-mm (Package Code UZ) Symbol Millimeters Min Nom Max A 0.50 0.55 0.60 A1 0.00 0.02 0.05 b 0.25 0.30 0.35 C --- 0.15REF --- D 3.90 4.00 4.10 D2 2.95 3.00 3.05 E 3.90 4.00 4.10 E2 2.25 2.30 2.35 e --- 0.80 --- L 0.35 0.40 0.45 y 0.00 --- 0.075 Note:The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be left floating or connected to t he device ground (GND pin). Avoid placement of exp osed PCB vias under the pad.

• 76 - 9.7 8-Ball WLCSP (Package Code BY) Symbol Millimeters Inches Min Nom Max Min Nom Max aaa 0.100 0.0040 bbb 0.100 0.0040 ccc 0.030 0.0012 ddd 0.150 0.0060 Notes: 1. Dimension b is measured at the maximum solder bump diameter, parallel to primary datum C.

Publication Release Date: May 23, 2016 - 77 - Revision K 9.8 16-Pin SOIC 300-mil (Package Code SF) GAUGE PLANE DETAIL A GAUGE PLANE DETAIL A SYMBOL MILLIMETERS INCHES Min Nom Max Min Nom Max e(2) 1.27 BSC. 0.050 BSC. Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.

• 78 - 9.9 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 ball array) Symbol Millimeters Inches Min Nom Max Min Nom Max D1 4.00 BSC 0.157 BSC E1 4.00 BSC 0.157 BSC SE 1.00 TYP 0.039 TYP SD 1.00 TYP 0.039 TYP e 1.00 BSC 0.039 BSC Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm

Publication Release Date: May 23, 2016 - 79 - Revision K 9.10 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array) SYMBOL MILLIMETERS INCHES Min Nom Max Min Nom Max D1 5.00 BSC 0.197 BSC E1 3.00 BSC 0.118 BSC e 1.00 BSC 0.039 BSC

• 80 - 10. ORDERING INFORMATION Notes: 1. The “W” prefix is not included on the part marking. 2. Only the 2nd letter is used for the part marking; WSON package type ZP is not used for the part marking. 3. Standard bulk shipments are in Tube (shape E). Please specify alternate packing m ethod, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 4. For special option Q devices, QE bit may be reset to 0 if Write Status Register command is only followed by 8-bit data (Status Register-1). 5. For shipments with OTP feature enabled devices (P), please contact Winbond W(1) 25Q 16D V xx(2) W = Winbond 25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 16D = 16M-bit V = 2.7V to 3.6V (4,5) G = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) Q = Green Package with QE=1 in Status Register-2 SN = SOIC-8 150-mil ZP = WSON-8 6x5-mm UU = 8-Pad USON 4x3mm UZ = 8-Pad USON 4x4mm SS = SOIC-8 208-mil DA = PDIP-8 300-mil BY = 8-ball WLCSP SF = 16-pin SOIC 300-mil TB = 5x5-1 balls TFBGA 8x6-mm TC = 6x4 balls TFBGA 8x6-mm I = Industrial (-40°C to +85°C)

Publication Release Date: May 23, 2016 - 81 - Revision K

10.1 Valid Part Numbers and Top Side Marking

The following table provides the valid part numbers for the W25Q16DV SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 12-digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 10-digit number. PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING SN(2) SOIC-8 150mil 16M-bit W25Q16DVSNIG 25Q16DVNIG SS SOIC-8 208mil 16M-bit W25Q16DVSSIG W25Q16DVSSIQ 25Q16DVSIG 25Q16DVSIQ SF SOIC-16 300-mil 16M-bit W25Q16DVSFIG 25Q16DVFIG ZP (1) WSON-8 6x5mm 16M-bit W25Q16DVZPIG W25Q16DVZPIQ 25Q16DVIG 25Q16DVIQ DA PDIP-8 300mil 16M-bit W25Q16DVDAIG W25Q16DVDAIQ 25Q16DVAIG 25Q16DVAIQ UU USON-8 4x3mm 16M-bit W25Q16DVUUIG Q16DVUUIG UU USON-8 4x4mm 16M-bit W25Q16DVUZIG Q16DVUZIG TB(2) TFBGA-24 8x6mm 5x5 ball array 16M-bit W25Q16DVTBIG 25Q16DVBIG TC(2) TFBGA-24 8x6mm 6x4 ball array 16M-bit W25Q16DVTCIG 25Q16DVCIG BY(2) 8-ball WLCSP 16M-bit W25Q16DVBYIG 4Cyw(3)

• DIG Notes: 1. WSON package type ZP is not used in the top side marking. 2. These Package types are Special Order only, please contact Winbond for more information. 3. y is year code; w is week code.

• 82 - 11. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A 03/22/12 New Create Preliminary B 07/30/12 All 10, 13, 63 Removed QPI functions Updated power down requirement C 10/02/12 63 Updated power-up timing parameters Updated ICC4 D 10/29/12 All 64, 66, 67 Removed preliminary designator Updated ICC1-4, Setup/hold time, tW, tBE Updated valid part numbers E 11/29/12 64 Updated ICC1 Updated valid part numbers F 10/15/13 79 5,79 Updated OTP enable feature, pls contact Winbond Removed non-available VSOP package G 05/23/14 5-6,74,78-79 52-54 Added USON 4X3 package Modified the description of 90h/92h/94h Removed unaviable package information H 10/06/14 77-78 Updated W25Q16DVSFIG information I 11/18/14 74,78-79 Updated USON 4X4mm information J 05/23/14 5,8, 76,81-82 Updated WLCSP information K 05/23/16 80 Updated Order information notice Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal in struments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Information in this document is provided solely in connection with Winbond products. Winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice.

Publication Release Date: May 23, 2016 - 83 - Revision K