25Q16BVAIG

W25Q16BV WINBOND | Alldatasheet

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Technical content

Publication Release Date: July 08, 2010 - 1 - R e v i s i o n F 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

• 2 - Table of Contents

Publication Release Date: July 08, 2010 - 3 - R e v i s i o n F

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Publication Release Date: July 08, 2010 - 5 - R e v i s i o n F 1. GENERAL DESCRIPTION The W25Q16BV (16M-bit) Serial Flash memory prov ides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code dire ctly from Dual/Quad SPI (XIP) and storing voice, text and dat a. The devices operate on a single 2. 7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space- saving packages. The W25Q16BV array is organized into 8,192 progra mmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q16BV has 512 erasable sectors and 32 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25Q16BV supports the standard Serial Peri pheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz for Dual Output and 416MHz for Quad Output when using the Fast Read Dual/Quad Output instructions. These transfe r rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read M ode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24- bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally , the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number. 2. FEATURES

• Family of SpiFlash Memories – W25Q16BV: 16M-bit / 2M-byte (2,097,152) – 256-bytes per programmable page
• Standard, Dual or Quad SPI – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
• Highest Performance Serial Flash – Up to 8X that of ordinary Serial Flash – 104MHz clock operation – 208MHz equivalent Dual SPI – 416MHz equivalent Quad SPI – 50MB/S continuous data transfer rate
• Efficient “Continuous Read Mode” – Low Instruction overhead – As few as 8 clocks to address memory – Allows true XIP (execute in place) operation – Outperforms X16 Parallel Flash
• Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply – 4mA active current, <1µA Power-down (typ.) – -40°C to +85°C operating range
• Flexible Architecture with 4KB sectors – Uniform Sector Erase (4K-bytes) – Block Erase (32K and 64K-bytes) – Program one to 256 bytes – More than 100,000 erase/write cycles – More than 20-year data retention
• Advanced Security Features – Software and Hardware Write-Protect – Top or Bottom, Sector or Block selection – Lock-Down and OTP protection (1) – 64-Bit Unique ID for each device
• Space Efficient Packaging – 8-pin SOIC 150(2)/208-mil – 8-pad WSON 6x5-mm – 8-pin PDIP 300-mil (2) – 16-pin SOIC 300-mil(2) – Contact Winbond for KGD and other options Notes 1. Refer to Ordering Information. 2. These package types are Special Order Only, please contact Winbond for more information.

Publication Release Date: July 08, 2010 - 7 - R e v i s i o n F 5. PAD CONFIGURATION PDIP 300-MIL /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) CLK DI (IO0) Figure 1c. W25Q16BV Pin Assignments, 8-pin PDIP (Package Code DA) 6. PIN DESCRIPTION SOIC 150/208-MIL, PDIP 300-MIL AND WSON 6X5-MM PIN NO. PIN NAME I/O FUNCTION 1 /CS I Chip Select Input

2 DO (IO1) I/O Data Output (Data Input Output 1)*1

3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)*2

4 GND Ground

5 DI (IO0) I/O Data Input (Data Input Output 0)*1

6 CLK I Serial Clock Input

7 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2

8 VCC Power Supply

*1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions

• 8 - 7. PIN CONFIGURATION SOIC 300-MIL 1/HOLD (IO3) VCC N/C N/C N/C N/C /CS DO (IO ) CLK DI (IO N/C N/C N/C N/C GND /WP (IO ) 1 2 1/HOLD (IO3) VCC N/C N/C N/C N/C /CS DO (IO ) CLK DI (IO N/C N/C N/C N/C GND /WP (IO ) 1 2 Figure 1d. W25Q16BV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 8. PIN DESCRIPTION SOIC 300-MIL PAD NO. PAD NAME I/O FUNCTION 1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2

2 VCC Power Supply

3 N/C No Connect

4 N/C No Connect

5 N/C No Connect

6 N/C No Connect

8 DO (IO1) I/O Data Output (Data Input Output 1)*1

9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2

10 GND Ground

11 N/C No Connect

12 N/C No Connect

13 N/C No Connect

14 N/C No Connect

15 DI (IO0) I/O Data Input (Data Input Output 0)*1

16 CLK I Serial Clock Input

*1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions

Publication Release Date: July 08, 2010 - 9 - R e v i s i o n F

8.1 Package Types

W25Q16BV is offered in an 8-pin plastic 150-mil or 208-mil width SOIC (package code SN & SS) and 6x5-mm WSON (package code ZP) as shown in figure 1a, and 1b, respectively. The 300-mil 8-pin PDIP is another option of package selections (Figure 1c). The W25Q16BV is also offered in a 16-pin plastic 300-mil width SOIC (package code SF) as shown in figure 1d. Package diagrams and dimensions are illustrated at the end of this datasheet.

8.2 Chip Select (/CS)

The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and inst ructions can be written to and data read from the device. After power-up, /CS must transition from high to low befor e a new instruction will be accepted. The /CS input must track the VCC supply level at power-up (see “Write Protection” and figure 32). If needed a pull-up resister on /CS can be used to accomplish this.

8.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)

The W25Q16BV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresse s or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge CLK. Dual and Quad SPI instruction use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Q uad Enable bit (QE) in Status Register-2 to be set. When QE=1 the /WP pin becomes IO2 and /HOLD pin becomes IO3.

8.4 Write Protect (/WP)

The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Pr otect (SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion or the entir e memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Regist er-2 is set for Quad I/O, the /WP pin (Hardware Write Protect) function is not available since this pin is used for IO2. See figure 1a, 1b, 1c, and 1d for the pin configuration of Quad I/O operation.

8.5 HOLD (/HOLD)

The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See figure 1a-d for the pin configuration of Quad I/O operation.

8.6 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations")

Figure 2. W25Q16BV Serial Flash Memory Block Diagram

• Block 0 (64KB) • 000000h 0000FFh 07FF00h 07FFFFh
• Block 7 (64KB) • 070000h 0700FFh 08FF00h 08FFFFh
• Block 8 (64KB) • 080000h 0800FFh 0FFF00h 0FFFFFh
• Block 15 (64KB) • 0F0000h 0F00FFh 10FF00h 10FFFFh
• Block 16 (64KB) • 100000h 1000FFh 1FFF00h 1FFFFFh
• Block 31 (64KB) • 1F0000h 1F00FFh Column Decode And 256-Byte Page Buffer Beginning Page Address Ending Page Address W25Q16BV SPI Command & Control Logic Byte Address Latch / Counter Status Register Write Control Logic Page Address Latch / Counter High Voltage Generators xx0F00h xx0FFFh
• Sector 0 (4KB) • xx0000h xx00FFh xx1F00h xx1FFFh
• Sector 1 (4KB) • xx1000h xx10FFh xx2F00h xx2FFFh
• Sector 2 (4KB) • xx2000h xx20FFh xxDF00h xxDFFFh
• Sector 13 (4KB) • xxD000h xxD0FFh xxEF00h xxEFFFh
• Sector 14 (4KB) • xxE000h xxE0FFh xxFF00h xxFFFFh
• Sector 15 (4KB) • xxF000h xxF0FFh Block Segmentation Data Write Protect Logic and Row Decode DO (IO1) DI (IO0) /CS CLK /HOLD (IO3) /WP (IO2) 00FF00h 00FFFFh
• Block 0 (64KB) • 000000h 0000FFh 07FF00h 07FFFFh
• Block 7 (64KB) • 070000h 0700FFh 08FF00h 08FFFFh
• Block 8 (64KB) • 080000h 0800FFh 0FFF00h 0FFFFFh
• Block 15 (64KB) • 0F0000h 0F00FFh 10FF00h 10FFFFh
• Block 16 (64KB) • 100000h 1000FFh 1FFF00h 1FFFFFh
• Block 31 (64KB) • 1F0000h 1F00FFh Column Decode And 256-Byte Page Buffer Beginning Page Address Ending Page Address W25Q16BV SPI Command & Control Logic Byte Address Latch / Counter Status Register Write Control Logic Page Address Latch / Counter High Voltage Generators xx0F00h xx0FFFh
• Sector 0 (4KB) • xx0000h xx00FFh xx1F00h xx1FFFh
• Sector 1 (4KB) • xx1000h xx10FFh xx2F00h xx2FFFh
• Sector 2 (4KB) • xx2000h xx20FFh xxDF00h xxDFFFh
• Sector 13 (4KB) • xxD000h xxD0FFh xxEF00h xxEFFFh
• Sector 14 (4KB) • xxE000h xxE0FFh xxFF00h xxFFFFh
• Sector 15 (4KB) • xxF000h xxF0FFh Block Segmentation Data Write Protect Logic and Row Decode DO (IO1) DI (IO0) /CS CLK /HOLD (IO3) /WP (IO2)

Publication Release Date: July 08, 2010 - 1 1 - R e v i s i o n F 10. FUNCTIONAL DESCRIPTION

10.1 SPI OPERATIONS

10.1.1 Standard SPI Instructions

The W25Q16BV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Ou tput (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or dat a to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge CLK. SPI bus operation Modes 0 (0,0) and 3 (1,1) are s upported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3 the CLK signal is normally high on the falling and rising edges of /CS.

10.1.2 Dual SPI Instructions

The W25Q16BV supports Dual SPI operation when usi ng the “Fast Read Dual Output and Dual I/O” (3B and BB hex) instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devic es. The Dual Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP ). When using Dual SPI instruct ions the DI and DO pins become bidirectional I/O pins: IO0 and IO1.

10.1.3 Quad SPI Instructions

The W25Q16BV supports Quad SPI operation when us ing the “Fast Read Quad Output”, “Fast Read Quad I/O”, “Word Read Quad I/O” and “Octal Word Q uad I/O” (6B, EB, E7 and E3 hex respectively). These instructions allow data to be transferred to or fr om the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RA M or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pi ns become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.

10.1.4 Hold Function

The /HOLD signal allows the W25Q16BV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where t he SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation, not during Quad SPI. To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK signal is already lo w. If the CLK is not already low the /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device.

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10.2 WRITE PROTECTION

Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise dat a integrity. To address this concern the W25Q16BV provides several means to protect data from inadvertent writes.

10.2.1 Write Protect Features

• Device resets when VCC is below threshold
• Time delay write disable after Power-up
• Write enable/disable instructions and automat ic write disable after program and erase
• Software and Hardware (/WP pin) write protection using Status Register
• Write Protection using Power-down instruction
• Lock Down write protection until next power-up (1)
• One Time Program (OTP) write protection (1) Note 1: These features are available upon special order. Please refer to Ordering Information. Upon power-up or at power-down, the W25Q16BV will ma intain a reset condition while VCC is below the threshold value of V WI, (See Power-up Timing and Voltage Levels and Figure 32). While reset, all operations are disabled and no instructions are re cognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program, Sector Eras e, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and t VSL time delay is reached. If needed a pull-up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Chip Erase or Write Status Register inst ruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled state of 0. Software controlled write protection is facilitated using the Write Stat us Register instruction and setting the Status Register Protect (SRP 0, SRP1) and Block Protect (SEC,T B, BP2, BP1 and BP0) bits. These settings allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register for further information. Additionally, t he Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction.

Publication Release Date: July 08, 2010 - 1 3 - R e v i s i o n F 11. CONTROL AND STATUS REGISTERS The Read Status Register-1 and Stat us Register-2 instructions can be used to provide status on the availability of the Flash memory array, if the dev ice is write enabled or dis abled, the state of write protection, the Quad SPI setting and Erase Suspend status. The Write Status Register instruction can be used to configure the devices writ e protection features and Quad SPI se tting. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and in some cases the /WP pin.

11.1 STATUS REGISTER

11.1.1 BUSY

BUSY is a read only bit in the status register (S0) t hat is set to a 1 state w hen the device is executing a Page Program, Sector Erase, Block Er ase, Chip Erase or Write Status Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase Suspend instruction (see t W, tPP, tSE, tBE, and tCE in AC Characteristics). When t he program, erase or write status register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.

11.1.2 Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.

11.1.3 Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see t W in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected.

11.1.4 Top/Bottom Block Protect (TB)

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as show n in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits.

11.1.5 Sector/Block Protect (SEC)

The non-volatile Sector protect bit (SEC) controls if the Block Protec t Bits (BP2, BP1, BP0) protect 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0.

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11.1.6 Status Register Protect (SRP1, SRP0)

The Status Register Protect bits (SRP1 and SRP0) are non- volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. SRP1 SRP0 /WP Status Register Description 0 0 X Software Protection /WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default] 0 1 0 Hardware Protected When /WP pin is low the Status Register locked and can not be written to. 0 1 1 Hardware Unprotected When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. 1 0 X Power Supply Lock-Down(1) Status Register is protected and can not be written to again until the next power-down, power-up cycle.(2) 1 1 X One Time Program(1) Status Register is permanently protected and can not be written to. Note: 1. These features are available upon special order. Please refer to Ordering Information. 2. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.

11.1.7 Erase Suspend Status (SUS)

The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing an Erase Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase Resume (7Ah) instruction as well as a power-down, power-up cycle.

11.1.8 Quad Enable (QE)

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S 9) that allows Quad SPI operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD functions are disabled. WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during standard SPI or Dual SPI operation, the QE bit should never be set to a 1.

• 16 - 1 1.1.9 Status Register Memory Protection STATUS REGISTER(1) W25Q16BV (16M-BIT) MEMORY PROTECTION SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 31 1F0000h – 1FFFFFh 64KB Upper 1/32 0 0 0 1 0 30 and 31 1E0000h – 1FFFFFh 128KB Upper 1/16 0 0 0 1 1 28 thru 31 1C0000h – 1FFFFFh 256KB Upper 1/8 0 0 1 0 0 24 thru 31 180000h – 1FFFFFh 512KB Upper 1/4 0 0 1 0 1 16 thru 31 100000h – 1FFFFFh 1MB Upper 1/2 0 1 0 0 1 0 000000h – 00FFFFh 64KB Lower 1/32 0 1 0 1 0 0 and 1 000000h – 01FFFFh 128KB Lower 1/16 0 1 0 1 1 0 thru 3 000000h – 03FFFFh 256KB Lower 1/8 0 1 1 0 0 0 thru 7 000000h – 07FFFFh 512KB Lower 1/4 0 1 1 0 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/2 X X 1 1 X 0 thru 31 000000h – 1FFFFFh 2MB ALL 1 0 0 0 1 31 1FF000h – 1FFFFFh 4KB Top Block 1 0 0 1 0 31 1FE000h – 1FFFFFh 8KB Top Block 1 0 0 1 1 31 1FC000h – 1FFFFFh 16KB Top Block 1 0 1 0 X 31 1F8000h – 1FFFFFh 32KB Top Block 1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block 1 1 0 1 0 0 000000h – 001FFFh 8KB Bottom Block 1 1 0 1 1 0 000000h – 003FFFh 16KB Bottom Block 1 1 1 0 X 0 000000h – 007FFFh 32KB Bottom Block Note: 1. x = don’t care

Publication Release Date: July 08, 2010 - 1 7 - R e v i s i o n F

11.2 INSTRUCTIONS

The instruction set of the W25Q16BV consists of thirty basic instructions that are fully controlled through the SPI bus (see Instruction Set table1-3). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagram s for each instruction are included in figures 4 through 32. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instructi on will be terminated. This feature further protects the device from inadvertent writes. Additionally, wh ile the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed.

11.2.1 Manufacturer and Device Identification

MANUFACTURER ID (M7-M0) Winbond Serial Flash EFh Device ID (ID7-ID0) (ID15-ID0) Instruction ABh, 90h 9Fh W25Q16BV 14h 4015h

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11.2.2 Instruction Set Table 1 (Erase, Program Instructions)(1)

(CODE) BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Write Enable 06h Write Disable 04h Read Status Register-1 05h (S7–S0) (2) Read Status Register-2 35h (S15-S8) (2) Write Status Register 01h (S7–S0) (S15-S8) Page Program 02h A23–A16 A15–A8 A7–A0 (D7–D0) Quad Page Program 32h A23–A16 A15–A8 A7–A0 (D7–D0, …) (3) Sector Erase (4KB) 20h A23–A16 A15–A8 A7–A0 Block Erase (32KB) 52h A23–A16 A15–A8 A7–A0 Block Erase (64KB) D8h A23–A16 A15–A8 A7–A0 Chip Erase C7h/60h Erase Suspend 75h Erase Resume 7Ah Power-down B9h Continuous Read Mode Reset (4) FFh FFh Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from the device on the DO pin. 2. The Status Register contents will repeat continuously until /C S terminates the instruction. 3. Quad Page Program Input Data: IO0 = (D4, D0, ……) IO1 = (D5, D1, ……) IO2 = (D6, D2, ……) IO3 = (D7, D3, ……) 4. This instruction is recommended w hen using the Dual or Quad “Continuous Read Mode” feature. See section 11.2.32 for more information.

Publication Release Date: July 08, 2010 - 1 9 - R e v i s i o n F

11.2.3 Instruction Set Table 2 (Read Instructions)

(CODE) BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0) Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …) (1) Fast Read Dual I/O BBh A23-A8(2) A7-A0, M7-M0 (2) (D7-D0, …) (1) Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …) (3) Fast Read Quad I/O EBh A23-A0, M7-M0(4) (x,x,x,x, D7-D0, …) (5) (D7-D0, …) (3) Word Read Quad I/O(7) E7h A23-A0, M7-M0(4) (x,x, D7-D0, …) (6) (D7-D0, …) (3) Octal Word Read Quad I/O(8) E3h A23-A0, M7-M0(4) (D7-D0, …) (3) Notes: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data 4. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0, …..) IO1 = (x, x, x, x, D5, D1, …..) IO2 = (x, x, x, x, D6, D2, …..) IO3 = (x, x, x, x, D7, D3, …..) 6. Word Read Quad I/O Data 7. The lowest address bit must be 0. ( A0 = 0 ) 8. The lowest 4 address bits must be 0. ( A0, A1, A2, A3 = 0 )

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11.2.4 Instruction Set Table 3 (ID, Security Instructions)

(CODE) BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Release Power down / Device ID ABh dummy dummy dummy (ID7-ID0)(1) Manufacturer/ Device ID (2) 90h dummy dummy 00h (MF7-MF0) (ID7-ID0) Manufacturer/Device ID by Dual I/O 92h A23-A8 A7-A0, M[7:0] (MF[7:0], ID[7:0]) Manufacture/Device ID by Quad I/O 94h A23-A0, M[7:0] xxxx, (MF[7:0], ID[7:0]) (MF[7:0], ID[7:0], …) JEDEC ID 9Fh (MF7-MF0) Manufacturer (ID15-ID8) Memory Type (ID7-ID0) Capacity Read Unique ID 4Bh dummy dummy dummy dummy (ID63-ID0) Notes: 1. The Device ID will repeat continuously until /CS terminates the instruction. 2. See Manufacturer and Devi ce Identification table for Device ID information.

11.2.5 Write Enable (06h)

1. The WEL bit must be set prior to every Page Pr ogram, Sector Erase, Block Erase, Chip Erase and

instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high. Figure 4. Write Enable Instruction Sequence Diagram

11.2.6 Write Disable (04h)

Figure 5. Write Disable Instruction Sequence Diagram

11.2.7 Read Status Register-1 (05h) and Read Status Register-2 (35h)

SRP1, QE and SUS bits (see description of the Status Register earlier in this datasheet). continuously, as shown in Figure 6. The instruction is completed by driving /CS high. Figure 6. Read Status Register Instruction Sequence Diagram

11.2.8 Write Status Register (01h)

sending the instruction code “01h”, and then writing the status register data byte as illustrated in figure 7. The Status Register bits are shown in figure 3 and described earlier in this datasheet. bit locations are read-only and will not be affected by the Write Status Register instruction. self-timed Write Status R egister cycle will commence for a time duration of t W (See AC Characteristics). cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. methods. Factory default for all status Register bits are 0. Figure 7. Write Status Register Instruction Sequence Diagram

11.2.9 Read Data (03h)

the clock continues. The instruction is completed by driving /CS high. (see AC Electrical Characteristics). Figure 8. Read Data Instruction Sequence Diagram

11.2.10 Fast Read (0Bh)

on the DO pin is a “don’t care”. Figure 9. Fast Read Instruction Sequence Diagram

11.2.11 Fast Read Dual Output (3Bh)

Figure 10. Fast Read Dual Output Instruction Sequence Diagram

11.2.12 Fast Read Quad Output (6Bh)

at four times the rate of standard SPI devices. be high-impedance prior to the falling edge of the first data out clock. Figure 11. Fast Read Quad Output Instruction Sequence Diagram

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11.2.13 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. Fast Read Dual I/O with “Continuous Read Mode” The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 12a. The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits (M7-0) equals “Ax” hex, then the next Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require the BBh instruction code, as shown in figure 12b. This reduces the instruction sequence by eight cl ocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits (M7-0) are any value other than “Ax” hex, the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can be used to reset (M7-0) before issuing normal instructions (See 11.2.32 for detailed descriptions). Figure 12a. Fast Read Dual I/O Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh)

Publication Release Date: July 08, 2010 - 2 9 - R e v i s i o n F Figure 12b. Fast Read Dual I/O Instruction Sequence Diagram (M7-0 = Axh)

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11.2.14 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO 0, IO1, IO2 and IO3 and four Dummy clocks are required prior to the data output . The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast read Quad I/O Instruction. Fast Read Quad I/O with “Continuous Read Mode” The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 13a. The upper nibble of the (M7-4) controls the length of the next Fast R ead Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits (M7-0) equals “Ax” hex, then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the EBh instruction code, as shown in figure 13b. This reduces the instruction sequence by eight cl ocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits (M7-0) are any value other than “Ax” hex, the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can be used to reset (M7-0) before issuing normal instructions (See 11.2.32 for detailed descriptions). Byte 1 Byte 2Byte 1 Byte 2 Figure 13a. Fast Read Quad I/O Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh)

Publication Release Date: July 08, 2010 - 3 1 - R e v i s i o n F Figure 13b. Fast Read Quad I/O Instruction Sequence Diagram (M7-0 = Axh)

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11.2.15 Word Read Quad I/O (E7h)

The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clocks are required prior to the data output. The Quad I/O dramatically reduces instruct ion overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word Read Quad I/O Instruction. Word Read Quad I/O with “Continuous Read Mode” The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 14a. The upper nibble of the (M7-4) controls the length of the next Fast R ead Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits (M7-0) equal s “Ax” hex, then the next Word Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E7h instruction code, as shown in figure 14b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If t he “Continuous Read Mode” bits (M7-0) are any value other than “Ax” hex, the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operati on. A “Continuous Read Mode” Reset instruction can be used to reset (M7-0) before issuing normal instructions (See 11.2.32 for detailed descriptions). Instruction (E7h) Byte 1 Byte 2 Byte 3 4040 40 5151 51 6262 62 7373 73 Instruction (E7h) Byte 1 Byte 2 Byte 3 40 4040 40 40 40 51 5151 51 51 51 62 6262 62 62 62 73 7373 73 73 73 Figure 14a. Word Read Quad I/O Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh)

Publication Release Date: July 08, 2010 - 3 3 - R e v i s i o n F Byte 1 Byte 2 Byte 3 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 Byte 1 Byte 2 Byte 3 4 04 0 4 04 0 4 04 0 5 15 1 5 15 1 5 15 1 6 26 2 6 26 2 6 26 2 7 37 3 7 37 3 7 37 3 Figure 14b. Word Read Quad I/O Instruction Sequence Diagram (M7-0 = Axh)

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11.2.16 Octal Word Read Quad I/O (E3h)

The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the four dummy clocks are not required, which further reduces the instru ction overhead allowing even faster random access for code execution (XIP). The Quad Enabl e bit (QE) of Status Register-2 must be set to enable the Octal Word Read Quad I/O Instruction. Octal Word Read Quad I/O with “Continuous Read Mode” The Octal Word Read Quad I/O instruction can fu rther reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 15a. The upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through the inclusion or exclusion of the fi rst byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-im pedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits (M7-0) equals “A x” hex, then the next Octal Word Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E3h instruction code, as shown in figure 15b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If t he “Continuous Read Mode” bits (M7-0) are any value other than “Ax” hex, the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operati on. A “Continuous Read Mode” Reset instruction can be used to reset (M7-0) before issuing normal instructions (See 11.2.32 for detailed descriptions). Figure 15a. Octal Word Read Quad I/O Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh) Instruction (E3h) Byte 1 Byte 2 Byte 3 4040 40 5151 51 6262 62 7373 73 Byte 4 Instruction (E3h) Byte 1 Byte 2 Byte 3 40 4040 40 40 40 51 5151 51 51 51 62 6262 62 62 62 73 7373 73 73 73 40 40 51 51 62 62 73 73 Byte 4

Publication Release Date: July 08, 2010 - 3 5 - R e v i s i o n F Figure 15b. Octal Word Read Quad I/O Instruction Sequence Diagram (M7-0 = Axh) Byte 2 Byte 3 Byte 4 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 Byte 1 4 0 5 1 6 2 7 3 Byte 2 Byte 3 Byte 4 4 04 0 4 04 0 4 04 0 5 15 1 5 15 1 5 15 1 6 26 2 6 26 2 6 26 2 7 37 3 7 37 3 7 37 3 Byte 1 4 04 0 5 15 1 6 26 2 7 37 3

11.2.17 Page Program (02h)

page and overwrite previously sent data. the Block Protect (BP2, BP1, and BP0) bits. Figure 16. Page Program Instruction Sequence Diagram

11.2.18 Quad Input Page Program (32h)

improve performance for PROM Programmer and applic ations that have slow clock speeds <5MHz. since the inherent page program time is much greater than the time it take to clock-in the data. instruction sequence is shown in figure 17. Figure 17. Quad Input Page Program Instruction Sequence Diagram

11.2.19 Sector Erase (20h)

Sector Erase instruction sequence is shown in figure 18. BP1, and BP0) bits (see Status Register Memory Protection table). Figure 18. Sector Erase Instruction Sequence Diagram

Erase instruction sequence is shown in figure 19. BP1, and BP0) bits (see Status Register Memory Protection table). Figure 19. 32KB Block Erase Instruction Sequence Diagram

Erase instruction sequence is shown in figure 20. Status Register Memory Protection table). Figure 20. 64KB Block Erase Instruction Sequence Diagram

11.2.22 Chip Erase (C7h / 60h)

instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure 21. Figure 21. Chip Erase Instruction Sequence Diagram

11.2.23 Erase Suspend (75h)

sequence is shown in figure 22. written during the Chip Erase or Program operation, the Erase Suspend instruction is ignored. time of “tSUS” following the preceding Resume instruction “7Ah”. Figure 22. Erase Suspend Instruction Sequence Diagram

11.2.24 Erase Resume (7Ah)

will be ignored by the device. The Erase Resume instruction sequence is shown in figure 23. SUS” following a previous Resume instruction. Figure 23. Erase Resume Instruction Sequence Diagram

11.2.25 Power-down (B9h)

instruction especially useful for battery powered applic ations (See ICC1 and ICC2 in AC Characteristics). Figure 24. Deep Power-down Instruction Sequence Diagram

Publication Release Date: July 08, 2010 - 4 5 - R e v i s i o n F

11.2.26 Release Power-down / Device ID (ABh)

The Release from Power-down / Device ID instructi on is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To release the device from the power-down state, the instruction is i ssued by driving the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in figure 25a. Release from power- down will take the time duration of t RES1 (See AC Characteristics) before the device will resume normal operation and other instructions are accepted. The /CS pin must remain high during the t RES1 time duration. When used only to obtain the Device ID while not in t he power-down state, the inst ruction is initiated by driving the /CS pin low and shifting the instruction c ode “ABh” followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 25b. The Device ID values for the W25Q16BV is list ed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. When used to release the device from the power-down state and obtain the Device ID, the instruction is the same as previously described, and shown in figure 25b, except that after /C S is driven high it must remain high for a time duration of t RES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instructions w ill be accepted. If the Release from Power-down / Device ID instruction is issued while an Erase, Pr ogram or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle. Figure 25a. Release Power-down Instruction Sequence Diagram

• 46 - Figure 25b. Release Power-down / Device ID Instruction Sequence Diagram

11.2.27 Read Manufacturer / Device ID (90h)

ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. the other. The instruction is completed by driving /CS high. Figure 26. Read Manufacturer / Device ID Instruction Sequence Diagram

11.2.28 Read Manufacturer / Device ID Dual I/O (92h)

The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. figure 27. The Device ID values for the W25Q16BV is listed in Manufacturer and Device Identification the other. The instruction is completed by driving /CS high. Figure 27. Read Manufacturer / Device ID Dual I/O Instruction Sequence Diagram The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction.

11.2.29 Read Manufacturer / Device ID Quad I/O (94h)

The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction. continuously, alternating from one to the other. The instruction is completed by driving /CS high. Figure 28. Read Manufacturer / Device ID Quad I/O Instruction Sequence Diagram The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Quad I/O instruction.

11.2.30 Read Unique ID Number (4Bh)

bit ID is shifted out on the falling edge of CLK as shown in figure 29. Figure 29. Read Unique ID Number Instruction Sequence Diagram

11.2.31 Read JEDEC ID (9Fh)

capacity values refer to Manufacturer and Device Identification table. Figure 30. Read JEDEC ID Instruction Sequence Diagram

11.2.32 Continuous Read Mode Reset (FFh or FFFFh)

Figure 31. Continuous Read Mode Reset for Fast Read Dual/Quad I/O needed to shift in instruction “FFFFh”.

Publication Release Date: July 08, 2010 - 5 3 - R e v i s i o n F 12. ELECTRICAL CHARACTERISTICS

12.1 Absolute Maximum Ratings (1)

PARAMETERS SYMBOL CONDITIONS RANGE UNIT Supply Voltage VCC –0.6 to +4.0 V Voltage Applied to Any Pin VIO Relative to Ground –0.6 to VCC+0.4 V Transient Voltage on any Pin VIOT <20nS Transient Relative to Ground –2.0V to VCC+2.0V V Storage Temperature TSTG –65 to +150 °C Lead Temperature TLEAD See Note (2) °C Electrostatic Discharge Voltage VESD Human Body Model(3) –2000 to +2000 V Notes: 1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage. 2. Compliant with JEDEC Standard J-STD-20C for sm all body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU. 3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).

12.2 Operating Ranges

SPEC PARAMETER SYMBOL CONDITIONS MIN MAX UNIT Supply Voltage(1) VCC FR = 80MHz, fR = 50MHz FR = 104MHz, fR = 50MHz FR = 50MHz (for E3h command) 2.7 3.0 3.0 3.6 3.6 3.6 V Ambient Temperature, Operating T A Commercial Industrial –40 +70 +85 Note: 1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming (erase/write) voltage.

12.3 Power-up Timing and Write Inhibit Threshold

1. These parameters are characterized only.

Figure 32. Power-up Timing and Voltage Levels

Publication Release Date: July 08, 2010 - 5 5 - R e v i s i o n F

12.4 DC Electrical Characteristics

SPEC PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Input Capacitance CIN(1) V IN = 0V(1) 6 pF Output Capacitance Cout(1) V OUT = 0V(1) 8 pF Input Leakage ILI ±2 µA I/O Leakage ILO ±2 µA Standby Current ICC1 /CS = VCC, VIN = GND or VCC 25 50 µA Power-down Current ICC2 /CS = VCC, VIN = GND or VCC 1 5 µA Current Read Data / Dual /Quad 1MHz (2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 4/5/6 6/8.5/10 mA Current Read Data / Dual /Quad 33MHz (2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 6/7/8 9/10.5/12 mA Current Read Data / Dual /Quad 50MHz (2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open Current Read Data / Dual Output Read/Quad Output Read 80MHz (2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 10/11/12 15/16.5/18 mA Current Write Status Register I CC4 /CS = VCC 8 12 mA Current Page Program ICC5 /CS = VCC 20 25 mA Current Sector/Block Erase I CC6 /CS = VCC 20 25 mA Current Chip Erase ICC7 /CS = VCC 20 25 mA Input Low Voltage VIL VCC x 0.3 V Input High Voltage VIH VCC x 0.7 V Output Low Voltage VOL I OL = 1.6 mA 0.4 V Output High Voltage VOH I OH = –100 µA VCC – 0.2 V Notes: 1. Tested on sample basis and specified through design and characterization data. TA=25° C, VCC 3V. 2. Checker Board Pattern.

12.5 AC Measurement Conditions

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 33. AC Measurement I/O Waveform

Publication Release Date: July 08, 2010 - 5 7 - R e v i s i o n F

12.6 AC Electrical Characteristics

Clock frequency for all instructions, except Read Data (03h) & Octal Word Read (E3h) 2.7V-3.6V VCC & Industrial Temperature F R f C D.C. 80 MHz Clock frequency for all instructions, except Read Data (03h) & Octal Word Read (E3h) 3.0V-3.6V VCC & Commercial Temperature F R f C D.C. 104 MHz Clock frequency for Octal Word Read (E3h) 3.0V-3.6V VCC & Industrial Temperature F R f C D.C. 50 MHz Clock freq. Read Data instruction (03h) fR D.C. 50 MHz Clock High, Low Time except Read Data (03h) tCLH, tCLL(1) 4.5 ns Clock High, Low Time for Read Data (03h) instruction t CRLH, tCRLL(1) 6 ns Clock Rise Time peak to peak tCLCH(2) 0.1 V/ns Clock Fall Time peak to peak tCHCL(2) 0.1 V/ns /CS Active Setup Time relative to CLK tSLCH t CSS 5 ns /CS Not Active Hold Time relative to CLK tCHSL 5 ns Data In Setup Time tDVCH t DSU 1.5 ns Data In Hold Time tCHDX t DH 4 ns /CS Active Hold Time relative to CLK tCHSH 5 ns /CS Not Active Setup Time relative to CLK tSHCH 5 ns /CS Deselect Time (for Array Read Æ Array Read / Erase or Program Æ Read Status Registers) tSHSL t CSH 7/40 ns Output Disable Time tSHQZ(2) t DIS 7 ns Clock Low to Output Valid tCLQV1 t V1 6 / 5 ns Clock Low to Output Valid (for Read ID instructions) t CLQV2 t V2 8.5 / 7.5 ns Output Hold Time tCLQX t HO 0 ns Continued – next page

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12.7 AC Electrical Characteristics (cont’d)

/HOLD Active Setup Time relative to CLK tHLCH 5 ns /HOLD Active Hold Time relative to CLK tCHHH 5 ns /HOLD Not Active Setup Time relative to CLK tHHCH 5 ns /HOLD Not Active Hold Time relative to CLK tCHHL 5 ns /HOLD to Output Low-Z tHHQX(2) t LZ 7 ns /HOLD to Output High-Z tHLQZ(2) t HZ 7 ns Write Protect Setup Time Before /CS Low tWHSL(3) 20 ns Write Protect Hold Time After /CS High tSHWL(3) 100 ns /CS High to Power-down Mode tDP(2) 3 µs /CS High to Standby Mode without Electronic Signature Read tRES1(2) 3 µs /CS High to Standby Mode with Electronic Signature Read t RES2(2) 1.8 µs /CS High to next Instruction after Suspend tSUS(2) 20 µs Write Status Register Time tW 10 15 ms Byte Program Time (First Byte) (4) tBP1 20 50 µs Additional Byte Program Time (After First Byte) (4) tBP2 2.5 12 µs Page Program Time tPP 0.7 3 ms Sector Erase Time (4KB) tSE 30 200/400(5) ms Block Erase Time (32KB) tBE1 120 800 ms Block Erase Time (64KB) tBE2 150 1000 ms Chip Erase Time tCE 3 10 s Notes: 1. Clock high + Clock low must be less than or equal to 1/f C. 2. Value guaranteed by design and/or characte rization, not 100% tested in production. 3. Only applicable as a constraint for a Write Stat us Register instruction when SRP0 is set to 1. 4. For multiple bytes after first byte within a page, tBPN = t BP1 + tBP2 * N (typical) and tBPN = t BP1 + tBP2 * N (max), where N = number of bytes programmed. 5. Max Value t SE with <50K cycles is 200ms and >50K & <100K cycles is 400ms.

Publication Release Date: July 08, 2010 - 5 9 - R e v i s i o n F

12.8 Serial Output Timing

12.9 Serial Input Timing

12.10 Hold Timing

• 60 - 13. PACKAGE SPECIFICATION 13.1 8-Pin SOIC 150-mil (Package Code SN) L θ c D A e b SEATING PLANE Y 0.25 GAUGE PLANE E HE L θ c D A e bbb SEATING PLANE Y 0.25 GAUGE PLANE E HEE HE MILLIMETERS INCHES SYMBOL Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.008 0.010 E (3) 3.80 4.00 0.150 0.157 D (3) 4.80 5.00 0.188 0.196 e (2) 1.27 BSC 0.050 BSC HE 5.80 6.20 0.228 0.244 Y (4) --- 0.10 --- 0.004 L 0.40 1.27 0.016 0.050 θ 0° 10° 0° 10° Notes: 1. Controlling dimensions: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches.

Publication Release Date: July 08, 2010 - 6 1 - R e v i s i o n F 13.2 8-Pin SOIC 208-mil (Package Code SS) θ GAUGE PLANE θ GAUGE PLANE MILLIMETERS INCHES SYMBOL Min Nom Max Min Nom Max e (2) 1.27 BSC. 0.050 BSC. Notes: 1. Controlling dimensions: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches.

• 62 - 13.3 8-Pin PDIP 300-mil (Package Code DA) MILLIMETERS INCHES SYMBO L Min Nom Max Min Nom Max E 7.62 BSC. 0.300 BSC.

Publication Release Date: July 08, 2010 - 6 3 - R e v i s i o n F 13.4 8-Contact 6x5mm WSON (Package Code ZP) MILLIMETERS INCHES SYMBOL Min Nom Max Min Nom Max e (2) 1.27 BSC. 0.050 BSC.

• 64 - 8-Contact 6x5mm WSON Cont’d. MILLIMETERS INCHES SYMBOL Min Nom Max Min Nom Max SOLDER PATTERN M 3.40 0.134 N 4.30 0.169 P 6.00 0.236 Q 0.50 0.020 R 0.75 0.026 Notes: 1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.

Publication Release Date: July 08, 2010 - 6 5 - R e v i s i o n F 13.5 16-Pin SOIC 300-mil (Package Code SF) GAUGE PLANE DETAIL A GAUGE PLANE DETAIL A MILLIMETERS INCHES SYMBOL Min Nom Max Min Nom Max e (2) 1.27 BSC. 0.050 BSC. Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.

• 66 - 14. ORDERING INFORMATION (1) W 25Q 16B V xx(1) (2) I = Industrial (-40°C to +85°C) SN = 8-pin SOIC 150-mil ZP = 8-pad WSON 6x5mm SF = 16-pin SOIC 300-mil SS = 8-pin SOIC 208-mil DA = 8-pin PDIP 300-mil V = 2.7V to 3.6V 16B = 16M-bit 25Q = SpiFlash Serial Flash Memo ry with 4KB sectors, Dual/Quad I/O W = Winbond G = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) P = Green Package with Status Register Power Lock-Down & OTP enabled Notes: 1a. Only the 2 nd letter is used for the part marking; WSON package type ZP is not used for the part marking. 1b. The “W” prefix is not included on the part marking. 2a. Standard bulk shipments are in Tube (shape E). Please spec ify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 2b. For shipments with OTP feature enabled, please specify when placing orders.

Publication Release Date: July 08, 2010 - 6 7 - R e v i s i o n F

14.1 Valid Part Numbers and Top Side Marking

The following table provides the valid part numbers for the W25Q16BV SpiFlash Memory. Please contact Winbond for specific availability by density and pa ckage type. Winbond SpiFlash memories use an 12- digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 10-digit number. PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING SN(2) SOIC-8 150mil 16M-bit W25Q16BVSNIG W25Q16BVSNIP 25Q16BVNIG 25Q16BVNIP SS SOIC-8 208mil 16M-bit W25Q16BVSSIG W25Q16BVSSIP 25Q16BVSIG 25Q16BVSIP SF(2) SOIC-16 300mil 16M-bit W25Q16BVSFIG W25Q16BVSFIP 25Q16BVFIG 25Q16BVFIP ZP(1) WSON-8 6x5mm 16M-bit W25Q16BVZPIG W25Q16BVZPIP 25Q16BVIG 25Q16BVIP DA(2) PDIP-8 300mil 16M-bit W25Q16BVDAIG W25Q16BVDAIP 25Q16BVAIG 25Q16BVAIP Note: 1. WSON package type ZP is not used in the top side marking. 2. These Package types are Special Order Only , please contact Winbond for more information.

• 68 - 15. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A 08/24/08 New Create Preliminary B 02/12/09 03/09/09 03/11/09 03/13/09 13, 14, 17, 51, 55, 63 & 64 Added Erase Suspend Status Bit Removed HPM instruction Updated max. read frequency Updated Ordering Information Added note 2b. Change Active Current to 4mA Change QE pin to QE Bit C 04/23/09 04/30/09 04/30/09 5,7,9,61,65,66 Added PDIP Package. Dual Data Read Icc3 1MHz Max = 8.5ma Quad Data Read Icc3 1MHz Max = 10ma D 08/20/09 5, 67 60-65 42, 43 Special Order Notes Updated package diagram Updated Erase Suspend/Resume descriptions UID Waveform Corrected E 11/04/09 Removed Preliminiary designator Corrected PDF TOC error Update 90h Waveform Diagram Update 9Fh Waveform Diagram F 07/08/10 60-65 55, 58 Updated Package Diagrams Updated parameter VIL/VIH, tSE Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, com bustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.