25Q16

W25Q80 WINBOND | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 61

Technical content

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 1 - P r e l i m i n a r y - R e v i s i o n B 8M-BIT, 16M-BIT AND 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

W25Q80, W25Q16, W25Q32 - 2 - Table of Contents

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 3 - P r e l i m i n a r y - R e v i s i o n B

W25Q80, W25Q16, W25Q32 - 4 -

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 5 - P r e l i m i n a r y - R e v i s i o n B 1. GENERAL DESCRIPTION The W25Q80 (8M-bit), W25Q16 (16M-bit), and W25Q32 (32M-bit) Serial Flash memories provide a storage solution for systems with limited space, pi ns and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices . They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP ) and storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 5mA active and 1µA for power-down. All devices are offered in space-saving packages. The W25Q80/16/32 array is organized into 4, 096/8,192/16,384 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time using the Page Program instructions. Pages can be erased in groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip eras e). The W25Q80/16/32 has 256/512/1024 erasable sectors and 16/32/64 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25Q80/16/32 supports the standard Serial Peri pheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI using SPI pins: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD ). SPI clock frequencies of up to 80MHz are supported allowing equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output when using the Fast Read Dual/Quad Output instru ctions. These transfer rates are comparable to those of 8 and 16-bit Parallel Flash memories. A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally , the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number. 2. FEATURES

• Family of SpiFlash Memories – W25Q80: 8M-bit / 1M -byte (1,048,576) – W25Q16: 16M-bit / 2M-byte (2,097,152) – W25Q32: 32M-bit / 4M-byte (4,194,304) – 256-bytes per programmable page
• Standard, Dual or Quad SPI – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Dual SPI: CLK, /CS, IO 0, IO1, /WP, /Hold – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
• Highest Performance Serial Flash – Up to 6X that of ordinary Serial Flash – 80MHz clock operation – 160MHz equivalent Dual SPI – 320MHz equivalent Quad SPI – 40MB/S continuous data transfer rate – 30MB/S random access (32-byte fetch) – Comparable to X16 Parallel Flash
• Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply – 4mA active current, <1µA Power-down (typ.) – -40°C to +85°C operating range
• Flexible Architecture with 4KB sectors – Uniform Sector Erase (4K-bytes) – Block Erase (32K and 64K-bytes) – Program one to 256 bytes – Up to 100,000 erase/write cycles – 20-year data retention
• Advanced Security Features – Software and Hardware Write-Protect – Top or Bottom, Sector or Block selection – Lock-Down and OTP protection (1) – 64-Bit Unique ID for each device(1) Note 1: These features are on special order. Please contact Winbond for details.
• Space Efficient Packaging – 8-pin SOIC 208-mil – 8-pad WSON 6x5-mm (W25Q80 & W25Q16) –16-pin SOIC 300-mil (W25Q16 & W25Q32)

W25Q80, W25Q16, W25Q32 - 6 - 3. PIN CONFIGURATION SOIC 208-MIL Figure 1a. W25Q80, W25Q16, W25Q32 Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 4. PAD CONFIGURATION WSON 6X5-MM Figure 1b. W25Q80, W25Q16 Pad Assignments, 8-pad WSON (Package Code ZP) 5. PIN DESCRIPTION SOIC 208-MIL, AND WSON 6X5-MM PIN NO. PIN NAME I/O FUNCTION 1 /CS I Chip Select Input

2 DO (IO1) I/O Data Output (Data Input Output 1)* 1

3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)* 2

4 GND Ground

5 DI (IO0) I/O Data Input (Data Input Output 0)*1

6 CLK I Serial Clock Input

7 /HOLD (IO3) I/O Hold Input (Data Input Output 3)* 2

8 VCC Power Supply

*1 IO0 and IO1 are used for Dual and Quad instructions *2 IO0 – IO3 are used for Quad instructions

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 7 - P r e l i m i n a r y - R e v i s i o n B 6. PIN CONFIGURATION SOIC 300-MIL Figure 1c. W25Q16 and W25Q32 Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 7. PIN DESCRIPTION SOIC 300-MIL PAD NO. PAD NAME I/O FUNCTION 1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)* 2

2 VCC Power Supply

3 N/C No Connect

4 N/C No Connect

5 N/C No Connect

6 N/C No Connect

8 DO (IO1) I/O Data Output (Data Input Output 1)* 1

9 /WP (IO2) I/O Write Protect Input (D ata Input Output 2)*2

10 GND Ground

11 N/C No Connect

12 N/C No Connect

13 N/C No Connect

14 N/C No Connect

15 DI (IO0) I/O Data Input (Data Input Output 0)*1

16 CLK I Serial Clock Input

*1 IO0 and IO1 are used for Dual and Quad instructions *2 IO0 – IO3 are used for Quad instructions

W25Q80, W25Q16, W25Q32 - 8 -

7.1 Package Types

W25Q80 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and 6x5-mm WSON (package code ZP). W25Q16 is offered in an 8-pi n plastic 208-mil width SOIC (package code SS) and 6x5-mm WSON as shown in figure 1a, and 1b, respectively. The W25Q16 and W25Q32 are offered in a 16-pin plastic 300-mil width SOIC (pa ckage code SF) as shown in figure 1c. Package diagrams and dimensions are illustrated at the end of this datasheet.

7.2 Chip Select (/CS)

The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power cons umption will be at standby levels unless an internal erase, program or status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and inst ructions can be written to and data read from the device. After power-up, /CS must transition from high to low befor e a new instruction will be accepted. The /CS input must track the VCC supply level at power-up (see “Write Protection” and figure 30). If needed a pull-up resister on /CS can be used to accomplish this.

7.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)

The W25Q80/16/32 support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addr esses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge CLK. Dual and Quad SPI instruction use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1 the /WP pin becomes IO2 and /HOLD pin becomes IO3.

7.4 Write Protect (/WP)

The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Pr otect (SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion or the entir e memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin (Hardware Write Protect) function is not available since this pin is used for IO2. See figure 1a, 1b, and 1c for the pin configuration of Quad I/O operation.

7.5 HOLD (/HOLD)

The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedanc e and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Q uad I/O, the /HOLD pin function is not available since this pin is used for IO3. See figure 1a, 1b, and 1c for the pin configuration of Quad I/O operation.

7.6 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides t he timing for serial input and output operations. ("See SPI Operations")

Figure 2. W25Q80, W25Q16 and W25Q32 Block Diagram

W25Q80, W25Q16, W25Q32 - 10 - 9. FUNCTIONAL DESCRIPTION

9.1 SPI OPERATIONS

9.1.1 Standard SPI Instructions

The W25Q80/16/32 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Ou tput (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or dat a to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge CLK. SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3 the CL K signal is normally high on the falling and rising edges of /CS.

9.1.2 Dual SPI Instructions

The W25Q80/16/32 supports Dual SPI operation when us ing the "Fast Read Dual Output and Dual I/O" (3B and BB hex) instructions. These instructions allo w data to be transferred to or from the device at two to three times the rate of ordinary Serial Flas h devices. The Dual Read instructions are ideal for quickly downloading code to RAM upon power-up (code-s hadowing) or for executing non-speed-critical code directly from the SPI bus (X IP). When using Dual SPI instruct ions the DI and DO pins become bidirectional I/O pins; IO0 and IO1.

9.1.3 Quad SPI Instructions

The W25Q80/16/32 supports Quad SPI operation when using the "Fast Read Quad Output and Fast Read Quad I/O" (6B and EB hex respectively). These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Q uad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.

9.1.4 Hold Function

The /HOLD signal allows the W25Q80/16/32 operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases w here the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so programmi ng can resume where it left off once the bus is available again. The /HOLD function is only ava ilable for standard SPI and Dual SPI operation, not during Quad SPI. To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK signal is already lo w. If the CLK is not already low the

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 1 1 - P r e l i m i n a r y - R e v i s i o n B /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device.

9.2 WRITE PROTECTION

Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the W25Q80/16/32 provides several means to protect data from inadvertent writes.

9.2.1 Write Protect Features

• Device resets when VCC is below threshold
• Time delay write disable after Power-up
• Write enable/disable instructions and automat ic write disable after program and erase
• Software and Hardware (/WP pin) writ e protection using Status Register
• Write Protection using Power-down instruction
• Lock Down write protection until next power-up (1)
• One Time Program (OTP) write protection (1) Note 1: These features are available upon special order. Please contact Winbond for details. Upon power-up or at power-down the W25Q80/16/32 will maintain a reset condition while VCC is below the threshold value of V WI, (See Power-up Timing and Voltage Levels and Figure 29). While reset, all operations are disabled and no instructions are re cognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of t PUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If needed a pull-up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Chip Erase or Write Status Regist er instruction will be accepted. After completing a program, erase or write instruction the Write Enabl e Latch (WEL) is automatically cleared to a write- disabled state of 0. Software controlled write protection is facilitated using the Write Stat us Register instruction and setting the Status Register Protect (SRP0, SRP1) and Block Protect (SEC,T B, BP2, BP1 and BP0) bits. These settings allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register for further information. Additionally, t he Power-down instruction offers an extra level of write protection as all instructi ons are ignored except for the Release Power-down instruction.

W25Q80, W25Q16, W25Q32 - 12 - 10. CONTROL AND STATUS REGISTERS The Read Status Register-1 and Stat us Register-2 instructions can be used to provide status on the availability of the Flash memory array, if the dev ice is write enabled or dis abled, the state of write protection and the Quad SPI setting. The Write Status Register instruction can be used to configure the devices write protection features and Quad SPI setting. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and in some cases the /WP pin.

10.1 STATUS REGISTER

10.1.1 BUSY

BUSY is a read only bit in the status register (S0) t hat is set to a 1 state w hen the device is executing a Page Program, Sector Erase, Block Er ase, Chip Erase or Write Status Register instruction. During this time the device will ignore further instructions ex cept for the Read Status Register and Erase Suspend instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.

10.1.2 Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.

10.1.3 Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0 ) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and stat us. Block Protect bits can be set using the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (s ee Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected.

10.1.4 Top/Bottom Block Protect (TB)

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits.

10.1.5 Sector/Block Protect (SEC)

The non-volatile Sector protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0.

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 1 3 - P r e l i m i n a r y - R e v i s i o n B

10.1.6 Status Register Protect (SRP1, SRP0)

The Status Register Protect bits (SRP1 and SRP0) are non- volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. SRP1 SRP0 /WP Status Register Description 0 0 X Software Protection /WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default] 0 1 0 Hardware Protected When /WP pin is low the Status Register locked and can not be written to. 0 1 1 Hardware Unprotected When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. 1 0 X Power Supply Lock-Down(1) Status Register is protected and can not be written to again until the next power-down, power-up cycle.(2) 1 1 X One Time Program(1) Status Register is permanently protected and can not be written to. Note: 1. These features are available upon special order. Please contact Winbond for details. 2. When SRP1, SRP0 = (1,0), a power-down, power-up cycle will change SRP1, SRP0 to (0,0) state.

10.1.7 Quad Enable (QE)

The Quad Enable (QE) bit is a non-volatile read/write bi t in the status register (S9) that allows Quad operation. When the QE bit is set to a 0 state (factory default) the /WP pin and /Hold are enabled. When the QE pin is set to a 1 the Quad IO2 and IO3 pins are enabled. WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins are tied directly to the power supply or ground.

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 1 5 - P r e l i m i n a r y - R e v i s i o n B

10.1.8 Status Register Memory Protection

STATUS REGISTER(1) W25Q32 (32M-BIT) MEMORY PROTECTION SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 63 3F0000h - 3FFFFFh 64KB Upper 1/64 0 0 0 1 0 62 and 63 3E0000h - 3FFFFFh 128KB Upper 1/32 0 0 0 1 1 60 thru 63 3C0000h - 3FFFFFh 256KB Upper 1/16 0 0 1 0 0 56 thru 63 380000h - 3FFFFFh 512KB Upper 1/8 0 0 1 0 1 48 thru 63 300000h - 3FFFFFh 1MB Upper 1/4 0 0 1 1 0 32 thru 63 200000h - 3FFFFFh 2MB Upper 1/2 0 1 0 0 1 0 000000h - 00FFFFh 64KB Lower 1/64 0 1 0 1 0 0 and 1 000000h - 01FFFFh 128KB Lower 1/32 0 1 0 1 1 0 thru 3 000000h - 03FFFFh 256KB Lower 1/16 0 1 1 0 0 0 thru 7 000000h - 07FFFFh 512KB Lower 1/8 0 1 1 0 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/4 0 1 1 1 0 0 thru 31 000000h – 1FFFFFh 2MB Lower 1/2 X X 1 1 1 0 thru 63 000000h – 3FFFFFh 4MB ALL 1 0 0 0 1 63 3FF000h – 3FFFFFh 4KB Top Block 1 0 0 1 0 63 3FE000h – 3FFFFFh 8KB Top Block 1 0 0 1 1 63 3FC000h – 3FFFFFh 16KB Top Block 1 0 1 0 X 63 3F8000h – 3FFFFFh 32KB Top Block 1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block 1 1 0 1 0 0 000000h – 001FFFh 8KB Bottom Block 1 1 0 1 1 0 000000h – 003FFFh 16KB Bottom Block 1 1 1 0 X 0 000000h – 007FFFh 32KB Bottom Block

W25Q80, W25Q16, W25Q32 - 16 - STATUS REGISTER(1) W25Q16 (16M-BIT) MEMORY PROTECTION SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 31 1F0000h - 1FFFFFh 64KB Upper 1/32 0 0 0 1 0 30 and 31 1E0000h - 1FFFFFh 128KB Upper 1/16 0 0 0 1 1 28 thru 31 1C0000h - 1FFFFFh 256KB Upper 1/8 0 0 1 0 0 24 thru 31 180000h - 1FFFFFh 512KB Upper 1/4 0 0 1 0 1 16 thru 31 100000h - 1FFFFFh 1MB Upper 1/2 0 1 0 0 1 0 000000h - 00FFFFh 64KB Lower 1/32 0 1 0 1 0 0 and 1 000000h - 01FFFFh 128KB Lower 1/16 0 1 0 1 1 0 thru 3 000000h - 03FFFFh 256KB Lower 1/8 0 1 1 0 0 0 thru 7 000000h - 07FFFFh 512KB Lower 1/4 0 1 1 0 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/2 X X 1 1 X 0 thru 31 000000h – 1FFFFFh 2MB ALL 1 0 0 0 1 31 1FF000h – 1FFFFFh 4KB Top Block 1 0 0 1 0 31 1FE000h – 1FFFFFh 8KB Top Block 1 0 0 1 1 31 1FC000h – 1FFFFFh 16KB Top Block 1 0 1 0 X 31 1F8000h – 1FFFFFh 32KB Top Block 1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block 1 1 0 1 0 0 000000h – 001FFFh 8KB Bottom Block 1 1 0 1 1 0 000000h – 003FFFh 16KB Bottom Block 1 1 1 0 X 0 000000h – 007FFFh 32KB Bottom Block

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 1 7 - P r e l i m i n a r y - R e v i s i o n B STATUS REGISTER(1) W25Q80 (8M-BIT) MEMORY PROTECTION SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 15 0F0000h - 0FFFFFh 64KB Upper 1/16 0 0 0 1 0 14 and 15 0E0000h - 0FFFFFh 128KB Upper 1/8 0 0 0 1 1 12 thru 15 0C0000h - 0FFFFFh 256KB Upper 1/4 0 0 1 0 0 8 thru 15 080000h - 0FFFFFh 512KB Upper 1/2 0 1 0 0 1 0 000000h - 00FFFFh 64KB Lower 1/16 0 1 0 1 0 0 and 1 000000h - 01FFFFh 128KB Lower 1/8 0 1 0 1 1 0 thru 3 000000h - 03FFFFh 256KB Lower 1/4 0 1 1 0 0 0 thru 7 000000h - 07FFFFh 512KB Lower 1/2 X X 1 1 X 0 thru 15 000000h – 0FFFFFh 1MB ALL 1 0 0 0 1 15 0FF000h – 0FFFFFh 4KB Top Block 1 0 0 1 0 15 0FE000h – 0FFFFFh 8KB Top Block 1 0 0 1 1 15 0FC000h – 0FFFFFh 16KB Top Block 1 0 1 0 X 15 0F8000h – 0FFFFFh 32KB Top Block 1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block 1 1 0 1 0 0 000000h – 001FFFh 8KB Bottom Block 1 1 0 1 1 0 000000h – 003FFFh 16KB Bottom Block 1 1 1 0 X 0 000000h – 007FFFh 32KB Bottom Block Note: 1. x = don’t care

W25Q80, W25Q16, W25Q32 - 18 -

10.2 INSTRUCTIONS

The instruction set of the W25Q80/16/ 32 consists of fifteen basic instru ctions that are fully controlled through the SPI bus (see Instruction Set table). Instru ctions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into t he DI input provides the in struction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some ca ses, a combination. Inst ructions are completed with the rising edge of edge /CS. Clock relative ti ming diagrams for each instruction are included in figures 4 through 19. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a full 8-bits have been clocked) otherwise t he instruction will be terminated. Th is feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed.

10.2.1 Manufacturer and Device Identification

MANUFACTURER ID (M7-M0) Winbond Serial Flash EFh Device ID (ID7-ID0) (ID15-ID0) Instruction ABh, 90h 9Fh W25Q80 13h 4014h W25Q16 14h 4015h W25Q32 15h 4016h

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 1 9 - P r e l i m i n a r y - R e v i s i o n B

10.2.2 Instruction Set Table 1 (1)

(CODE) BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Write Enable 06h Write Disable 04h Read Status Register-1 05h (S7–S0) (2) Read Status Register-2 35h (S15-S8) (2) Write Status Register 01h (S7–S0) (S15-S8) Page Program 02h A23–A16 A15–A8 A7–A0 (D7–D0) Quad Page Program 32h A23–A16 A15–A8 A7–A0 (D7–D0, …) (3) Block Erase (64KB) D8h A23–A16 A15–A8 A7–A0 Block Erase (32KB) 52h A23–A16 A15–A8 A7–A0 Sector Erase (4KB) 20h A23–A16 A15–A8 A7–A0 Chip Erase C7h/60h Erase Suspend 75h Erase Resume 7Ah Power-down B9h High Performance Mode A3h dummy dummy dummy Mode Bit Reset (4) FFh FFh Release Power down or HPM / Device ID ABh dummy dummy dummy (ID7-ID0) (5) Manufacturer/ Device ID (6) 90h dummy dummy 00h (M7-M0) (ID7-ID0) Read Unique ID(7) 4Bh dummy dummy dummy Dummy (ID63-ID0) JEDEC ID 9Fh (M7-M0) Manufacturer (ID15-ID8) Memory Type (ID7-ID0) Capacity Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from the device on the DO pin. 2. The Status Register contents will repeat continuously until /CS terminates the instruction. 3. Quad Page Program Input Data IO0 = (D4, D0, ……) IO1 = (D5, D1, ……) IO2 = (D6, D2, ……) IO3 = (D7, D3, ……) 4. This instruction is recommended when using the Dual or Quad Mode bit feature. See section 10.2.28 for more information. 5. The Device ID will repeat continuously until /CS terminates the instruction. 6. See Manufacturer and Device Identification table for Device ID information. 7. This feature is available upon special order. Please contact Winbond for details.

W25Q80, W25Q16, W25Q32 - 20 -

10.2.3 Instruction Set Table 2 (Read Instructions)

(CODE) BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Read Data 03h A23–A16 A15–A8 A7–A0 (D7–D0) Fast Read 0Bh A23–A16 A15–A8 A7–A0 dummy (D7–D0) Fast Read Dual Output 3Bh A23–A16 A15–A8 A7–A0 dummy (D7–D0, …) (1) Fast Read Dual I/O BBh A23-A8(2) A7-A0, M7-M0 (2) (D7–D0, …) (1) Fast Read Quad Output 6Bh A23–A16 A15–A8 A7–A0 dummy (D7–D0, …) (3) Fast Read Quad I/O EBh A23-A0, M7-M0(4) (x,x,x,x, D7–D0, …) (5) (D7-D0, …) (3) Notes: 1: Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2: Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3: Quad Output Data 4: Quad Input Address IO0 = A20, A16, A12, A8 , A4, A0, M4, M0 IO1 = A21, A17, A13, A9 , A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5: Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0, …..) IO1 = (x, x, x, x, D5, D1, …..) IO2 = (x, x, x, x, D6, D2, …..) IO3 = (x, x, x, x, D7, D3, …..)

10.2.4 Write Enable (06h)

1. The WEL bit must be set prior to every Page Pr ogram, Sector Erase, Block Erase, Chip Erase and

instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high. Figure 4. Write Enable Instruction Sequence Diagram

10.2.5 Write Disable (04h)

Figure 5. Write Disable Instruction Sequence Diagram

10.2.6 Read Status Register-1 (05h) and Read Status Register-2 (35h)

SRP0, SRP1 and QE bits (see description of the Status Register earlier in this datasheet). continuously, as shown in Figure 6. The instruction is completed by driving /CS high. Figure 6. Read Status Register Instruction Sequence Diagram

10.2.7 Write Status Register (01h)

figure 7. The Status Register bits are shown in figure 3 and described earlier in this datasheet. bit locations are read-only and will not be affected by the Write Status Register instruction. Register will be cleared to 0. protection methods. Factory default for all status Register bits are 0. Figure 7. Write Status Register Instruction Sequence Diagram

10.2.8 Read Data (03h)

Electrical Characteristics). Figure 8. Read Data Instruction Sequence Diagram

10.2.9 Fast Read (0Bh)

data value on the DO pin is a “don’t care”. Figure 9. Fast Read Instruction Sequence Diagram

10.2.10 Fast Read Dual Output (3Bh)

segments to RAM for execution. Figure 10. Fast Read Dual Output Instruction Sequence Diagram

10.2.11 Fast Read Quad Output (6Bh)

W25Q80/16/32 at four times the rate of standard SPI devices. pins should be high-impedance prior to the falling edge of the first data out clock. Figure 11. Fast Read Quad Output Instruction Sequence Diagram

W25Q80, W25Q16, W25Q32 - 28 -

10.2.12 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from t he Dual SPI in some applications. To ensure optimum performance the High Performance Mode (HPM) instruction (A3h) must be executed once, prior to the Fast Read Dual I/O Instruction. The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the Mode bits (M7-0) after the input Address bits (A23-0), as shown in figure 12a. The upper nibble of the Mode (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the Mode bits (M7-0) equals “Ax” hex, then the next Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require the BBh instructi on code, as shown in figure 12b.. This reduces the instruction sequence by eight clocks and allows t he address to be immediately entered after /CS is asserted low. If the Mode bits (M7-0) are any value other than “Ax” hex, the next instruction (after /CS is raised and then lowered) requires the first byte instru ction code, thus returning to normal operation. A Mode Bit Reset instruction can be used to reset Mode Bits (M7-0) before issuing normal instructions (See 10.2.28 for detailed descriptions). Figure 12a. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh)

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 2 9 - P r e l i m i n a r y - R e v i s i o n B Figure 12b. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = Axh)

W25Q80, W25Q16, W25Q32 - 30 -

10.2.13 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO 0, IO1, IO2 and IO3 and four Dummy clock are required prior to the data output . The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (X IP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast read Quad I/O Instruction. To ensure optimum performance the High Performance Mode (H PM) instruction (A3h) must be executed once, prior to the Fast Read Quad I/O Instruction. The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the Mode bits (M7-0) after the input Address bits (A23-0), as shown in figure 13a. The upper nibble of the Mode (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the Mode bits (M7-0) equals “Ax” hex, then the nex t Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the EBh in struction code, as shown in figure 13b. This reduces the instruction sequence by eight clocks and allows the address to be immediately entered after /CS is asserted low. If the Mode bits (M7-0) ar e any value other than “Ax” hex, the next instruction (after /CS is raised and then lowered) requires the firs t byte instruction code, thus returning to normal operation. A Mode Bit Reset instruction can be used to reset Mode Bits (M7-0) before issuing normal instructions (See 10.2.28 for detailed descriptions). Figure 13a. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh)

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 3 1 - P r e l i m i n a r y - R e v i s i o n B Figure 13b. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = Axh)

10.2.14 Page Program (02h)

beginning of the page and overwrite previously sent data. protected by the Block Protect (BP2, BP1, and BP0) bits. Figure 14. Page Program Instruction Sequence Diagram

10.2.15 Quad Input Page Program (32h)

improve performance for PROM Programmer and applic ations that have slow clock speeds <5MHz. since the inherent page program time is much greater than the time it take to clock-in the data. Program instruction sequence is shown in figure 15. Figure 15. Quad Input Page Program Instruction Sequence Diagram

10.2.16 Sector Erase (20h)

Sector Erase instruction sequence is shown in figure 16. and BP0) bits (see Status Register Memory Protection table). Figure 16. Sector Erase Instruction Sequence Diagram

Block Erase instruction sequence is shown in figure 17. and BP0) bits (see Status Register Memory Protection table). Figure 17. 32KB Block Erase Instruction Sequence Diagram when SEC bit in Status Register is set to “1”.

Block Erase instruction sequence is shown in figure 18. and BP0) bits (see Status Register Memory Protection table). Figure 18. 64KB Block Erase Instruction Sequence Diagram when SEC bit in Status Register is set to “1”.

10.2.19 Chip Erase (C7h / 60h)

instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure 19. progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. Figure 19. Chip Erase Instruction Sequence Diagram

10.2.20 Erase Suspend (75h)

clear to 0 after Erase Suspend. Figure 20. Erase Suspend Instruction Sequence

10.2.21 Erase Resume (7Ah)

Figure 21. Erase Resume Instruction Sequence

10.2.22 Power-down (B9h)

“B9h” as shown in figure 22. Power-down / Device ID instruction, which restores the device to normal operation, will be recognized. with the standby current of ICC1. Figure 22. Deep Power-down Instruction Sequence Diagram

10.2.23 High Performance Mode (A3h)

(ABh) can be used to return to standard SPI standby current (Icc1). Figure 23. High Performance Mode Instruction Sequence

10.2.24 Release Power-down or High Performance Mode / Device ID (ABh)

or obtain the devices electronic identification (ID) number. by driving the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in figure 24. during the tRES1 time duration. figure 25. The Device ID values for the W25Q80, W25Q16, and W25Q32 are listed in Manufacturer and

10.2.25 Read Manufacturer / Device ID (90h)

read continuously, alternating from one to the other. The instruction is completed by driving /CS high. Figure 26. Read Manufacturer / Device ID Diagram

10.2.26 Read Unique ID Number(1)

dummy clocks. After which, the 64-bit ID is shifted out on the falling edge of CLK as shown in figure 27. Figure 27. Read Unique ID Number Instruction Sequence

1. For W25Q16, this feature is available upon special request. Please contact Winbond for details.

10.2.27 JEDEC ID (9Fh)

capacity values refer to Manufacturer and Device Identification table. Figure 28. Read JEDEC ID

10.2.28 Mode Bit Reset (FFh or FFFFh)

Fast Read Quad I/O for detail descriptions). recognized. The Mode Bits Reset instruction is shown in figure 29. Figure 29. Mode Bit Reset for Fast Read Dual/Quad I/O reset Mode Bit during Dual I/O operation, sixteen clocks are needed to shift in instruction “FFFFh”.

W25Q80, W25Q16, W25Q32 - 46 - 11. ELECTRICAL CHARACTERISTICS (PRELIMINARY) (4)

11.1 Absolute Maximum Ratings (1)

PARAMETERS SYMBOL CONDITIONS RANGE UNIT Supply Voltage VCC –0.6 to +4.0 V Voltage Applied to Any Pin V IO Relative to Ground –0.6 to VCC+0.4 V Transient Voltage on any Pin V IOT <20nS Transient Relative to Ground –2.0V to VCC+2.0V V Storage Temperature T STG –65 to +150 °C Lead Temperature T LEAD See Note (2) °C Electrostatic Discharge Voltage VESD Human Body Model (3) –2000 to +2000 V Notes: 1. This device has been designed and tested for t he specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maxi mum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage. 2. Compliant with JEDEC Standard J-STD-20C for sm all body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU. 3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms). 4. See preliminary designation at the end of this datasheet.

11.2 Operating Ranges

SPEC PARAMETER SYMBOL CONDITIONS MIN MAX UNIT Supply Voltage(1) VCC F R = 80MHz, fR = 50MHz 2.7 3.6 V Ambient Temperature, Operating TA Commercial Industrial –40 +70 +85 Note: 1. VCC voltage during Read can operate across the min and ma x range but should not exceed ±10% of the programming (erase/write) voltage.

11.3 Endurance and Data Retention

11.4 Power-up Timing and Write Inhibit Threshold

1. These parameters are characterized only.

Figure 30. Power-up Timing and Voltage Levels

W25Q80, W25Q16, W25Q32 - 48 -

11.5 DC Electrical Characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Input Capacitance C IN(1) V IN = 0V(2) 6 pF Output Capacitance Cout (1) V OUT = 0V(2) 8 pF Input Leakage I LI ±2 µA I/O Leakage I LO ±2 µA Standby Current I CC1 /CS = VCC, VIN = GND or VCC 25 50 µA Power-down Current I CC2 /CS = VCC, VIN = GND or VCC 1 5 µA High performance current I CC3 After enable High Performance mode 50 100 µA Current Read Data / Dual /Quad 1MHz (2) ICC4 C = 0.1 VCC / 0.9 VCC DO = Open 4/5/6 6/7.5/9 mA Current Read Data / Dual /Quad 33MHz (2) ICC4 C = 0.1 VCC / 0.9 VCC DO = Open 6/7/8 9/10.5/12 mA Current Read Data / Dual /Quad 50MHz (2) ICC4 C = 0.1 VCC / 0.9 VCC DO = Open Current Read Data / Dual Output Read/Quad Output Read 80MHz (2) ICC4 C = 0.1 VCC / 0.9 VCC DO = Open 10/11/12 15/16.5/18 mA Current Write Status Register I CC6 /CS = VCC 8 12 mA Current Page Program I CC7 /CS = VCC 20 25 mA Current Sector/Block Erase I CC8 /CS = VCC 20 25 mA Current Chip Erase I CC9 /CS = VCC 20 25 mA Input Low Voltage V IL –0.5 VCC x 0.3 V Input High Voltage V IH VCC x 0.7 VCC + 0.4 V Output Low Voltage V OL I OL = 1.6 mA 0.4 V Output High Voltage V OH I OH = –100 µA VCC – 0.2 V Notes: 1. Tested on sample basis and specified through design and characterization data. TA=25° C, VCC 3V. 2. Checker Board Pattern.

11.6 AC Measurement Conditions

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 31. AC Measurement I/O Waveform

W25Q80, W25Q16, W25Q32 - 50 -

11.7 AC Electrical Characteristics

for all instructions, except Read Data (03h) 2.7V-3.6V VCC & Industrial Temperature FR f C D.C. 80 MHz Clock freq. Read Data instruction (03h) f R D.C. 50 MHz Clock High, Low Time except Read Data (03h) tCLH, tCLL(1) 6/7 ns Clock High, Low Time for Read Data (03h) instruction tCRLH, tCRLL(1) 8 ns Clock Rise Time peak to peak t CLCH(2) 0.1 V/ns Clock Fall Time peak to peak t CHCL(2) 0.1 V/ns /CS Active Setup Time relative to CLK t SLCH t CSS 5 ns /CS Not Active Hold Time relative to CLK t CHSL 5 ns Data In Setup Time t DVCH t DSU 2 ns Data In Hold Time t CHDX t DH 5 ns /CS Active Hold Time relative to CLK t CHSH 5 ns /CS Not Active Setup Time relative to CLK t SHCH 5 ns /CS Deselect Time (for Array Read Æ Array Read / Erase or Program Æ Read Status Registers) tSHSL t CSH 10/5 0 ns Output Disable Time t SHQZ(2) tDIS 7 ns Clock Low to Output Valid tCLQV1 t V1 7 / 6 ns Clock Low to Output Valid (for Read ID instructions) tCLQV2 t V2 8.5 / 7.5 ns Output Hold Time t CLQX t HO 0 ns /HOLD Active Setup Time relative to CLK t HLCH 5 ns Continued – next page

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 5 1 - P r e l i m i n a r y - R e v i s i o n B

11.8 AC Electrical Characteristics ( cont’d)

/HOLD Active Hold Time relative to CLK t CHHH 5 ns /HOLD Not Active Setup Time relative to CLK t HHCH 5 ns /HOLD Not Active Hold Time relative to CLK t CHHL 5 ns /HOLD to Output Low-Z t HHQX(2) tLZ 7 ns /HOLD to Output High-Z t HLQZ(2) t HZ 12 ns Write Protect Setup Time Before /CS Low t WHSL(3) 20 ns Write Protect Hold Time After /CS High t SHWL(3) 100 ns /CS High to Power-down Mode t DP(2) 3 µs /CS High to Standby Mode without Electronic Signature Read tRES1(2) 3 µs /CS High to Standby Mode with Electronic Signature Read t RES2(2) 1.8 µs /CS High to next Instruction after Suspend t SUS(2) 20 µs Write Status Register Time t W 10 15 ms Byte Program Time (First Byte) (5) t BP1 30 50 µs Additional Byte Program Time (After First Byte) (5) tBP2 6 12 µs Page Program Time t PP 1.5 3 ms Sector Erase Time (4KB) t SE 120 200 ms Block Erase Time (32KB) t BE1 0.5 1 s Block Erase Time (64KB) t BE2 0.75 1.5 s Chip Erase Time W25Q80 Chip Erase Time W25Q16 Chip Erase Time W25Q32 t CE 12 s s s Notes: 1. Clock high + Clock low must be less than or equal to 1/f C. 2. Value guaranteed by design and/or characte rization, not 100% tested in production. 3. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1. 4. Commercial temperature only applies to Fast Read (F R0 & FR1). Industrial temperature applies to all other parameters. 5. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes programmed.

W25Q80, W25Q16, W25Q32 - 52 -

11.9 Serial Output Timing

11.10 Input Timing

11.11 Hold Timing

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 5 3 - P r e l i m i n a r y - R e v i s i o n B 12. PACKAGE SPECIFICATION 12.1 8-Pin SOIC 208-mil (Package Code SS) MILLIMETERS INCHES SYMBOL MIN MAX MIN MAX A 1.75 2.16 0.069 0.085 A1 0.05 0.25 0.002 0.010 A2 1.70 1.91 0.067 0.075 b 0.35 0.48 0.014 0.019 C 0.19 0.25 0.007 0.010 D 5.18 5.38 0.204 0.212 E 7.70 8.10 0.303 0.319 E1 5.18 5.38 0.204 0.212 e 1.27 BSC 0.050 BSC L 0.50 0.80 0.020 0.031 θ 0o 8 o 0 o 8 o Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within .0004 inches at the seating plane.

W25Q80, W25Q16, W25Q32 - 54 - 12.2 8-Pin PDIP 300-mil (Package Code DA) 1.631.470.0640.058 Symbol Min Nom Max Max NomMin Dimension in inch Dimension in mm A B c D e A L S A A E 0.060 1.52 0.175 4.45 0.010 0.125 0.016 0.130 0.018 0.135 0.022 3.18 0.41 0.25 3.30 0.46 3.43 0.56 0.008 0.120 0.375 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 9.53 e 0.360 0.380 9.14 9.65 01 5 0.045 1.14 0.3550.335 8.51 9.02 150 Seating Plane eA c E Base Plane1A L A S D B 8 5 1 4 α α

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 5 5 - P r e l i m i n a r y - R e v i s i o n B 12.3 8-contact 6x5 WSON (Package Code ZP)

W25Q80, W25Q16, W25Q32 - 56 - 12.4 8-contact 6x5 WSON Cont’d.

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 5 7 - P r e l i m i n a r y - R e v i s i o n B 12.5 16-Pin SOIC 300-mil (Package Code SF) MILLIMETERS INCHES SYMBOL MIN MAX MIN MAX A 2.36 2.64 0.093 0.104 A1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 C 0.18 0.28 0.007 0.011 D(3) 10.08 10.49 0.397 0.413 E 10.01 10.64 0.394 0.419 E1(3) 7.39 7.59 0.291 0.299 e(2) 1.27 BSC 0.050 BSC L 0.39 1.27 0.015 0.050 θ 0o 8 o 0 o 8 o Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.

W25Q80, W25Q16, W25Q32 - 58 - 13. ORDERING INFORMATION (1) Notes: 1a. Only the 2 nd letter is used for the part marking. 1b. Standard bulk shipments are in Tube (shape E). Please s pecify alternate packing method, such as Tape and Reel (shape T), when placing orders. 1c. The “W” prefix is not included on the part marking.

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 5 9 - P r e l i m i n a r y - R e v i s i o n B

13.1 Valid Part Numbers and Top Side Marking

The following table provides the valid part number s for the 25Q80/16/32 SpiFlash Memories. Please contact Winbond for specific availability by densit y and package type. Winbond SpiFlash memories use an 11-digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 9-digit number. PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING 8M-bit W25Q80VSSIG 25Q80VSIG 16M-bit W25Q16VSSIG 25Q16VSIG SS SOIC-8 208mil 32M-bit W25Q32VSSIG 25Q32VSIG 16M-bit W25Q16VSFIG 25Q16VFIG SF SOIC-16 300mil 32M-bit W25Q32VSFIG 25Q32VFIG 8M-bit W25Q80VZPIG 25Q80VPIG ZP WSON-8 6x5mm 16M-bit W25Q16VZPIG 25Q16VPIG

W25Q80, W25Q16, W25Q32 - 60 - 14. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A 10/20/06 New Create Advanced A1 11/9/06 Various Figures 2, 3A-B, 13A–14C, 16, 24, 25 Table 10.2.2: Write Status Reg 1 and 2 Erase Suspend 10.2.21 tCHSH, tSHCH = 5nS A2 11/15/06 49 tSHSL = 10ns for Read & 50ns for Write, Erase and Program instructions A3 2/22/07 20, 45, 49 & 57 Removed Burst Read Quad I/O Instruction. Updated ordering Information. Added transient voltage specification. A4 4/20/07 19, 28, 30 & 45 Added Mode Bi t Reset instruction and description. A5 6/20/07 13, 15-17 & 23 Added note for SRP1,0 status during Power Lock- Down protection. Updated Status Register memory protection tables. B 9/26/07 5, 11, 13, 15-17, 19, 35, 36, 43, 45-47, 50 & 59 Updated Instruction Diagrams. Updated Status Register memory protection tables. Added note for Power Lock-Down, OTP functions. Added note for 64 Bit unique ID. Added note for 32KB/64KB block erase command. Updated Mode Bit Reset command description. Updated data retention temperature. Updated tSHSL description, added tCLQV2. Updated tBP1. Preliminary Designation The “Preliminary” designation on a Winbond SpiFlash memory datasheet indicates that the product is not fully characterized. The specifications are subject to change and are not guaranteed. Winbond or an authorized sales representative should be consulted for current information before using this product. Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner.

W25Q80, W25Q16, W25Q32 Publication Release Date: September 26, 2007 - 6 1 - P r e l i m i n a r y - R e v i s i o n B Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical im plantation, atomic energy control instruments, airplane or spaceship instruments, transporta tion instruments, traffic signal instruments, combustion control instruments, or for other a pplications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.