25Q128FVSQ

W25Q128FV_V01 WINBOND | Alldatasheet

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Technical content

Publication Release Date: May 13, 2016 Revision M 3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

• 1 - Table of Contents

Publication Release Date: May 13, 2016 - 2 - Revision M

• 3 -

Publication Release Date: May 13, 2016 - 4 - Revision M

• 5 - 1. GENERAL DESCRIPTIONS The W25Q128FV (128M -bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from D ual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power -down. All devices are offered in space - saving packages. The W25Q128FV array is organized into 65,536 programmable pages of 256 -bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128FV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.) The W25Q128FV support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2-clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast R ead Dual/Quad I/O and QPI instructions. These transfer rates can outperform standard Asynchronous 8 and 16 -bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8 -clocks of instruction -overhead to read a 24 -bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protect ion, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufact urer and device ID and SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers. 2. FEATURES  New Family of SpiFlash Memories – W25Q128FV: 128M-bit / 16M-byte – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 – QPI: CLK, /CS, IO0, IO1, IO2, IO3 – Software & Hardware Reset  Highest Performance Serial Flash – 104MHz Single, Dual/Quad SPI clocks – 208/416MHz equivalent Dual/Quad SPI – 50MB/S continuous data transfer rate – More than 100,000 erase/program cycles – More than 20-year data retention  Efficient “Continuous Read” and QPI Mode – Continuous Read with 8/16/32/64-Byte Wrap – As few as 8 clocks to address memory – Quad Peripheral Interface (QPI) reduces instruction overhead – Allows true XIP (execute in place) operation – Outperforms X16 Parallel Flash  Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply – 4mA active current, <1µA Power-down (typ.) – -40°C to +85°C operating range  Flexible Architecture with 4KB sectors – Uniform Sector/Block Erase (4K/32K/64K-Byte) – Program 1 to 256 byte per programmable page – Erase/Program Suspend & Resume  Advanced Security Features – Software and Hardware Write-Protect – Power Supply Lock-Down and OTP protection – Top/Bottom, Complement array protection – Individual Block/Sector array protection – 64-Bit Unique ID for each device – Discoverable Parameters (SFDP) Register – 3X256-Bytes Security Registers with OTP locks – Volatile & Non-volatile Status Register Bits  Space Efficient Packaging – 8-pin SOIC / VSOP 208-mil – 8-pin PDIP 300-mil – 8-pad WSON 6x5-mm / 8x6-mm – 16-pin SOIC 300-mil (additional /RESET pin) – 24-ball TFBGA 8x6-mm – Contact Winbond for KGD and other options

Publication Release Date: May 13, 2016 - 6 - Revision M 3. PACKAGE TYPES AND PIN CONFIGURATIONS

3.1 Pin Configuration SOIC / VSOP 208-mil

/CS DO (IO1) /WP (IO2) GND VCC /HOLD or /RESET (IO3) DI (IO0) CLK Top View Figure 1a. W25Q128FV Pin Assignments, 8-pin SOIC / VSOP 208-mil (Package Code S, T)

3.2 Pad Configuration WSON 6x5-mm / 8x6-mm

/CS DO (IO1) /WP (IO2) GND VCC /HOLD or /RESET (IO3) DI (IO0) CLK Top View Figure 1b. W25Q128FV Pad Assignments, 8-pad WSON 6x5-mm / 8x6-mm (Package Code P, E)

3.3 Pin Description SOIC / VSOP 208-mil, WSON 6x5-mm / 8x6-mm

PIN NO. PIN NAME I/O FUNCTION 1 /CS I Chip Select Input

2 DO (IO1) I/O Data Output (Data Input Output 1)(1)

3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)(2)

4 GND Ground

5 DI (IO0) I/O Data Input (Data Input Output 0)(1)

6 CLK I Serial Clock Input

/RESET (IO3) I/O Hold or Reset Input (Data Input Output 3)(2)

8 VCC Power Supply

Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.

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3.4 Pin Configuration SOIC 300-mil

/CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) DI (IO0) CLK Top View NC /RESET NC NC NC NC NC NC5 Figure 1c. W25Q128FV Pin Assignments, 16-pin SOIC 300-mil (Package Code F)

3.5 Pin Description SOIC 300-mil

PIN NO. PIN NAME I/O FUNCTION 1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)(2)

2 VCC Power Supply

3 /RESET I Reset Input(3)

4 N/C No Connect

5 N/C No Connect

6 N/C No Connect

8 DO (IO1) I/O Data Output (Data Input Output 1)(1)

9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)(2)

10 GND Ground

11 N/C No Connect

12 N/C No Connect

13 N/C No Connect

14 N/C No Connect

15 DI (IO0) I/O Data Input (Data Input Output 0)(1)

16 CLK I Serial Clock Input

Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI. 3. The /RESET pin on SOIC-16 package is independent of the HOLD/RST bit and QE bit settings in the Status Register. This pin can be treated as ‘No Connect’ in the system if RESET function is not needed

Publication Release Date: May 13, 2016 - 8 - Revision M

3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)

/HOLD(IO3) /RESETDI(IO0)DO(IO1) /WP (IO2) D2 D3 D4 NC NCNCNC E2 E3 E4 NC NCNCNC F2 F3 F4 NC NCNCNC A2 A3 A4 NC VCCGNDCLK B2 B3 B4 NC NC/CS C2 C3 C4 NC Top View Package Code C /HOLD(IO3) /RESETDI(IO0)DO(IO1) /WP (IO2) D2 D3 D4 NC NCNCNC E2 E3 E4 NC NCNCNC A2 A3 A4 NC VCCGNDCLK B2 B3 B4 NC NC/CS C2 C3 C4 NC Top View Package Code B NC NC NC NC Figure 1d. W25Q128FV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code B & C)

3.7 Ball Description TFBGA 8x6-mm

NO. PIN NAME I/O FUNCTION B2 CLK I Serial Clock Input B3 GND Ground B4 VCC Power Supply C2 /CS I Chip Select Input C4 /WP (IO2) I/O Write Protect Input (Data Input Output 2)(2) D2 DO (IO1) I/O Data Output (Data Input Output 1)(1) D3 DI (IO0) I/O Data Input (Data Input Output 0)(1) /HOLD or /RESET (IO3) I/O Hold or Reset Input (Data Input Output 3)(2) Multiple NC No Connect Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.

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3.8 Pin Configuration PDIP 300-mil

/CS DO (IO1) /WP (IO2) GND VCC /HOLD or /RESET (IO3) DI (IO0) CLK Top View Figure 1e. W25Q128FV Pin Assignments, 8-pin PDIP (Package Code A)

3.9 Pin Description PDIP 300-mil

PIN NO. PIN NAME I/O FUNCTION 1 /CS I Chip Select Input 3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)(2) /HOLD or /RESET (IO3) I/O Hold or Reset Input (Data Input Output 3)(2) Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.

Publication Release Date: May 13, 2016 - 10 - Revision M 4. PIN DESCRIPTIONS

4.1 Chip Select (/CS)

The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure 58). If needed a pull-up resister on the /CS pin can be used to accomplish this.

4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)

The W25Q128FV sup ports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also u ses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK an d read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non -volatile Quad Enable bit (QE) in Status Register -2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

4.3 Write Protect (/WP)

The Wr ite Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sect or or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register -2 is set for Quad I/O, the /WP pin function is not available since this pin is used for IO2. See Figure 1a -c for the pin configuration of Quad I/O operation.

4.4 HOLD (/HOLD)

The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register -2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See Figure 1a-c for the pin configuration of Quad I/O operation.

4.5 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations")

4.6 Reset (/RESET)

The /RESET pin allows the device to be reset by the controller. For 8 -pin packages, when QE=0, the IO3 pin can be configured either as a /HOLD pin or as a /RESET pin depending on Status Register setting. When QE=1, the /HOLD or /RESET function is not available for 8 -pin configuration. On the 16 - pin SOIC package, a dedicated /RESET pin is provided and it is independent of QE bit setting.

Figure 2. W25Q128FV Serial Flash Memory Block Diagram

• Sector 0 (4KB) • xx0000h xx00FFh xx1F00h xx1FFFh
• Sector 1 (4KB) • xx1000h xx10FFh xx2F00h xx2FFFh
• Sector 2 (4KB) • xx2000h xx20FFh xxDF00h xxDFFFh
• Sector 13 (4KB) • xxD000h xxD0FFh xxEF00h xxEFFFh
• Sector 14 (4KB) • xxE000h xxE0FFh xxFF00h xxFFFFh
• Sector 15 (4KB) • xxF000h xxF0FFh Block Segmentation Data Security Register 1 - 3 Write Protect Logic and Row Decode 000000h 0000FFh SFDP Register 00FF00h 00FFFFh
• Block 0 (64KB) • 000000h 0000FFh 3FFF00h 3FFFFFh
• Block 63 (64KB) • 3F0000h 3F00FFh 40FF00h 40FFFFh
• Block 64 (64KB) • 400000h 4000FFh 7FFF00h 7FFFFFh
• Block 127 (64KB) • 7F0000h 7F00FFh 80FF00h 80FFFFh
• Block 128 (64KB) • 800000h 8000FFh FFFF00h FFFFFFh
• Block 255 (64KB) • FF0000h FF00FFh

6.1 SPI / QPI Operations

Figure 3. W25Q128FV Serial Flash Memory Operation Diagram

6.1.1 Standard SPI Instructions

CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.

6.1.2 Dual SPI Instructions

pins become bidirectional I/O pins: IO0 and IO1.

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6.1.3 Quad SPI Instructions

The W25Q128FV supports Quad SPI operation when using instructions such as “Fast Read Quad Output (6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O (E3h)”. These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code -shadowing to RAM or execution directly from the SPI bus (XIP) . When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non - volatile Quad Enable bit (QE) in Status Register-2 to be set.

6.1.4 QPI Instructions

The W25Q128FV supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI protocol requires that the byte -long instruction code being shifted into the device only via DI pin in eight serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks are required. This can significan tly reduce the SPI instruction overhead and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are use d to switch between these two modes. Upon power -up or after a software reset using “Reset (99h)” instruction, the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non -volatile Quad Enable bit (QE) in Status Register -2 is required to be set. When using QPI instructions, the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. See Figure 3 for the device operation modes.

6.1.5 Hold Function

For Standard SPI and Dual SPI opera tions, the /HOLD signal allows the W25Q128FV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is avail able again. The /HOLD function is only available for standard SPI and Dual SPI operation, not during Quad SPI or QPI. The Quad Enable Bit QE in Status Register -2 is used to determine if the pin is used as /HOLD pin or data I/O pin. When QE=0 (factory defau lt), the pin is /HOLD, when QE=1, the pin will become an I/O pin, /HOLD function is no longer available. To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not al ready low the /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device.

Publication Release Date: May 13, 2016 - 14 - Revision M

6.1.6 Software Reset & Hardware /RESET pin

The W25Q128FV can be reset to the initial power -on state by a software Reset sequence, either in SPI mode or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset (99h). If the command sequence is successfully accepted, the device will take approximately 30uS (tRST) to reset. No command will be accepted during the reset period. For the WSON-8 and TFBGA package types, W25Q128FV can also be configured to utilize a hardware /RESET pin. The HOLD/RST bit in the Status Register -3 is the configuration bit for /HOLD pin function or RESET pin function. When HOLD/RST=0 (facto ry default), the pin acts as a /HOLD pin as described above; when HOLD/RST=1, the pin acts as a /RESET pin. Drive the /RESET pin low for a minimum period of ~1us (tRESET*) will reset the device to its initial power -on state. Any on-going Program/Erase operation will be interrupted and data corruption may happen. While /RESET is low, the device will not accept any command input. If QE bit is set to 1, the /HOLD or /RESET function will be disabled, the pin will become one of the four data I/O pins. For the S OIC-16 package, W25Q128FV provides a dedicated /RESET pin in addition to the /HOLD (IO3) pin as illustrated in Figure 1b. Drive the /RESET pin low for a minimum period of ~1us (tRESET*) will reset the device to its initial power -on state. The HOLD/RST bit or QE bit in the Status Register will not affect the function of this dedicated /RESET pin. Hardware /RESET pin has the highest priority among all the input signals. Drive /RESET low for a minimum period of ~1us (tRESET*) will interrupt any on -going external/internal operations, regardless the status of other SPI signals (/CS, CLK, IOs, /WP and/or /HOLD). Note: 1. While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended to ensure reliable operation. 2. There is an internal pull-up resistor for the dedicated /RESET pin on the SOIC -16 package. If the reset function is not needed, this pin can be left floating in the system.

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6.2 Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the W25Q128FV provides several means to protect the data from inadvertent writes.

6.2.1 Write Protect Features

 Device resets when VCC is below threshold  Time delay write disable after Power-up  Write enable/disable instructions and automatic write disable after erase or program  Software and Hardware (/WP pin) write protection using Status Registers  Additional Individual Block/Sector Locks for array protection  Write Protection using Power-down instruction  Lock Down write protection for Status Register until the next power-up  One Time Program (OTP) write protection for array and Security Registers using Status Register* * Note: This feature is available upon special order. Please contact Winbond for details. Upon power-up or at power -down, the W25Q128FV will maintain a reset condition while VCC is below the threshold value of V WI, (See Power -up Timing and Voltage Levels and Figure 43). While reset, all operations are disabled and no instructions are recognized. During power -up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of t PUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached, and it must also track the VCC supply level at power-down to prevent adverse command sequence. If needed a pull -up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Writ e Enable Latch (WEL) is automatically cleared to a write-disabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP 0, SRP1 ) and Block Protect (CMP , SEC, TB, BP[2:0]) bits. These settings allow a portion or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status R egister section for further information. Additionally, the Power -down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction. The W25Q128FV also provides another Write Protect met hod using the Individual Block Locks. Each 64KB block (except the top and bottom blocks, total of 510 blocks) and each 4KB sector within the top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or Program commands issued to the corresponding sector or block will be ignored. When the device is powered on, all Individual Block Lock bits will be 1, so th e entire memory array is protected from Erase/Program. An “Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector or block. The WPS bit in Status Register -3 is used to decide which Write Protect scheme should be used. When WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas of the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.

Publication Release Date: May 13, 2016 - 16 - Revision M 7. STATUS AND CONFIGURATION REGISTERS Three Status a nd Configuration Registers are provided for W25Q128FV. The Read Status Register - 1/2/3 instructions can be used to provide status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, Erase/Program Suspend status, output driver strength, power -up and current Address Mode. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting, Security Register OTP locks, Hold/Reset functions, output driver strength and power- up Address Mode. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP 0, SRP1 ), the Write Enable instructi on, and during Standard/Dual SPI operations, the /WP pin.

7.1 Status Registers

SRP0 SEC TB BP2 BP1 BP0 WEL BUSY Status Register Protect 0 (Volatile/Non-Volatile Writable) Top/Bottom Protect Bit (Volatile/Non-Volatile Writable) Block Protect Bits (Volatile/Non-Volatile Writable) Write Enable Latch (Status-Only) Erase/Write In Progress (Status-Only) Sector Protect Bit (Volatile/Non-Volatile Writable) Figure 4a. Status Register-1

7.1.1 Erase/Write In Progress (BUSY) – Status Only

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is execu ting a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/ Program Suspend instruction (see t W, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status/security register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.

7.1.2 Write Enable Latch (WEL) – Status Only

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power -up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register.

7.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable

The Block Protect Bits (BP2, BP1, BP0) are non -volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set u sing the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can

• 17 - be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected.

7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits.

7.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable

The non -volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0.

7.1.6 Complement Protect (CMP) – Volatile/Non-Volatile Writable

The Complement Protect bit (CMP) is a non -volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when CMP=1, the top 64KB block will become unprotected while the rest of the array become read -only. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0.

7.1.7 Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable

The Status Register Protect bits (SRP 1 and SRP0 ) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. SRP1 SRP0 /WP Status Register Description 0 0 X Software Protection /WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default] 0 1 0 Hardware Protected When /WP pin is low the Status Register locked and cannot be written to. 0 1 1 Hardware Unprotected When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. 1 0 X Power Supply Lock-Down Status Register is protected and cannot be written to again until the next power-down, power-up cycle.(1) 1 1 X One Time Program(2) Status Register is permanently protected and cannot be written to. Notes: 1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available upon special order. Please contact Winbond for details.

Publication Release Date: May 13, 2016 - 18 - Revision M S15 S14 S13 S12 S11 S10 S9 S8 SUS CMP LB3 LB2 LB1 (R) QE SRP1 Status Register Protect 1 (Volatile/Non-Volatile Writable) Complement Protect (Volatile/Non-Volatile Writable) Security Register Lock Bits (Volatile/Non-Volatile OTP Writable) Reserved Quad Enable (Volatile/Non-Volatile Writable) Suspend Status (Status-Only) Figure 4b. Status Register-2

7.1.8 Erase/Program Suspend Status (SUS) – Status Only

The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle.

7.1.9 Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable

The Security Register Lock Bits (LB3, LB2, LB1) are non -volatile One Time Program (OTP) bits in Status Register (S13, S12, S11) that provide the write protect control and statu s to the Security Registers. The default state of LB3 -1 is 0, Security Registers are unlocked. LB3 -1 can be set to 1 individually using the Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the corresponding 256-Byte Security Register will become read-only permanently.

7.1.10 Quad Enable (QE) – Volatile/Non-Volatile Writable

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI and QPI operation . When the QE bit is set to a 0 state (factory default for part number with ordering options “IG”,”IP” and “IF”), the /WP pin and /HOLD are enabled . When the QE bit is set to a 1 (factory default for Quad Enabled part numbers with ordering option “IQ”), the Quad IO2 and IO3 pins a re enabled, and /WP and /HOLD functions are disabled. QE bit is required to be set to a 1 before issuing an “Enter QPI (38h)” to switch the device from Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI mode, QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE bit from a “1” to a “0”. WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during standard SPI or Dual SPI operation, the QE bit should never be set to a 1.

• 19 - S23 S22 S21 S20 S19 S18 S17 S16 HOLD /RST DRV1 DRV0 (R) (R) WPS Output Driver Strength (Volatile/Non-Volatile Writable) Reserved Write Protect Selection (Volatile/Non-Volatile Writable) /HOLD or /RESET Function (Volatile/Non-Volatile Writable) (R) (R) Reserved Figure 4c. Status Register-3

7.1.11 Write Protect Selection (WPS) – Volatile/Non-Volatile Writable

The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will use the combination of CMP, SEC, TB, BP[2:0] bits to protect a specific area of the memory array. When WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The default value for all Individual Block Lock bits is 1 upon device power on or after reset.

7.1.12 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable

The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations. DRV1, DRV0 Driver Strength 0, 0 100% 0, 1 75% 1, 0 50% 1, 1 25% (default) 7.1.13 /HOLD or /RESET Pin Function (HOLD/RST) – Volatile/Non-Volatile Writable The HOLD/RST bit is used to determine whether /HOLD or /RESET function should be implemented on the hardware pin for 8 -pin packages. When HOLD/RST=0 (factory default), the pin acts as /HOL D; when HOLD/RST=1, the pin acts as /RESET. However, /HOLD or /RESET functions are only available when QE=0. If QE is set to 1, the /HOLD and /RESET functions are disabled, the pin acts as a dedicated data I/O pin.

Publication Release Date: May 13, 2016 - 20 - Revision M

7.1.14 Reserved Bits – Non Functional

There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be written as “0”, but there will not be any effects.

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7.1.15 W25Q128FV Status Register Memory Protection (WPS = 0, CMP = 0)

STATUS REGISTER(1) W25Q128FV (128M-BIT) MEMORY PROTECTION(3) SEC TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED DENSITY PROTECTED PORTION(2) X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 252 thru 255 FC0000h – FFFFFFh 256KB Upper 1/64 0 0 0 1 0 248 thru 255 F80000h – FFFFFFh 512KB Upper 1/32 0 0 0 1 1 240 thru 255 F00000h – FFFFFFh 1MB Upper 1/16 0 0 1 0 0 224 thru 255 E00000h – FFFFFFh 2MB Upper 1/8 0 0 1 0 1 192 thru 255 C00000h – FFFFFFh 4MB Upper 1/4 0 0 1 1 0 128 thru 255 800000h – FFFFFFh 8MB Upper 1/2 0 1 0 0 1 0 thru 3 000000h – 03FFFFh 256KB Lower 1/64 0 1 0 1 0 0 thru 7 000000h – 07FFFFh 512KB Lower 1/32 0 1 0 1 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/16 0 1 1 0 0 0 thru 31 000000h – 1FFFFFh 2MB Lower 1/8 0 1 1 0 1 0 thru 63 000000h – 3FFFFFh 4MB Lower 1/4 0 1 1 1 0 0 thru 127 000000h – 7FFFFFh 8MB Lower 1/2 X X 1 1 1 0 thru 255 000000h – FFFFFFh 16MB ALL 1 0 0 0 1 255 FFF000h – FFFFFFh 4KB U - 1/4096 1 0 0 1 0 255 FFE000h – FFFFFFh 8KB U - 1/2048 1 0 0 1 1 255 FFC000h – FFFFFFh 16KB U - 1/1024 1 0 1 0 X 255 FF8000h – FFFFFFh 32KB U - 1/512 1 1 0 0 1 0 000000h – 000FFFh 4KB L - 1/4096 1 1 0 1 0 0 000000h – 001FFFh 8KB L - 1/2048 1 1 0 1 1 0 000000h – 003FFFh 16KB L - 1/1024 1 1 1 0 X 0 000000h – 007FFFh 32KB L - 1/512 Notes: 1. X = don’t care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored

Publication Release Date: May 13, 2016 - 22 - Revision M

7.1.16 W25Q128FV Status Register Memory Protection (WPS = 0, CMP = 1)

STATUS REGISTER(1) W25Q128FV (128M-BIT) MEMORY PROTECTION(3) SEC TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED DENSITY PROTECTED PORTION(2) X X 0 0 0 0 thru 255 000000h - FFFFFFh 16MB ALL 0 0 0 0 1 0 thru 251 000000h - FBFFFFh 16,128KB Lower 63/64 0 0 0 1 0 0 thru 247 000000h – F7FFFFh 15,872KB Lower 31/32 0 0 0 1 1 0 thru 239 000000h - EFFFFFh 15MB Lower 15/16 0 0 1 0 0 0 thru 223 000000h - DFFFFFh 14MB Lower 7/8 0 0 1 0 1 0 thru 191 000000h - BFFFFFh 12MB Lower 3/4 0 0 1 1 0 0 thru 127 000000h - 7FFFFFh 8MB Lower 1/2 0 1 0 0 1 4 thru 255 040000h - FFFFFFh 16,128KB Upper 63/64 0 1 0 1 0 8 thru 255 080000h - FFFFFFh 15,872KB Upper 31/32 0 1 0 1 1 16 thru 255 100000h - FFFFFFh 15MB Upper 15/16 0 1 1 0 0 32 thru 255 200000h - FFFFFFh 14MB Upper 7/8 0 1 1 0 1 64 thru 255 400000h - FFFFFFh 12MB Upper 3/4 0 1 1 1 0 128 thru 255 800000h - FFFFFFh 8MB Upper 1/2 X X 1 1 1 NONE NONE NONE NONE 1 0 0 0 1 0 thru 255 000000h – FFEFFFh 16,380KB L - 4095/4096 1 0 0 1 0 0 thru 255 000000h – FFDFFFh 16,376KB L - 2047/2048 1 0 0 1 1 0 thru 255 000000h – FFBFFFh 16,368KB L - 1023/1024 1 0 1 0 X 0 thru 255 000000h – FF7FFFh 16,352KB L - 511/512 1 1 0 0 1 0 thru 255 001000h – FFFFFFh 16,380KB U - 4095/4096 1 1 0 1 0 0 thru 255 002000h – FFFFFFh 16,376KB U - 2047/2048 1 1 0 1 1 0 thru 255 004000h – FFFFFFh 16,368KB U -1023/1024 1 1 1 0 X 0 thru 255 008000h – FFFFFFh 16,352KB U - 511/512 Notes: 1. X = don’t care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored

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7.1.17 W25Q128FV Individual Block Memory Protection (WPS=1)

Sector 0 (4KB) Sector 1 (4KB) Sector 14 (4KB) Sector 15 (4KB) Block 1 (64KB) Block 254 (64KB) Sector 0 (4KB) Sector 1 (4KB) Sector 14 (4KB) Sector 15 (4KB) Block 0 (64KB) Block 255 (64KB) Individual Block Locks:

32 Sectors (Top/Bottom)

254 Blocks

Individual Block Lock: 36h + Address Individual Block Unlock: 39h + Address Read Block Lock: 3Dh + Address Global Block Lock: 7Eh Global Block Unlock: 98h Figure 4d. Individual Block/Sector Locks Notes: 1.Individual Block/Sector protection is only valid when WPS=1. 2.All individual block/sector lock bits are set to 1 by default after power up, all memory array is protected.

Publication Release Date: May 13, 2016 - 24 - Revision M 8. INSTRUCTIONS The Standard/Dual/Quad SPI instruction set of the W25Q128FV consists of 45 basic instr uctions that are fully controlled through the SPI bus (see Instruction Set Table1 -2). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. The QPI instruction set of the W25Q128FV consists of 32 basic instructions that are fully controlled through the SPI bus (see Instruction Set Table 3). Instructions are initiat ed with the falling edge of Chip Select (/CS). The first byte of data clocked through IO[3:0] pins provides the instruction code. Data on all four IO pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI instructions, addresses, data and dummy bytes are using all four IO pins to transfer every byte of data with every two serial clocks (CLK). Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don ’t care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 5 through 57. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed.

8.1 Device ID and Instruction Set Tables

8.1.1 Manufacturer and Device Identification

MANUFACTURER ID (MF7 - MF0) Winbond Serial Flash EFh Device ID (ID7 - ID0) (ID15 - ID0) Instruction ABh, 90h, 92h, 94h 9Fh W25Q128FV (SPI Mode) 17h 4018h W25Q128FV (QPI Mode) 17h 6018h

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8.1.2 Instruction Set Table 1 (Standard/Dual/Quad SPI Instructions)(1)

Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Write Enable 06h Volatile SR Write Enable 50h Write Disable 04h Read Status Register-1 05h (S7-S0)(2) Write Status Register-1(4) 01h (S7-S0)(4) Read Status Register-2 35h (S15-S8)(2) Write Status Register-2 31h (S15-S8) Read Status Register-3 15h (S23-S16)(2) Write Status Register-3 11h (S23-S16) Chip Erase C7h/6 Erase / Program Suspend 75h Erase / Program Resume 7Ah Power-down B9h Release Power-down / ID ABh Dummy Dummy Dummy (ID7-ID0)(2) Manufacturer/Device ID 90h Dummy Dummy 00h (MF7-MF0) (ID7-ID0) JEDEC ID 9Fh (MF7-MF0) (ID15-ID8) (ID7-ID0) Global Block Lock 7Eh Global Block Unlock 98h Enter QPI Mode 38h Enable Reset 66h Reset Device 99h

Publication Release Date: May 13, 2016 - 26 - Revision M

8.1.3 Instruction Set Table 2 (Standard/Dual/Quad SPI Instructions)(1)

Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Read Unique ID 4Bh Dummy Dummy Dummy Dummy (UID63-UID0) Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3) Quad Page Program 32h A23-A16 A15-A8 A7-A0 D7-D0, …(9) D7-D0, …(3) Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0 Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0 Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0 Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read 0Bh A23-A16 A15-A8 A7-A0 Dummy (D7-D0) Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 Dummy (D7-D0, …)(7) Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 Dummy (D7-D0, …)(9) Read SFDP Register 5Ah A23-A16 A15-A8 A7-A0 Dummy (D7-D0) Erase Security Register(5) 44h A23-A16 A15-A8 A7-A0 Program Security Register(5) 42h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3) Read Security Register(5) 48h A23-A16 A15-A8 A7-A0 Dummy (D7-D0) Individual Block Lock 36h A23-A16 A15-A8 A7-A0 Individual Block Unlock 39h A23-A16 A15-A8 A7-A0 Read Block Lock 3Dh A23-A16 A15-A8 A7-A0 (L7-L0) Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Fast Read Dual I/O BBh A23-A16 A15-A8 A7-A0 Dummy (D7-D0) Mftr./Device ID Dual I/O 92h A23-A16 A15-A8 A7-A0 Dummy (MF7-MF0) (ID7-ID0) Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Byte 8 Byte 9 (18, 19) (20, 21) (22, 23) Set Burst with Wrap 77h Dummy Dummy Dummy W8-W0 Fast Read Quad I/O EBh A23-A16 A15-A8 A7-A0 M7-M0 Dummy Dummy (D7-D0) (D7-D0) Word Read Quad I/O(12) E7h A23-A16 A15-A8 A7-A0 M7-M0 Dummy (D7-D0) (D7-D0) (D7-D0) Octal Word Read Quad I/O(13) E3h A23-A16 A15-A8 A7-A0 M7-M0 (D7-D0) (D7-D0) (D7-D0) (D7-D0) Mftr./Device ID Quad I/O 94h A23-A16 A15-A8 A7-A0 M7-M0 Dummy Dummy (MF7-MF0) (ID7-ID0)

• 27 -

8.1.4 Instruction Set Table 3 (QPI Instructions)(14)

Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Write Enable 06h Volatile SR Write Enable 50h Write Disable 04h Read Status Register-1 05h (S7-S0)(2) Write Status Register-1(4) 01h (S7-S0)(4) Read Status Register-2 35h (S15-S8)(2) Write Status Register-2 31h (S15-S8) Read Status Register-3 15h (S23-S16)(2) Write Status Register-3 11h (S23-S16) Chip Erase C7h/60h Erase / Program Suspend 75h Erase / Program Resume 7Ah Power-down B9h Set Read Parameters C0h P7-P0 Release Powerdown / ID ABh Dummy Dummy Dummy (ID7-ID0)(2) Manufacturer/Device ID 90h Dummy Dummy 00h (MF7-MF0) (ID7-ID0) JEDEC ID 9Fh (MF7-MF0) (ID15-ID8) (ID7-ID0) Global Block Lock 7Eh Global Block Unlock 98h Exit QPI Mode FFh Enable Reset 66h Reset Device 99h Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0(9) D7-D0(3) Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0 Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0 Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0 Fast Read 0Bh A23-A16 A15-A8 A7-A0 Dummy(13) (D7-D0) Burst Read with Wrap(14) 0Ch A23-A16 A15-A8 A7-A0 Dummy(13) (D7-D0) Fast Read Quad I/O EBh A23-A16 A15-A8 A7-A0 M7-M0(13) (D7-D0) Individual Block Lock 36h A23-A16 A15-A8 A7-A0 Individual Block Unlock 39h A23-A16 A15-A8 A7-A0 Read Block Lock 3Dh A23-A16 A15-A8 A7-A0 (L7-L0)

Publication Release Date: May 13, 2016 - 28 - Revision M Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data output from the device on either 1, 2 or 4 IO pins. 2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction. 3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. 4. Write Status Register-1 (01h) can also be used to program Status Register -1&2, see section 8.2.5. 5. Security Register Address: Security Register 1: A23 -16 = 00h; A15 -8 = 10h; A7 -0 = byte address Security Register 2: A23 -16 = 00h; A15 -8 = 20h; A7 -0 = byte address Security Register 3: A23 -16 = 00h; A15 -8 = 30h; A7 -0 = byte address 6. Dual SPI address input format: IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M 2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 7. Dual SPI data output format: IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 8. Quad SPI address input format: Set Burst with Wrap input format: IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO2 = x, x, x, x, x, x, W6, x IO3 = A23, A19, A15, A11, A7, A3, M7, M3 IO3 = x, x, x, x, x, x, x, x 9. Quad SPI data input/output format: 10. Fast Read Quad I/O data output format: IO0 = (x, x, x, x, D4, D0, D4, D0) IO1 = (x, x, x, x, D5, D1, D5, D1) IO2 = (x, x, x, x, D6, D2, D6, D2) IO3 = (x, x, x, x, D7, D3, D7, D3) 11. Word Read Quad I/O data output format: IO0 = (x, x, D4, D0, D4, D0, D4, D0) IO1 = (x, x, D5, D1, D5, D1, D5, D1) IO2 = (x, x, D6, D2, D6, D2, D6, D2) IO3 = (x, x, D7, D3, D7, D3, D7, D3) 12. QPI Command, Address, Data input/output format: CLK # 0 1 2 3 4 5 6 7 8 9 10 11 IO0 = C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0 IO1 = C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1 IO2 = C6, C2, A22, A18 , A14, A10, A6, A2, D6, D2, D6, D2 IO3 = C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3 13. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is controlled by read parameter P7 – P4. 14. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 – P0.

8.2 Instruction Descriptions

8.2.1 Write Enable (06h)

(DI) pin on the rising edge of CLK, and then driving /CS high. Figure 5. Write Enable Instruction for SPI Mode (left) or QPI Mode (right)

8.2.2 Write Enable for Volatile Status Register (50h)

Figure 6. Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI Mode (right)

8.2.3 Write Disable (04h)

Page Program, Sector Erase, Block Erase, Chip Erase and Reset instructions. Figure 7. Write Disable Instruction for SPI Mode (left) or QPI Mode (right)

8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)

shown in Figure 8. Refer to section 7.1 for Status Register descriptions. continuously, as shown in Figure 8. The instruction is completed by driving /CS high.

• 31 - /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 05h/35h/15h 2 3 4 5 4 0 4 0 5 1 6 2 7 3 5 1 6 2 7 3 SR-1/2/3 out SR-1/2/3 out Instruction Figure 8b. Read Status Register Instruction (QPI Mode)

8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)

The Write Status Register instruction allows the Status Registers to be written. The writable Status Register bits include: SRP0, SEC, TB, BP[2:0] in Status Register -1; CMP, LB[3:1], QE, SRP1 in Status Register-2; HOLD/RST, DRV1, DRV0, WPS & ADP in Status Register -3. All other Status Register bit locations are read-only and will not be affected by the Write Status Register instruction. LB[3:1] are non- volatile OTP bits, once it is set to 1, it cannot be cleared to 0. To write non -volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been executed for the device to accept the Write Status Register instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by d riving /CS low, sending the instruction code “01h/31h/11h”, and then writing the status register data byte as illustrated in Figure 9a & 9b. To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However, SRP1 and LB[3:1] cannot be changed from “1” to “0” because of the OTP protection for these bits. Upon power off or the execution of a Software/Hardware Reset, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will be restored. During non-volatile Status Register write operation (06h combined with 01h/31h/11h), after /CS is driven high, the self -timed Wri te Status Register cycle will commence for a time duration of t W (See AC Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.

8.2.6 Read Data (03h)

as long as the clock continues. The instruction is completed by driving /CS high. (see AC Electrical Characteristics). The Read Data (03h) instruction is only supported in Standard SPI mode. Figure 14. Read Data Instruction (SPI Mode only)

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8.2.7 Fast Read (0Bh)

The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F R (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24 -bit address as shown in Figure 16. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a “don’t care”. /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (0Bh) High Impedance 8 9 10 28 29 30 31 24-Bit Address 23 22 21 3 2 1 0 Data Out 1 /CS CLK DI (IO0) DO (IO1) 32 33 34 35 36 37 38 39 Dummy Clocks High Impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 Data Out 2 7 6 5 4 3 2 1 0 4331 = MSB* Figure 16a. Fast Read Instruction (SPI Mode)

Publication Release Date: May 13, 2016 - 36 - Revision M Fast Read (0Bh) in QPI Mode The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide range of applications with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 2. /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 0Bh 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Dummy* Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 IOs switch from Input to Output * "Set Read Parameters" instruction (C0h) can set the number of dummy clocks. Instruction Figure 16b. Fast Read Instruction (QPI Mode)

8.2.8 Fast Read Dual Output (3Bh)

Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution. Figure 18. Fast Read Dual Output Instruction (SPI Mode only)

8.2.9 Fast Read Quad Output (6Bh)

pins should be high-impedance prior to the falling edge of the first data out clock. Figure 20. Fast Read Quad Output Instruction (SPI Mode only)

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8.2.10 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random acces s while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23 -0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. Fast Read Dual I/O with “Continuous Read Mode” The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7 -0) after the input Address bits (A 23-0), as shown in Figure 22 a. The upper nibble of the (M7 -4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require the BB h instruction code, as shown in Figure 22 b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5 -4 do not equal to (1,0), the next instr uction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFFFh on IO0 for the next instruction (16 clocks), to ensure M4 = 1 and return the device to normal operation. /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (BBh) 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 /CS CLK DI (IO0) DO (IO1) 32 33 34 35 36 37 38 39 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * IOs switch from Input to Output 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 16 17 18 20 21 2219 23 A23-16 A15-8 A7-0 M7-0 Byte 1 Byte 2 Byte 3 Byte 4 = MSB* * Figure 22a. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4  10, SPI Mode only)

Publication Release Date: May 13, 2016 - 40 - Revision M /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 /CS CLK DI (IO0) DO (IO1) 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * IOs switch from Input to Output 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 A23-16 A15-8 A7-0 M7-0 Byte 1 Byte 2 Byte 3 Byte 4 0 1 2 3 4 5 6 7 16 17 18 20 21 2219 23 = MSB* Figure 22b. Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)

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8.2.11 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO 0, IO1, IO2 and IO3 and four Dummy clocks are required in SPI mode prior to the data output. T he Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction. Fast Read Quad I/O with “Continuous Read Mode” The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7 -0) after the input Address bits (A23 -0), as shown in Figure 24 a. The upper nibble of the (M7 -4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5 -4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the EBh instruction code, as shown in Figure 24b. This reduces the i nstruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5 -4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the fir st byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation. Figure 24a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-410, SPI Mode) M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output Byte 3 15 16 17 18 19 20 21 22 23 Dummy DummyInstruction (EBh)

Publication Release Date: May 13, 2016 - 42 - Revision M M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output Byte 3 Dummy Dummy Figure 24b. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode) Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h) command can either enable or disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64 - byte section of a 256-byte page. The output data starts at th e initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 -byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” instruction allows three “W rap Bits”, W6 -4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6 -5 are used to specify the length of the wrap around section within a page. Refer to section 8.2.24 for detail descriptions.

• 43 - Fast Read Quad I/O (EBh) in QPI Mode The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 19c. When QPI mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide range of applicatio ns with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 2 . In QPI mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the default setting, the data output will follow the Continuous Read Mode bits immediately. “Continuous Read Mode” featur e is also available in QPI mode for Fast Read Quad I/O instruction. Please refer to the description on previous pages. “Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch) instruction must be used. Please refer to 8.2.45 for details. Figure 24c. Fast Read Quad I/O Instruction (Initial instruction or previous M5-410, QPI Mode) M7-0* /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 EBh 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output * "Set Read Parameters" instruction (C0h) can set the number of dummy clocks. Byte 3 Instruction

Publication Release Date: May 13, 2016 - 44 - Revision M

8.2.12 Word Read Quad I/O (E7h)

The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clocks are required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register -2 must be set to enable the Word Read Quad I/O Instruction. Word Read Quad I/O with “Continuous Read Mode” The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7 -0) after the input Address bits (A23 -0), as shown in Figure 26 a. The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5 -4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E7h instruction code, as shown in Figure 26b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5 -4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requi res the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation. Figure 26a. Word Read Quad I/O Instruction (Initial instruction or previous M5-4  10, SPI Mode only) M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output Byte 3 15 16 17 18 19 20 21 DummyInstruction (E7h)

• 45 - M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 4 0 5 1 6 2 7 3 A15-8 A7-0 4 0 5 1 6 2 7 3 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 IOs switch from Input to Output Byte 3 8 9 10 11 12 13 Dummy Figure 26b. Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only) Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Word Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) command prior to E7h. The “Se t Burst with Wrap” (77h) command can either enable or disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64 - byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 -byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” ins truction allows three “Wrap Bits”, W6 -4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6 -5 are used to specify the length of the wrap around section within a page. See 8.2.24 for detail descriptions.

Publication Release Date: May 13, 2016 - 46 - Revision M

8.2.13 Octal Word Read Quad I/O (E3h)

The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution (XIP). The Quad Enable bit (QE) of Status Register -2 must be set to enable the Octal Word Read Quad I/O Instruction. Octal Word Read Quad I/O with “Continuous Read Mode” The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7 -0) after the input Address bits (A23 -0), as shown in Figure 27a. The upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3 -0) are don’t care (“x”). However, the IO pins should be high -impedance prior to the falling edge of the first dat a out clock. If the “Continuous Read Mode” bits M5 -4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E3h instruction code, as shown in Figure 27b. This reduces the instruction sequence by ei ght clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5 -4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation. M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 IOs switch from Input to Output Byte 3 15 16 17 18 19 20 21 Instruction (E3h) 4 0 5 1 6 2 7 3 Byte 4 Figure 27a. Octal Word Read Quad I/O Instruction (Initial instruction or previous M5-4  10, SPI Mode only)

• 47 - M7-0 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 4 0 5 1 6 2 7 3 A15-8 A7-0 4 0 5 1 6 2 7 3 Byte 1 Byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 IOs switch from Input to Output Byte 3 8 9 10 11 12 13 4 0 5 1 6 2 7 3 Byte 4 Figure 27b. Octal Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)

8.2.14 Set Burst with Wrap (77h)

system code execution performance. low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7 -0. The instruction sequence is shown in Figure 28. Wrap bit W7 and the lower nibble W3-0 are not used. after a software/hardware reset is 1. Figure 28. Set Burst with Wrap Instruction (SPI Mode only)

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8.2.15 Page Program (02h)

The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24 -bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program instruction sequence is shown in Figure 29. If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant add ress bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed wi thout having any effect on other bytes within the same page. One condition to perform a partial page program is that the number of clocks cannot exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven high, the self -timed Page Program instruction will commence for a time duration of tpp (See AC Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking th e status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks. /CS CLK DI (IO0) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (02h) 8 9 10 28 29 30 39 24-Bit Address 23 22 21 3 2 1 /CS CLK DI (IO0) 40 41 42 43 44 45 46 47 Data Byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 5139 32 33 34 35 36 37 38 Data Byte 1 7 6 5 4 3 2 1 Mode 0 Mode 3 Data Byte 3 2073 2074 2075 2076 2077 2078 2079 Data Byte 256 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 = MSB* Figure 29a. Page Program Instruction (SPI Mode)

Publication Release Date: May 13, 2016 - 50 - Revision M /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 02h Instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Byte1 Byte 2 Byte 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 Byte 255 Byte 256 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 Mode 0 Mode 3 516 517 518 519 Figure 29b. Page Program Instruction (QPI Mode)

8.2.16 Quad Input Page Program (32h)

improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. since the inherent page program time is much greater than the time it take to clock-in the data. instruction code “32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. Page Program instruction sequence is shown in Figure 30. Figure 30. Quad Input Page Program Instruction (SPI Mode only)

Publication Release Date: May 13, 2016 - 52 - Revision M

8.2.17 Sector Erase (20h)

The Sector Erase instruction sets all memory within a specified sector (4K -bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “20h” followed a 24 -bit sector address (A23 -A0). T he Sector Erase instruction sequence is shown in Figure 31a & 31b. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase instruction will commence for a time duration of t SE (See AC Characteristics). While the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks. /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (20h) High Impedance 8 9 29 30 31 24-Bit Address 23 22 2 1 0 Mode 0 Mode 3 = MSB* Figure 31a. Sector Erase Instruction (SPI Mode) /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 20h Instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 4 0 5 1 6 2 7 3 A15-8 A7-0 Mode 0 Mode 3 Figure 31b. Sector Erase Instruction (QPI Mode)

8.2.20 Chip Erase (C7h / 60h)

instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 34. Individual Block/Sector Locks. Figure 34. Chip Erase Instruction for SPI Mode (left) or QPI Mode (right)

Publication Release Date: May 13, 2016 - 56 - Revision M

8.2.21 Erase / Program Suspend (75h)

The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase operation or a Page Program operation and the n read from or program/erase data to, any other sectors or blocks. The Erase/Program Suspend instruction sequence is shown in Figure 35a & 35b. The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not allowe d during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Register instructions (01h, 31h, 11h) and Program instruc tions (02h, 32h, 42h) are not allowed during Program Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation. The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation is on -going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by the device. A maximum of time of “t SUS” (See AC Characteristics) is required to suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within “t SUS” and the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase/Program Suspend. For a previously resumed Erase/Program operation, it is also required that the Suspend instruction “75h” is not issued earlier than a minimum of time of “t SUS” following the preceding Resume instruction “7Ah”. Unexpected power off during the Era se/Program suspend state will reset the device and release the suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was being suspended may become corrupted. It is recommended for the user to im plement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state. /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (75h) High Impedance Mode 0 Mode 3 tSUS Accept instructions Figure 35a. Erase/Program Suspend Instruction (SPI Mode)

• 57 - /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 75h Instruction Mode 0 Mode 3 tSUS Accept instructions Figure 35b. Erase/Program Suspend Instruction (QPI Mode)

Publication Release Date: May 13, 2016 - 58 - Revision M

8.2.22 Erase / Program Resume (7Ah)

The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction “7Ah” will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 36a & 36b. Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of “tSUS” following a previous Resume instruction. /CS CLK DI (IO0) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (7Ah) Mode 0 Mode 3 Resume previously suspended Program or Erase Figure 36a. Erase/Program Resume Instruction (SPI Mode) /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 7Ah Instruction Mode 0 Mode 3 Resume previously suspended Program or Erase Figure 36b. Erase/Program Resume Instruction (QPI Mode)

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8.2.23 Power-down (B9h)

Although the standby current during normal operation is relatively low, standby current can be f urther reduced with the Power -down instruction. The lower power consumption makes the Power -down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the /CS pin l ow and shifting the instruction code “B9h” as shown in Figure 37a & 37b. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down instruction will not be executed. After /CS is driven high, the power -down state will entered within the time duration of t DP (See AC Characteristics). While in the power -down state only the Release Power - down / Device ID (ABh) instruction, which restores the device to normal operation, will be recognized. All other instructions a re ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always power s-up in the normal operation with the standby current of ICC1. /CS CLK DI (IO0) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (B9h) Mode 0 Mode 3 tDP Power-down currentStand-by current Figure 37a. Deep Power-down Instruction (SPI Mode) /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 B9h Instruction Mode 0 Mode 3 tDP Power-down currentStand-by current Figure 37b. Deep Power-down Instruction (QPI Mode)

Publication Release Date: May 13, 2016 - 60 - Revision M

8.2.24 Release Power-down / Device ID (ABh)

The Release from Power -down / Device ID instruction is a multi -purpose instruction. It can be used to release the device from the power -down state , or obtain the devices electronic identification (ID) number. To release the device from the power -down state, the instruction is issued by driving the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in Figure 38a & 38b . Release from power-down will take the time duration of t RES1 (See AC Characteristics) before the device will resume normal operation and other instructions are accepted. The /CS pin must remain high during the t RES1 time duration. When used only to obtain the Device ID while not in the power -down state, the instruction is initiated by driving the /CS pin lo w and shifting the instruction code “ABh” followed by 3 -dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID value for the W25Q128FV is listed in Manufacturer and Device Identi fication table. The Device ID can be read continuously. The instruction is completed by driving /CS high. When used to release the device from the power -down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 38c & 38d, except that after /CS is driven high it must remain high for a time duration of t RES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instructions will be accepted. If the Release from Power- down / Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle. /CS CLK DI (IO0) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (ABh) Mode 0 Mode 3 tRES1 Power-down current Stand-by current Figure 38a. Release Power-down Instruction (SPI Mode)

• 61 - /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 ABh Instruction Mode 0 Mode 3 tRES1 Power-down current Stand-by current Figure 38b. Release Power-down Instruction (QPI Mode) tRES2 /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (ABh) High Impedance 8 9 29 30 31

3 Dummy Bytes

Power-down current Stand-by current= MSB* Figure 38c. Release Power-down / Device ID Instruction (SPI Mode) Power-down current Stand-by current Device ID /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 ABh 2 3 4 5 X X X X X X X X 6 7 8 4 0 5 1 6 2 7 3 IOs switch from Input to Output Instruction tRES2 Mode 0 Mode 3 X X X X X X X X X X X X X X X X Figure 38d. Release Power-down / Device ID Instruction (QPI Mode)

8.2.25 Read Manufacturer / Device ID (90h)

ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. Identification table. The instruction is completed by driving /CS high. Figure 39. Read Manufacturer / Device ID Instruction (SPI Mode)

8.2.26 Read Manufacturer / Device ID Dual I/O (92h)

The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. 24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock . Figure 40. Read Manufacturer / Device ID Dual I/O Instruction (SPI Mode only) The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction.

8.2.27 Read Manufacturer / Device ID Quad I/O (94h)

continuously, alternating from one to the other. The instruction is completed by driving /CS high. Figure 41. Read Manufacturer / Device ID Quad I/O Instruction (SPI Mode only) The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Quad I/O instruction.

8.2.28 Read Unique ID Number (4Bh)

which, the 64-bit ID is shifted out on the falling edge of CLK as shown in Figure 42. Figure 42. Read Unique ID Number Instruction (SPI Mode only)

Publication Release Date: May 13, 2016 - 66 - Revision M

8.2.29 Read JEDEC ID (9Fh)

For compatibility reasons, the W25Q128FV provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer I D byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 43a & 43b . For memory type and capacity values refer to Manufacturer and Device Identification table. /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (9Fh) High Impedance 8 9 10 12 13 14 15 Capacity ID7-0 /CS CLK DI (IO0) DO (IO1) 16 17 18 19 20 21 22 23 Manufacturer ID (EFh) 24 25 26 28 29 30 7 6 5 4 3 2 1 0 2715 Mode 0 Mode 3 7 6 5 4 3 2 1 0 Memory Type ID15-8 = MSB* Figure 43a. Read JEDEC ID Instruction (SPI Mode) /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 9Fh 2 3 4 5 12 8 13 9 14 10 15 11 EFh 4 0 5 1 6 2 7 3 ID15-8 ID7-0 IOs switch from Input to Output Instruction Mode 0 Mode 3 Figure 43b. Read JEDEC ID Instruction (QPI Mode)

8.2.30 Read SFDP Register (5Ah)

2011 (date code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet. Winbond Application Note for SFDP Definition Table. Note 1: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register. Figure 34. Read SFDP Register Instruction Sequence Diagram

8.2.31 Erase Security Registers (44h)

important information separately from the main memory array. register will be ignored (Refer to section 7.1.8 for detail descriptions). Figure 45. Erase Security Registers Instruction (SPI Mode only)

8.2.32 Program Security Registers (42h)

is being sent to the device. Figure 46. Program Security Registers Instruction (SPI Mode only)

8.2.33 Read Security Registers (48h)

address is automatically incremented to the next byte address after each byte of data is shifted out. instruction allows clock rates from D.C. to a maximum of FR (see AC Electrical Characteristics). Figure 47. Read Security Registers Instruction (SPI Mode only)

8.2.34 Set Read Parameters (C0h)

with Wrap (0Ch)” instruction. any 0Bh, EBh or 0Ch instructions. Figure 48. Set Read Parameters Instruction (QPI Mode only)

8.2.35 Burst Read with Wrap (0Ch)

“Wrap Length” once the ending boundary is reached. set the number of dummy clocks. Figure 49. Burst Read with Wrap Instruction (QPI Mode only)

8.2.36 Enter QPI Mode (38h)

instruction is the only way to switch the device from SPI mode to QPI mode. See Instruction Set Table 3 for all the commands supported in QPI mode. Suspend status, and the Wrap Length setting will remain unchanged. Figure 50. Enter QPI Instruction (SPI Mode only)

8.2.37 Exit QPI Mode (FFh)

Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. Figure 51. Exit QPI Instruction (QPI Mode only)

• 75 -

8.2.38 Individual Block/Sector Lock (36h)

The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register -3 must be set to 1. If WPS=0, the write protection will be d etermined by the combination of CMP, SEC, TB, BP[2:0] bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected. To lock a specific block or sector as illustrated in Figure 4d, an Individual Block/Sector Lock command must be issued by driving /CS low, shifting the instruction code “36h” into the Data Input (DI) pin on the rising edge of CLK, followed by a 24 -bit address and then driving /CS high. A Write Enable instruction must be executed before the device will accept the Individual Block/Sector Lock Instruction (Status Register bit WEL= 1). /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (36h) High Impedance 8 9 29 30 31 24-Bit Address 23 22 2 1 0 Mode 0 Mode 3 = MSB* Figure 52a. Individual Block/Sector Lock Instruction (SPI Mode) /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 36h Instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 4 0 5 1 6 2 7 3 A15-8 A7-0 Mode 0 Mode 3 Figure 52b. Individual Block/Sector Lock Instruction (QPI Mode)

Publication Release Date: May 13, 2016 - 76 - Revision M

8.2.39 Individual Block/Sector Unlock (39h)

The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Secto r Locks, the WPS bit in Status Register -3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0] bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default val ues after device power up or after a Reset are 1, so the entire memory array is being protected. To unlock a specific block or sector as illustrated in Figure 4d, an Individual Block/Sector Unlock command must be issued by driving /CS low, shifting the ins truction code “39h” into the Data Input (DI) pin on the rising edge of CLK, followed by a 24 -bit address and then driving /CS high. A Write Enable instruction must be executed before the device will accept the Individual Block/Sector Unlock Instruction (Status Register bit WEL= 1). /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (39h) High Impedance 8 9 29 30 31 24-Bit Address 23 22 2 1 0 Mode 0 Mode 3 = MSB* Figure 53a. Individual Block Unlock Instruction (SPI Mode) /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 39h Instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 4 0 5 1 6 2 7 3 A15-8 A7-0 Mode 0 Mode 3 Figure 53b. Individual Block Unlock Instruction (QPI Mode)

• 77 -

8.2.40 Read Block/Sector Lock (3Dh)

The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register -3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0] bits in the St atus Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected. To read out the lock bit value of a specific block or sector as illustr ated in Figure 4d, a Read Block/Sector Lock command must be issued by driving /CS low, shifting the instruction code “3Dh” into the Data Input (DI) pin on the rising edge of CLK, followed by a 24 -bit address. The Block/Sector Lock bit value will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 54. If the least significant bit (LSB) is 1, the corresponding block/sector is locked; if LSB=0, the corresponding block/sector is unlocked, Erase/Program operation can be performed. /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (3Dh) High Impedance 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 X X X X X X X 0 24-Bit Address 23 22 21 3 2 1 0 Lock Value Out = MSB* Mode 0 Mode 3 Figure 54a. Read Block Lock Instruction (SPI Mode) /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 3Dh 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 A23-16 6 7 8 9 4 0 5 1 6 2 7 3 A15-8 A7-0 Lock Value X 0 X X X X X X IOs switch from Input to Output Instruction Mode 0 Mode 3 Figure 54b. Read Block Lock Instruction (QPI Mode)

8.2.41 Global Block/Sector Lock (7Eh)

device will accept the Global Block/Sector Lock Instruction (Status Register bit WEL= 1). Figure 55. Global Block Lock Instruction for SPI Mode (left) or QPI Mode (right)

8.2.42 Global Block/Sector Unlock (98h)

device will accept the Global Block/Sector Unlock Instruction (Status Register bit WEL= 1). Figure 56. Global Block Unlock Instruction for SPI Mode (left) or QPI Mode (right)

• 79 -

8.2.43 Enable Reset (66h) and Reset Device (99h)

Because of the small package and the limitation on the number of pins, the W25Q128FV provide a software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going internal operations will be terminated and the d evice will return to its default power -on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Read parameter setting (P7 -P0), Continuous Read Mode bit setting (M7-M0) and Wrap Bit setting (W6-W4). “Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode. To avoid accidental reset, both instructions must be issued in sequence. Any other commands other than “Reset (99h)” after the “Enable Reset (66h)” command will disable the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset command is accepted by the device, the device will take approximately tRST =30us to reset. During this period, no command will be accepted. Data corruption may happen if there is an on -going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (99h) Mode 0 Mode 3 /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (66h) High Impedance Figure 57a. Enable Reset and Reset Instruction Sequence (SPI Mode) Mode 0 Mode 3 0 1 99h Instruction Mode 0 Mode 3 /CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 66h Instruction Figure 57b. Enable Reset and Reset Instruction Sequence (QPI Mode)

Publication Release Date: May 13, 2016 - 80 - Revision M 9. ELECTRICAL CHARACTERISTICS

9.1 Absolute Maximum Ratings (1)(2)

PARAMETERS SYMBOL CONDITIONS RANGE UNIT Supply Voltage VCC –0.6 to 4.6V V Voltage Applied to Any Pin VIO Relative to Ground –0.6 to VCC+0.4 V Transient Voltage on any Pin VIOT <20nS Transient Relative to Ground –2.0V to VCC+2.0V V Storage Temperature TSTG –65 to +150 °C Lead Temperature TLEAD (3) See Note (3) °C Electrostatic Discharge Voltage VESD(2) Human Body Model –2000 to +2000 V Notes: 1.This device has been designed and tested for the spe cified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage. 2.JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms). 3.Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.

9.2 Operating Ranges

X Supply Voltage VCC (1) FR = 104MHz, f R = 50MHz 2.7 3.6 V Ambient Temperature, Operating TA Industrial –40 +85 °C Note: 1.VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programmi ng (erase/write) voltage.

• 81 -

9.3 Power-Up Power-Down Timing and Requirements(1)

VCC (min) to /CS Low tVSL 20 µs Time Delay Before Write Instruction tPUW 5 ms Write Inhibit Threshold Voltage VWI 1.0 2.0 V Note: 1. These parameters are characterized only. VCC tVSL Read Instructions Allowed Device is fully Accessible tPUW /CS must track VCC Program, Erase and Write Instructions are ignored Reset State VCC (max) VCC (min) VWI Time Figure 58a. Power-up Timing and Voltage Levels VCC Time /CS must track VCC during VCC Ramp Up/Down /CS Figure 58b. Power-up, Power-Down Requirement

Publication Release Date: May 13, 2016 - 82 - Revision M

9.4 DC Electrical Characteristics

Input Capacitance CIN(1) VIN = 0V 6 pF Output Capacitance Cout(1) VOUT = 0V 8 pF Input Leakage ILI ±2 µA I/O Leakage ILO ±2 µA Standby Current ICC1 /CS = VCC, VIN = GND or VCC 10 50 µA Power-down Current ICC2 /CS = VCC, VIN = GND or VCC 1 20 µA Current Read Data / Dual /Quad 50MHz ICC3(2) C = 0.1 VCC / 0.9 VCC DO = Open 15 mA Current Read Data / Dual /Quad 80MHz ICC3(2) C = 0.1 VCC / 0.9 VCC DO = Open 18 mA Current Read Data / Dual Output Read/Quad Output Read 104MHz ICC3(2) C = 0.1 VCC / 0.9 VCC DO = Open 20 mA Current Write Status Register ICC4 /CS = VCC 8 12 mA Current Page Program ICC5 /CS = VCC 20 25 mA Current Sector/Block Erase ICC6 /CS = VCC 20 25 mA Current Chip Erase ICC7 /CS = VCC 20 25 mA Input Low Voltage VIL –0.5 VCC x 0.3 V Input High Voltage VIH VCC x 0.7 VCC + 0.4 V Output Low Voltage VOL IOL = 100 µA 0.2 V Output High Voltage VOH IOH = –100 µA VCC – 0.2 V Notes: 1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.0V, 25% driver strength. 2. Checker Board Pattern.

9.5 AC Measurement Conditions(1)

1. Output Hi-Z is defined as the point where data out is no longer driven.

0.9 VCC

0.1 VCC

0.5 VCC

Figure 59. AC Measurement I/O Waveform

Publication Release Date: May 13, 2016 - 84 - Revision M

9.6 AC Electrical Characteristics(6)

Clock frequency for all other instructions 2.7V-3.6V VCC & Industrial Temperature except Read data instructions (03h) FR fC1 D.C. 104 MHz Clock frequency for Read Data instruction (03h) fR fC2 D.C. 50 MHz Clock High, Low Time for all instructions except for Read Data (03h) tCLH, tCLL(1) 4 ns Clock High, Low Time for Read Data (03h) instruction tCRLH, tCRLL(1) 8 ns Clock Rise Time peak to peak tCLCH(2) 0.1 V/ns Clock Fall Time peak to peak tCHCL(2) 0.1 V/ns /CS Active Setup Time relative to CLK tSLCH tCSS 5 ns /CS Not Active Hold Time relative to CLK tCHSL 5 ns Data In Setup Time tDVCH tDSU 2 ns Data In Hold Time tCHDX tDH 3 ns /CS Active Hold Time relative to CLK tCHSH 3 ns /CS Not Active Setup Time relative to CLK tSHCH 3 ns /CS Deselect Time (for Read) tSHSL1 tCSH 10 ns /CS Deselect Time (for Erase or Program or write) tSHSL2 tCSH 50 ns Output Disable Time tSHQZ(2) tDIS 7 ns Clock Low to Output Valid tCLQV tV 7 ns Output Hold Time tCLQX tHO 2 ns /HOLD Active Setup Time relative to CLK tHLCH 5 ns /HOLD Active Hold Time relative to CLK tCHHH 5 ns /HOLD Not Active Setup Time relative to CLK tHHCH 5 ns /HOLD Not Active Hold Time relative to CLK tCHHL 5 ns Continued – next page AC Electrical Characteristics (cont’d)

• 85 - DESCRIPTION SYMBOL ALT SPEC UNI T MIN TYP MAX /HOLD to Output Low-Z tHHQX(2) tLZ 7 ns /HOLD to Output High-Z tHLQZ(2) tHZ 12 ns Write Protect Setup Time Before /CS Low tWHSL(3) 20 ns Write Protect Hold Time After /CS High tSHWL(3) 100 ns /CS High to Power-down Mode tDP(2) 3 µs /CS High to Standby Mode without ID Read tRES1(2) 3 µs /CS High to Standby Mode with ID Read tRES2(2) 1.8 µs /CS High to next Instruction after Suspend tSUS(2) 20 µs /CS High to next Instruction after Reset tSUS(2) 30 µs /RESET pin Low period to reset the device tRST(2)(5) 1 µs Write Status Register Time tW 10 15 ms Byte Program Time (First Byte) (4) tBP1(4) 30 50 µs Additional Byte Program Time (After First Byte) (4) tBP2(4) 2.5 12 µs Page Program Time tPP 0.7 3 ms Sector Erase Time (4KB) W25Q128FVxxIG tSE 100 400 ms W25Q128FVxxIQ W25Q128FVxxIF 45 Block Erase Time (32KB) tBE1 120 1,600 ms Block Erase Time (64KB) tBE2 150 2,000 ms Chip Erase Time tCE 40 200 s Notes: 1.Clock high + Clock low must be less than or equal to 1/fC. 2.Value guaranteed by design and/or characterization, not 100% tested in production. 3.Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1). 4.For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes programmed. 5.It’s possible to reset the device with shorter t RESET (as short as a few hundred ns), a 1us minimum is recommended to ensure reliable operation. 6.4-bytes address alignment for QPI/Quad Read

Publication Release Date: May 13, 2016 - 86 - Revision M

9.7 Serial Output Timing

/CS CLK IO output tCLQX tCLQV tCLQX tCLQV tSHQZtCLL LSB OUT tCLH MSB OUT

9.8 Serial Input Timing

/CS CLK IO input tCHSL MSB IN tSLCH tDVCH tCHDX tSHCHtCHSH tCLCH tCHCL LSB IN tSHSL 9.9 /HOLD Timing /CS CLK IO output /HOLD tCHHL tHLCH tCHHH tHHCH tHLQZ tHHQX IO input 9.10 /WP Timing /CS CLK /WP tWHSL tSHWL IO input Write Status Register is allowed Write Status Register is not allowed

• 87 - 10. PACKAGE SPECIFICATIONS 10.1 8-Pin SOIC 208-mil (Package Code S) θ Symbo l Millimeters Inches Min Nom Max Min Nom Max e 1.27 BSC 0.050 BSC

Publication Release Date: May 13, 2016 - 88 - Revision M 10.2 8-Pin VSOP 208-mil (Package Code T) θ θ Symbol Millimeters Inches Min Nom Max Min Nom Max c 0.127 REF 0.005 REF θ 0° ― 8° 0° ― 8°

• 89 - 10.3 8-Pin PDIP 300-mil (Package Code A) Symbol Millimeters Inches Min Nom Max Min Nom Max E 7.62 BSC 0.300 BSC

Publication Release Date: May 13, 2016 - 90 - Revision M 10.4 8-Pad WSON 6x5-mm (Package Code P) Symbol Millimeters Inches Min Nom Max Min Nom Max e 1.27 BSC 0.050 BSC Note: The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.

• 91 - 10.5 8-Pad WSON 8x6-mm (Package Code E) Symbol Millimeters Inches Min Nom Max Min Nom Max REF --- Note: The metal pad area on the bottom center o f the package is not connected to any internal electrical signals. It can be left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.

Publication Release Date: May 13, 2016 - 92 - Revision M 10.6 16-Pin SOIC 300-mil (Package Code F) Symbol Millimeters Inches Min Nom Max Min Nom Max e 1.27 BSC 0.050 BSC

• 93 - 10.7 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 ball array) Symbol Millimeters Inches Min Nom Max Min Nom Max D1 4.00 BSC 0.157 BSC E1 4.00 BSC 0.157 BSC SE 1.00 TYP 0.039 TYP SD 1.00 TYP 0.039 TYP e 1.00 BSC 0.039 BSC Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm

Publication Release Date: May 13, 2016 - 94 - Revision M 10.8 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 ball array) Symbol Millimeters Inches Min Nom Max Min Nom Max D1 5.00 BSC 0.197 BSC E1 3.00 BSC 0.118 BSC e 1.00 BSC 0.039 BSC Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm

• 95 - 11. ORDERING INFORMATION Notes: 1. The “W” prefix and the Temperature designator “I” are not included on the part marking. 2. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 3. For shipments with OTP feature enabled, please contact Winbond W(1) 25Q 128F V x I (1) W = Winbond 25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 128F = 12 8M-bit V = 2.7V to 3.6V S = 8-pin SOIC 208-mil T = 8 -pin VSOP 208-mil A = 8 -pin PDIP 300-mil F = 16-pin SOIC 300-mil P = WSON8 6x5 -mm E = WSON8 8x6-mm B = TFBGA 8x6-mm (5x5-1 ball array) C = TFBGA 8x6-mm (6x4 ball array) I = Industrial ( -40°C to +85°C) (2,3) G = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) F = Green Package with Fast Sector Erase time (tSE) Q = Green Package with QE=1 in Status Register-2

Publication Release Date: May 13, 2016 - 96 - Revision M

11.1 Valid Part Numbers and Top Side Marking

The following table provides the valid part numbers for the W25Q128FV SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use a 12-digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages uses an abbreviated 10-digit number. PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING S SOIC-8 208-mil 128M-bit W25Q128FVSIG W25Q128FVSIQ W25Q128FVSIF 25Q128FVSG 25Q128FVSQ 25Q128FVSF T(1) VSOP-8 208-mil 128M-bit W25Q128FVTIG W25Q128FVTIQ W25Q128FVTIF 25Q128FVTG 25Q128FVTQ 25Q128FVTF A PDIP-8 300-mil 128M-bit W25Q128FVAIG W25Q128FVAIQ W25Q128FVAIF 25Q128FVIG 25Q128FVIQ 25Q128FVIF F SOIC-16 300-mil 128M-bit W25Q128FVFIG W25Q128FVFIQ W25Q128FVFIF 25Q128FVFG 25Q128FVFQ 25Q128FVFF P WSON-8 6x5- mm 128M-bit W25Q128FVPIG W25Q128FVPIQ W25Q128FVPIF 25Q128FVPG 25Q128FVPQ 25Q128FVPF E WSON-8 8x6- mm 128M-bit W25Q128FVEIG W25Q128FVEIQ W25Q128FVEIF 25Q128FVEG 25Q128FVEQ 25Q128FVEF B(1) TFBGA-24 8x6- mm (5x5 Ball Array) 128M-bit W25Q128FVBIG W25Q128FVBIF 25Q128FVBG 25Q128FVBF C(1) TFBGA-24 8x6- mm (6x4 Ball Array) 128M-bit W25Q128FVCIG W25Q128FVCIF 25Q128FVCG 25Q128FVCIF Note: 1. These package types are special order, please contact Winbond for more information.

• 97 - 12. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A 07/20/2011 All New Create Preliminary B 04/13/2012 10, 14, 84 6, 9, 87-88, 94- Updated RESET descriptions Updated frequency definition Referred to SFDP definition application note Updated Erase Time Updated WSON metal pad size Removed preliminary designator Added VSOP, PDIP package types, Q order option C 07/13/2012 19, 84 10, 15, 80 Updated default driver strength setting Added power-down requirement Updated PDIP part number and marking D 10/01/2012 80 Updated power-up timing parameters Updated WSON part numbers E 11/14/2012 88 Updated PDIP package dimension drawing E1 01/25/2013 8,16 Added rest pin description of SOIC-16 300-mil F 03/15/2013 84 95,96 Modified the tSE of W25Q128FVxxIQ & IF Added W25Q128FVxxIF into order information G 04/12/2013 84 Modified the tSE of W25Q128FVxxIQ & IF H 04/29/2013 91,92 Added Quad Enable default description Added description of DRV default setting Modified the typo of Supply Voltage Updated note for metal pad for WSON, USON I 10/09/2013 63-64 80-85 95-96 Modified the description of 92h, 94h Modified the description of DC/AC table Removed the W25Q128FVxIP J 07/24/2014 86 Updated WP timing information K 06/18/2015 92 21-22 Updated SOIC 300-mil POD Updated table sift L 08/24/2015 96 Updated W25Q128FVTIQ information M 05/13/2016 84 Updated formatting setting

Publication Release Date: May 13, 2016 - 98 - Revision M Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy con trol instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for a pplications wherein failure of Winbond products could result or lead to a situation where in personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Information in this document is provided solely in connection with Winbond products. Winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice.