25080DVSIG

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Publication Release Date: July 2 1, 2015 - 1 - Preli mry-Revision G 3V 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

Publication Release Date: July 2 1, 2015 - 2 - Preli mry-Revision G Table of Contents

Publication Release Date: July 2 1, 2015 - 3 - Preli mry-Revision G

Publication Release Date: July 2 1, 2015 - 4 - Preli mry-Revision G

Publication Release Date: July 2 1, 2015 - 5 - Preli mry-Revision G 1. GENERAL DESCRIPTION The W25Q80DV (8M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 1µA for power-down. All devices are offered in space-saving packages. The W25Q80DV array is organized into 4,096 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q80DV has 256 erasable sectors and 16 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25Q80DV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SP I: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. A Hold pin, Write Protect pin and programmable write protect ion, with top, bottom or complement array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64 -bit Unique Serial Number. 2. FEATURES  Family of SpiFlash Memories – W25Q80DV: 8M-bit/1M-byte (1,048,576) – 256-byte per programmable page – Standard SPI: CLK,/CS,DI,DO,/WP,/Hold – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 – Uniform 4KB Sectors, 32KB & 64KB Blocks  Highest Performance Serial Flash – 104MHz Dual/Quad SPI clocks – 208/416MHz equivalent Dual/Quad SPI – 50MB/S continuous data transfer rate  Software and Hardware Write Protection – Write-Protect all or portion of memory – Enable/Disable protection with /WP pin – Top or bottom array protection  Flexible Architecture with 4KB sectors – Uniform Sector/Block Erase (4/32/64-kbytes) – Program one to 256 bytes < 0.8ms – Erase/Program Suspend & Resume – More than 100,000 erase/write cycles – More than 20-year data retention  Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply – <1µA Power-down(typ.)  Space Efficient Packaging(1): – 8-pin SOIC 150-mil/208mil, VSOP 150-mil – 8-pad WSON 6x5-mm, USON 2x3-mm – 8-pin PDIP 300-mil – 8-ball WLCSP – Contact Winbond for KGD and other options Note 1. Some package types are special orders, please contact Winbond for ordering information.

Publication Release Date: July 21, 2015 - 6 - Prelimry-Revision G 3. PACKAGE TYPES AND PIN CONFIGURATIONS

3.1 Pin Configuration SOIC 150-MIL/208-mil AND VSOP 150-mil:

Figure 1a.W25Q80DV Pin Assignments, 8-pin SOIC 150-MIL(Package Code SN) & 208-MIL(Package Code SS) & VSOP 150-mil (Package Code SV)

3.2 Pad Configuration WSON 6x5-mm, USON 2X3-mm

Figure 1b. W25Q80DV Pad Assignments, 8-pad WSON 6x5-mm, USON 2x3-mm (Package Code ZP & UX) /CS DO (IO1) /WP (IO2) GND VCC /HOLD or /RESET (IO3) DI (IO0) CLK Top View /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) DI (IO0) CLK Top View

Publication Release Date: July 21, 2015 - 7 - Prelimry-Revision G

3.3 Pin Configuration PDIP 300-mil

Figure 1c. W25Q80DV Pin Assignments, 8-pin PDIP (Package Code DA)

3.4 Pin Description SOIC/VSOP , WSON/USON & PDIP 300-mil

PIN NO. PIN NAME I/O FUNCTION 1 /CS I Chip Select Input

2 DO (IO1) I/O Data Output (Data Input Output 1)*1

3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)*2

4 GND Ground

5 DI (IO0) I/O Data Input (Data Input Output 0)*1

6 CLK I Serial Clock Input

7 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2

8 VCC Power Supply

*1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions /CS DO (IO1) /WP (IO2) GND VCC /HOLD (IO3) DI (IO0) CLK Top View

Publication Release Date: July 21, 2015 - 8 - Prelimry-Revision G

3.5 Ball Configuration WLCSP

Figure 1d. W25Q80DV Ball Assignments, 8-ball WLCSP (Package Code BY)

3.6 Ball Description WLCSP

BALL NO. PIN NAME I/O FUNCTION A1 VCC Power Supply A2 /CS I Chip Select Input B1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2 B2 DO (IO1) I/O Data Output (Data Input Output 1)*1 C1 CLK I Serial Clock Input C2 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2 D1 DI (IO0) I/O Data Input (Data Input Output 0)*1 D2 GND Ground *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – IO3 are used for Quad SPI instructions GND DI(IO0) /CS VCC DO(IO1) /HOLD(IO3) /WP(IO2) CLK Top View GND DI(IO0) /CS VCC DO(IO1) /HOLD(IO3) /WP(IO2) CLK Bottom View

Publication Release Date: July 21, 2015 - 9 - Prelimry-Revision G 4. PIN DESCRIPTIONS

4.1 Chip Select (/CS)

The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be w ritten to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power -up (see “ Power-up Timing and Write inhibit threshold” and figure 45). If needed, a pull-up resister on /CS can be used to accomplish this.

4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)

The W25Q80DV support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register 2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

4.3 Write Protect (/WP)

The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP0) bits, a portion as small as 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register -2 is set for Quad I/O, the /WP pin function is not available since this pin is used for IO2.

4.4 HOLD (/HOLD)

The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. Th e /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See figure 1a and 1b for the pin configuration of Quad I/O operation.

4.5 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations.

• Sector 0 (4KB) • xx0000h xx00FFh xx1F00h xx1FFFh
• Sector 1 (4KB) • xx1000h xx10FFh xx2F00h xx2FFFh
• Sector 2 (4KB) • xx2000h xx20FFh xxDF00h xxDFFFh
• Sector 13 (4KB) • xxD000h xxD0FFh xxEF00h xxEFFFh
• Sector 14 (4KB) • xxE000h xxE0FFh xxFF00h xxFFFFh
• Sector 15 (4KB) • xxF000h xxF0FFh Block Segmentation Data Security Register 1 - 3 Write Protect Logic and Row Decode 000000h 0000FFh SFDP Register 00FF00h 00FFFFh
• Block 0 (64KB) • 000000h 0000FFh 03FF00h 03FFFFh
• Block 3 (64KB) • 030000h 0300FFh 04FF00h 04FFFFh
• Block 4 (64KB) • 040000h 0400FFh 07FF00h 07FFFFh
• Block 7 (64KB) • 070000h 0700FFh 08FF00h 08FFFFh
• Block 8 (64KB) • 080000h 0800FFh 0FFF00h 0FFFFFh
• Block 15 (64KB) • 0F0000h 0F00FFh 003000h 0030FFh 002000h 0020FFh 001000h 0010FFh Column Decode And 256-Byte Page Buffer Beginning Page Address Ending Page Address W25Q80BL SPI Command & Control Logic Byte Address Latch / Counter Status Register Write Control Logic Page Address Latch / Counter DO (IO1) DI (IO0) /CS CLK /HOLD (IO3) /WP (IO2) High Voltage Generators xx0F00h xx0FFFh
• Sector 0 (4KB) • xx0000h xx00FFh xx1F00h xx1FFFh
• Sector 1 (4KB) • xx1000h xx10FFh xx2F00h xx2FFFh
• Sector 2 (4KB) • xx2000h xx20FFh xxDF00h xxDFFFh
• Sector 13 (4KB) • xxD000h xxD0FFh xxEF00h xxEFFFh
• Sector 14 (4KB) • xxE000h xxE0FFh xxFF00h xxFFFFh
• Sector 15 (4KB) • xxF000h xxF0FFh Block Segmentation Data Security Register 1 - 3 Write Protect Logic and Row Decode 000000h 0000FFh SFDP Register 00FF00h 00FFFFh
• Block 0 (64KB) • 000000h 0000FFh 03FF00h 03FFFFh
• Block 3 (64KB) • 030000h 0300FFh 04FF00h 04FFFFh
• Block 4 (64KB) • 040000h 0400FFh 07FF00h 07FFFFh
• Block 7 (64KB) • 070000h 0700FFh 08FF00h 08FFFFh
• Block 8 (64KB) • 080000h 0800FFh 0FFF00h 0FFFFFh
• Block 15 (64KB) • 0F0000h 0F00FFh W25Q80DL

Figure 2. W25Q80DV Serial Flash Memory Block Diagram

Publication Release Date: July 21, 2015 - 11 - Prelimry-Revision G 6. FUNCTIONAL DESCRIPTION

6.1 SPI OPERATIONS

The W25Q80DV are accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge CLK. SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the nor mal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3 the CLK signal is normally high on the fal ling and rising edges of /CS. Dual SPI Instructions The W25Q80DV support Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power -up (code-shadowing) or for executing non-speed- critical code directly from the SPI bus (XIP) . When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI Instructions The W25Q80DV support Quad SPI operation when using the “Fast Read Quad Output (6Bh)”, “Fast Read Quad I/O (EBh)” instructions. These instructions allow data to be transferred to or from the device six to eight times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register 2 to be set. Hold Function For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q80DV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so pro gramming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation, not during Quad SPI.

Publication Release Date: July 21, 2015 - 12 - Prelimry-Revision G To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of t he /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and S erial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active low for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device.

6.2 WRITE PROTECTION

Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the W25Q80DV provide several means to protect the data from inadvertent writes. Write Protect Features  Device resets when VCC is below threshold  Time delay write disable after Power-up  Write enable/disable instructions  Automatic write disable after erase or program  Software and Hardware (/WP pin) write protection using Status Register  Write Protection using Power-down instruction  Lock Down write protection until next power-up  One Time Program (OTP) write protection* * Note: This feature is available upon special order. Please contact Winbond for details. Upon power-up or at power-down, the W25Q80DV will maintain a reset condition while VCC is below the threshold value of V WI, (See Power-up Timing and Voltage Levels and Figure 45). While reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of t PUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC -min level and t VSL time delay is reached. If needed , a pull-up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be a ccepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0) bits. These settings allow a portion as small as 4KB sector or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register section for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction.

Publication Release Date: July 21, 2015 - 13 - Prelimry-Revision G 7. CONTROL AND STATUS REGISTERS The Read Status Register -1 and Status Register -2 instructions can be used to provide status on the availability of the Flash memory array, if the device is write enabled or dis abled, the state of write protection, Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting and Security Register OTP lock. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP 0, SRP1), the Write Enable instruction, and during Standard/Dual SPI operations, the /WP pin.

7.1 STATUS REGISTER

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status/security register instruction h as completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions. Write Enable Latch (WEL) Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power -up or after any of the following instructions finished: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register. Block Protect Bits (BP2, BP1, BP0) The Block Protect Bits (BP2, BP1, BP0) are non -volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected. Top/Bottom Block Protect (TB) The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits. Sector/Block Protect (SEC) The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0. Complement Protect (CMP) The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protect ion set by SEC, TB, BP2, BP1 and BP0 will be reversed.

Publication Release Date: July 21, 2015 - 14 - Prelimry-Revision G For instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not; when CMP=1, the top 4KB sector will become unprotected while the rest of the array become read -only. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0. Status Register Protect (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). T he SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. SRP1 SRP0 /WP Status Register Description 0 0 X Software Protection /WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default] 0 1 0 Hardware Protected When /WP pin is low the Status Register locked and can not be written to. 0 1 1 Hardware Unprotected When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. 1 0 X Power Supply Lock-Down Status Register is protected and can not be written to again until the next power-down, power-up cycle.(1) 1 1 X One Time Program(2) Status Register is permanently protected and can not be written to. Note: 1. When SRP1, SRP0 = (1, 0), a power -down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available upon special order. Please contact Winbond for details. Erase/Program Suspend Status (SUS) The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle. Security Register Lock Bits (LB3, LB2, LB1) The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the Write Status Register instruction. LB3 -1 are One Time Programmable (OTP), once it’s set to 1, the corresponding 256-Byte Security Register will become read-only permanently.

Publication Release Date: July 21, 2015 - 15 - Prelimry-Revision G Quad Enable (QE) The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI operation. When the QE bit is set to a 0 state (factory default for part numbers with ordering options “IG”), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD functions are disabled. WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins are tied directly to the power supply or ground. Figure3a. Status Register-1 Figure3b. Status Register-2 S7 S6 S5 S4 S3 S2 S1 S0 SRP0 BP1 BP0 WEL BUSY WRITE ENABLE LATCH ERASE/WRITE IN PROGRESS S7 S6 S5 S4 S3 S2 S1 S0 BLOCK PROTECT BITS STATUS REGISTER PROTECT0 (Non-volatile) (volatile) BP2TBSEC (Non-volatile) TOP/BOTTOM PROTECT (Non-volatile) SECTOR PROTECT (Non-volatile) S15 S14 S13 S12 S11 S10 S9 S8 SUS CMP LB3 LB2 LB1 (R) QE SRP1 Status Register Protect 1 (Volatile/Non-Volatile Writable) Complement Protect (Volatile/Non-Volatile Writable) Security Register Lock Bits (Volatile/Non-Volatile OTP Writable) Reserved Quad Enable (Volatile/Non-Volatile Writable) Suspend Status (Status-Only)

Publication Release Date: July 21, 2015 - 16 - Prelimry-Revision G Status Register Memory Protection (CMP = 0) STATUS REGISTER(1) W25Q80DV (8M-BIT) MEMORY PROTECTION(2) SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 15 0F0000h – 0FFFFFh 64KB Upper 1/16 0 0 0 1 0 14 and 15 0E0000h – 0FFFFFh 128KB Upper 1/8 0 0 0 1 1 12 thru 15 0C0000h – 0FFFFFh 256KB Upper 1/4 0 0 1 0 0 8 thru 15 080000h – 0FFFFFh 512KB Upper 1/2 0 1 0 0 1 0 000000h – 00FFFFh 64KB Lower 1/16 0 1 0 1 0 0 and 1 000000h – 01FFFFh 128KB Lower 1/8 0 1 0 1 1 0 thru 3 000000h – 03FFFFh 256KB Lower 1/4 0 1 1 0 0 0 thru 7 000000h – 07FFFFh 512KB Lower 1/2 1 0 0 0 1 15 0FF000h – 0FFFFFh 4KB Upper 1/256 1 0 0 1 0 15 0FE000h – 0FFFFFh 8KB Upper 1/128 1 0 0 1 1 15 0FC000h – 0FFFFFh 16KB Upper 1/64 1 0 1 0 0 15 0F8000h – 0FFFFFh 32KB Upper 1/32 1 1 0 0 1 0 000000h – 000FFFh 4KB Lower 1/256 1 1 0 1 0 0 000000h – 001FFFh 8KB Lower 1/128 1 1 0 1 1 0 000000h – 003FFFh 16KB Lower 1/64 1 1 1 0 0 0 000000h – 007FFFh 32KB Lower 1/32 X X 1 1 1 0 thru 15 000000h – 0FFFFFh 1MB ALL Notes: 1. X = don’t care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.

Publication Release Date: July 21, 2015 - 17 - Prelimry-Revision G Status Register Memory Protection (CMP = 1) STATUS REGISTER(1) W25Q80DV (8M-BIT) MEMORY PROTECTION(2) SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION X X 0 0 0 0 thru 15 000000h – 0FFFFFh 1MB ALL 0 0 0 0 1 0 thru 14 000000h – 0EFFFFh 960KB Lower 15/16 0 0 0 1 0 0 thru 13 000000h – 0DFFFFh 896KB Lower 7/8 0 0 0 1 1 0 thru 11 000000h – 0BFFFFh 768KB Lower 3/4 0 0 1 0 0 0 thru 7 000000h – 07FFFFh 512KB Lower 1/2 0 1 0 0 1 1 thru 15 010000h – 0FFFFFh 960KB Upper 15/16 0 1 0 1 0 2 thru 15 020000h – 0FFFFFh 896KB Upper 7/8 0 1 0 1 1 4 thru 15 040000h – 0FFFFFh 768KB Upper 3/4 0 1 1 0 0 8 thru 15 080000h – 0FFFFFh 512KB Upper 1/2 1 0 0 0 1 0 thru 15 000000h – 0FEFFFh 1,020KB Lower 1 0 0 1 0 0 thru 15 000000h– 0FDFFFh 1,016KB Lower 1 0 0 1 1 0 thru 15 000000h – 0FBFFFh 1,008KB Lower 63/64 1 0 1 0 0 0 thru 15 000000h – 0F7FFFh 992KB Lower 31/32 1 1 0 0 1 0 thru 15 001000h – 0FFFFFh 1,020KB Upper 1 1 0 1 0 0 thru 15 002000h – 0FFFFFh 1,016KB Upper 1 1 0 1 1 0 thru 15 004000h – 0FFFFFh 1,008KB Upper 63/64 1 1 1 0 0 0 thru 15 008000h – 0FFFFFh 992KB Upper 31/32 X X 1 1 1 NONE NONE NONE NONE Notes: 1. X = don’t care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.

Publication Release Date: July 21, 2015 - 18 - Prelimry-Revision G 8. INSTRUCTIONS The instruction set of the W25Q80DV consists of 34 basic instructions that are fully controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in figures 4 through 3 9. All read instructions can be comp leted after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed.

8.1 Manufacturer and Device Identification

MANUFACTURER ID (MF7-MF0) Winbond Serial Flash EFh Device ID (ID7-ID0) (ID15-ID0) Instruction ABh, 90h, 92h, 94h 9Fh W25Q80DV 13h 4014h

Publication Release Date: July 21, 2015 - 19 - Prelimry-Revision G

8.2 Instruction Set Table 1 (Standard SPI Instructions)(1)

INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Write Enable 06h Volatile SR Write Enable 50h Write Disable 04h Read Status Register-1 05h (S7-S0)(2) Read Status Register-2 35h (S15-S8)(2) Write Status Register 01h (S7-S0) (S15-S8) Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3) Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0 Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0 Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0 Chip Erase C7h/60h Erase / Program Suspend 75h Erase / Program Resume 7Ah Power-down B9h Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0) Release Powerdown / ID(4) ABh dummy dummy dummy (ID7-ID0)(2) Manufacturer/Device ID(4) 90h dummy dummy 00h (MF7-MF0) (ID7-ID0) JEDEC ID(4) 9Fh (MF7-MF0) Manufacturer (ID15-ID8) Memory Type (ID7-ID0) Capacity Read Unique ID 4Bh dummy dummy dummy dummy (UID63-UID0) Read SFDP Register 5Ah A23-A16 A15-A8 A7-A0 Dummy (D7-D0) Erase Security Registers(5) 44h A23-A16 A15-A8 A7-A0 Program Security Registers(5) 42h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3) Read Security Registers(5) 48h A23-A16 A15-A8 A7-A0 dummy (D7-D0) Enable Reset 66h Reset 99h

Publication Release Date: July 21, 2015 - 20 - Prelimry-Revision G

8.3 Instruction Set Table 2 (Dual SPI Instructions)

INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …)(7) Fast Read Dual I/O BBh A23-A8(6) A7-A0, M7-M0 Manufacturer/Device ID by Dual I/O(4) 92h A23-A8(6) A7-A0, M7-M0 (6)(8)(11) (MF7-MF0, ID7-ID0)

8.4 Instruction Set Table 3 (Quad SPI Instructions)

INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Quad Page Program 32h A23-A16 A15-A8 A7-A0 D7-D0, …(9) D7-D0, …(3) Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …)(9) Fast Read Quad I/O EBh A23-A0, Set Burst with Wrap 77h xxxxxx, W6-W4(8) Manufacture/Device ID by Quad I/O(4) 94h A23-A0, M7-M0(8)(11) xxxx, (MF7-MF0, ID7-ID0) (MF7-MF0, ID7-ID0, …) Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data output from the device on either 1, 2 or 4 IO pins. 2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction. 3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. 4. Write Status Register-1 (01h) can also be used to program Status Register-1&2, see section 8.2.5. 5. Security Register Address: Security Register 1: A23 -16 = 00h; A15 -8 = 10h; A7 -0 = byte address Security Register 2: A23 -16 = 00h; A15 -8 = 20h; A7 -0 = byte address Security Register 3: A23 -16 = 00h; A15 -8 = 30h; A7 -0 = byte address 6. Dual SPI address input format: IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 7. Dual SPI data output format: IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 8. Quad SPI address input format: Set Burst with Wrap input format: IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO2 = x, x, x, x, x, x, W6, x IO3 = A23, A19, A15, A11, A7, A3, M7, M3 IO3 = x, x, x, x, x, x, x, x

Publication Release Date: July 21, 2015 - 21 - Prelimry-Revision G 9. Quad SPI data input/output format: 10. Fast Read Quad I/O data output format: IO0 = (x, x, x, x, D4, D0, D4, D0) IO1 = (x, x, x, x, D5, D1, D5, D1) IO2 = (x, x, x, x, D6, D2, D6, D2) IO3 = (x, x, x, x, D7, D3, D7, D3) 11. M[7:0] should be set to FFh

8.5 Instruction Descriptions

(DI) pin on the rising edge of CLK, and then driving /CS high. Figure 4. Write Enable Instruction Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram

Figure 6. Write Disable Instruction Sequence Diagram

SRP0, SRP1, QE, LB3-1, CMP and SUS bits (see Status Register section earlier in this datasheet). continuously, as shown in Figure 7. The instruction is completed by driving /CS high. Figure 7. Read Status Register Instruction Sequence Diagram

instruction as long as the clock continues. The instruction is completed by driving /CS high. (see AC Electrical Characteristics). Figure 9. Read Data Instruction Sequence Diagram

on the DO pin is a “don’t care”. Figure 10. Fast Read Instruction Sequence Diagram

segments to RAM for execution. Figure 11. Fast Read Dual Output Instruction Sequence Diagram

W25Q80DV at four times the rate of standard SPI devices. should be high-impedance prior to the falling edge of the first data out clock. Figure 12. Fast Read Quad Output Instruction Sequence Diagram

Publication Release Date: July 21, 2015 - 30 - Prelimry-Revision G Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. Figure 13a. Fast Read Dual I/O Instruction Sequence (M[7:0] =FFh) /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (BBh) 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 /CS CLK DI (IO0) DO (IO1) 32 33 34 35 36 37 38 39 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * IOs switch from Input to Output 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 16 17 18 20 21 2219 23 A23-16 A15-8 A7-0 M7-0 Byte 1 Byte 2 Byte 3 Byte 4 = MSB* *

Publication Release Date: July 21, 2015 - 31 - Prelimry-Revision G Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clock are required prior to the data output . The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction. Figure 14a. Fast Read Quad I/O Instruction Sequence (M[7:0] =FFh) Byte 1 Byte 2Byte 1 Byte 2

Publication Release Date: July 21, 2015 - 32 - Prelimry-Revision G Figure 14b. Fast Read Quad I/O Instruction Sequence (M[7:0] =FFh) Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” command prior to EBh. The “Set Burst with Wrap” command can either enable or disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64 -byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 -byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6 -4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6 -5 are used to specify the length of the wrap around section within a page. See 8.2.18 for detail descriptions.

Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. instruction sequence is shown in figure 15. Wrap bit W7 and the lower nibble W3-0 are not used. Figure 15. Set Burst with Wrap Instruction Sequence

improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. since the inherent page program time is much greater than the time it take to clock-in the data. Program instruction sequence is shown in Figure 20. Figure 20. Quad Input Page Program Instruction Sequence Diagram

Publication Release Date: July 21, 2015 - 36 - Prelimry-Revision G Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “20h” followed a 24 -bit sector address (A23 -A0) (see Figure 2). The Sector Erase instruction sequence is shown in figure 21a The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Sector Erase instruction will not be executed. After /CS is driven high, the self -timed Sector Erase instruction will commence for a time duration of t SE (See AC Characteristics). While the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 21a. Sector Erase Instruction Sequence Diagram /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (20h) High Impedance 8 9 29 30 31 24-Bit Address 23 22 2 1 0 Mode 0 Mode 3 = MSB*

Publication Release Date: July 21, 2015 - 37 - Prelimry-Revision G 32KB Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “52h” followed a 24 -bit block address (A23 -A0) (see Figure 2). The Block Erase instruction sequence is shown in Figure 22a. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self -timed Block Erase instruction will commence for a time duration of t BE1 (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 22a. 32KB Block Erase Instruction Sequence Diagram /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (52h) High Impedance 8 9 29 30 31 24-Bit Address 23 22 2 1 0 Mode 0 Mode 3 = MSB*

Block Erase instruction sequence is shown in figure 23. BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 23. 64KB Block Erase Instruction Sequence Diagram

instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure 24. Figure 24. Chip Erase Instruction

or blocks. The Erase/Program Suspend instruction sequence is shown in figure 25. preceding Resume instruction “7Ah”. erase/program suspend state. Figure 25. Erase/Program Suspend Instruction Sequence

Publication Release Date: July 21, 2015 - 41 - Prelimry-Revision G Erase / Program Resume (7Ah) The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction “7Ah” will be ignored by the device. The Erase/Program Resume instruction sequence is shown in figure 26. Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of “tSUS” following a previous Resume instruction. Figure 26a. Erase/Program Resume Instruction Sequence

“B9h” as shown in figure 27. Power-down / Device ID instruction, which restores the device to normal operation, will be recognized. with the standby current of ICC1. Figure 27. Deep Power-down Instruction Sequence Diagram

Publication Release Date: July 21, 2015 - 44 - Prelimry-Revision G Figure 28b. Release Power-down / Device ID Instruction Sequence Diagram tRES2 /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (ABh) High Impedance 8 9 29 30 31

3 Dummy Bytes

Power-down current Stand-by current= MSB*

ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. table. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. Figure 29. Read Manufacturer / Device ID Diagram

The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. a 24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock. Figure 30. Read Manufacturer / Device ID Dual I/O Diagram

1. The “Continuous Read Mode” bits M7-0 must be set to FFh to be compatible with Fast Read Dual I/O instruction.

The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction. a 24-bit address (A23-A0) of 000000h,but with the capability to input the Address bits four bits per clock. Figure 31. Read Manufacturer / Device ID Quad I/O Diagram

1. The “Continuous Read Mode” bits M7-0 must be set to FFh to be compatible with Fast Read Quad I/O instruction.

which, the 64-bit ID is shifted out on the falling edge of CLK as shown in figure 32. Figure 32. Read Unique ID Number Instruction Sequence

Publication Release Date: July 21, 2015 - 49 - Prelimry-Revision G Read JEDEC ID (9Fh) For compatibility reasons, the W25Q80DV provide several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15 -ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 3 3a. For memory type and capacity values refer to Manufacturer and Device Identification table. Figure 33a. Read JEDEC ID Instruction Sequence

Publication Release Date: July 21, 2015 - 50 - Prelimry-Revision G Read SFDP Register (5Ah) The W25Q80DV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about devices operational capability such as available commands, timing and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP standard initially established in 2010 for PC and other applications. Most Winbond SpiFlash Memories shipped after June 2011 (date code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet. The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code “5Ah” followed by a 24-bit address (A23-A0)(1) into the DI pin. Eight “dummy” clocks are also required before the SFDP register contents are shifted out on the falling edge of the 40 th CLK with most significant bit (MSB) first as shown in figure 34b. For SFDP register values and descriptions, please refer to the Winbond Application Note for SFDP Definition Table, Notes: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register Figure 34b. Read SFDP Register Instruction Sequence Diagram Instruction (5Ah)Instruction (5Ah)

important information separately from the main memory array. that register will be ignored (See 8.1.9 for detail descriptions). Figure 35. Erase Security Registers Instruction Sequence

is being sent to the device. Figure 36. Program Security Registers Instruction Sequence

D.C. to a maximum of FR (see AC Electrical Characteristics). Figure 37. Read Security Registers Instruction Sequence

Publication Release Date: July 21, 2015 - 54 - Prelimry-Revision G Enable Reset (66h) and Reset (99h) Because of the small package and the limitation on the number of pins, the W25Q80DV provide a software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going internal operations will be terminated and the d evice will return to its default power -on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Read parameter setting (P7 -P0), Wrap Bit setting (W6- W4). “Enable Reset (66h)” and “Reset (99h)” instructions can be issued to avoid accidental reset, both instructions must be issued in sequence. Any other commands other than “Reset (99h)” after the “Enable Reset (66h)” command will disable the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset command is accepted by the device, the device will take approximately tRST=30us to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. Figure 39a. Enable Reset and Reset Instruction Sequence Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (99h) Mode 0 Mode 3 /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (66h) High Impedance

Publication Release Date: July 21, 2015 - 55 - Prelimry-Revision G 9. ELECTRICAL CHARACTERISTICS

9.1 Absolute Maximum Ratings(1)(2)

PARAMETERS SYMBOL CONDITIONS RANGE UNIT Supply Voltage VCC –0.6 to VCC+0.6 V Voltage Applied to Any Pin VIO Relative to Ground –0.6 to VCC+0.4 V Transient Voltage on any Pin VIOT <20nS Transient Relative to Ground –2.0V to VCC+2.0V V Storage Temperature TSTG –65 to +150 °C Lead Temperature TLEAD See Note 3 °C Electrostatic Discharge Voltage VESD Human Body Model –2000 to +2000 V Notes: 1.This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage. 2.JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms). 3.Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.

9.2 Operating Ranges

PARAMETER SYMBOL CONDITIONS SPEC UNIT MIN MAX Supply Voltage VCC(1) FR = 104MHz, f R = 50MHz 2.7 3.6 V Ambient Temperature, Operating TA Industrial –40 +85 °C Note: 1.VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming (erase/write) voltage.

Publication Release Date: July 21, 2015 - 56 - Prelimry-Revision G

9.3 Power-up Timing and Write Inhibit Threshold(1)

VCC (min) to /CS Low tVSL 10 µs Time Delay Before Write Instruction tPUW 5 ms Write Inhibit Threshold Voltage VWI 1 2 V Note: 1. These parameters are characterized only. Figure 40a. Power-up Timing and Voltage Levels Figure 40b. Power-up, Power-Down Requirement

Publication Release Date: July 21, 2015 - 57 - Prelimry-Revision G

9.4 DC Electrical Characteristics

PARAMETER SYMBOL CONDITIONS SPEC UNIT MIN TYP MAX Input Capacitance CIN(1) VIN = 0V 6 pF Output Capacitance Cout(1) VOUT = 0V 8 pF Input Leakage ILI ±2 µA I/O Leakage ILO ±2 µA Standby Current Icc1 /CS = VCC, VIN = GND or VCC 10 50 µA Power-down Current Icc2 /CS = VCC, VIN = GND or VCC 1 5 µA Current Read Data / 50MHz Icc3(2) C = 0.1 VCC / 0.9 VCC DO = Open 7 15 mA Current Dual Output / Quad Output Read 80MHz Icc3(2) C = 0.1 VCC / 0.9 VCC DO = Open 10 20 mA Current Quad Output Read 104MHz Icc3(2) C = 0.1 VCC / 0.9 VCC DO = Open 12 25 mA Current Write Status Register Icc4 /CS = VCC 20 25 mA Current Page Program Icc5 /CS = VCC 20 25 mA Current Sector/Block Erase Icc6 /CS = VCC 20 25 mA Current Chip Erase Icc7 /CS = VCC 20 25 mA Input Low Voltage Vil -0.5 VCC x 0.3 V Input High Voltage Vih VCC x 0.7 V Output Low Voltage Vol Iol = 100 µA 0.2 V Output High Voltage Voh Ioh = –100 µA VCC – 0.2 V Notes: 1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3V. 2. Checker Board Pattern.

Publication Release Date: July 21, 2015 - 58 - Prelimry-Revision G

9.5 AC Measurement Conditions

Input Rise and Fall Times TR, TF 5 ns Input Pulse Voltages VIN 0.1 VCC to 0.9 VCC V Input Timing Reference Voltages IN 0.3 VCC to 0.7 VCC V Output Timing Reference Voltages OUT 0.5 VCC to 0.5 VCC V Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Input Levels

0.9 VCC

0.1 VCC

0.5 VCC

AC Measurement I/O Waveform

Publication Release Date: July 21, 2015 - 59 - Prelimry-Revision G

9.6 AC Electrical Characteristics

DESCRIPTION: SYMBOL ALT SPEC UNIT MIN TYP MAX Clock frequency for all other instructions 2.7V-3.6V VCC & Industrial Temperature FR fC1 D.C. 104 MHz Clock frequency for Read Data instruction(03h) 2.7-3.6V fR fC3 D.C. 50 MHz Clock High, Low Time for all instructions except for Read Data (03h) tCLH, tCLL(1) 4 ns Clock High, Low Time for Read Data (03h) instruction tCRLH, tCRLL(1) 6 ns Clock Rise Time peak to peak tCLCH(2) 0.1 V/ns Clock Fall Time peak to peak tCHCL(2) 0.1 V/ns /CS Active Setup Time relative to CLK tSLCH tCSS 5 ns /CS Not Active Hold Time relative to CLK tCHSL 5 ns Data In Setup Time tDVCH tDSU 2 ns Data In Hold Time tCHDX tDH 3 ns /CS Active Hold Time relative to CLK tCHSH 3 ns /CS Not Active Setup Time relative to CLK tSHCH 3 ns /CS Deselect Time tSHSL tCSH 50 ns Output Disable Time tSHQZ(2) tDIS 7 ns Clock Low to Output Valid tCLQV tV 6 ns Output Hold Time tCLQX tHO 0 ns /HOLD Active Setup Time relative to CLK tHLCH 5 ns /HOLD Active Hold Time relative to CLK tCHHH 5 ns Continued – next page

Publication Release Date: July 21, 2015 - 60 - Prelimry-Revision G DESCRIPTION SYMBOL ALT SPEC UN IT MIN TYP MAX /HOLD Not Active Setup Time relative to CLK tHHCH 5 ns /HOLD Not Active Hold Time relative to CLK tCHHL 5 ns /HOLD to Output Low-Z tHHQX(2) tLZ 7 ns /HOLD to Output High-Z tHLQZ(2) tHZ 12 ns Write Protect Setup Time Before /CS Low tWHSL(3) 20 ns Write Protect Hold Time After /CS High tSHWL(3) 100 ns /CS High to Power-down Mode tDP(2) 3 µs /CS High to Standby Mode without ID Read tRES1(2) 3 µs /CS High to Standby Mode with ID Read tRES2(2) 1.8 µs /CS High to next Instruction after Suspend tSUS(2) 20 µs /CS High to next Instruction after Reset tRST(2) 30 µs Write Status Register Time tW 10 15 ms Byte Program Time (First Byte) tBP1(4) 15 30 µs Additional Byte Program Time (After First Byte) tBP2(4) 2.5 5 µs Page Program Time tPP 0.8 3 ms Sector Erase Time (4KB) tSE 45 300 ms Block Erase Time (32KB) tBE1 120 800 ms Block Erase Time (64KB) tBE2 150 1000 ms Chip Erase Time tCE 2 6 s Note: 1. Clock high + Clock low must be less than or equal to 1/fC. 2. Value guaranteed by design and/or characterization, not 100% tested in production. 3. Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1). 4. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes programmed. 5. 4-bytes address alignment for Quad Read Conmmand, Address[1,0]=0.

Publication Release Date: July 21, 2015 - 61 - Prelimry-Revision G

9.7 Serial Output Timing

9.8 Serial Input Timing

9.9 Hold Timing

9.10 /WP Timing /CS CLK IO output tCLQX tCLQV tCLQX tCLQV tSHQZtCLL LSB OUT tCLH MSB OUT /CS CLK IO input tCHSL MSB IN tSLCH tDVCH tCHDX tSHCHtCHSH tCLCH tCHCL LSB IN tSHSL /CS CLK IO output /HOLD tCHHL tHLCH tCHHH tHHCH tHLQZ tHHQX IO input /CS CLK /WP tWHSL tSHWL IO input Write Status Register is allowed Write Status Register is not allowed

Publication Release Date: July 21, 2015 - 62 - Prelimry-Revision G 10. PACKAGE SPECIFICATION 10.1 8-Pin SOIC8 150-mil (Package Code SN) SYMBOL MILLIMETERS INCHES Min Nom Max Min Nom Max e 1.27BSC 0.050BSC Notes: 1. Controlling dimensions: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches.

Publication Release Date: July 21, 2015 - 63 - Prelimry-Revision G 10.2 8-Pin SOIC8 208-mil (Package Code SS) SYMBOL MILLIMETERS INCHES Min Nom Max Min Nom Max e(2) 1.27 BSC. 0.050 BSC. Notes: 1. Controlling dimensions: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches. θ GAUGE PLANE θ GAUGE PLANE

Publication Release Date: July 21, 2015 - 64 - Prelimry-Revision G 10.3 8-Pin VSOP8 150-mil (Package Code SV) SYMBOL MILLIMETER INCHES MIN TYP. MAX MIN TYP. MAX A1 0.00 0.05 ― 0.00 0.002 ― b 0.33 ― 0.51 0.33 ― 0.020 c 0.125 BSC 0.005 BSC e 1.27BSC 0.050 BSC Notes: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include inter -lead flash or protrusions. Inter -lead flash and protrusions shall not exceed 0.25mm per side.

Publication Release Date: July 21, 2015 - 65 - Prelimry-Revision G 10.4 8-Pad WSON 6x5mm (Package Code ZP) SYMBOL MILLIMETERS INCHES Min Nom Max Min Nom Max e (2) 1.27 BSC. 0.050 BSC. Notes: 1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under th pad.

Publication Release Date: July 21, 2015 - 66 - Prelimry-Revision G 10.5 8-Pad USON 2x3x0.6-mm^³ (Package Code UX, W25Q80DVUXIE)

Publication Release Date: July 21, 2015 - 67 - Prelimry-Revision G 10.6 8-Pin PDIP 300-mil (Package Code DA) SYMBOL MILLIMETERS INCHES Min Nom Max Min Nom Max E 7.62 BSC. 0.300 BSC.

Publication Release Date: July 21, 2015 - 68 - Prelimry-Revision G 10.7 8-Ball WLCSP (Package Code BY) Note: Dimension b is measured at the maximum solder bump diameter, parallel to primary datum C. SYMBOL MILLIMETERS INCHES Min Nom Max Min Nom Max aaa 0.100 0.0040 bbb 0.100 0.0040 ccc 0.030 0.0012 ddd 0.150 0.0060

Publication Release Date: July 21, 2015 - 69 - Prelimry-Revision G

10.8 Ordering Information

Notes: 1. The “W” prefix is not included on the part marking. 2. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 3. For shipments with OTP feature enabled, please contact Winbond. 4. Only the 2nd letter is used for the part marking.WSON package type ZP is not used for the part marking. USON package type UX has special top marking due to size limitation. W(1) 25Q 80D V xx W = Winbond 25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 80D = 8M-bit V = 2.7V to 3.6V SN = SOIC-8 150-mil SV = 8 -pin VSOP 150-mil ZP = WSON-8 6x5-mm SS = SOIC -8 208-mil UX = 8 -pad USON 2x3-mm DA = PDIP-8 300-mil BY = 8 -ball WLCSP I = Industrial Grade (-40°C to +85°C) (2,3,4) G = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) E = Green Package with Extended Pad G = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) I

Publication Release Date: July 21, 2015 - 70 - Prelimry-Revision G

10.9 Valid Part Numbers and Top Side Marking

The following table provides the valid part numbers for the W25Q80DV SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 12-digit Product Number for or dering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 10-digit number. Part Numbers for Industrial Grade Temperature(1): PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING SN SOIC-8 150mil 8M-bit W25Q80DVSNIG 25Q80DVNIG SS SOIC-8 208mil 8M-bit W25Q80DVSSIG 25Q80DVSIG SV VSOP-8 150mil 8M-bit W25Q80DVSVIG 25Q80DVVIG ZP(1) WSON-8 6x5mm 8M-bit W25Q80DVZPIG 25Q80DVIG UX USON-8 2x3x0.6(max.)mm³ 8M-bit W25Q80DVUXIE(3) 8Nyww(4) 0Exxxx DA PDIP-8 300mil 8M-bit W25Q80DVDAIG 25Q80DVAIG BY WLCSP-8 8M-bit W25Q80DVBYIG 3CD(5) Xx Note: 1. WSON package type ZP is not used in the top side marking. 2. These Package types are Special Order only, please contact Winbond for more information. 3. E is for extended pad 4. y: year; ww: week; xxxx: lot-id 5. Xx is date code

Publication Release Date: July 21, 2015 - 71 - Prelimry-Revision G 11. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A 2013/10/24 All New Create Preliminary B 2013/12/13 All Removed “ Preliminary” C 2014/05/22 5-7,68-69 Updated VSOP-150mil Removed unaviable package information D 2014/07/29 5-7,65-68 Updated USON 2x3mm E 2014/12/16 5-8,68-70 Updated WLCSP package information F 2015/02/11 68 Updated WLCSP POD G 2015/07/21 62 Updated SOIC8 150-mil POD Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.