ICS18051 ICST | Alldatasheet

Document overview

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Technical content

Features

  • Pin and function compatible to Cypress W180-51
  • Packaged in 8-pin SOIC
  • Provides a spread spectrum output clock
  • Accepts a clock input and provides same frequency dithered output
  • Input frequency of 8 to 28 MHz
  • Peak reduction by 7dB - 14dB typical on 3rd - 19th odd harmonics
  • Spread percentage selection for +/-0.625% and +/-1.875%
  • Operating voltage of 3.3 V and 5 V
  • Advanced, low-power CMOS process Block Diagram PLL Clock Synthesis and Spread Spectrum Circuitry SS% CLK GND VDD FS2:1 X1/CLKIN Clock Buffer/ Crystal Oscillator

Integrated Circuit Systemsl 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201l www.icst.com Pin Assignment Spread Spectrum Select Table 0 = connect to GND 1 = connect directly to VDD Note: SS% pin has an internal pull-up resistor Frequency Range Selection Table Pin Descriptions X1/CLKIN GND FS1 SS% VDD CLKOUT FS2 8 pin (150 mil) SOIC SS% (Pin 4) Spread Direction Spread Percentage (%) Center +/-0.625% Center +/1.875% FS2 (Pin 8) FS1 (Pin 7) Frequency Range Selection (MHz) 8-10 10-15 15-18 18-28 Pin Number Pin Name Pin Type Pin Description X1/CLKIN Input Crystal or Clock Input. Output Crystal output. Float for a clock input. GND Power Connect to ground. SS% Input Select pin for spread amount. See table above. Internal pull-up resistor. CLKOUT Output Spread spectrum clock output per table above. VDD Power Connect to 3.3 V or 5 V. FS1 Input Select pin for input frequency. See table above. Internal pull-up resistor. FS2 Input Select pin for input frequency. See table above. Internal pull-up resistor.

Integrated Circuit Systemsl 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201l www.icst.com External Components The ICS180-51 requires a minimum number of external components for proper operation. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between VDD and GND on pins 6 and 3, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. value of these capacitors is given by the following equation: PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS180-51. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS180-51. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C Parameter Min. Typ. Max. Units Ambient Operating Temperature +70 Power Supply Voltage (measured in respect to GND) +3.135 +5.5 V

Integrated Circuit Systemsl 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201l www.icst.com Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70°C Unless stated otherwise, VDD = 5 V, ±10%, Ambient Temperature 0 to +70°C Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.135 3.465 V Supply Current IDD No load mA Input High Voltage VIH 2.4 V Input Low Voltage VIL 0.8 V Output High Voltage VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -15 mA 2.4 V Output Low Voltage VOL IOL = 15 mA 0.4 V Input Capacitance CIN pF Output Impedance Rout ohms Input Pull-up Resistor 500 KΩ Power-up Time First locked clock cycle after steady power ms Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 4.5 5.5 V Supply Current IDD No load mA Input High Voltage VIH 0.7VDD V Input Low Voltage VIL 0.15VDD V Output High Voltage VOH IOH = -24 mA 2.4 V Output Low Voltage VOL IOL = 24 mA 0.4 V Output Impedance Rout ohms Input Capacitance CIN pF Input Pull-up Resistor 500 KΩ Power-up Time First locked clock cycle after steady power ms

Integrated Circuit Systemsl 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201l www.icst.com Unless stated otherwise, VDD = 3.3 V±5% or 5 V±10%, Ambient Temperature 0 to +70° C, CL=15 pf Note 1: Measured with 15 pF load Thermal Characteristics Marking Diagram Marking Diagram (Pb free) Notes: 2. YYWW is the last two digits of the year and week that the part was assembled. 3. “LF” denotes Pb (lead) free package. 4. Bottom marking: country of origin. Parameter Symbol Conditions Min. Typ. Max. Units Input/Output Clock Frequency MHz Input Clock Duty Cycle Time above VDD/2 Output Clock Duty Cycle Note 1 Output Rise Time tOR 0.8 to 2.4 V, note 1 ns Output Fall Time tOF 2.4 to 0.8 V, note 1 ns Jitter Cycle-to-cycle 250 300 ps Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 150 °C/W θJA 1 m/s air flow 140 °C/W θJA 3 m/s air flow 120 °C/W Thermal Resistance Junction to Case θJC °C/W 180M-51 YYWW 180M51LF YYWW

Integrated Circuit Systemsl 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201l www.icst.com Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

“LF” denotes Pb free packaging. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping packaging Package Temperature ICS180M-51 see page 5 Tubes 8-pin SOIC 0 to +70° C ICS180M-51T Tape and Reel 8-pin SOIC 0 to +70° C ICS180M-51LF Tubes 8-pin SOIC 0 to +70° C ICS180M-51LFT Tape and Reel 8-pin SOIC 0 to +70° C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 0.10 0.25 .0040 .0098 B 0.33 0.51 .013 .020 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e

1.27 BASIC

0.050 BASIC

H 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 L 0.40 1.27 .016 .050 α