ESP32-C61 overview
ESP32-C61 is a component documented by ESPRESSIF SYSTEMS (SHAN. The PDF description identifies it as "32-bit RISC-V single-core microprocessor 2.4 GHz Wi-Fi 6 (IEEE 802.11ax) v1.0." This guide condenses the most useful engineering information from the available PDF so that designers and sourcing teams can identify the checks that still need confirmation in the original document.
Datasheet snapshot
- Manufacturer: ESPRESSIF SYSTEMS (SHAN...
- Part number: ESP32-C61
- Category: Microcontroller
- Datasheet length: 73 Pages
Key features noted in the PDF
- 1T1R in 2.4 GHz single band
- Operating frequency: 2412~ 2484 MHz
- IEEE 802.11ax-compliant – 20 MHz-only non-AP mode – Uplink and downlink OFDMA to enhance connectivity and performance in congested environments for IoT applications – Downlink MU.
- Fully compatible with IEEE 802.11b/g/n protocol – 20 MHz and 40 MHz bandwidth – Data rate up to 150 Mbps – Wi-Fi Multimedia (WMM) – TX/RX A-MPDU, TX/RX A-MSDU – Immediate Block AC.
- Bluetooth LE: Bluetooth Core 6.0 certified
- Bluetooth mesh 1.1
- High power mode (20 dBm)
Applications listed in the PDF
- Smart Home
- Industrial Automation
- Health Care
- Consumer Electronics
- Smart Agriculture
- POS Machines
Specifications and operating details
The following points were extracted from the PDF text. Check the associated conditions, notes and limits in the complete document before using a value in a design.
- ESP32-C61 integrates 2.4 GHz Wi-Fi 6 and Bluetooth® Low Energy (Bluetooth LE).
- Espressif Systems 2 ESP32-C61 Series Datasheet v1.0 1T1R in 2.4 GHz single band Operating frequency: 2412~ 2484 MHz IEEE 802.11ax-compliant – 20 MHz-only non-AP mode – Uplink and downlink OFDMA to enhance connectivity and performance in co.
- Except for GPIO12 and GPIO13 whose default drive strength is 40 mA, the default drive strength for all the other pins is 20 mA.
- Analog Signals Routed to Analog Functions Pin Function Signal Description ADC1_CHn ADC1 channeln signal ADC1 channeln interface XTAL_32K_N Negative clock signal The differential clock input of the chip, connecting to the 32 kHz differentia.
- Voltage Regulators Voltage Regulator Output Power Supply HP 1.1 V HP power domain LP 1.1 V LP power domain Espressif Systems 24 ESP32-C61 Series Datasheet v1.0 VDDPST1 VDDPST2 VDDA1 VDDA2 Analog VDD_SPI LP IO HP IO RSPI C61/C31 VDDA3 VDDA4.
- Feature List Five-stage pipeline that supports an operating clock frequency up to 160 MHz RV32IMAC ISA (instruction set architecture) Zc extensions (Zcb, Zcmp, and Zcmt) Two-cycle pipelined multiplier and radix-4 SRT divider Compatible wit.
- Espressif Systems 36 ESP32-C61 Series Datasheet v1.0 High-speed clocks for HP system – 40 MHz external crystal clock Note: * ESP32-C61 cannot operate without the external crystal clock. * ESP32-C61 can automatically filter out high-frequen.
Topics covered by the datasheet
The document includes sections related to:
- Datasheet sections
- Features
- Applications
- Revision History
Engineering review checklist
- Confirm supply rails, clock limits, memory size, peripheral mapping and I/O voltage compatibility.
- Check package pinout, boot configuration, programming interface and silicon-revision errata.
- Budget decoupling, thermal margin, startup timing and firmware recovery behavior before release.
Always confirm values against the latest manufacturer-controlled datasheet, especially when qualifying a substitute or releasing a production BOM.
View the complete PDF and model record
Open the ESP32-C61 datasheet and model details to review the complete PDF, document pages and available product information.
Source attribution
Adapted from the PDF associated with this DigiCamel model page.
Source model URL: https://www.digicamel.com/product.php?slug=esp32-c61-espressif-systems-shan