DRA80M overview
DRA80M is a component documented by Texas Instruments. The PDF description identifies it as "Infotainment Applications Processor Silicon Revision 1.0." This guide condenses the most useful engineering information from the available PDF so that designers and sourcing teams can identify the checks that still need confirmation in the original document.
Datasheet snapshot
- Manufacturer: Texas Instruments
- Part number: DRA80M
- Category: IC
- Datasheet length: 278 Pages
Key features noted in the PDF
- Quad-Core Arm® Cortex®-A53 Microprocessor Subsystem at up to 1.1 GHz – Two Dual-Core Cortex-A53 Clusters with 512KB L2 Cache Including SECDED – Each A53 Core has 32KB L1 ICache an.
- Dual-Core Arm Cortex-R5F at up to 400 MHz – Supports Lockstep Mode – 16KB ICache, 16KB DCache, and 64KB RAM per R5F Core Ethernet Subsystem:
- Three Industrial Subsystem with Ethernet support: – Two 10/100/1000 Ethernet Ports per Subsystem – Supports Two 10/100/1000 SGMII Ports (1) – Compatibility with 10/100Mb Memory Su.
- Up to 2MB of On-Chip L3 RAM with SECDED
- Multi-Core Shared Memory Controller (MSMC) – Up to 2MB (2 banks × 1MB) SRAM with SECDED – Shared Coherent Level 2 or Level 3 Memory- Mapped SRAM – Shared Coherent Level 3 Cache –.
- DDR Subsystem (DDRSS) – Supports DDR3L/DDR4 Memory Types up to DDR-1600 – Supports LPDDR4 Memory Type up to DDR- 1333 – 32-Bit Data Bus and 7-Bit SECDED Bus – 32GB of Total Addres.
- General-Purpose Memory Controller (GPMC) Safety:
Applications listed in the PDF
- Automotive Gateway
- Automotive Telematics
- Automotive V2X
- Vehicle Computing
- Other General Use
- Supports dynamic clock gating on all logic units
Specifications and operating details
The following points were extracted from the PDF text. Check the associated conditions, notes and limits in the complete document before using a value in a design.
- DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 DRA80xMInfotainmentApplicationsProcessor SiliconRevision1.0 1Processor Cores: Quad-Core Arm® Cortex®-A53 Microprocessor Subsystem at up to 1.1 GHz – Two Dual-Core Cortex-A53 Clusters with 51.
- Device Information PART NUMBER PACKAGE BODY SIZE DRA804M (784-Pin) S-PBGA 23.0 mm × 23.0 mm DRA802M (784-Pin) S-PBGA 23.0 mm × 23.0 mm ADVANCE□INFORMATION Interconnect Media & Data Storage Audio Peripherals General Connectivity Automotive.
- ADC0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_ADC0_REFN ADC Reference Input (negative) A K2 MCU_ADC0_REFP ADC Reference Input (positive) A K3 MCU_ADC0_AIN0 ADC Analog Input 0 A K5 MCU_ADC0_AIN1 ADC Anal.
- ADC1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_ADC1_REFN ADC Reference Input (negative) A H3 MCU_ADC1_REFP ADC Reference Input (positive) A H2 MCU_ADC1_AIN0 ADC Analog Input 0 A F4 MCU_ADC1_AIN1 ADC Anal.
- No external voltage should be applied to this pin. (2) An external 240Ω ±1% resistor must be connected between this pin and VSS.
- 0x0 = USB3, 0x1 = PCIe0 Lane0, 0x2 = ICSS2 SGMII Lane0. (2) The required resistor value is 3kΩ ±1%.
- 0x0 = PCIe1 Lane0, 0x1 = PCIe0 Lane1, 0x2 = ICSS2 SGMII Lane1. (2) The required resistor value is 3kΩ ±1%.
Topics covered by the datasheet
The document includes sections related to:
- Features
- applications
Engineering review checklist
- Confirm supply rails, clock limits, memory size, peripheral mapping and I/O voltage compatibility.
- Check package pinout, boot configuration, programming interface and silicon-revision errata.
- Budget decoupling, thermal margin, startup timing and firmware recovery behavior before release.
Always confirm values against the latest manufacturer-controlled datasheet, especially when qualifying a substitute or releasing a production BOM.
View the complete PDF and model record
Open the DRA80M datasheet and model details to review the complete PDF, document pages and available product information.
Source attribution
Adapted from the PDF associated with this DigiCamel model page.
Source model URL: https://www.digicamel.com/product.php?slug=dra80m-texas-instruments