DRA80M

Texas Instruments

Infotainment Applications Processor Silicon Revision 1.0

Manufacturer: Texas Instruments

Document: 278 Pages / 2Mb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse D parts

Online Datasheet

Read DRA80M online.

DRA80M TI1 | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 278

Technical content

ADVANCE□INFORMATION Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 DRA80xMInfotainmentApplicationsProcessor SiliconRevision1.0

1 Device Overview

1.1 Features

1Processor Cores:

Quad-Core Arm® Cortex®-A53 Microprocessor Subsystem at up to 1.1 GHz – Two Dual-Core Cortex-A53 Clusters with 512KB L2 Cache Including SECDED – Each A53 Core has 32KB L1 ICache and 32K L1 DCache
Dual-Core Arm Cortex-R5F at up to 400 MHz – Supports Lockstep Mode – 16KB ICache, 16KB DCache, and 64KB RAM per R5F Core Ethernet Subsystem:
Three Industrial Subsystem with Ethernet support: – Two 10/100/1000 Ethernet Ports per Subsystem – Supports Two 10/100/1000 SGMII Ports (1) – Compatibility with 10/100Mb Memory Subsystem:
Up to 2MB of On-Chip L3 RAM with SECDED
Multi-Core Shared Memory Controller (MSMC) – Up to 2MB (2 banks × 1MB) SRAM with SECDED – Shared Coherent Level 2 or Level 3 Memory- Mapped SRAM – Shared Coherent Level 3 Cache – 256-Bit Processor Port Bus and 40-Bit Physical Address Bus – Coherent Unified Bi-Directional Interfaces to Connect to Processors or Device Masters – L2, L3 Cache Pre-Warming and Post Flushing – Bandwidth Management with Starvation Bound – One Infrastructure Master Interface – Single External Memory Master Interface – Supports Distributed Virtual System – Supports Internal DMA Engine – DRU (Data Routing Unit) – ECC Error Protection
DDR Subsystem (DDRSS) – Supports DDR3L/DDR4 Memory Types up to DDR-1600 – Supports LPDDR4 Memory Type up to DDR- 1333 – 32-Bit Data Bus and 7-Bit SECDED Bus – 32GB of Total Addressable Space
General-Purpose Memory Controller (GPMC) Safety:
DRA80xM Helps System Designers Address Safety Requirements – The Dual Cortex-R5F System is Undergoing Assessment to be Certified at TÜV SÜD According to ISO 26262, Targeting ASIL-D – The A53 Cores and Entire System on Chip (SoC) is Undergoing Assessment to be Certified at TÜV SÜD According to ISO 26262, Targeting ASIL-B – ECC or Parity on Calculation-Critical Memories – ECC and Parity on Internal Bus Interconnect – Firewalls to Help Provide Freedom From Interference (FFI) – Built-In Self-Test (BIST) for CPU, High-End Timers, and On-Chip RAM – Hardware Error Injection Support for Test-for- Diagnostics – Error Signaling Modules (ESM) for Capture of Safety Related Errors – Voltage, Temperature, and Clock Monitoring – Windowed and Non-Windowed Watchdog Timers in Multiple Clock Domains
MCU Island – Isolation of the Dual-Core Arm Cortex-R5F Microprocessor Subsystem to Help Provide Freedom From Interference (FFI) – Separate Voltage, Clocks, Resets, and Dedicated Peripherals – Internal MCSPI Connection to the Rest of SoC Security:
Secure Boot Supported – Hardware-Enforced Root-of-Trust – Support to Switch Root-of-Trust via Backup Key – Support for Takeover Protection, IP Protection, and Anti-Roll Back Protection
Cryptographic Acceleration Supported – Session-Aware Cryptographic Engine with Ability to Auto-Switch Key-Material Based on Incoming Data Stream – Supports Cryptographic Cores – AES – 128/192/256 Bits Key Sizes – 3DES – 56/112/168 Bits Key Sizes – MD5, SHA1 – SHA2 – 224/256/384/512

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Device Overview Copyright © 2018, Texas Instruments Incorporated – DRBG with True Random Number Generator – PKA (Public Key Accelerator) to Assist in RSA/ECC Processing – DMA Support

Debugging Security – Secure Software Controlled Debug Access – Security Aware Debugging
Trusted Execution Environment (TEE) Supported – Arm TrustZone® Based TEE – Extensive Firewall Support for Isolation – Secure DMA Path and Interconnect – Secure Watchdog/Timer/IPC
Secure Storage Support
On-the-Fly Encryption and Authentication Support for OSPI Interface
Networking Security Support for Data (Payload) Encryption/Authentication via Packet Based Hardware Cryptographic Engine
Security Co-Processor (DMSC) for Key and Security Management, with Dedicated Device Level Interconnect for Security SoC Services:
Device Management Security Controller (DMSC) – Centralized SoC System Controller – Manages System Services Including Initial Boot, Security, Safety and Clock/Reset/Power Management – Power Management Controller for Active and Low Power Modes – Communication with Various Processing Units over Message Manager – Simplified Interface for Optimizing Unused Peripherals – Tracing and Debugging Capability
Sixteen 32-Bit General-Purpose Timers
Two Data Movement and Control Navigator Subsystems (NAVSS) – Ring Accelerator (RA) – Unified DMA (UDMA) – Up to 2 Timer Managers (TM) (1024 Timers Each) High-Speed Interfaces:
One Gigabit Ethernet (CPSW) Interface Supporting – RMII (10/100) or RGMII (10/100/1000) – IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP – Audio/Video Bridging (P802.1Qav/D6.0) – Energy-Efficient Ethernet (802.3az) – Jumbo Frames (2024 bytes) – Clause 45 MDIO PHY Management
Two PCI-Express® Revision 3.1 Subsystems (1) – Supports Gen3 (8.0GT/s) Operation – Two Independent 1-lane, or a Single 2-lane Port – Support for Concurrent Root-Complex and/or End-Point Operation
USB 3.1 Dual-Role Device Subsystem (1) – One Enhanced SuperSpeed Gen1 Port – One USB 2.0 Port – Each Port Independently Configurable as USB Host, USB Peripheral, or USB Dual-Role Device General Connectivity:
6× Inter-Integrated Circuit (I2C) Ports
5× Configurable UART/IrDA/CIR Modules
Two Simultaneous Flash Interfaces Configured – Two OSPI™ Flash Interfaces – or Hyperbus™ and OSPI1 Flash Interface
2× 12-Bit Analog-to-Digital Converters (ADC) – Up to 4 Msamples/s – Eight Multiplexed Analog Inputs
8× Multichannel Serial Peripheral Interfaces (MCSPI) Controllers – Two with Internal Connections – Six with External Interfaces
General-Purpose I/O (GPIO) Pins Automotive Interfaces:
2× Modular Controller Area Network (MCAN) Modules with Full CAN-FD Support Audio Interfaces:
3× Multichannel Audio Serial Port (MCASP) Modules Media and Data Storage:
2× MultiMedia Card/Secure Digital (MMC/SD) Interfaces Simplified Power Management:
Simplified Power Sequence with Full Support for Dual Voltage I/O
Integrated LDOs Reduces Power Solution Complexity
Integrated SDIO LDO for Handling Automatic Voltage Transition for SD Interface
Integrated POR (Power on Reset) Generation Reducing Power Solution Complexity
Integrated Voltage Supervisor for Safety Monitoring
Integrated Power Supply Glitch Detector for Detecting Fast Power Supply Transients Analog/System Integration:
Integrated USB VBUS Detection
Fail Safe I/O for DDR RESET
All I/O Pins Drivers Disabled During Reset to Avoid Bus Conflicts
Default I/O Pulls Disabled During Reset to Avoid System Conflicts
Support Dynamic I/O Pinmux Configuration Change System on Chip (SoC) Architecture:

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Device OverviewCopyright © 2018, Texas Instruments Incorporated

Supports Primary Boot from UART, I2C, MCSPI, HyperBus, Parallel NOR Flash, SD or eMMC, USB, PCIe, and Ethernet Interfaces
28-nm CMOS Technology
23 mm × 23 mm, 0.8-mm Pitch, 784-Pin S-PBGA (ACD)

1.2 Applications

Automotive Gateway
Automotive Telematics
Automotive V2X
Vehicle Computing
Other General Use

1.3 Description

Automobiles are becoming more and more connected - both inside the car, within the various subsystems / domains as well as with the outside world, with connectivity via Bluetooth, LTE, WiFi etc. Much more information and data are being shared or transferred between the various domains; for example, video from rear and surround view cameras for displayed in the head unit; data from the chassis is sent to the on-board diagnostic unit, etc. As the amount of data that has to be integrated and transported between the various domains in a time sensitive manner has increased, car manufacturers are looking to include a network gateway, based on Ethernet protocols, in cars. Such gateways should be able to handle multiple connectivity protocols such as CAN, CAN-FD, TCP/IP to name a few. TI’s DRA80x family of products enable automotive manufacturers to build scalable and cost optimized network gateway features in cars, thanks to its high level of integration and purpose built peripherals, such as Gigabit Ethernet MACs. DRA80x Automotive Gateway processors are built to meet the intense processing needs of automotive gateway. The DRA80x family of devices combines four or two Arm® Cortex-A53 cores with an ASIL-C capable dual Cortex-R5 MCU subsystem and six Gigabit Ethernet MACs in the MAIN domain and one Gigabit Ethernet MAC in the MCU domain to create an SoC capable of implementing an Automotive Gateway system with plenty of automotive connectivity and functional safety processing. The four A53 cores are arranged in two dual-core clusters with shared L2 memory to create two processing channels to address additional safety concepts. Extensive ECC is included for on-chip memory and interconnects for reliability. Cryptographic acceleration and secure boot are available on DRA80x devices, in addition to granular whitelist firewalls managed by a security controller core. Programmability is provided by the quad-core Arm Cortex-A53 RISC CPUs with Neon™ extension, and the dual Cortex-R5 MCU subsystem is available for general purpose use. The Ethernet subsystem can be used to provide up to six ports of Ethernets, including TSN, for standard Ethernet connectivity. Additionally, TI provides a complete set of development tools for the Arm cores including C compilers and a debugging interface for visibility into source code execution. Safety documentation is available for applications needing to meet functional safety standards. Device Information PART NUMBER PACKAGE BODY SIZE DRA804M (784-Pin) S-PBGA 23.0 mm × 23.0 mm DRA802M (784-Pin) S-PBGA 23.0 mm × 23.0 mm

ADVANCE□INFORMATION Interconnect Media & Data Storage Audio Peripherals General Connectivity Automotive Interfaces intro_001 DRA80x 2x MMC/SD 3x MCASP PCIe® 2x Single/1x Dual Lane Gen 3 (3) GPIO 1x USB 2.0 DRD High-Speed Serial Interfaces 4x UART 5x MCSPI (2) Copyright © 2018, Texas Instruments Incorporated 5x I2C 2x ADC (1) 2x Arm® Cortex –A53® 512KB L2 with ECC Memory Subsystem DDRSS with ECCGPMC Navigator Subsystem MCU Island 2x Arm Cortex -R5F 1x USB 3.1 DRD 2x RTI/WWDT System Services 12x GP Timers PDMA Debug PDMA 2x Arm® Cortex –A53® 512KB L2 with ECC DMSC Security Accelerators AESAES AESPKA AESMD5 AESSHA AESDRBG AES3DES 2x OSPI or 1x OSPI + 1x Hyperbus (1) MSMC 2MB SRAM with ECC ELM 3x MCSPI (1)(2) 1x UART (1) 1x I2C (1) 2x MCAN-FD (1) (With optional Lockstep) 10/100/1000 Ethernet (1) PDMA4x RTI/WWDT UDMA Proxy 2x PVU CPTS RA MCRC INTR 12x Mailbox Spinlock 3x INTA 2x TIMER_MGR Channelized FW Navigator Subsystem UDMA Proxy MCRC RA INTR INTA Channelized FW 2x RTI/WWDT 4x GP TimersPDMA ESM Scratchpad RAM 512B MCU_MSRAM 512KB ESM Ethernet Subsystem 3x PRU_ICSSG (3) (Up to 6x Ethernet ports) (3) DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Device Overview Copyright © 2018, Texas Instruments Incorporated

1.4 Functional Block Diagram

Figure 1-1 is functional block diagram for the device. (1) This interface is located on the MCU Island but is available for the full system to access. (2) One port is internally connected only; not connected to any pins. (3) SGMII, USB3.1 and PCIe share a total of two SerDes lanes. Figure 1-1. DRA80x Block Diagram

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Table of ContentsCopyright © 2018, Texas Instruments Incorporated Table of Contents

5.8 VPP Specifications for One-Time Programmable

7.3 High Speed Differential Signal Routing Guidance. 265

7.5 Power Distribution Network Implementation

8.5 Receiving Notification of Documentation Updates. 275

9 Mechanical Packaging and Orderable

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Revision History Copyright © 2018, Texas Instruments Incorporated

2 Revision History

Changes from July 16, 2018 to October 15, 2018 (from A Revision (July 2018) to B Revision) Page

Updated MCAN Signal Descriptions in Table 4-21, MCAN0 Signal Descriptions and Table 4-22, MCAN1 Signal

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Device ComparisonCopyright © 2018, Texas Instruments Incorporated

3 Device Comparison

Table 3-1 shows a comparison between devices, highlighting the differences. Table 3-1. Device Comparison FEATURES REFERENCE NAME DRA804M DRA802M

Features

CTRLMMR_WKUP_JTAG_DEVICE_ID[31:11] DEVICE_ID register bitfield value (4) DRA804M: 0x161FC DRA802M: 0x161BC PROCESSORS AND ACCELERATORS Speed Grades See Table 5-1 Arm Cortex-A53 Microprocessor Subsystem Arm A53 Quad Core Dual Core Dual-Core Arm Cortex-R5F Arm R5F Yes (optional lockstep(3)) Device Management Security Controller DMSC Yes Safety Features Safety Optional(3) PROGRAM AND DATA STORAGE On-Chip Shared Memory (RAM) MCU_MSRAM 512KB Multicore Shared Memory Controller MSMC 2MB (On-Chip Shared SRAM with ECC) DDR3L/DDR4/LPDDR4 DDR Subsystem DDRSS Up to 32GB (32-Bit data) SECDED 7-Bit General-Purpose Memory Controller GPMC Up to 1GB with ECC Error Location Module ELM Yes PERIPHERALS Modular Controller Area Network Interface MCAN 2 Peripheral Direct Memory Access PDMA Yes Navigator Subsystem NAVSS 2 General-Purpose I/O GPIO Up to 242 Inter-Integrated Circuit Interface I2C 6 Analog-to-Digital Converter ADC 2 Multichannel Serial Peripheral Interface MCSPI 8 Multichannel Audio Serial Port MCASP0 16 Serializers MCASP1 10 Serializers MCASP2 4 Serializers MultiMedia Card/ Secure Digital Interface MMCSD0 8-bits MMCSD1 4-bits Flash Subsystem (FSS) OSPI0 8-bits (2) OSPI1 4-bits HyperBus Yes (2) Security Accelerator SA Yes Error Signalling Module ESM Yes 2x PCI Express 3.1 Port with Integrated PHY PCIE0 Up to Two Lanes (1) PCIE1 Single Lane (1) 3x Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (Ethernet Subsystem) PRU_ICSSG0 Yes (2× RGMII) PRU_ICSSG1 Yes (2× RGMII) PRU_ICSSG2 Yes (2× RGMII, 2× SGMII (1)) Gigabit Ethernet Interface CPSW RMII or RGMII General-Purpose Timers TIMER 16 Universal Asynchronous Receiver and Transmitter UART 5

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Device Comparison Copyright © 2018, Texas Instruments Incorporated Table 3-1. Device Comparison (continued) FEATURES REFERENCE NAME DRA804M DRA802M Universal Serial Bus (USB3.1) SuperSpeed Dual-Role-Device (DRD) Ports with SS PHY USB0 Yes(1) Universal Serial Bus (USB2.0) HighSpeed Dual-Role-Device (DRD) Ports with HS/FS PHY USB1 Yes (1) SGMII0, SGMII1, USB3.1, PCIE0, and PCIE1 share total of two SerDes lanes. (2) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1. (3) Device supports features to aid in functional safety system designs such as lockstep Arm R5F if the part number is designated with the F option. (4) For more details about the CTRLMMR_WKUP_JTAG_DEVICE_ID register and DEVICE_ID bitfield, see the AM65x/DRA80xM Technical Reference Manual.

3.1 Related Products

Companion Products for DRA80x Review products that are frequently purchased or used in conjunction with this product. Reference Designs for DRA80x TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump-start your system design, all TI Designs include schematic or block diagrams, BOMs and design files to speed your time to market. Search and download designs at ti.com/tidesigns.

ADVANCE□INFORMATION C E G J L N R U W AA AC D F H K M P T V Y AB AD A B AE AG AF AH DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated

4 Terminal Configuration and Functions

4.1 Pin Diagram

The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt is made to use "ball" only when referring to the physical package. Figure 4-1 shows the ball locations for the 784 plastic ball grid array (S-PBGA) package that are used in conjunction with Table 4-1 through to locate signal names and ball grid numbers. Figure 4-1. ACD S-PBGA-N784 Package (Bottom View)

4.2 Pin Attributes

Table 4-1 describes the terminal characteristics and the signals multiplexed on each ball.

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] P17 CAP_VDDAR_CORE0 CAP_VDDAR_CORE0 CAP V17 CAP_VDDAR_CORE1 CAP_VDDAR_CORE1 CAP W16 CAP_VDDAR_CORE2 CAP_VDDAR_CORE2 CAP M14 CAP_VDDAR_CORE3 CAP_VDDAR_CORE3 CAP L15 CAP_VDDAR_CORE4 CAP_VDDAR_CORE4 CAP U10 CAP_VDDAR_MCU CAP_VDDAR_MCU CAP M12 CAP_VDDAR_MPU0_0 CAP_VDDAR_MPU0_0 CAP N12 CAP_VDDAR_MPU0_1 CAP_VDDAR_MPU0_1 CAP N18 CAP_VDDAR_MPU1_0 CAP_VDDAR_MPU1_0 CAP N15 CAP_VDDAR_MPU1_1 CAP_VDDAR_MPU1_1 CAP Y10 CAP_VDDAR_WKUP CAP_VDDAR_WKUP CAP AA8 CAP_VDDA_1P8_IOLDO_WKUP CAP_VDDA_1P8_IOLDO_WKUP CAP J17 CAP_VDDA_1P8_SDIO CAP_VDDA_1P8_SDIO CAP G19 CAP_VDDA_1P8_IOLDO0 CAP_VDDA_1P8_IOLDO0 CAP Y19 CAP_VDDA_1P8_IOLDO1 CAP_VDDA_1P8_IOLDO1 CAP H18 CAP_VDDSHV_SDIO CAP_VDDSHV_SDIO CAP V9 CAP_VDD_WKUP CAP_VDD_WKUP CAP A10 DDR_AC0 DDR_AC0 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D9 DDR_AC1 DDR_AC1 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C9 DDR_AC2 DDR_AC2 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E9 DDR_AC3 DDR_AC3 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A9 DDR_AC4 DDR_AC4 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E8 DDR_AC5 DDR_AC5 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD F8 DDR_AC6 DDR_AC6 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C7 DDR_AC7 DDR_AC7 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C8 DDR_AC8 DDR_AC8 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D7 DDR_AC9 DDR_AC9 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E7 DDR_AC10 DDR_AC10 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A6 DDR_AC11 DDR_AC11 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] F7 DDR_AC12 DDR_AC12 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D6 DDR_AC13 DDR_AC13 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C6 DDR_AC14 DDR_AC14 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD F6 DDR_AC15 DDR_AC15 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E6 DDR_AC16 DDR_AC16 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E5 DDR_AC17 DDR_AC17 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D8 DDR_AC18 DDR_AC18 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D10 DDR_AC19 DDR_AC19 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E10 DDR_AC20 DDR_AC20 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C10 DDR_AC21 DDR_AC21 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD F11 DDR_AC22 DDR_AC22 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B10 DDR_AC23 DDR_AC23 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D11 DDR_AC24 DDR_AC24 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B11 DDR_AC25 DDR_AC25 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C11 DDR_AC26 DDR_AC26 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E11 DDR_AC27 DDR_AC27 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E12 DDR_AC28 DDR_AC28 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D12 DDR_AC29 DDR_AC29 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D5 DDR_ALERTn DDR_ALERTn IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B8 DDR_CK0N DDR_CK0N IO drive 1 (OFF) 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A8 DDR_CK0P DDR_CK0P IO drive 0 (OFF) 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B7 DDR_CK1N DDR_CK1N IO drive 1 (OFF) 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A7 DDR_CK1P DDR_CK1P IO drive 0 (OFF) 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] E1 DDR_DM0 DDR_DM0 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C5 DDR_DM1 DDR_DM1 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D14 DDR_DM2 DDR_DM2 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B17 DDR_DM3 DDR_DM3 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A3 DDR_DQ0 DDR_DQ0 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B2 DDR_DQ1 DDR_DQ1 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C2 DDR_DQ2 DDR_DQ2 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D2 DDR_DQ3 DDR_DQ3 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E2 DDR_DQ4 DDR_DQ4 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD G1 DDR_DQ5 DDR_DQ5 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD F2 DDR_DQ6 DDR_DQ6 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD F1 DDR_DQ7 DDR_DQ7 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E3 DDR_DQ8 DDR_DQ8 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C3 DDR_DQ9 DDR_DQ9 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D3 DDR_DQ10 DDR_DQ10 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B3 DDR_DQ11 DDR_DQ11 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D4 DDR_DQ12 DDR_DQ12 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C4 DDR_DQ13 DDR_DQ13 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B4 DDR_DQ14 DDR_DQ14 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B5 DDR_DQ15 DDR_DQ15 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E13 DDR_DQ16 DDR_DQ16 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C14 DDR_DQ17 DDR_DQ17 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B14 DDR_DQ18 DDR_DQ18 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] A14 DDR_DQ19 DDR_DQ19 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E14 DDR_DQ20 DDR_DQ20 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B13 DDR_DQ21 DDR_DQ21 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C13 DDR_DQ22 DDR_DQ22 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D13 DDR_DQ23 DDR_DQ23 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D15 DDR_DQ24 DDR_DQ24 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C15 DDR_DQ25 DDR_DQ25 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E16 DDR_DQ26 DDR_DQ26 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E15 DDR_DQ27 DDR_DQ27 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D16 DDR_DQ28 DDR_DQ28 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B16 DDR_DQ29 DDR_DQ29 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C16 DDR_DQ30 DDR_DQ30 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A17 DDR_DQ31 DDR_DQ31 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C1 DDR_DQS0N DDR_DQS0N IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D1 DDR_DQS0P DDR_DQS0P IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A4 DDR_DQS1N DDR_DQS1N IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A5 DDR_DQS1P DDR_DQS1P IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A12 DDR_DQS2N DDR_DQS2N IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A13 DDR_DQS2P DDR_DQS2P IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A16 DDR_DQS3N DDR_DQS3N IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A15 DDR_DQS3P DDR_DQS3P IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B19 DDR_ECC_D0 DDR_ECC_D0 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD B18 DDR_ECC_D1 DDR_ECC_D1 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] C18 DDR_ECC_D2 DDR_ECC_D2 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D18 DDR_ECC_D3 DDR_ECC_D3 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E18 DDR_ECC_D4 DDR_ECC_D4 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD E17 DDR_ECC_D5 DDR_ECC_D5 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD D17 DDR_ECC_D6 DDR_ECC_D6 IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD C17 DDR_ECC_DM DDR_ECC_DM IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A18 DDR_ECC_DQSN DDR_ECC_DQSN IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD A19 DDR_ECC_DQSP DDR_ECC_DQSP IO OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD F16 DDR_FS_RESETn DDR_FS_RESETn IO drive 0 (OFF) 1.1 V/1.2 V/1.35 V VDDS_DDR LVCMOS PD A11 DDR_RESETn DDR_RESETn IO drive 0 (OFF) 1.1 V/1.2 V/1.35 V VDDS_DDR DDR PU/PD F12 DDR_VREF0 DDR_VREF0 A OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR F15 DDR_VREF_ZQ DDR_VREF_ZQ A OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR F13 DDR_VTP DDR_VTP A OFF 1.1 V/1.2 V/1.35 V VDDS_DDR DDR D21 ECAP0_IN_APWM_OUT SYNC0_OUT 1 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1 CPTS0_RFT_CLK 2 I 0 GPIO1_86 7 IO 0 AA2 EMU0 EMU0 0 IO PU 0 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 1/1 AA1 EMU1 EMU1 0 IO PU 0 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 1/1 A22 EXT_REFCLK1 EXT_REFCLK1 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1 SYNC1_OUT 1 O GPIO1_87 7 IO 0 P25 GPMC0_ADVn_ALE GPMC0_ADVn_ALE 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/1 GPIO0_17 7 IO 0 BOOTMODE16 Bootstrap I 0 R28 GPMC0_CLK GPMC0_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 GPIO0_16 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] M25 GPMC0_AD7 GPMC0_AD7 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/1 GPIO0_7 7 IO 0 BOOTMODE07 Bootstrap I 0 N23 GPMC0_AD8 GPMC0_AD8 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/1 PRG2_PRU0_GPO12 3 IO 0 PRG2_PRU0_GPI12 4 I 0 PRG2_PWM2_A0 5 IO 0 GPIO0_8 7 IO 0 BOOTMODE08 Bootstrap I 0 M26 GPMC0_AD9 GPMC0_AD9 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/1 PRG2_PRU0_GPO13 3 IO 0 PRG2_PRU0_GPI13 4 I 0 PRG2_PWM2_B0 5 IO 1 GPIO0_9 7 IO 0 BOOTMODE09 Bootstrap I 0 P28 GPMC0_AD10 GPMC0_AD10 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/1 PRG2_PRU0_GPO14 3 IO 0 PRG2_PRU0_GPI14 4 I 0 PRG2_PWM0_TZ_IN 6 I 0 GPIO0_10 7 IO 0 BOOTMODE10 Bootstrap I 0 P27 GPMC0_AD11 GPMC0_AD11 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/1 PRG2_PRU0_GPO15 3 IO 0 PRG2_PRU0_GPI15 4 I 0 PRG2_PWM2_A1 5 IO 0 GPIO0_11 7 IO 0 BOOTMODE11 Bootstrap I 0 N26 GPMC0_AD12 GPMC0_AD12 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/1 PRG2_PRU1_GPO12 3 IO 0 PRG2_PRU1_GPI12 4 I 0 PRG2_PWM2_B1 5 IO 1 GPIO0_12 7 IO 0 BOOTMODE12 Bootstrap I 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] R25 GPMC0_CSn2 GPMC0_CSn2 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0/1 GPMC0_A27 3 OZ PRG2_IEP1_EDC_LATCH_IN1 4 I 0 I2C2_SDA 5 IOD 1 PRG2_IEP0_EDIO_DATA_IN_OUT30 6 IO 0 GPIO0_28 7 IO 0 T27 GPMC0_CSn3 GPMC0_CSn3 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0/1 GPMC0_A26 3 OZ PRG2_IEP1_EDC_SYNC_OUT1 4 O I2C2_SCL 5 IOD 1 PRG2_IEP0_EDIO_DATA_IN_OUT31 6 IO 0 GPIO0_29 7 IO 0 R26 GPMC0_WAIT0 GPMC0_WAIT0 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 0/1 GPIO0_22 7 IO 0 R23 GPMC0_WAIT1 GPMC0_WAIT1 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 0/1 PRG2_PWM1_A0 3 IO 0 PRG2_IEP1_EDC_LATCH_IN0 4 I 0 TIMER_IO3 5 IO 0 PRG2_IEP0_EDIO_DATA_IN_OUT28 6 IO 0 GPIO0_23 7 IO 0 D20 I2C0_SCL I2C0_SCL 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS- FS PU/PD 1 1/1 C21 I2C0_SDA I2C0_SDA 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS- FS PU/PD 1 1/1 B21 I2C1_SCL I2C1_SCL 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS- FS PU/PD 1 1/1 CPTS0_HW1TSPUSH 1 I 0 E21 I2C1_SDA I2C1_SDA 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS- FS PU/PD 1 1/1 CPTS0_HW2TSPUSH 1 I 0 K2 MCU_ADC0_REFN MCU_ADC0_REFN A OFF 1.8 V VDDA_ADC_MC U Analog K3 MCU_ADC0_REFP MCU_ADC0_REFP A OFF 1.8 V VDDA_ADC_MC U Analog H3 MCU_ADC1_REFN MCU_ADC1_REFN A OFF 1.8 V VDDA_ADC_MC U Analog H2 MCU_ADC1_REFP MCU_ADC1_REFP A OFF 1.8 V VDDA_ADC_MC U Analog K5 MCU_ADC0_AIN0 MCU_ADC0_AIN0 A OFF 1.8 V VDDA_ADC_MC U Analog J3 MCU_ADC0_AIN1 MCU_ADC0_AIN1 A OFF 1.8 V VDDA_ADC_MC U Analog

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] J1 MCU_ADC0_AIN2 MCU_ADC0_AIN2 A OFF 1.8 V VDDA_ADC_MC U Analog J5 MCU_ADC0_AIN3 MCU_ADC0_AIN3 A OFF 1.8 V VDDA_ADC_MC U Analog K4 MCU_ADC0_AIN4 MCU_ADC0_AIN4 A OFF 1.8 V VDDA_ADC_MC U Analog J4 MCU_ADC0_AIN5 MCU_ADC0_AIN5 A OFF 1.8 V VDDA_ADC_MC U Analog J2 MCU_ADC0_AIN6 MCU_ADC0_AIN6 A OFF 1.8 V VDDA_ADC_MC U Analog J6 MCU_ADC0_AIN7 MCU_ADC0_AIN7 A OFF 1.8 V VDDA_ADC_MC U Analog F4 MCU_ADC1_AIN0 MCU_ADC1_AIN0 A OFF 1.8 V VDDA_ADC_MC U Analog G6 MCU_ADC1_AIN1 MCU_ADC1_AIN1 A OFF 1.8 V VDDA_ADC_MC U Analog G4 MCU_ADC1_AIN2 MCU_ADC1_AIN2 A OFF 1.8 V VDDA_ADC_MC U Analog H5 MCU_ADC1_AIN3 MCU_ADC1_AIN3 A OFF 1.8 V VDDA_ADC_MC U Analog F5 MCU_ADC1_AIN4 MCU_ADC1_AIN4 A OFF 1.8 V VDDA_ADC_MC U Analog G5 MCU_ADC1_AIN5 MCU_ADC1_AIN5 A OFF 1.8 V VDDA_ADC_MC U Analog G3 MCU_ADC1_AIN6 MCU_ADC1_AIN6 A OFF 1.8 V VDDA_ADC_MC U Analog H4 MCU_ADC1_AIN7 MCU_ADC1_AIN7 A OFF 1.8 V VDDA_ADC_MC U Analog V5 MCU_BYP_POR MCU_BYP_POR I OFF 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS AD8 MCU_I2C0_SCL MCU_I2C0_SCL 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_WKU P Yes I2C OPEN DRAIN 1 1/0 AD7 MCU_I2C0_SDA MCU_I2C0_SDA 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_WKU P Yes I2C OPEN DRAIN 1 1/0 W2 MCU_MCAN0_RX MCU_MCAN0_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0 0/1 WKUP_GPIO0_55 7 IO 0 W1 MCU_MCAN0_TX MCU_MCAN0_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0 0/1 WKUP_GPIO0_54 7 IO 0 L1 MCU_MDIO0_MDC MCU_MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0/1 WKUP_GPIO0_47 7 IO 0 L4 MCU_MDIO0_MDIO MCU_MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0 0/1 WKUP_GPIO0_46 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] V1 MCU_OSPI0_CLK MCU_OSPI0_CLK 0 O OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0/1 MCU_HYPERBUS0_CK 1 O WKUP_GPIO0_12 7 IO 0 U2 MCU_OSPI0_DQS MCU_OSPI0_DQS 0 I OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_RWDS 1 IO 0 WKUP_GPIO0_14 7 IO 0 U1 MCU_OSPI0_LBCLKO MCU_OSPI0_LBCLKO 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0/1 MCU_HYPERBUS0_CKn 1 O WKUP_GPIO0_13 7 IO 0 T1 MCU_OSPI1_CLK MCU_OSPI1_CLK 0 O OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0/1 WKUP_GPIO0_25 7 IO 0 P2 MCU_OSPI1_DQS MCU_OSPI1_DQS 0 I OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_OSPI0_CSn3 1 O MCU_HYPERBUS0_INTn 2 I 1 WKUP_GPIO0_27 7 IO 0 R1 MCU_OSPI1_LBCLKO MCU_OSPI1_LBCLKO 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_OSPI0_CSn2 1 O MCU_HYPERBUS0_RESETOn 2 I 1 WKUP_GPIO0_26 7 IO 0 R4 MCU_OSPI0_CSn0 MCU_OSPI0_CSn0 0 O OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0/1 MCU_HYPERBUS0_CSn0 1 O WKUP_GPIO0_23 7 IO 0 R5 MCU_OSPI0_CSn1 MCU_OSPI0_CSn1 0 O OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0/1 MCU_HYPERBUS0_RESETn 1 O WKUP_GPIO0_24 7 IO 0 U4 MCU_OSPI0_D0 MCU_OSPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ0 1 IO 0 WKUP_GPIO0_15 7 IO 0 U5 MCU_OSPI0_D1 MCU_OSPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ1 1 IO 0 WKUP_GPIO0_16 7 IO 0 T2 MCU_OSPI0_D2 MCU_OSPI0_D2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ2 1 IO 0 WKUP_GPIO0_17 7 IO 0 T3 MCU_OSPI0_D3 MCU_OSPI0_D3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ3 1 IO 0 WKUP_GPIO0_18 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] T4 MCU_OSPI0_D4 MCU_OSPI0_D4 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ4 1 IO 0 WKUP_GPIO0_19 7 IO 0 T5 MCU_OSPI0_D5 MCU_OSPI0_D5 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ5 1 IO 0 WKUP_GPIO0_20 7 IO 0 R2 MCU_OSPI0_D6 MCU_OSPI0_D6 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ6 1 IO 0 WKUP_GPIO0_21 7 IO 0 R3 MCU_OSPI0_D7 MCU_OSPI0_D7 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ7 1 IO 0 WKUP_GPIO0_22 7 IO 0 N2 MCU_OSPI1_CSn0 MCU_OSPI1_CSn0 0 O OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0/1 WKUP_GPIO0_32 7 IO 0 N3 MCU_OSPI1_CSn1 MCU_OSPI1_CSn1 0 O OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0/1 MCU_HYPERBUS0_WPn 1 O MCU_TIMER_IO0 2 IO 0 MCU_HYPERBUS0_CSn1 3 O MCU_UART0_RTSn 4 O MCU_SPI0_CS2 5 IO 1 WKUP_GPIO0_33 7 IO 0 P3 MCU_OSPI1_D0 MCU_OSPI1_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 WKUP_GPIO0_28 7 IO 0 P4 MCU_OSPI1_D1 MCU_OSPI1_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_UART0_RXD 4 I 1 MCU_SPI1_CS1 5 IO 1 WKUP_GPIO0_29 7 IO 0 P5 MCU_OSPI1_D2 MCU_OSPI1_D2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_UART0_TXD 4 O MCU_SPI1_CS2 5 IO 1 WKUP_GPIO0_30 7 IO 0 P1 MCU_OSPI1_D3 MCU_OSPI1_D3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_UART0_CTSn 4 I 1 MCU_SPI0_CS1 5 IO 1 WKUP_GPIO0_31 7 IO 0 W5 MCU_PORz MCU_PORz I OFF 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] V2 MCU_PORz_OUT MCU_PORz_OUT 0 O OFF 0 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0/0 V3 MCU_RESETSTATz MCU_RESETSTATz 0 O OFF 0 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0/0 W4 MCU_RESETz MCU_RESETz 0 I PU 0 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 1/1 M1 MCU_RGMII1_RXC MCU_RGMII1_RXC 0 I OFF 7 1.8 V/3.3 V VDDSHV2_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_RMII1_REF_CLK 1 I 0 WKUP_GPIO0_41 7 IO 0 N5 MCU_RGMII1_RX_CTL MCU_RGMII1_RX_CTL 0 I OFF 7 1.8 V/3.3 V VDDSHV2_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_RMII1_RX_ER 1 I 0 WKUP_GPIO0_35 7 IO 0 N1 MCU_RGMII1_TXC MCU_RGMII1_TXC 0 IO OFF 7 1.8 V/3.3 V VDDSHV2_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_RMII1_TX_EN 1 O WKUP_GPIO0_40 7 IO 0 N4 MCU_RGMII1_TX_CTL MCU_RGMII1_TX_CTL 0 O OFF 7 1.8 V/3.3 V VDDSHV2_WKU P Yes LVCMOS PU/PD 0/1 MCU_RMII1_CRS_DV 1 I 0 WKUP_GPIO0_34 7 IO 0 L6 MCU_RGMII1_RD0 MCU_RGMII1_RD0 0 I OFF 7 1.8 V/3.3 V VDDSHV2_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_RMII1_RXD0 1 I 0 WKUP_GPIO0_45 7 IO 0 M6 MCU_RGMII1_RD1 MCU_RGMII1_RD1 0 I OFF 7 1.8 V/3.3 V VDDSHV2_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_RMII1_RXD1 1 I 0 WKUP_GPIO0_44 7 IO 0 L5 MCU_RGMII1_RD2 MCU_RGMII1_RD2 0 I OFF 7 1.8 V/3.3 V VDDSHV2_WKU P Yes LVCMOS PU/PD 0 0/1 WKUP_GPIO0_43 7 IO 0 L2 MCU_RGMII1_RD3 MCU_RGMII1_RD3 0 I OFF 7 1.8 V/3.3 V VDDSHV2_WKU P Yes LVCMOS PU/PD 0 0/1 WKUP_GPIO0_42 7 IO 0 M5 MCU_RGMII1_TD0 MCU_RGMII1_TD0 0 O OFF 7 1.8 V/3.3 V VDDSHV2_WKU P Yes LVCMOS PU/PD 0/1 MCU_RMII1_TXD0 1 O WKUP_GPIO0_39 7 IO 0 M4 MCU_RGMII1_TD1 MCU_RGMII1_TD1 0 O OFF 7 1.8 V/3.3 V VDDSHV2_WKU P Yes LVCMOS PU/PD 0/1 MCU_RMII1_TXD1 1 O WKUP_GPIO0_38 7 IO 0 M3 MCU_RGMII1_TD2 MCU_RGMII1_TD2 0 O OFF 7 1.8 V/3.3 V VDDSHV2_WKU P Yes LVCMOS PU/PD 0/1 WKUP_GPIO0_37 7 IO 0 M2 MCU_RGMII1_TD3 MCU_RGMII1_TD3 0 O OFF 7 1.8 V/3.3 V VDDSHV2_WKU P Yes LVCMOS PU/PD 0/1 WKUP_GPIO0_36 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] W3 MCU_SAFETY_ERRORn MCU_SAFETY_ERRORn 0 IO PD 0 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 1/0 Y1 MCU_SPI0_CLK MCU_SPI0_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0 1/1 WKUP_GPIO0_48 7 IO 0 MCU_BOOTMODE06 Bootstrap I 0 Y4 MCU_SPI0_CS0 MCU_SPI0_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 1 0/1 WKUP_GPIO0_51 7 IO 0 Y3 MCU_SPI0_D0 MCU_SPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0 1/1 WKUP_GPIO0_49 7 IO 0 MCU_BOOTMODE07 Bootstrap I 0 Y2 MCU_SPI0_D1 MCU_SPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0 1/1 WKUP_GPIO0_50 7 IO 0 MCU_BOOTMODE05 Bootstrap I 0 D24 MMC0_CALPAD MMC0_CALPAD A OFF 1.8 V/3.3 V VDDSHV6 UHS-I (8bit PHY) B25 MMC0_CLK MMC0_CLK 0 O PD 7 1.8 V/3.3 V VDDSHV6 UHS-I (8bit PHY) PU/PD 1 GPIO1_10 7 O 0 B27 MMC0_CMD MMC0_CMD 0 IO PU 7 1.8 V/3.3 V VDDSHV6 UHS-I (8bit PHY) PU/PD 1 GPIO1_11 7 IO 0 C25 MMC0_DS MMC0_DS 0 I PD 7 1.8 V/3.3 V VDDSHV6 UHS-I (8bit PHY) PU/PD 1 GPIO1_12 7 I 0 A23 MMC0_SDCD MMC0_SDCD 0 I OFF 7 1.8 V/3.3 V VDDSHV6 Yes LVCMOS PU/PD 1 0/1 PRG2_IEP0_EDIO_OUTVALID 6 O GPIO1_13 7 IO 0 B23 MMC0_SDWP MMC0_SDWP 0 I OFF 7 1.8 V/3.3 V VDDSHV6 Yes LVCMOS PU/PD 1 0/1 GPIO1_14 7 IO 0 F23 MMC1_CALPAD MMC1_CALPAD A OFF 1.8 V/3.3 V VDDSHV7 UHS-I (4bit PHY) C27 MMC1_CLK MMC1_CLK 0 O PD 7 1.8 V/3.3 V VDDSHV7 UHS-I (4bit PHY) PU/PD 1 GPIO1_77 7 O 0 C28 MMC1_CMD MMC1_CMD 0 IO PU 7 1.8 V/3.3 V VDDSHV7 UHS-I (4bit PHY) PU/PD 1 GPIO1_78 7 IO 0 B24 MMC1_SDCD MMC1_SDCD 0 I OFF 7 1.8 V/3.3 V VDDSHV7 Yes LVCMOS PU/PD 1 0/1 GPIO1_79 7 IO 0 C24 MMC1_SDWP MMC1_SDWP 0 I OFF 7 1.8 V/3.3 V VDDSHV7 Yes LVCMOS PU/PD 1 0/1 GPIO1_80 7 IO 0 A26 MMC0_DAT0 MMC0_DAT0 0 IO PU 7 1.8 V/3.3 V VDDSHV6 UHS-I (8bit PHY) PU/PD 1 GPIO1_9 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] E25 MMC0_DAT1 MMC0_DAT1 0 IO PU 7 1.8 V/3.3 V VDDSHV6 UHS-I (8bit PHY) PU/PD 1 GPIO1_8 7 IO 0 C26 MMC0_DAT2 MMC0_DAT2 0 IO PU 7 1.8 V/3.3 V VDDSHV6 UHS-I (8bit PHY) PU/PD 1 GPIO1_7 7 IO 0 A25 MMC0_DAT3 MMC0_DAT3 0 IO PU 7 1.8 V/3.3 V VDDSHV6 UHS-I (8bit PHY) PU/PD 1 GPIO1_6 7 IO 0 E24 MMC0_DAT4 MMC0_DAT4 0 IO PU 7 1.8 V/3.3 V VDDSHV6 UHS-I (8bit PHY) PU/PD 1 UART0_RIN 1 I 1 GPIO1_5 7 IO 0 A24 MMC0_DAT5 MMC0_DAT5 0 IO PU 7 1.8 V/3.3 V VDDSHV6 UHS-I (8bit PHY) PU/PD 1 UART0_DTRn 1 O GPIO1_4 7 IO 0 B26 MMC0_DAT6 MMC0_DAT6 0 IO PU 7 1.8 V/3.3 V VDDSHV6 UHS-I (8bit PHY) PU/PD 1 UART0_DSRn 1 I 1 GPIO1_3 7 IO 0 D25 MMC0_DAT7 MMC0_DAT7 0 IO PU 7 1.8 V/3.3 V VDDSHV6 UHS-I (8bit PHY) PU/PD 1 UART0_DCDn 1 I 1 GPIO1_2 7 IO 0 D28 MMC1_DAT0 MMC1_DAT0 0 IO PU 7 1.8 V/3.3 V VDDSHV7 UHS-I (4bit PHY) PU/PD 1 GPIO1_76 7 IO 0 E27 MMC1_DAT1 MMC1_DAT1 0 IO PU 7 1.8 V/3.3 V VDDSHV7 UHS-I (4bit PHY) PU/PD 1 GPIO1_75 7 IO 0 D26 MMC1_DAT2 MMC1_DAT2 0 IO PU 7 1.8 V/3.3 V VDDSHV7 UHS-I (4bit PHY) PU/PD 1 GPIO1_74 7 IO 0 D27 MMC1_DAT3 MMC1_DAT3 0 IO PU 7 1.8 V/3.3 V VDDSHV7 UHS-I (4bit PHY) PU/PD 1 GPIO1_73 7 IO 0 F18 NMIn NMIn 0 I PU 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS- FS PU/PD 1 1/1 PRG2_PWM1_TZ_IN 6 I 0 L25 OLDI0_CLKN OLDI0_CLKN IO OFF 1.8 V VDDA_1P8_OLD OLDI_LVDS K25 OLDI0_CLKP OLDI0_CLKP IO OFF 1.8 V VDDA_1P8_OLD OLDI_LVDS J28 OLDI0_A0N OLDI0_A0N IO OFF 1.8 V VDDA_1P8_OLD OLDI_LVDS K28 OLDI0_A0P OLDI0_A0P IO OFF 1.8 V VDDA_1P8_OLD OLDI_LVDS L27 OLDI0_A1N OLDI0_A1N IO OFF 1.8 V VDDA_1P8_OLD OLDI_LVDS

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] W24 PRG0_PRU0_GPO2 PRG0_PRU0_GPO2 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI2 1 I 0 PRG0_RGMII1_RD2 2 I 0 PRG0_PWM2_A0 3 IO 0 MCASP0_ACLKR 5 IO 0 GPIO1_31 7 IO 0 AA27 PRG0_PRU0_GPO3 PRG0_PRU0_GPO3 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI3 1 I 0 PRG0_RGMII1_RD3 2 I 0 PRG0_PWM3_A2 3 IO 0 MCASP0_AFSR 5 IO 0 GPIO1_32 7 IO 0 Y24 PRG0_PRU0_GPO4 PRG0_PRU0_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI4 1 I 0 PRG0_RGMII1_RX_CTL 2 I 0 PRG0_PWM2_B0 3 IO 1 MCASP0_AXR0 5 IO 0 GPIO1_33 7 IO 0 V28 PRG0_PRU0_GPO5 PRG0_PRU0_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI5 1 I 0 PRG0_PWM3_B2 3 IO 1 MCASP0_AXR1 5 IO 0 GPIO1_34 7 IO 0 Y25 PRG0_PRU0_GPO6 PRG0_PRU0_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI6 1 I 0 PRG0_RGMII1_RXC 2 I 0 PRG0_PWM3_A1 3 IO 0 MCASP0_AXR2 5 IO 0 GPIO1_35 7 IO 0 U27 PRG0_PRU0_GPO7 PRG0_PRU0_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI7 1 I 0 PRG0_IEP0_EDC_LATCH_IN1 2 I 0 PRG0_PWM3_B1 3 IO 1 PRG0_ECAP0_SYNC_IN 4 I 0 MCASP0_AXR3 5 IO 0 GPIO1_36 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AC26 PRG0_PRU0_GPO13 PRG0_PRU0_GPO13 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI13 1 I 0 PRG0_RGMII1_TD1 2 O PRG0_PWM0_B0 3 IO 1 MCASP0_AXR9 5 IO 0 GPIO1_42 7 IO 0 AD26 PRG0_PRU0_GPO14 PRG0_PRU0_GPO14 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI14 1 I 0 PRG0_RGMII1_TD2 2 O PRG0_PWM0_A1 3 IO 0 MCASP0_AXR10 5 IO 0 GPIO1_43 7 IO 0 AA24 PRG0_PRU0_GPO15 PRG0_PRU0_GPO15 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI15 1 I 0 PRG0_RGMII1_TD3 2 O PRG0_PWM0_B1 3 IO 1 MCASP0_AXR11 5 IO 0 GPIO1_44 7 IO 0 AD28 PRG0_PRU0_GPO16 PRG0_PRU0_GPO16 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI16 1 I 0 PRG0_RGMII1_TXC 2 IO 0 PRG0_PWM0_A2 3 IO 0 MCASP0_AXR12 5 IO 0 MCASP1_AHCLKR 6 IO 0 GPIO1_45 7 IO 0 U26 PRG0_PRU0_GPO17 PRG0_PRU0_GPO17 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI17 1 I 0 PRG0_IEP0_EDC_SYNC_OUT1 2 O PRG0_PWM0_B2 3 IO 1 PRG0_ECAP0_SYNC_OUT 4 O MCASP0_AXR13 5 IO 0 MCASP1_AHCLKX 6 IO 0 GPIO1_46 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AA25 PRG0_PRU1_GPO4 PRG0_PRU1_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI4 1 I 0 PRG0_RGMII2_RX_CTL 2 I 0 PRG0_PWM2_B2 3 IO 1 MCASP1_AXR0 5 IO 0 MCASP0_AHCLKR 6 IO 0 GPIO1_53 7 IO 0 U23 PRG0_PRU1_GPO5 PRG0_PRU1_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI5 1 I 0 MCASP1_AXR1 5 IO 0 MCASP0_AHCLKX 6 IO 0 GPIO1_54 7 IO 0 AB27 PRG0_PRU1_GPO6 PRG0_PRU1_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI6 1 I 0 PRG0_RGMII2_RXC 2 I 0 MCASP1_AXR2 5 IO 0 GPIO1_55 7 IO 0 W28 PRG0_PRU1_GPO7 PRG0_PRU1_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI7 1 I 0 PRG0_IEP1_EDC_LATCH_IN1 2 I 0 SPI3_CS0 4 IO 1 MCASP1_AXR3 5 IO 0 UART2_TXD 6 O GPIO1_56 7 IO 0 W27 PRG0_PRU1_GPO8 PRG0_PRU1_GPO8 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI8 1 I 0 PRG0_PWM2_TZ_OUT 3 O MCASP1_AXR4 5 IO 0 GPIO1_57 7 IO 0 Y28 PRG0_PRU1_GPO9 PRG0_PRU1_GPO9 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI9 1 I 0 PRG0_UART0_RXD 2 I 1 SPI3_CS3 4 IO 1 MCASP1_AXR5 5 IO 0 PRG0_IEP0_EDIO_DATA_IN_OUT30 6 IO 0 GPIO1_58 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AC24 PRG0_PRU1_GPO16 PRG0_PRU1_GPO16 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI16 1 I 0 PRG0_RGMII2_TXC 2 IO 0 PRG0_PWM1_A2 3 IO 0 MCASP2_AXR0 5 IO 0 GPIO1_65 7 IO 0 Y27 PRG0_PRU1_GPO17 PRG0_PRU1_GPO17 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI17 1 I 0 PRG0_IEP1_EDC_SYNC_OUT1 2 O PRG0_PWM1_B2 3 IO 1 SPI3_CLK 4 IO 0 MCASP2_AXR1 5 IO 0 UART2_RXD 6 I 1 GPIO1_66 7 IO 0 Y26 PRG0_PRU1_GPO18 PRG0_PRU1_GPO18 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI18 1 I 0 PRG0_IEP1_EDC_LATCH_IN0 2 I 0 PRG0_PWM1_TZ_IN 3 I 0 SPI3_D0 4 IO 0 MCASP2_AFSX 5 IO 0 UART2_CTSn 6 I 1 GPIO1_67 7 IO 0 W26 PRG0_PRU1_GPO19 PRG0_PRU1_GPO19 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI19 1 I 0 PRG0_IEP1_EDC_SYNC_OUT0 2 O PRG0_PWM1_TZ_OUT 3 O SPI3_D1 4 IO 0 MCASP2_ACLKX 5 IO 0 UART2_RTSn 6 O GPIO1_68 7 IO 0 AH18 PRG1_MDIO0_MDC PRG1_MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0/1 SPI1_CS3 1 IO 1 PRG2_PWM1_B1 3 IO 1 GPIO1_1 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AF22 PRG1_PRU0_GPO6 PRG1_PRU0_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI6 1 I 0 PRG1_RGMII1_RXC 2 I 0 PRG1_PWM3_A1 3 IO 0 GPIO0_62 7 IO 0 AG27 PRG1_PRU0_GPO7 PRG1_PRU0_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI7 1 I 0 PRG1_IEP0_EDC_LATCH_IN1 2 I 0 PRG1_PWM3_B1 3 IO 1 GPIO0_63 7 IO 0 AF28 PRG1_PRU0_GPO8 PRG1_PRU0_GPO8 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI8 1 I 0 PRG1_PWM2_A1 3 IO 0 GPIO0_64 7 IO 0 AF26 PRG1_PRU0_GPO9 PRG1_PRU0_GPO9 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI9 1 I 0 PRG1_UART0_CTSn 2 I 1 PRG1_PWM3_TZ_IN 3 I 0 SPI2_CS1 4 IO 1 PRG1_IEP0_EDIO_DATA_IN_OUT28 6 IO 0 GPIO0_65 7 IO 0 AH25 PRG1_PRU0_GPO10 PRG1_PRU0_GPO10 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI10 1 I 0 PRG1_UART0_RTSn 2 O PRG1_PWM2_B1 3 IO 1 SPI2_CS2 4 IO 1 PRG1_IEP0_EDIO_DATA_IN_OUT29 6 IO 0 GPIO0_66 7 IO 0 AF21 PRG1_PRU0_GPO11 PRG1_PRU0_GPO11 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI11 1 I 0 PRG1_RGMII1_TX_CTL 2 O PRG1_PWM3_TZ_OUT 3 O GPIO0_67 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AG26 PRG1_PRU0_GPO19 PRG1_PRU0_GPO19 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI19 1 I 0 PRG1_IEP0_EDC_SYNC_OUT0 2 O PRG1_PWM0_TZ_OUT 3 O GPIO0_75 7 IO 0 AH24 PRG1_PRU1_GPO0 PRG1_PRU1_GPO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI0 1 I 0 PRG1_RGMII2_RD0 2 I 0 GPIO0_76 7 IO 0 AH23 PRG1_PRU1_GPO1 PRG1_PRU1_GPO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI1 1 I 0 PRG1_RGMII2_RD1 2 I 0 GPIO0_77 7 IO 0 AG21 PRG1_PRU1_GPO2 PRG1_PRU1_GPO2 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI2 1 I 0 PRG1_RGMII2_RD2 2 I 0 PRG1_PWM2_A2 3 IO 0 GPIO0_78 7 IO 0 AH22 PRG1_PRU1_GPO3 PRG1_PRU1_GPO3 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI3 1 I 0 PRG1_RGMII2_RD3 2 I 0 GPIO0_79 7 IO 0 AE21 PRG1_PRU1_GPO4 PRG1_PRU1_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI4 1 I 0 PRG1_RGMII2_RX_CTL 2 I 0 PRG1_PWM2_B2 3 IO 1 GPIO0_80 7 IO 0 AC22 PRG1_PRU1_GPO5 PRG1_PRU1_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI5 1 I 0 GPIO0_81 7 IO 0 AG22 PRG1_PRU1_GPO6 PRG1_PRU1_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI6 1 I 0 PRG1_RGMII2_RXC 2 I 0 GPIO0_82 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AH19 PRG1_PRU1_GPO14 PRG1_PRU1_GPO14 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI14 1 I 0 PRG1_RGMII2_TD2 2 O PRG1_PWM1_A1 3 IO 0 GPIO0_90 7 IO 0 AG19 PRG1_PRU1_GPO15 PRG1_PRU1_GPO15 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI15 1 I 0 PRG1_RGMII2_TD3 2 O PRG1_PWM1_B1 3 IO 1 GPIO0_91 7 IO 0 AE19 PRG1_PRU1_GPO16 PRG1_PRU1_GPO16 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI16 1 I 0 PRG1_RGMII2_TXC 2 IO 0 PRG1_PWM1_A2 3 IO 0 GPIO0_92 7 IO 0 AE23 PRG1_PRU1_GPO17 PRG1_PRU1_GPO17 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI17 1 I 0 PRG1_IEP1_EDC_SYNC_OUT1 2 O PRG1_PWM1_B2 3 IO 1 SPI2_CLK 4 IO 0 PRG1_ECAP0_SYNC_OUT 5 O UART1_RXD 6 I 1 GPIO0_93 7 IO 0 AD22 PRG1_PRU1_GPO18 PRG1_PRU1_GPO18 0 IO OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI18 1 I 0 PRG1_IEP1_EDC_LATCH_IN0 2 I 0 PRG1_PWM1_TZ_IN 3 I 0 SPI2_D0 4 IO 0 PRG1_ECAP0_SYNC_IN 5 I 0 UART1_CTSn 6 I 1 GPIO0_94 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AG17 PRG2_PRU0_GPO4 PRG2_PRU0_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes LVCMOS PU/PD 0 0/1 PRG2_PRU0_GPI4 1 I 0 PRG2_RGMII1_RX_CTL 2 I 0 GPMC0_A21 3 OZ TRC_DATA2 4 O PRG2_PWM0_A0 6 IO 0 GPIO0_34 7 IO 0 AF17 PRG2_PRU0_GPO5 PRG2_PRU0_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes LVCMOS PU/PD 0 0/1 PRG2_PRU0_GPI5 1 I 0 PRG2_RGMII1_RXC 2 I 0 GPMC0_A20 3 OZ TRC_DATA3 4 O PRG2_PWM3_A1 6 IO 0 GPIO0_35 7 IO 0 AE17 PRG2_PRU0_GPO6 PRG2_PRU0_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes LVCMOS PU/PD 0 0/1 PRG2_PRU0_GPI6 1 I 0 PRG2_RGMII1_TX_CTL 2 O GPMC0_A19 3 OZ TRC_DATA4 4 O PRG2_PWM3_B1 6 IO 1 GPIO0_36 7 IO 0 AC19 PRG2_PRU0_GPO7 PRG2_PRU0_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes LVCMOS PU/PD 0 0/1 PRG2_PRU0_GPI7 1 I 0 PRG2_MDIO0_MDIO 2 IO 0 GPMC0_A18 3 OZ TRC_DATA5 4 O GPIO0_37 7 IO 0 AH16 PRG2_PRU0_GPO8 PRG2_PRU0_GPO8 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes LVCMOS PU/PD 0 0/1 PRG2_PRU0_GPI8 1 I 0 PRG2_RGMII1_TD0 2 O GPMC0_A17 3 OZ TRC_DATA6 4 O PRG2_PWM0_B0 6 IO 1 GPIO0_38 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AC16 PRG2_PRU1_GPO1 PRG2_PRU1_GPO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes LVCMOS PU/PD 0 0/1 PRG2_PRU1_GPI1 1 I 0 PRG2_RGMII2_RD1 2 I 0 GPMC0_A11 3 OZ TRC_DATA12 4 O PRG2_PWM3_B2 6 IO 1 GPIO0_44 7 IO 0 AD17 PRG2_PRU1_GPO2 PRG2_PRU1_GPO2 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes LVCMOS PU/PD 0 0/1 PRG2_PRU1_GPI2 1 I 0 PRG2_RGMII2_RD2 2 I 0 GPMC0_A10 3 OZ TRC_DATA13 4 O PRG2_PWM0_B1 6 IO 1 GPIO0_45 7 IO 0 AH14 PRG2_PRU1_GPO3 PRG2_PRU1_GPO3 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes LVCMOS PU/PD 0 0/1 PRG2_PRU1_GPI3 1 I 0 PRG2_RGMII2_RD3 2 I 0 GPMC0_A9 3 OZ TRC_DATA14 4 O GPIO0_46 7 IO 0 AG14 PRG2_PRU1_GPO4 PRG2_PRU1_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes LVCMOS PU/PD 0 0/1 PRG2_PRU1_GPI4 1 I 0 PRG2_RGMII2_RX_CTL 2 I 0 GPMC0_A8 3 OZ TRC_DATA15 4 O PRG2_ECAP0_SYNC_OUT 6 O GPIO0_47 7 IO 0 AG15 PRG2_PRU1_GPO5 PRG2_PRU1_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes LVCMOS PU/PD 0 0/1 PRG2_PRU1_GPI5 1 I 0 PRG2_RGMII2_RXC 2 I 0 GPMC0_A7 3 OZ TRC_DATA16 4 O GPIO0_48 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AD14 PRG2_PRU1_GPO11 PRG2_PRU1_GPO11 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes LVCMOS PU/PD 0 0/1 PRG2_PRU1_GPI11 1 I 0 PRG2_RGMII2_TD3 2 O GPMC0_A1 3 OZ TRC_DATA22 4 O PRG2_ECAP0_SYNC_IN 6 I 0 GPIO0_54 7 IO 0 AE14 PRG2_PRU1_GPO16 PRG2_PRU1_GPO16 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes LVCMOS PU/PD 0 0/1 PRG2_PRU1_GPI16 1 I 0 PRG2_RGMII2_TXC 2 IO 0 GPMC0_A0 3 OZ TRC_DATA23 4 O PRG2_PWM1_TZ_OUT 6 O GPIO0_55 7 IO 0 AF9 REFCLK0N REFCLK0N O OFF 1.8 V VDDA_1P8_SER DES0 LJCB CLK AF10 REFCLK0P REFCLK0P O OFF 1.8 V VDDA_1P8_SER DES0 LJCB CLK AE8 REFCLK1N REFCLK1N O OFF 1.8 V VDDA_1P8_SER DES0 LJCB CLK AE9 REFCLK1P REFCLK1P O OFF 1.8 V VDDA_1P8_SER DES0 LJCB CLK D19 RESETSTATz RESETSTATz 0 O OFF 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/0 F17 RESETz RESETz 0 I PU 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1/1 AG5 SERDES0_REFCLKN SERDES0_REFCLKN I OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES0 AG6 SERDES0_REFCLKP SERDES0_REFCLKP I OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES0 AC9 SERDES0_REFRES SERDES0_REFRES A OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES0 AH3 SERDES0_RXN SERDES0_RXN I OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES0 AG2 SERDES0_RXP SERDES0_RXP I OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES0 AH4 SERDES0_TXN SERDES0_TXN O OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES0 AG3 SERDES0_TXP SERDES0_TXP O OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES0 AH6 SERDES1_REFCLKN SERDES1_REFCLKN I OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES1 AH7 SERDES1_REFCLKP SERDES1_REFCLKP I OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES1

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AC14 SERDES1_REFRES SERDES1_REFRES A OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES1 AG9 SERDES1_RXN SERDES1_RXN I OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES1 AH10 SERDES1_RXP SERDES1_RXP I OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES1 AH9 SERDES1_TXN SERDES1_TXN O OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES1 AG8 SERDES1_TXP SERDES1_TXP O OFF 0 1.8 V VDDA_1P8_SER DES0 SERDES1 E20 SOC_SAFETY_ERRORn SOC_SAFETY_ERRORn 0 IO PD 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1/0 AH13 SPI0_CLK SPI0_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 GPIO1_17 7 IO 0 AH12 SPI1_CLK SPI1_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG2_IEP0_EDC_SYNC_OUT0 3 O PRG2_UART0_RTSn 4 O GPIO1_22 7 IO 0 AG13 SPI0_CS0 SPI0_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 1 0/1 GPIO1_15 7 IO 0 AF13 SPI0_CS1 SPI0_CS1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 1 0/1 CPTS0_TS_COMP 1 O I2C3_SCL 2 IOD 1 PRG1_IEP0_EDIO_OUTVALID 6 O GPIO1_16 7 IO 0 AE13 SPI0_D0 SPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 GPIO1_18 7 IO 0 AD13 SPI0_D1 SPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 GPIO1_19 7 IO 0 AD12 SPI1_CS0 SPI1_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 1 0/1 PRG2_IEP0_EDC_LATCH_IN0 3 I 0 PRG2_UART0_CTSn 4 I 1 PRG0_IEP0_EDIO_OUTVALID 6 O GPIO1_20 7 IO 0 AG12 SPI1_CS1 SPI1_CS1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 1 0/1 CPTS0_TS_SYNC 1 O I2C3_SDA 2 IOD 1 GPIO1_21 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AE12 SPI1_D0 SPI1_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG2_IEP0_EDC_LATCH_IN1 3 I 0 PRG2_UART0_RXD 4 I 1 GPIO1_23 7 IO 0 AF12 SPI1_D1 SPI1_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG2_IEP0_EDC_SYNC_OUT1 3 O PRG2_UART0_TXD 4 O GPIO1_24 7 IO 0 AA4 TCK TCK 0 I PU 0 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 1/1 C20 TDI TDI 0 I PU 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1/1 A20 TDO TDO 0 OZ PU 0 1.8 V/3.3 V VDDSHV0 LVCMOS PU/PD 0/0 W6 TEMP_DIODE_P TEMP_DIODE_P A OFF 1.8 V Power B22 TIMER_IO0 TIMER_IO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1 SYSCLKOUT0 2 O GPIO1_88 7 IO 0 C23 TIMER_IO1 TIMER_IO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1 OBSCLK0 2 O GPIO1_89 7 IO 0 A21 TMS TMS 0 I PU 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1/1 AA3 TRSTn TRSTn 0 I PD 0 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 1/1 AG11 UART0_CTSn UART0_CTSn 0 I OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 1 0/1 TIMER_IO4 1 IO 0 SPI0_CS2 2 IO 1 GPIO1_27 7 IO 0 AD11 UART0_RTSn UART0_RTSn 0 O OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0/1 TIMER_IO5 1 IO 0 SPI0_CS3 2 IO 1 GPIO1_28 7 IO 0 AF11 UART0_RXD UART0_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 1 0/1 GPIO1_25 7 IO 0 AE11 UART0_TXD UART0_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0/1 GPIO1_26 7 IO 0 AE2 USB0_DM USB0_DM IO OFF 3.3 V VDDA_3P3_USB USBHS AF1 USB0_DP USB0_DP IO OFF 3.3 V VDDA_3P3_USB USBHS AD9 USB0_DRVVBUS USB0_DRVVBUS 0 O PD 0 1.8 V/3.3 V VDDSHV8 Yes LVCMOS PU/PD 0/0 GPIO1_71 7 IO 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AF7 USB0_ID USB0_ID A OFF 3.3 V VDDA_3P3_USB USBHS AE7 USB0_VBUS USB0_VBUS A OFF 5.0 V VDDA_3P3_USB USBHS AD2 USB1_DM USB1_DM IO OFF 3.3 V VDDA_3P3_USB USBHS AE1 USB1_DP USB1_DP IO OFF 3.3 V VDDA_3P3_USB USBHS AC8 USB1_DRVVBUS USB1_DRVVBUS 0 O PD 0 1.8 V/3.3 V VDDSHV8 Yes LVCMOS PU/PD 0/0 GPIO1_72 7 IO 0 AF5 USB1_ID USB1_ID A OFF 3.3 V VDDA_3P3_USB USBHS AF6 USB1_VBUS USB1_VBUS A OFF 5.0 V VDDA_3P3_USB USBHS AB6 VDDA_1P8_MON_WKUP VDDA_1P8_MON_WKUP PWR G17 VDDA_1P8_SDIO VDDA_1P8_SDIO PWR L20, M21 VDDA_1P8_CSI0 VDDA_1P8_CSI0 PWR AC6 VDDA_1P8_MON0 VDDA_1P8_MON0 PWR L22 VDDA_1P8_OLDI0 VDDA_1P8_OLDI0 PWR AA14, AB13, AB15 VDDA_1P8_SERDES0 VDDA_1P8_SERDES0 PWR AB9 VDDA_3P3_IOLDO_WKUP VDDA_3P3_IOLDO_WKUP PWR U6 VDDA_3P3_MON_WKUP VDDA_3P3_MON_WKUP PWR H17 VDDA_3P3_SDIO VDDA_3P3_SDIO PWR AC12 VDDA_3P3_USB VDDA_3P3_USB PWR G18 VDDA_3P3_IOLDO0 VDDA_3P3_IOLDO0 PWR AA21 VDDA_3P3_IOLDO1 VDDA_3P3_IOLDO1 PWR AC10 VDDA_3P3_MON0 VDDA_3P3_MON0 PWR M7, M9 VDDA_ADC_MCU VDDA_ADC_MCU PWR AB8 VDDA_LDO_WKUP VDDA_LDO_WKUP PWR U12 VDDA_MCU VDDA_MCU PWR H15 VDDA_PLL0_DDR VDDA_PLL0_DDR PWR H11 VDDA_PLL1_DDR VDDA_PLL1_DDR PWR Y17 VDDA_PLL_CORE VDDA_PLL_CORE PWR L21 VDDA_PLL_DSS VDDA_PLL_DSS PWR L12 VDDA_PLL_MPU0 VDDA_PLL_MPU0 PWR K15 VDDA_PLL_MPU1 VDDA_PLL_MPU1 PWR AB7 VDDA_PLL_PER0 VDDA_PLL_PER0 PWR Y9 VDDA_POR_WKUP VDDA_POR_WKUP PWR M19 VDDA_SRAM_CORE0 VDDA_SRAM_CORE0 PWR V16 VDDA_SRAM_CORE1 VDDA_SRAM_CORE1 PWR K7 VDDA_SRAM_MPU0 VDDA_SRAM_MPU0 PWR L18 VDDA_SRAM_MPU1 VDDA_SRAM_MPU1 PWR AC11 VDDA_VSYS_MON VDDA_VSYS_MON PWR

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AA9 VDDA_WKUP VDDA_WKUP PWR G12 VDDS0 VDDS0 PWR V8 VDDS0_WKUP VDDS0_WKUP PWR AA16 VDDS1 VDDS1 PWR T9 VDDS1_WKUP VDDS1_WKUP PWR P20 VDDS2 VDDS2 PWR N8 VDDS2_WKUP VDDS2_WKUP PWR T20 VDDS3 VDDS3 PWR Y20 VDDS4 VDDS4 PWR AC18 VDDS5 VDDS5 PWR F20 VDDS6 VDDS6 PWR K20 VDDS7 VDDS7 PWR AA10 VDDS8 VDDS8 PWR G15, H16 VDDSHV0 VDDSHV0 PWR U8, V7, W8, Y7 VDDSHV0_WKUP VDDSHV0_WKUP PWR AA18, AB17 VDDSHV1 VDDSHV1 PWR R6, R8, T7 VDDSHV1_WKUP VDDSHV1_WKUP PWR N20, N22, P21, R20, R22 VDDSHV2 VDDSHV2 PWR N6, P7, P9 VDDSHV2_WKUP VDDSHV2_WKUP PWR T21, U20, U22, V21, V23 VDDSHV3 VDDSHV3 PWR AA22, W20, W22, Y21, Y23 VDDSHV4 VDDSHV4 PWR AA20, AB19, AB21, AB23 VDDSHV5 VDDSHV5 PWR G20, H19, H21 VDDSHV6 VDDSHV6 PWR J20, J22, K21 VDDSHV7 VDDSHV7 PWR AB11 VDDSHV8 VDDSHV8 PWR G10, G14, G8, H13, H7, H9 VDDS_DDR VDDS_DDR PWR J16 VDDS_OSC1 VDDS_OSC1 PWR AA12, J10, J12, J14, J19, J8, K13, L14, L19, M13, N14, P13, P15, P19, R14, R16, R18, T13, T15, T17, T19, U14, U16, U18, V13, V15, V19, W14, W18, Y11, Y13, Y15 VDD_CORE VDD_CORE PWR G22 VDD_DLL_MMC0 VDD_DLL_MMC0 PWR

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] A1, A2, A28, AA11, AA13, AA15, AA17, AA19, AA23, AA26, AA7, AB10, AB12, AB14, AB16, AB18, AB20, AB22, AD4, AE10, AE25, AE5, AF15, AF2, AF20, AF8, AG1, AG10, AG28, AG4, AG7, AH1, AH11, AH2, AH27, AH28, AH5, AH8, B12, B15, B20, B6, B9, D22, E26, E28, E4, F14, F19, F22, F25, F27, F3, G11, G13, G16, G2, G21, G23, G7, G9, H1, H10, H12, H14, H20, H22, H24, H26, H28, H6, H8, J11, J13, J15, J18, J21, J23, J25, J27, J7, J9, K1, K10, K12, K14, K17, K19, K22, K23, K6, K8, L11, L13, L16, L23, L24, L26, L28, L3, L7, L9, M10, M15, M17, M20, M8, N11, N13, N16, N19, N21, N7, N9, P10, P12, P14, P16, P18, P22, P6, P8, R11, R13, R15, R17, R19, R21, R7, R9, T10, T12, T14, T16, T18, T22, T26, T8, U11, U13, U15, U17, U19, U21, U3, U7, U9, V10, V12, V14, V18, V20, V22, V6, W11, W13, W15, W17, W19, W21, W23, W7, W9, Y12, Y14, Y16, Y18, Y22, Y6, Y8 VSS VSS GND AF4 WKUP_GPIO0_0 WKUP_GPIO0_0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0 1/1 MCU_SPI1_CLK 1 IO 0 WKUP_GPIO0_0 7 IO 0 MCU_BOOTMODE00 Bootstrap I 0

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUXMODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RXACTIVE/ TXDISABL E [14] AB4 WKUP_GPIO0_9 WKUP_GPIO0_9 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0 1/1 MCU_CPTS0_TS_COMP 2 O WKUP_GPIO0_9 7 IO 0 MCU_BOOTMODE09 Bootstrap I 0 AB3 WKUP_GPIO0_10 WKUP_GPIO0_10 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_EXT_REFCLK0 1 I 0 MCU_CPTS0_RFT_CLK 4 I 0 MCU_SYSCLKOUT0 5 O WKUP_GPIO0_10 7 IO 0 AB2 WKUP_GPIO0_11 WKUP_GPIO0_11 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 0 0/1 MCU_OBSCLK0 1 O MCU_TIMER_IO1 4 IO 0 MCU_CLKOUT0 6 O WKUP_GPIO0_11 7 IO 0 AC7 WKUP_I2C0_SCL WKUP_I2C0_SCL 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_WKU P Yes I2C OPEN DRAIN 1 1/0 AD6 WKUP_I2C0_SDA WKUP_I2C0_SDA 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_WKU P Yes I2C OPEN DRAIN 1 1/0 AE4 WKUP_LFOSC0_XI WKUP_LFOSC0_XI I OFF 1.8 V VDDA_WKUP Analog AC4 WKUP_LFOSC0_XO WKUP_LFOSC0_XO O OFF 1.8 V VDDA_WKUP Analog AD5 WKUP_OSC0_XI WKUP_OSC0_XI I OFF 1.8 V VDDA_WKUP Analog AE6 WKUP_OSC0_XO WKUP_OSC0_XO O OFF 1.8 V VDDA_WKUP Analog AB1 WKUP_UART0_RXD WKUP_UART0_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 1 0/1 WKUP_GPIO0_52 7 IO 0 AB5 WKUP_UART0_TXD WKUP_UART0_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV0_WKU P Yes LVCMOS PU/PD 1 0/1 WKUP_GPIO0_53 7 IO 0

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated The following list describes the table column headers: 1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom. 2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0). 3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0). NOTE Table 4-1, Pin Attributes, does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.3, Signal Descriptions. 4. MUXMODE: Multiplexing mode number: a. MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default muxmode. NOTE The default muxmode is the mode at the release of the reset; also see the BALL RESET REL. MUXMODE column. b. MUXMODE 1 through 7 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used. c. Bootstrap are Special Configuration Pins, latched on rising edge of PORn / RESETFULLn. These are not programable MUXMODE. d. An empty box means Not Applicable. 5. TYPE: Signal type and direction: – I = Input – O = Output – IO = Input or Output – IOD = Open drain terminal - Input or Output – IOZ = Input, Output or Three-state terminal – OZ = Output or Three-state terminal – A = Analog – PWR = Power – GND = Ground – CAP = LDO Capacitor. 6. BALL RESET STATE: The state of the terminal at power-on reset: – DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated). – DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated). – OFF: High-impedance – PD: High-impedance with an active pulldown resistor – PU: High-impedance with an active pullup resistor – An empty box means Not Applicable. For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see chapter Device Configuration of the device TRM. 7. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal. An empty box means Not Applicable. 8. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply). An empty box means Not Applicable. 9. POWER: The voltage supply that powers the terminal IO buffers.

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated An empty box means Not Applicable. 10. HYS: Indicates if the input buffer has hysteresis: – Yes: With hysteresis – No: Without hysteresis An empty box means No. For more information, see the hysteresis values in Section 5.7, Electrical Characteristics. 11. BUFFER TYPE: This column describes the associated output buffer type An empty box means Not Applicable. For drive strength of the associated output buffer, refer to Section 5.7, Electrical Characteristics. 12. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software. – PU: Internal pullup – PD: Internal pulldown – PU/PD: Internal pullup and pulldown – An empty box means No pull. 13. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0", logic "1", or "PIN" level) when the peripheral pin function is not selected by any of the PINCNTLx registers. – 0: Logic 0 driven on the input signal port of the peripheral. – 1: Logic 1 driven on the input signal port of the peripheral. – An empty box means Not Applicable. 14. RXACTIVE / TXDISABLE:This column indicates the default value of the RXACTIVE / TXDISABLE bits in the PADCONFIG register. – RXACTIVE: 0 = receiver disabled, 1 = receiver enabled. – TXDISABLE: 0 = driver enabled, 1 = driver disabled. – An empty box means Not Applicable. NOTE Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (HiZ mode is not an input signal). NOTE When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

4.3 Signal Descriptions

Many signals are available on multiple pins, according to the software configuration of the pin multiplexing options. The following list describes the column headers: (1) SIGNAL NAME: The name of the signal passing through the pin. NOTE In Table 4-1 and Table 4-61 are not described the subsystem multiplexing signals. (2) DESCRIPTION: Description of the signal (3) PIN TYPE: Signal direction and type:

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated – I = Input – O = Output – IO = Input or Output – IOD = Open drain terminal - Input or Output – IOZ = Input, Output or Three-state terminal – OZ = Output or Three-state terminal – A = Analog – PWR = Power – GND = Ground – CAP = LDO Capacitor (4) BALL: Associated balls bottom For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM.

4.3.1 ADC

4.3.1.1 MCU Domain

Table 4-2. ADC Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_ADC_EXT_TRIGGER0 ADC Trigger Input I AC3 MCU_ADC_EXT_TRIGGER1 ADC Trigger Input I AD3 Table 4-3. ADC0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_ADC0_REFN ADC Reference Input (negative) A K2 MCU_ADC0_REFP ADC Reference Input (positive) A K3 MCU_ADC0_AIN0 ADC Analog Input 0 A K5 MCU_ADC0_AIN1 ADC Analog Input 1 A J3 MCU_ADC0_AIN2 ADC Analog Input 2 A J1 MCU_ADC0_AIN3 ADC Analog Input 3 A J5 MCU_ADC0_AIN4 ADC Analog Input 4 A K4 MCU_ADC0_AIN5 ADC Analog Input 5 A J4 MCU_ADC0_AIN6 ADC Analog Input 6 A J2 MCU_ADC0_AIN7 ADC Analog Input 7 A J6 Table 4-4. ADC1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_ADC1_REFN ADC Reference Input (negative) A H3 MCU_ADC1_REFP ADC Reference Input (positive) A H2 MCU_ADC1_AIN0 ADC Analog Input 0 A F4 MCU_ADC1_AIN1 ADC Analog Input 1 A G6 MCU_ADC1_AIN2 ADC Analog Input 2 A G4 MCU_ADC1_AIN3 ADC Analog Input 3 A H5 MCU_ADC1_AIN4 ADC Analog Input 4 A F5 MCU_ADC1_AIN5 ADC Analog Input 5 A G5 MCU_ADC1_AIN6 ADC Analog Input 6 A G3 MCU_ADC1_AIN7 ADC Analog Input 7 A H4

4.3.2 CPSW2G

4.3.2.1 MCU Domain

Table 4-5. CPSW2G0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_CPTS0_RFT_CLK CPTS Reference Clock I AB3 MCU_CPTS0_TS_COMP CPTS Time Stamp Counter Compare O AB4 MCU_CPTS0_TS_SYNC CPTS Time Stamp Counter Bit O AC5 MCU_CPTS0_HW1TSPUSH CPTS Hardware Time Stamp Push 1 I AC2 MCU_CPTS0_HW2TSPUSH CPTS Hardware Time Stamp Push 2 I AC1 MCU_MDIO0_MDC MDIO Clock O L1 MCU_MDIO0_MDIO MDIO Data IO L4 MCU_RGMII1_RXC RGMII Receive Clock I M1 MCU_RGMII1_RX_CTL RGMII Receive Control I N5 MCU_RGMII1_TXC RGMII Transmit Clock IO N1 MCU_RGMII1_TX_CTL RGMII Transmit Control O N4 MCU_RGMII1_RD0 RGMII Receive Data 0 I L6 MCU_RGMII1_RD1 RGMII Receive Data 1 I M6 MCU_RGMII1_RD2 RGMII Receive Data 2 I L5 MCU_RGMII1_RD3 RGMII Receive Data 3 I L2 MCU_RGMII1_TD0 RGMII Transmit Data 0 O M5 MCU_RGMII1_TD1 RGMII Transmit Data 1 O M4 MCU_RGMII1_TD2 RGMII Transmit Data 2 O M3 MCU_RGMII1_TD3 RGMII Transmit Data 3 O M2 MCU_RMII1_CRS_DV RMII Carrier Sense / Data Valid I N4 MCU_RMII1_REF_CLK RMII Reference Clock I M1 MCU_RMII1_RX_ER RMII Receive Data Error I N5 MCU_RMII1_TX_EN RMII Transmit Enable O N1 MCU_RMII1_RXD0 RMII Receive Data 0 I L6 MCU_RMII1_RXD1 RMII Receive Data 1 I M6 MCU_RMII1_TXD0 RMII Transmit Data 0 O M5 MCU_RMII1_TXD1 RMII Transmit Data 1 O M4

4.3.3 DMTIMER

4.3.3.1 MAIN Domain

Table 4-6. DMTIMER Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] TIMER_IO0 Timer Inputs and Outputs (not tied to single timer instance) IO B22 TIMER_IO1 Timer Inputs and Outputs (not tied to single timer instance) IO C23 TIMER_IO2 Timer Inputs and Outputs (not tied to single timer instance) IO P23 TIMER_IO3 Timer Inputs and Outputs (not tied to single timer instance) IO R23 TIMER_IO4 Timer Inputs and Outputs (not tied to single timer instance) IO AG11

4.3.3.2 MCU Domain

Table 4-7. DMTIMER Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_TIMER_IO0 Timer Inputs and Outputs (not tied to single timer instance) IO N3 MCU_TIMER_IO1 Timer Inputs and Outputs (not tied to single timer instance) IO AB2

4.3.4 DDRSS

4.3.4.1 MAIN Domain

Table 4-8. DDRSS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] DDR_AC0 DDRSS Address and Command Bus IO A10 DDR_AC1 DDRSS Address and Command Bus IO D9 DDR_AC2 DDRSS Address and Command Bus IO C9 DDR_AC3 DDRSS Address and Command Bus IO E9 DDR_AC4 DDRSS Address and Command Bus IO A9 DDR_AC5 DDRSS Address and Command Bus IO E8 DDR_AC6 DDRSS Address and Command Bus IO F8 DDR_AC7 DDRSS Address and Command Bus IO C7 DDR_AC8 DDRSS Address and Command Bus IO C8 DDR_AC9 DDRSS Address and Command Bus IO D7 DDR_AC10 DDRSS Address and Command Bus IO E7 DDR_AC11 DDRSS Address and Command Bus IO A6 DDR_AC12 DDRSS Address and Command Bus IO F7 DDR_AC13 DDRSS Address and Command Bus IO D6 DDR_AC14 DDRSS Address and Command Bus IO C6 DDR_AC15 DDRSS Address and Command Bus IO F6 DDR_AC16 DDRSS Address and Command Bus IO E6 DDR_AC17 DDRSS Address and Command Bus IO E5 DDR_AC18 DDRSS Address and Command Bus IO D8 DDR_AC19 DDRSS Address and Command Bus IO D10 DDR_AC20 DDRSS Address and Command Bus IO E10 DDR_AC21 DDRSS Address and Command Bus IO C10 DDR_AC22 DDRSS Address and Command Bus IO F11 DDR_AC23 DDRSS Address and Command Bus IO B10 DDR_AC24 DDRSS Address and Command Bus IO D11

4.3.4.2 DDRSS Mapping

Table 4-9 presents DDRSS interface signal mapping per device memory type. Table 4-9. DDRSS Signal Mapping SIGNAL NAME [1] MEMORY TYPE PIN TYPE [3] BALL [4] DDR3L DDR4 LPDDR4(1) DDR_AC0 A0 A0 CA0_A IO A10 DDR_AC1 A1 A1 CA1_A IO D9 DDR_AC2 A2 A2 CA2_A IO C9 DDR_AC3 A3 A3 CA3_A IO E9 DDR_AC4 A4 A4 CA4_A IO A9 DDR_AC5 A5 A5 CA5_A IO E8 DDR_AC6 A6 A6 CA0_B IO F8 DDR_AC7 A7 A7 CA1_B IO C7 DDR_AC8 A8 A8 CA2_B IO C8 DDR_AC9 A9 A9 CA3_B IO D7 DDR_AC10 A10 A10 CA4_B IO E7 DDR_AC11 A11 A11 CA5_B IO A6 DDR_AC12 A12 A12 CS0_B IO F7 DDR_AC13 A13 A13 CKE0_B IO D6 DDR_AC14 A14 A14/WE_n CS1_B IO C6

4.3.5 GPIO

4.3.5.1 MAIN Domain

Table 4-10. GPIO0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPIO0_0 General Purpose Input/Output IO M27 GPIO0_1 General Purpose Input/Output IO M23 GPIO0_2 General Purpose Input/Output IO M28 GPIO0_3 General Purpose Input/Output IO M24 GPIO0_4 General Purpose Input/Output IO N24

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated Table 4-10. GPIO0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPIO0_5 General Purpose Input/Output IO N27 GPIO0_6 General Purpose Input/Output IO N28 GPIO0_7 General Purpose Input/Output IO M25 GPIO0_8 General Purpose Input/Output IO N23 GPIO0_9 General Purpose Input/Output IO M26 GPIO0_10 General Purpose Input/Output IO P28 GPIO0_11 General Purpose Input/Output IO P27 GPIO0_12 General Purpose Input/Output IO N26 GPIO0_13 General Purpose Input/Output IO N25 GPIO0_14 General Purpose Input/Output IO P24 GPIO0_15 General Purpose Input/Output IO R27 GPIO0_16 General Purpose Input/Output IO R28 GPIO0_17 General Purpose Input/Output IO P25 GPIO0_18 General Purpose Input/Output IO P26 GPIO0_19 General Purpose Input/Output IO U28 GPIO0_20 General Purpose Input/Output IO T28 GPIO0_21 General Purpose Input/Output IO P23 GPIO0_22 General Purpose Input/Output IO R26 GPIO0_23 General Purpose Input/Output IO R23 GPIO0_24 General Purpose Input/Output IO T25 GPIO0_25 General Purpose Input/Output IO T24 GPIO0_26 General Purpose Input/Output IO R24 GPIO0_27 General Purpose Input/Output IO T23 GPIO0_28 General Purpose Input/Output IO R25 GPIO0_29 General Purpose Input/Output IO T27 GPIO0_30 General Purpose Input/Output IO AF18 GPIO0_31 General Purpose Input/Output IO AE18 GPIO0_32 General Purpose Input/Output IO AH17 GPIO0_33 General Purpose Input/Output IO AG18 GPIO0_34 General Purpose Input/Output IO AG17 GPIO0_35 General Purpose Input/Output IO AF17 GPIO0_36 General Purpose Input/Output IO AE17 GPIO0_37 General Purpose Input/Output IO AC19 GPIO0_38 General Purpose Input/Output IO AH16 GPIO0_39 General Purpose Input/Output IO AG16 GPIO0_40 General Purpose Input/Output IO AF16 GPIO0_41 General Purpose Input/Output IO AE16 GPIO0_42 General Purpose Input/Output IO AD16 GPIO0_43 General Purpose Input/Output IO AH15 GPIO0_44 General Purpose Input/Output IO AC16 GPIO0_45 General Purpose Input/Output IO AD17 GPIO0_46 General Purpose Input/Output IO AH14 GPIO0_47 General Purpose Input/Output IO AG14 GPIO0_48 General Purpose Input/Output IO AG15 GPIO0_49 General Purpose Input/Output IO AC17 GPIO0_50 General Purpose Input/Output IO AE15 GPIO0_51 General Purpose Input/Output IO AD15

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated Table 4-10. GPIO0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPIO0_52 General Purpose Input/Output IO AF14 GPIO0_53 General Purpose Input/Output IO AC15 GPIO0_54 General Purpose Input/Output IO AD14 GPIO0_55 General Purpose Input/Output IO AE14 GPIO0_56 General Purpose Input/Output IO AE22 GPIO0_57 General Purpose Input/Output IO AG24 GPIO0_58 General Purpose Input/Output IO AF23 GPIO0_59 General Purpose Input/Output IO AD21 GPIO0_60 General Purpose Input/Output IO AG23 GPIO0_61 General Purpose Input/Output IO AF27 GPIO0_62 General Purpose Input/Output IO AF22 GPIO0_63 General Purpose Input/Output IO AG27 GPIO0_64 General Purpose Input/Output IO AF28 GPIO0_65 General Purpose Input/Output IO AF26 GPIO0_66 General Purpose Input/Output IO AH25 GPIO0_67 General Purpose Input/Output IO AF21 GPIO0_68 General Purpose Input/Output IO AH20 GPIO0_69 General Purpose Input/Output IO AH21 GPIO0_70 General Purpose Input/Output IO AG20 GPIO0_71 General Purpose Input/Output IO AD19 GPIO0_72 General Purpose Input/Output IO AD20 GPIO0_73 General Purpose Input/Output IO AH26 GPIO0_74 General Purpose Input/Output IO AG25 GPIO0_75 General Purpose Input/Output IO AG26 GPIO0_76 General Purpose Input/Output IO AH24 GPIO0_77 General Purpose Input/Output IO AH23 GPIO0_78 General Purpose Input/Output IO AG21 GPIO0_79 General Purpose Input/Output IO AH22 GPIO0_80 General Purpose Input/Output IO AE21 GPIO0_81 General Purpose Input/Output IO AC22 GPIO0_82 General Purpose Input/Output IO AG22 GPIO0_83 General Purpose Input/Output IO AD23 GPIO0_84 General Purpose Input/Output IO AE24 GPIO0_85 General Purpose Input/Output IO AF25 GPIO0_86 General Purpose Input/Output IO AF24 GPIO0_87 General Purpose Input/Output IO AC20 GPIO0_88 General Purpose Input/Output IO AE20 GPIO0_89 General Purpose Input/Output IO AF19 GPIO0_90 General Purpose Input/Output IO AH19 GPIO0_91 General Purpose Input/Output IO AG19 GPIO0_92 General Purpose Input/Output IO AE19 GPIO0_93 General Purpose Input/Output IO AE23 GPIO0_94 General Purpose Input/Output IO AD22 GPIO0_95 General Purpose Input/Output IO AC21

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated Table 4-11. GPIO1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ACD [4] GPIO1_0 General Purpose Input/Output IO AD18 GPIO1_1 General Purpose Input/Output IO AH18 GPIO1_2 General Purpose Input/Output IO D25 GPIO1_3 General Purpose Input/Output IO B26 GPIO1_4 General Purpose Input/Output IO A24 GPIO1_5 General Purpose Input/Output IO E24 GPIO1_6 General Purpose Input/Output IO A25 GPIO1_7 General Purpose Input/Output IO C26 GPIO1_8 General Purpose Input/Output IO E25 GPIO1_9 General Purpose Input/Output IO A26 GPIO1_10 General Purpose Input/Output O B25 GPIO1_11 General Purpose Input/Output IO B27 GPIO1_12 General Purpose Input/Output I C25 GPIO1_13 General Purpose Input/Output IO A23 GPIO1_14 General Purpose Input/Output IO B23 GPIO1_15 General Purpose Input/Output IO AG13 GPIO1_16 General Purpose Input/Output IO AF13 GPIO1_17 General Purpose Input/Output IO AH13 GPIO1_18 General Purpose Input/Output IO AE13 GPIO1_19 General Purpose Input/Output IO AD13 GPIO1_20 General Purpose Input/Output IO AD12 GPIO1_21 General Purpose Input/Output IO AG12 GPIO1_22 General Purpose Input/Output IO AH12 GPIO1_23 General Purpose Input/Output IO AE12 GPIO1_24 General Purpose Input/Output IO AF12 GPIO1_25 General Purpose Input/Output IO AF11 GPIO1_26 General Purpose Input/Output IO AE11 GPIO1_27 General Purpose Input/Output IO AG11 GPIO1_28 General Purpose Input/Output IO AD11 GPIO1_29 General Purpose Input/Output IO V24 GPIO1_30 General Purpose Input/Output IO W25 GPIO1_31 General Purpose Input/Output IO W24 GPIO1_32 General Purpose Input/Output IO AA27 GPIO1_33 General Purpose Input/Output IO Y24 GPIO1_34 General Purpose Input/Output IO V28 GPIO1_35 General Purpose Input/Output IO Y25 GPIO1_36 General Purpose Input/Output IO U27 GPIO1_37 General Purpose Input/Output IO V27 GPIO1_38 General Purpose Input/Output IO V26 GPIO1_39 General Purpose Input/Output IO U25 GPIO1_40 General Purpose Input/Output IO AB25 GPIO1_41 General Purpose Input/Output IO AD27 GPIO1_42 General Purpose Input/Output IO AC26 GPIO1_43 General Purpose Input/Output IO AD26 GPIO1_44 General Purpose Input/Output IO AA24 GPIO1_45 General Purpose Input/Output IO AD28

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated Table 4-11. GPIO1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] ACD [4] GPIO1_46 General Purpose Input/Output IO U26 GPIO1_47 General Purpose Input/Output IO V25 GPIO1_48 General Purpose Input/Output IO U24 GPIO1_49 General Purpose Input/Output IO AB28 GPIO1_50 General Purpose Input/Output IO AC28 GPIO1_51 General Purpose Input/Output IO AC27 GPIO1_52 General Purpose Input/Output IO AB26 GPIO1_53 General Purpose Input/Output IO AA25 GPIO1_54 General Purpose Input/Output IO U23 GPIO1_55 General Purpose Input/Output IO AB27 GPIO1_56 General Purpose Input/Output IO W28 GPIO1_57 General Purpose Input/Output IO W27 GPIO1_58 General Purpose Input/Output IO Y28 GPIO1_59 General Purpose Input/Output IO AA28 GPIO1_60 General Purpose Input/Output IO AB24 GPIO1_61 General Purpose Input/Output IO AC25 GPIO1_62 General Purpose Input/Output IO AD25 GPIO1_63 General Purpose Input/Output IO AD24 GPIO1_64 General Purpose Input/Output IO AE27 GPIO1_65 General Purpose Input/Output IO AC24 GPIO1_66 General Purpose Input/Output IO Y27 GPIO1_67 General Purpose Input/Output IO Y26 GPIO1_68 General Purpose Input/Output IO W26 GPIO1_69 General Purpose Input/Output IO AE26 GPIO1_70 General Purpose Input/Output IO AE28 GPIO1_71 General Purpose Input/Output IO AD9 GPIO1_72 General Purpose Input/Output IO AC8 GPIO1_73 General Purpose Input/Output IO D27 GPIO1_74 General Purpose Input/Output IO D26 GPIO1_75 General Purpose Input/Output IO E27 GPIO1_76 General Purpose Input/Output IO D28 GPIO1_77 General Purpose Input/Output O C27 GPIO1_78 General Purpose Input/Output IO C28 GPIO1_79 General Purpose Input/Output IO B24 GPIO1_80 General Purpose Input/Output IO C24 GPIO1_86 General Purpose Input/Output IO D21 GPIO1_87 General Purpose Input/Output IO A22 GPIO1_88 General Purpose Input/Output IO B22 GPIO1_89 General Purpose Input/Output IO C23

4.3.5.2 WKUP Domain

Table 4-12. GPIO0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_GPIO0_0 General Purpose Input/Output IO AF4 WKUP_GPIO0_1 General Purpose Input/Output IO AF3

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated Table 4-12. GPIO0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_GPIO0_2 General Purpose Input/Output IO AE3 WKUP_GPIO0_3 General Purpose Input/Output IO AD1 WKUP_GPIO0_4 General Purpose Input/Output IO AC3 WKUP_GPIO0_5 General Purpose Input/Output IO AD3 WKUP_GPIO0_6 General Purpose Input/Output IO AC2 WKUP_GPIO0_7 General Purpose Input/Output IO AC1 WKUP_GPIO0_8 General Purpose Input/Output IO AC5 WKUP_GPIO0_9 General Purpose Input/Output IO AB4 WKUP_GPIO0_10 General Purpose Input/Output IO AB3 WKUP_GPIO0_11 General Purpose Input/Output IO AB2 WKUP_GPIO0_12 General Purpose Input/Output IO V1 WKUP_GPIO0_13 General Purpose Input/Output IO U1 WKUP_GPIO0_14 General Purpose Input/Output IO U2 WKUP_GPIO0_15 General Purpose Input/Output IO U4 WKUP_GPIO0_16 General Purpose Input/Output IO U5 WKUP_GPIO0_17 General Purpose Input/Output IO T2 WKUP_GPIO0_18 General Purpose Input/Output IO T3 WKUP_GPIO0_19 General Purpose Input/Output IO T4 WKUP_GPIO0_20 General Purpose Input/Output IO T5 WKUP_GPIO0_21 General Purpose Input/Output IO R2 WKUP_GPIO0_22 General Purpose Input/Output IO R3 WKUP_GPIO0_23 General Purpose Input/Output IO R4 WKUP_GPIO0_24 General Purpose Input/Output IO R5 WKUP_GPIO0_25 General Purpose Input/Output IO T1 WKUP_GPIO0_26 General Purpose Input/Output IO R1 WKUP_GPIO0_27 General Purpose Input/Output IO P2 WKUP_GPIO0_28 General Purpose Input/Output IO P3 WKUP_GPIO0_29 General Purpose Input/Output IO P4 WKUP_GPIO0_30 General Purpose Input/Output IO P5 WKUP_GPIO0_31 General Purpose Input/Output IO P1 WKUP_GPIO0_32 General Purpose Input/Output IO N2 WKUP_GPIO0_33 General Purpose Input/Output IO N3 WKUP_GPIO0_34 General Purpose Input/Output IO N4 WKUP_GPIO0_35 General Purpose Input/Output IO N5 WKUP_GPIO0_36 General Purpose Input/Output IO M2 WKUP_GPIO0_37 General Purpose Input/Output IO M3 WKUP_GPIO0_38 General Purpose Input/Output IO M4 WKUP_GPIO0_39 General Purpose Input/Output IO M5 WKUP_GPIO0_40 General Purpose Input/Output IO N1 WKUP_GPIO0_41 General Purpose Input/Output IO M1 WKUP_GPIO0_42 General Purpose Input/Output IO L2 WKUP_GPIO0_43 General Purpose Input/Output IO L5 WKUP_GPIO0_44 General Purpose Input/Output IO M6 WKUP_GPIO0_45 General Purpose Input/Output IO L6 WKUP_GPIO0_46 General Purpose Input/Output IO L4 WKUP_GPIO0_47 General Purpose Input/Output IO L1 WKUP_GPIO0_48 General Purpose Input/Output IO Y1

4.3.6 GPMC

4.3.6.1 MAIN Domain

Table 4-13. GPMC0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPMC0_ADVn_ALE GPMC Address Valid (active low) or Address Latch Enable O P25 GPMC0_CLK GPMC Clock Output IO R28 GPMC0_DIR GPMC Data Bus Signal Direction Control O T24 GPMC0_OEn_REn GPMC Output Enable (active low) or Read Enable (active low) O P26 GPMC0_WEn GPMC Write Enable (active low) O U28 GPMC0_WPn GPMC Flash Write Protect (active low) O T25 GPMC0_A0 GPMC Address 0 Output. Only used to effectively address 8-bit data non-multiplexed memories OZ AE14 GPMC0_A1 GPMC address 1 Output in A/D non-multiplexed mode and Address 17 in A/D multiplexed mode OZ AD14 GPMC0_A2 GPMC address 2 Output in A/D non-multiplexed mode and Address 18 in A/D multiplexed mode OZ AC15 GPMC0_A3 GPMC address 3 Output in A/D non-multiplexed mode and Address 19 in A/D multiplexed mode OZ AF14 GPMC0_A4 GPMC address 4 Output in A/D non-multiplexed mode and Address 20 in A/D multiplexed mode OZ AD15 GPMC0_A5 GPMC address 5 Output in A/D non-multiplexed mode and Address 21 in A/D multiplexed mode OZ AE15 GPMC0_A6 GPMC address 6 Output in A/D non-multiplexed mode and Address 22 in A/D multiplexed mode OZ AC17 GPMC0_A7 GPMC address 7 Output in A/D non-multiplexed mode and Address 23 in A/D multiplexed mode OZ AG15 GPMC0_A8 GPMC address 8 Output in A/D non-multiplexed mode and Address 24 in A/D multiplexed mode OZ AG14 GPMC0_A9 GPMC address 9 Output in A/D non-multiplexed mode and Address 25 in A/D multiplexed mode OZ AH14 GPMC0_A10 GPMC address 10 Output in A/D non-multiplexed mode and Address 26 in A/D multiplexed mode OZ AD17 GPMC0_A11 GPMC address 11 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AC16 GPMC0_A12 GPMC address 12 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AH15 GPMC0_A13 GPMC address 13 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AD16 GPMC0_A14 GPMC address 14 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AE16

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated Table 4-13. GPMC0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPMC0_A15 GPMC address 15 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AF16 GPMC0_A16 GPMC address 16 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AG16 GPMC0_A17 GPMC address 17 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AH16 GPMC0_A18 GPMC address 18 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AC19 GPMC0_A19 GPMC address 19 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AE17 GPMC0_A20 GPMC address 20 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AF17 GPMC0_A21 GPMC address 21 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AG17 GPMC0_A22 GPMC address 22 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AG18 GPMC0_A23 GPMC address 23 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AH17 GPMC0_A24 GPMC address 24 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AE18 GPMC0_A25 GPMC address 25 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AF18 GPMC0_A26 GPMC address 26 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ T27 GPMC0_A27 GPMC address 27 in A/D non-multiplexed mode and Address 27 in A/D multiplexed mode OZ R25 GPMC0_AD0 GPMC Data 0 Input/Output in A/D non-multiplexed mode and additionally Address 1 Output in A/D multiplexed mode IO M27 GPMC0_AD1 GPMC Data 1 Input/Output in A/D non-multiplexed mode and additionally Address 2 Output in A/D multiplexed mode IO M23 GPMC0_AD2 GPMC Data 2 Input/Output in A/D non-multiplexed mode and additionally Address 3 Output in A/D multiplexed mode IO M28 GPMC0_AD3 GPMC Data 3 Input/Output in A/D non-multiplexed mode and additionally Address 4 Output in A/D multiplexed mode IO M24 GPMC0_AD4 GPMC Data 4 Input/Output in A/D non-multiplexed mode and additionally Address 5 Output in A/D multiplexed mode IO N24 GPMC0_AD5 GPMC Data 5 Input/Output in A/D non-multiplexed mode and additionally Address 6 Output in A/D multiplexed mode IO N27 GPMC0_AD6 GPMC Data 6 Input/Output in A/D non-multiplexed mode and additionally Address 7 Output in A/D multiplexed mode IO N28 GPMC0_AD7 GPMC Data 7 Input/Output in A/D non-multiplexed mode and additionally Address 8 Output in A/D multiplexed mode IO M25 GPMC0_AD8 GPMC Data 8 Input/Output in A/D non-multiplexed mode and additionally Address 9 Output in A/D multiplexed mode IO N23 GPMC0_AD9 GPMC Data 9 Input/Output in A/D non-multiplexed mode and additionally Address 10 Output in A/D multiplexed mode IO M26

4.3.7 HYPERBUS

4.3.7.1 MCU Domain

Table 4-14. HYPERBUS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_HYPERBUS0_CK Hyperbus Differential Clock (positive) O V1 MCU_HYPERBUS0_CKn Hyperbus Differential Clock (negative) O U1 MCU_HYPERBUS0_INTn Hyperbus Interrupt (active low) I P2 MCU_HYPERBUS0_RESETn Hyperbus Reset (active low) Output O R5 MCU_HYPERBUS0_RESETOn Hyperbus Reset Status Indicator (active low) from Hyperbus Memory I R1 MCU_HYPERBUS0_RWDS Hyperbus Read-Write Data Strobe IO U2 MCU_HYPERBUS0_WPn Hyperbus Write Protect (Not in use) O N3 MCU_HYPERBUS0_CSn0 Hyperbus Chip Select 0 O R4 MCU_HYPERBUS0_CSn1 Hyperbus Chip Select 1 O N3 MCU_HYPERBUS0_DQ0 Hyperbus Data 0 IO U4 MCU_HYPERBUS0_DQ1 Hyperbus Data 1 IO U5 MCU_HYPERBUS0_DQ2 Hyperbus Data 2 IO T2 MCU_HYPERBUS0_DQ3 Hyperbus Data 3 IO T3 MCU_HYPERBUS0_DQ4 Hyperbus Data 4 IO T4 MCU_HYPERBUS0_DQ5 Hyperbus Data 5 IO T5 MCU_HYPERBUS0_DQ6 Hyperbus Data 6 IO R2

4.3.8 I2C

4.3.8.1 MAIN Domain

Table 4-15. I2C0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] I2C0_SCL I2C Clock IOD D20 I2C0_SDA I2C Data IOD C21 Table 4-16. I2C1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] I2C1_SCL I2C Clock IOD B21 I2C1_SDA I2C Data IOD E21 Table 4-17. I2C2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] I2C2_SCL I2C Clock IOD T27 I2C2_SDA I2C Data IOD R25 Table 4-18. I2C3 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] I2C3_SCL I2C Clock IOD AF13 I2C3_SDA I2C Data IOD AG12

4.3.8.2 MCU Domain

Table 4-19. I2C0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_I2C0_SCL I2C Clock IOD AD8 MCU_I2C0_SDA I2C Data IOD AD7

4.3.8.3 WKUP Domain

Table 4-20. I2C0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_I2C0_SCL I2C Clock IOD AC7 WKUP_I2C0_SDA I2C Data IOD AD6

4.3.9 MCAN

4.3.9.1 MCU Domain

Table 4-21. MCAN0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_MCAN0_RX MCAN Receive Data I W2 MCU_MCAN0_TX MCAN Transmit Data O W1 Table 4-22. MCAN1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_MCAN1_RX MCAN Receive Data I AD3 MCU_MCAN1_TX MCAN Transmit Data O AC3

4.3.10 MCASP

4.3.10.1 MAIN Domain

Table 4-23. MCASP0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP0_ACLKR MCASP Receive Bit Clock IO W24 MCASP0_ACLKX MCASP Transmit Bit Clock IO V24 MCASP0_AFSR MCASP Receive Frame Sync IO AA27 MCASP0_AFSX MCASP Transmit Frame Sync IO W25 MCASP0_AHCLKR MCASP Receive Master Clock IO AA25 MCASP0_AHCLKX MCASP Transmit Master Clock IO U23 MCASP0_AXR0 MCASP Serial Data (Input/Output) IO Y24 MCASP0_AXR1 MCASP Serial Data (Input/Output) IO V28 MCASP0_AXR2 MCASP Serial Data (Input/Output) IO Y25 MCASP0_AXR3 MCASP Serial Data (Input/Output) IO U27 MCASP0_AXR4 MCASP Serial Data (Input/Output) IO V27 MCASP0_AXR5 MCASP Serial Data (Input/Output) IO V26 MCASP0_AXR6 MCASP Serial Data (Input/Output) IO U25 MCASP0_AXR7 MCASP Serial Data (Input/Output) IO AB25 MCASP0_AXR8 MCASP Serial Data (Input/Output) IO AD27 MCASP0_AXR9 MCASP Serial Data (Input/Output) IO AC26 MCASP0_AXR10 MCASP Serial Data (Input/Output) IO AD26 MCASP0_AXR11 MCASP Serial Data (Input/Output) IO AA24 MCASP0_AXR12 MCASP Serial Data (Input/Output) IO AD28 MCASP0_AXR13 MCASP Serial Data (Input/Output) IO U26 MCASP0_AXR14 MCASP Serial Data (Input/Output) IO V25 MCASP0_AXR15 MCASP Serial Data (Input/Output) IO U24 Table 4-24. MCASP1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP1_ACLKR MCASP Receive Bit Clock IO AC27

4.3.11 MCSPI

4.3.11.1 MAIN Domain

Table 4-26. MCSPI0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SPI0_CLK SPI Clock IO AH13 SPI0_CS0 SPI Chip Select 0 IO AG13 SPI0_CS1 SPI Chip Select 1 IO AF13 SPI0_CS2 SPI Chip Select 2 IO AG11 SPI0_CS3 SPI Chip Select 3 IO AD11 SPI0_D0 SPI Data 0 IO AE13 SPI0_D1 SPI Data 1 IO AD13

4.3.11.2 MCU Domain

Table 4-30. MCSPI0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_SPI0_CLK SPI Clock IO Y1 MCU_SPI0_CS0 SPI Chip Select 0 IO Y4 MCU_SPI0_CS1 SPI Chip Select 1 IO P1 MCU_SPI0_CS2 SPI Chip Select 2 IO N3 MCU_SPI0_CS3 SPI Chip Select 3 IO AC3 MCU_SPI0_D0 SPI Data 0 IO Y3 MCU_SPI0_D1 SPI Data 1 IO Y2 Table 4-31. MCSPI1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_SPI1_CLK SPI Clock IO AF4

4.3.12 MMC

4.3.12.1 MAIN Domain

Table 4-32. MMC0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MMC0_CALPAD MMC/SD Calibration Resistor A D24 MMC0_CLK MMC/SD Clock O B25 MMC0_CMD MMC/SD Command IO B27 MMC0_DS MMC Data Strobe I C25 MMC0_SDCD SD Card Detect I A23 MMC0_SDWP SD Write Protect I B23 MMC0_DAT0 MMC/SD Data IO A26 MMC0_DAT1 MMC/SD Data IO E25 MMC0_DAT2 MMC/SD Data IO C26 MMC0_DAT3 MMC/SD Data IO A25 MMC0_DAT4 MMC/SD Data IO E24 MMC0_DAT5 MMC/SD Data IO A24 MMC0_DAT6 MMC/SD Data IO B26 MMC0_DAT7 MMC/SD Data IO D25 Table 4-33. MMC1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MMC1_CALPAD MMC/SD Calibration Resistor A F23 MMC1_CLK MMC/SD Clock O C27 MMC1_CMD MMC/SD Command IO C28 MMC1_SDCD SD Card Detect I B24 MMC1_SDWP SD Write Protect I C24 MMC1_DAT0 MMC/SD Data IO D28 MMC1_DAT1 MMC/SD Data IO E27 MMC1_DAT2 MMC/SD Data IO D26 MMC1_DAT3 MMC/SD Data IO D27

4.3.13 CPTS

4.3.13.1 MAIN Domain

Table 4-34. CPTS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] CPTS0_RFT_CLK CPTS Reference Clock I D21 CPTS0_TS_COMP CPTS Time Stamp Counter Compare O AF13 CPTS0_TS_SYNC CPTS Time Stamp Counter Bit O AG12 CPTS0_HW1TSPUSH CPTS Hardware Time Stamp Push 1 I B21 CPTS0_HW2TSPUSH CPTS Hardware Time Stamp Push 2 I E21

4.3.14 OLDI

4.3.14.1 MAIN Domain

Table 4-35. OLDI0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] OLDI0_CLKN OLDI Differential Clock (negative) IO L25 OLDI0_CLKP OLDI Differential Clock (positive) IO K25 OLDI0_A0N OLDI Differential Data (negative) IO J28 OLDI0_A0P OLDI Differential Data (positive) IO K28 OLDI0_A1N OLDI Differential Data (negative) IO L27 OLDI0_A1P OLDI Differential Data (positive) IO K27 OLDI0_A2N OLDI Differential Data (negative) IO K24 OLDI0_A2P OLDI Differential Data (positive) IO J24 OLDI0_A3N OLDI Differential Data (negative) IO J26 OLDI0_A3P OLDI Differential Data (positive) IO K26

4.3.15 OSPI

4.3.15.1 MCU Domain

Table 4-36. OSPI0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_OSPI0_CLK OSPI Clock O V1 MCU_OSPI0_DQS OSPI Data Strobe (DQS) or Loopback Clock Input I U2 MCU_OSPI0_LBCLKO OSPI Loopback Clock Output IO U1 MCU_OSPI0_CSn0 OSPI Chip Select 0 (active low) O R4 MCU_OSPI0_CSn1 OSPI Chip Select 1 (active low) O R5 MCU_OSPI0_CSn2 OSPI Chip Select 2 (active low) O R1 MCU_OSPI0_CSn3 OSPI Chip Select 3 (active low) O P2 MCU_OSPI0_D0 OSPI Data 0 IO U4 MCU_OSPI0_D1 OSPI Data 1 IO U5 MCU_OSPI0_D2 OSPI Data 2 IO T2 MCU_OSPI0_D3 OSPI Data 3 IO T3 MCU_OSPI0_D4 OSPI Data 4 IO T4 MCU_OSPI0_D5 OSPI Data 5 IO T5

4.3.16 PRU-ICSSG

4.3.16.1 MAIN Domain

The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in the device TRM. Table 4-38. PRU-ICSSG0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG0_ECAP0_IN_APWM_OUT PRU-ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Ouput IO V25 PRG0_ECAP0_SYNC_IN PRU-ICSSG ECAP Sync Input I U27 PRG0_ECAP0_SYNC_OUT PRU-ICSSG ECAP Sync Output O U26 PRG0_IEP0_EDIO_OUTVALID PRU_ICSSG Industrial Ethernet Digital I/O Outvalid O AD12 PRG0_IEP0_EDC_LATCH_IN0 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I V25 PRG0_IEP0_EDC_LATCH_IN1 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I U27 PRG0_IEP0_EDC_SYNC_OUT0 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O U24 PRG0_IEP0_EDC_SYNC_OUT1 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O U26 PRG0_IEP0_EDIO_DATA_IN_OUT28 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/Output IO V26 PRG0_IEP0_EDIO_DATA_IN_OUT29 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/Output IO U25 PRG0_IEP0_EDIO_DATA_IN_OUT30 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/Output IO Y28 PRG0_IEP0_EDIO_DATA_IN_OUT31 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/Output IO AA28

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated Table 4-38. PRU-ICSSG0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG0_IEP1_EDC_LATCH_IN0 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I Y26 PRG0_IEP1_EDC_LATCH_IN1 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I W28 PRG0_IEP1_EDC_SYNC_OUT0 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O W26 PRG0_IEP1_EDC_SYNC_OUT1 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O Y27 PRG0_MDIO0_MDC PRU-ICSSG MDIO Clock O AE28 PRG0_MDIO0_MDIO PRU-ICSSG MDIO Data IO AE26 PRG0_PRU0_GPI0 PRU-ICSSG PRU Data Input I V24 PRG0_PRU0_GPI1 PRU-ICSSG PRU Data Input I W25 PRG0_PRU0_GPI2 PRU-ICSSG PRU Data Input I W24 PRG0_PRU0_GPI3 PRU-ICSSG PRU Data Input I AA27 PRG0_PRU0_GPI4 PRU-ICSSG PRU Data Input I Y24 PRG0_PRU0_GPI5 PRU-ICSSG PRU Data Input I V28 PRG0_PRU0_GPI6 PRU-ICSSG PRU Data Input I Y25 PRG0_PRU0_GPI7 PRU-ICSSG PRU Data Input I U27 PRG0_PRU0_GPI8 PRU-ICSSG PRU Data Input I V27 PRG0_PRU0_GPI9 PRU-ICSSG PRU Data Input I V26 PRG0_PRU0_GPI10 PRU-ICSSG PRU Data Input I U25 PRG0_PRU0_GPI11 PRU-ICSSG PRU Data Input I AB25 PRG0_PRU0_GPI12 PRU-ICSSG PRU Data Input I AD27 PRG0_PRU0_GPI13 PRU-ICSSG PRU Data Input I AC26 PRG0_PRU0_GPI14 PRU-ICSSG PRU Data Input I AD26 PRG0_PRU0_GPI15 PRU-ICSSG PRU Data Input I AA24 PRG0_PRU0_GPI16 PRU-ICSSG PRU Data Input I AD28 PRG0_PRU0_GPI17 PRU-ICSSG PRU Data Input I U26 PRG0_PRU0_GPI18 PRU-ICSSG PRU Data Input I V25 PRG0_PRU0_GPI19 PRU-ICSSG PRU Data Input I U24 PRG0_PRU0_GPO0 PRU-ICSSG PRU Data Output IO V24 PRG0_PRU0_GPO1 PRU-ICSSG PRU Data Output IO W25 PRG0_PRU0_GPO2 PRU-ICSSG PRU Data Output IO W24 PRG0_PRU0_GPO3 PRU-ICSSG PRU Data Output IO AA27 PRG0_PRU0_GPO4 PRU-ICSSG PRU Data Output IO Y24 PRG0_PRU0_GPO5 PRU-ICSSG PRU Data Output IO V28 PRG0_PRU0_GPO6 PRU-ICSSG PRU Data Output IO Y25 PRG0_PRU0_GPO7 PRU-ICSSG PRU Data Output IO U27 PRG0_PRU0_GPO8 PRU-ICSSG PRU Data Output IO V27 PRG0_PRU0_GPO9 PRU-ICSSG PRU Data Output IO V26 PRG0_PRU0_GPO10 PRU-ICSSG PRU Data Output IO U25 PRG0_PRU0_GPO11 PRU-ICSSG PRU Data Output IO AB25 PRG0_PRU0_GPO12 PRU-ICSSG PRU Data Output IO AD27 PRG0_PRU0_GPO13 PRU-ICSSG PRU Data Output IO AC26 PRG0_PRU0_GPO14 PRU-ICSSG PRU Data Output IO AD26 PRG0_PRU0_GPO15 PRU-ICSSG PRU Data Output IO AA24 PRG0_PRU0_GPO16 PRU-ICSSG PRU Data Output IO AD28 PRG0_PRU0_GPO17 PRU-ICSSG PRU Data Output IO U26

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated Table 4-38. PRU-ICSSG0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG0_PRU0_GPO18 PRU-ICSSG PRU Data Output IO V25 PRG0_PRU0_GPO19 PRU-ICSSG PRU Data Output IO U24 PRG0_PRU1_GPI0 PRU-ICSSG PRU Data Input I AB28 PRG0_PRU1_GPI1 PRU-ICSSG PRU Data Input I AC28 PRG0_PRU1_GPI2 PRU-ICSSG PRU Data Input I AC27 PRG0_PRU1_GPI3 PRU-ICSSG PRU Data Input I AB26 PRG0_PRU1_GPI4 PRU-ICSSG PRU Data Input I AA25 PRG0_PRU1_GPI5 PRU-ICSSG PRU Data Input I U23 PRG0_PRU1_GPI6 PRU-ICSSG PRU Data Input I AB27 PRG0_PRU1_GPI7 PRU-ICSSG PRU Data Input I W28 PRG0_PRU1_GPI8 PRU-ICSSG PRU Data Input I W27 PRG0_PRU1_GPI9 PRU-ICSSG PRU Data Input I Y28 PRG0_PRU1_GPI10 PRU-ICSSG PRU Data Input I AA28 PRG0_PRU1_GPI11 PRU-ICSSG PRU Data Input I AB24 PRG0_PRU1_GPI12 PRU-ICSSG PRU Data Input I AC25 PRG0_PRU1_GPI13 PRU-ICSSG PRU Data Input I AD25 PRG0_PRU1_GPI14 PRU-ICSSG PRU Data Input I AD24 PRG0_PRU1_GPI15 PRU-ICSSG PRU Data Input I AE27 PRG0_PRU1_GPI16 PRU-ICSSG PRU Data Input I AC24 PRG0_PRU1_GPI17 PRU-ICSSG PRU Data Input I Y27 PRG0_PRU1_GPI18 PRU-ICSSG PRU Data Input I Y26 PRG0_PRU1_GPI19 PRU-ICSSG PRU Data Input I W26 PRG0_PRU1_GPO0 PRU-ICSSG PRU Data Output IO AB28 PRG0_PRU1_GPO1 PRU-ICSSG PRU Data Output IO AC28 PRG0_PRU1_GPO2 PRU-ICSSG PRU Data Output IO AC27 PRG0_PRU1_GPO3 PRU-ICSSG PRU Data Output IO AB26 PRG0_PRU1_GPO4 PRU-ICSSG PRU Data Output IO AA25 PRG0_PRU1_GPO5 PRU-ICSSG PRU Data Output IO U23 PRG0_PRU1_GPO6 PRU-ICSSG PRU Data Output IO AB27 PRG0_PRU1_GPO7 PRU-ICSSG PRU Data Output IO W28 PRG0_PRU1_GPO8 PRU-ICSSG PRU Data Output IO W27 PRG0_PRU1_GPO9 PRU-ICSSG PRU Data Output IO Y28 PRG0_PRU1_GPO10 PRU-ICSSG PRU Data Output IO AA28 PRG0_PRU1_GPO11 PRU-ICSSG PRU Data Output IO AB24 PRG0_PRU1_GPO12 PRU-ICSSG PRU Data Output IO AC25 PRG0_PRU1_GPO13 PRU-ICSSG PRU Data Output IO AD25 PRG0_PRU1_GPO14 PRU-ICSSG PRU Data Output IO AD24 PRG0_PRU1_GPO15 PRU-ICSSG PRU Data Output IO AE27 PRG0_PRU1_GPO16 PRU-ICSSG PRU Data Output IO AC24 PRG0_PRU1_GPO17 PRU-ICSSG PRU Data Output IO Y27 PRG0_PRU1_GPO18 PRU-ICSSG PRU Data Output IO Y26 PRG0_PRU1_GPO19 PRU-ICSSG PRU Data Output IO W26 PRG0_PWM0_TZ_IN PRU_ICSSG PWM Trip Zone Input I V25 PRG0_PWM0_TZ_OUT PRU_ICSSG PWM Trip Zone Output O U24 PRG0_PWM1_TZ_IN PRU_ICSSG PWM Trip Zone Input I Y26 PRG0_PWM1_TZ_OUT PRU_ICSSG PWM Trip Zone Output O W26 PRG0_PWM2_TZ_IN PRU_ICSSG PWM Trip Zone Input I AA28

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated Table 4-38. PRU-ICSSG0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG0_PWM2_TZ_OUT PRU_ICSSG PWM Trip Zone Output O W27 PRG0_PWM3_TZ_IN PRU_ICSSG PWM Trip Zone Input I V26 PRG0_PWM3_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AB25 PRG0_PWM0_A0 PRU_ICSSG PWM Output A IO AD27 PRG0_PWM0_A1 PRU_ICSSG PWM Output A IO AD26 PRG0_PWM0_A2 PRU_ICSSG PWM Output A IO AD28 PRG0_PWM0_B0 PRU_ICSSG PWM Output B IO AC26 PRG0_PWM0_B1 PRU_ICSSG PWM Output B IO AA24 PRG0_PWM0_B2 PRU_ICSSG PWM Output B IO U26 PRG0_PWM1_A0 PRU_ICSSG PWM Output A IO AC25 PRG0_PWM1_A1 PRU_ICSSG PWM Output A IO AD24 PRG0_PWM1_A2 PRU_ICSSG PWM Output A IO AC24 PRG0_PWM1_B0 PRU_ICSSG PWM Output B IO AD25 PRG0_PWM1_B1 PRU_ICSSG PWM Output B IO AE27 PRG0_PWM1_B2 PRU_ICSSG PWM Output B IO Y27 PRG0_PWM2_A0 PRU_ICSSG PWM Output A IO W24 PRG0_PWM2_A1 PRU_ICSSG PWM Output A IO V27 PRG0_PWM2_A2 PRU_ICSSG PWM Output A IO AC27 PRG0_PWM2_B0 PRU_ICSSG PWM Output B IO Y24 PRG0_PWM2_B1 PRU_ICSSG PWM Output B IO U25 PRG0_PWM2_B2 PRU_ICSSG PWM Output B IO AA25 PRG0_PWM3_A0 PRU_ICSSG PWM Output A IO V24 PRG0_PWM3_A1 PRU_ICSSG PWM Output A IO Y25 PRG0_PWM3_A2 PRU_ICSSG PWM Output A IO AA27 PRG0_PWM3_B0 PRU_ICSSG PWM Output B IO W25 PRG0_PWM3_B1 PRU_ICSSG PWM Output B IO U27 PRG0_PWM3_B2 PRU_ICSSG PWM Output B IO V28 PRG0_RGMII1_RXC PRU_ICSSG RGMII Receive Clock I Y25 PRG0_RGMII1_RX_CTL PRU_ICSSG RGMII Receive Control I Y24 PRG0_RGMII1_TXC PRU_ICSSG RGMII Transmit Clock IO AD28 PRG0_RGMII1_TX_CTL PRU_ICSSG RGMII Transmit Control O AB25 PRG0_RGMII2_RXC PRU_ICSSG RGMII Receive Clock I AB27 PRG0_RGMII2_RX_CTL PRU_ICSSG RGMII Receive Control I AA25 PRG0_RGMII2_TXC PRU_ICSSG RGMII Transmit Clock IO AC24 PRG0_RGMII2_TX_CTL PRU_ICSSG RGMII Transmit Control O AB24 PRG0_RGMII1_RD0 PRU_ICSSG RGMII Receive Data I V24 PRG0_RGMII1_RD1 PRU_ICSSG RGMII Receive Data I W25 PRG0_RGMII1_RD2 PRU_ICSSG RGMII Receive Data I W24 PRG0_RGMII1_RD3 PRU_ICSSG RGMII Receive Data I AA27 PRG0_RGMII1_TD0 PRU_ICSSG RGMII Transmit Data O AD27 PRG0_RGMII1_TD1 PRU_ICSSG RGMII Transmit Data O AC26 PRG0_RGMII1_TD2 PRU_ICSSG RGMII Transmit Data O AD26 PRG0_RGMII1_TD3 PRU_ICSSG RGMII Transmit Data O AA24 PRG0_RGMII2_RD0 PRU_ICSSG RGMII Receive Data I AB28 PRG0_RGMII2_RD1 PRU_ICSSG RGMII Receive Data I AC28 PRG0_RGMII2_RD2 PRU_ICSSG RGMII Receive Data I AC27 PRG0_RGMII2_RD3 PRU_ICSSG RGMII Receive Data I AB26

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated Table 4-38. PRU-ICSSG0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG0_RGMII2_TD0 PRU_ICSSG RGMII Transmit Data O AC25 PRG0_RGMII2_TD1 PRU_ICSSG RGMII Transmit Data O AD25 PRG0_RGMII2_TD2 PRU_ICSSG RGMII Transmit Data O AD24 PRG0_RGMII2_TD3 PRU_ICSSG RGMII Transmit Data O AE27 PRG0_UART0_CTSn PRU-ICSSG UART Clear to Send (active low) I V26 PRG0_UART0_RTSn PRU-ICSSG UART Request to Send (active low) O U25 PRG0_UART0_RXD PRU-ICSSG UART Receive Data I Y28 PRG0_UART0_TXD PRU-ICSSG UART Transmit Data O AA28 Table 4-39. PRU-ICSSG1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG1_ECAP0_IN_APWM_OUT PRU-ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Ouput IO AC21 PRG1_ECAP0_SYNC_IN PRU-ICSSG ECAP Sync Input I AD22 PRG1_ECAP0_SYNC_OUT PRU-ICSSG ECAP Sync Output O AE23 PRG1_IEP0_EDIO_OUTVALID PRU_ICSSG Industrial Ethernet Digital I/O Outvalid O AF13 PRG1_IEP0_EDC_LATCH_IN0 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AG25 PRG1_IEP0_EDC_LATCH_IN1 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AG27 PRG1_IEP0_EDC_SYNC_OUT0 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AG26 PRG1_IEP0_EDC_SYNC_OUT1 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AH26 PRG1_IEP0_EDIO_DATA_IN_OUT28 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/Output IO AF26 PRG1_IEP0_EDIO_DATA_IN_OUT29 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/Output IO AH25 PRG1_IEP0_EDIO_DATA_IN_OUT30 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/Output IO AF25 PRG1_IEP0_EDIO_DATA_IN_OUT31 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/Output IO AF24 PRG1_IEP1_EDC_LATCH_IN0 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AD22 PRG1_IEP1_EDC_LATCH_IN1 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AD23 PRG1_IEP1_EDC_SYNC_OUT0 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AC21 PRG1_IEP1_EDC_SYNC_OUT1 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AE23 PRG1_MDIO0_MDC PRU-ICSSG MDIO Clock O AH18 PRG1_MDIO0_MDIO PRU-ICSSG MDIO Data IO AD18 PRG1_PRU0_GPI0 PRU-ICSSG PRU Data Input I AE22 PRG1_PRU0_GPI1 PRU-ICSSG PRU Data Input I AG24 PRG1_PRU0_GPI2 PRU-ICSSG PRU Data Input I AF23 PRG1_PRU0_GPI3 PRU-ICSSG PRU Data Input I AD21 PRG1_PRU0_GPI4 PRU-ICSSG PRU Data Input I AG23 PRG1_PRU0_GPI5 PRU-ICSSG PRU Data Input I AF27 PRG1_PRU0_GPI6 PRU-ICSSG PRU Data Input I AF22 PRG1_PRU0_GPI7 PRU-ICSSG PRU Data Input I AG27

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated Table 4-39. PRU-ICSSG1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG1_PRU0_GPI8 PRU-ICSSG PRU Data Input I AF28 PRG1_PRU0_GPI9 PRU-ICSSG PRU Data Input I AF26 PRG1_PRU0_GPI10 PRU-ICSSG PRU Data Input I AH25 PRG1_PRU0_GPI11 PRU-ICSSG PRU Data Input I AF21 PRG1_PRU0_GPI12 PRU-ICSSG PRU Data Input I AH20 PRG1_PRU0_GPI13 PRU-ICSSG PRU Data Input I AH21 PRG1_PRU0_GPI14 PRU-ICSSG PRU Data Input I AG20 PRG1_PRU0_GPI15 PRU-ICSSG PRU Data Input I AD19 PRG1_PRU0_GPI16 PRU-ICSSG PRU Data Input I AD20 PRG1_PRU0_GPI17 PRU-ICSSG PRU Data Input I AH26 PRG1_PRU0_GPI18 PRU-ICSSG PRU Data Input I AG25 PRG1_PRU0_GPI19 PRU-ICSSG PRU Data Input I AG26 PRG1_PRU0_GPO0 PRU-ICSSG PRU Data Output IO AE22 PRG1_PRU0_GPO1 PRU-ICSSG PRU Data Output IO AG24 PRG1_PRU0_GPO2 PRU-ICSSG PRU Data Output IO AF23 PRG1_PRU0_GPO3 PRU-ICSSG PRU Data Output IO AD21 PRG1_PRU0_GPO4 PRU-ICSSG PRU Data Output IO AG23 PRG1_PRU0_GPO5 PRU-ICSSG PRU Data Output IO AF27 PRG1_PRU0_GPO6 PRU-ICSSG PRU Data Output IO AF22 PRG1_PRU0_GPO7 PRU-ICSSG PRU Data Output IO AG27 PRG1_PRU0_GPO8 PRU-ICSSG PRU Data Output IO AF28 PRG1_PRU0_GPO9 PRU-ICSSG PRU Data Output IO AF26 PRG1_PRU0_GPO10 PRU-ICSSG PRU Data Output IO AH25 PRG1_PRU0_GPO11 PRU-ICSSG PRU Data Output IO AF21 PRG1_PRU0_GPO12 PRU-ICSSG PRU Data Output IO AH20 PRG1_PRU0_GPO13 PRU-ICSSG PRU Data Output IO AH21 PRG1_PRU0_GPO14 PRU-ICSSG PRU Data Output IO AG20 PRG1_PRU0_GPO15 PRU-ICSSG PRU Data Output IO AD19 PRG1_PRU0_GPO16 PRU-ICSSG PRU Data Output IO AD20 PRG1_PRU0_GPO17 PRU-ICSSG PRU Data Output IO AH26 PRG1_PRU0_GPO18 PRU-ICSSG PRU Data Output IO AG25 PRG1_PRU0_GPO19 PRU-ICSSG PRU Data Output IO AG26 PRG1_PRU1_GPI0 PRU-ICSSG PRU Data Input I AH24 PRG1_PRU1_GPI1 PRU-ICSSG PRU Data Input I AH23 PRG1_PRU1_GPI2 PRU-ICSSG PRU Data Input I AG21 PRG1_PRU1_GPI3 PRU-ICSSG PRU Data Input I AH22 PRG1_PRU1_GPI4 PRU-ICSSG PRU Data Input I AE21 PRG1_PRU1_GPI5 PRU-ICSSG PRU Data Input I AC22 PRG1_PRU1_GPI6 PRU-ICSSG PRU Data Input I AG22 PRG1_PRU1_GPI7 PRU-ICSSG PRU Data Input I AD23 PRG1_PRU1_GPI8 PRU-ICSSG PRU Data Input I AE24 PRG1_PRU1_GPI9 PRU-ICSSG PRU Data Input I AF25 PRG1_PRU1_GPI10 PRU-ICSSG PRU Data Input I AF24 PRG1_PRU1_GPI11 PRU-ICSSG PRU Data Input I AC20 PRG1_PRU1_GPI12 PRU-ICSSG PRU Data Input I AE20 PRG1_PRU1_GPI13 PRU-ICSSG PRU Data Input I AF19 PRG1_PRU1_GPI14 PRU-ICSSG PRU Data Input I AH19

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated Table 4-39. PRU-ICSSG1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG1_PRU1_GPI15 PRU-ICSSG PRU Data Input I AG19 PRG1_PRU1_GPI16 PRU-ICSSG PRU Data Input I AE19 PRG1_PRU1_GPI17 PRU-ICSSG PRU Data Input I AE23 PRG1_PRU1_GPI18 PRU-ICSSG PRU Data Input I AD22 PRG1_PRU1_GPI19 PRU-ICSSG PRU Data Input I AC21 PRG1_PRU1_GPO0 PRU-ICSSG PRU Data Output IO AH24 PRG1_PRU1_GPO1 PRU-ICSSG PRU Data Output IO AH23 PRG1_PRU1_GPO2 PRU-ICSSG PRU Data Output IO AG21 PRG1_PRU1_GPO3 PRU-ICSSG PRU Data Output IO AH22 PRG1_PRU1_GPO4 PRU-ICSSG PRU Data Output IO AE21 PRG1_PRU1_GPO5 PRU-ICSSG PRU Data Output IO AC22 PRG1_PRU1_GPO6 PRU-ICSSG PRU Data Output IO AG22 PRG1_PRU1_GPO7 PRU-ICSSG PRU Data Output IO AD23 PRG1_PRU1_GPO8 PRU-ICSSG PRU Data Output IO AE24 PRG1_PRU1_GPO9 PRU-ICSSG PRU Data Output IO AF25 PRG1_PRU1_GPO10 PRU-ICSSG PRU Data Output IO AF24 PRG1_PRU1_GPO11 PRU-ICSSG PRU Data Output IO AC20 PRG1_PRU1_GPO12 PRU-ICSSG PRU Data Output IO AE20 PRG1_PRU1_GPO13 PRU-ICSSG PRU Data Output IO AF19 PRG1_PRU1_GPO14 PRU-ICSSG PRU Data Output IO AH19 PRG1_PRU1_GPO15 PRU-ICSSG PRU Data Output IO AG19 PRG1_PRU1_GPO16 PRU-ICSSG PRU Data Output IO AE19 PRG1_PRU1_GPO17 PRU-ICSSG PRU Data Output IO AE23 PRG1_PRU1_GPO18 PRU-ICSSG PRU Data Output IO AD22 PRG1_PRU1_GPO19 PRU-ICSSG PRU Data Output IO AC21 PRG1_PWM0_TZ_IN PRU_ICSSG PWM Trip Zone Input I AG25 PRG1_PWM0_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AG26 PRG1_PWM1_TZ_IN PRU_ICSSG PWM Trip Zone Input I AD22 PRG1_PWM1_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AC21 PRG1_PWM2_TZ_IN PRU_ICSSG PWM Trip Zone Input I AF24 PRG1_PWM2_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AE24 PRG1_PWM3_TZ_IN PRU_ICSSG PWM Trip Zone Input I AF26 PRG1_PWM3_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AF21 PRG1_PWM0_A0 PRU_ICSSG PWM Output A IO AH20 PRG1_PWM0_A1 PRU_ICSSG PWM Output A IO AG20 PRG1_PWM0_A2 PRU_ICSSG PWM Output A IO AD20 PRG1_PWM0_B0 PRU_ICSSG PWM Output B IO AH21 PRG1_PWM0_B1 PRU_ICSSG PWM Output B IO AD19 PRG1_PWM0_B2 PRU_ICSSG PWM Output B IO AH26 PRG1_PWM1_A0 PRU_ICSSG PWM Output A IO AE20 PRG1_PWM1_A1 PRU_ICSSG PWM Output A IO AH19 PRG1_PWM1_A2 PRU_ICSSG PWM Output A IO AE19 PRG1_PWM1_B0 PRU_ICSSG PWM Output B IO AF19 PRG1_PWM1_B1 PRU_ICSSG PWM Output B IO AG19 PRG1_PWM1_B2 PRU_ICSSG PWM Output B IO AE23 PRG1_PWM2_A0 PRU_ICSSG PWM Output A IO AF23 PRG1_PWM2_A1 PRU_ICSSG PWM Output A IO AF28

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated Table 4-39. PRU-ICSSG1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG1_PWM2_A2 PRU_ICSSG PWM Output A IO AG21 PRG1_PWM2_B0 PRU_ICSSG PWM Output B IO AG23 PRG1_PWM2_B1 PRU_ICSSG PWM Output B IO AH25 PRG1_PWM2_B2 PRU_ICSSG PWM Output B IO AE21 PRG1_PWM3_A0 PRU_ICSSG PWM Output A IO AE22 PRG1_PWM3_A1 PRU_ICSSG PWM Output A IO AF22 PRG1_PWM3_A2 PRU_ICSSG PWM Output A IO AD21 PRG1_PWM3_B0 PRU_ICSSG PWM Output B IO AG24 PRG1_PWM3_B1 PRU_ICSSG PWM Output B IO AG27 PRG1_PWM3_B2 PRU_ICSSG PWM Output B IO AF27 PRG1_RGMII1_RXC PRU_ICSSG RGMII Receive Clock I AF22 PRG1_RGMII1_RX_CTL PRU_ICSSG RGMII Receive Control I AG23 PRG1_RGMII1_TXC PRU_ICSSG RGMII Transmit Clock IO AD20 PRG1_RGMII1_TX_CTL PRU_ICSSG RGMII Transmit Control O AF21 PRG1_RGMII2_RXC PRU_ICSSG RGMII Receive Clock I AG22 PRG1_RGMII2_RX_CTL PRU_ICSSG RGMII Receive Control I AE21 PRG1_RGMII2_TXC PRU_ICSSG RGMII Transmit Clock IO AE19 PRG1_RGMII2_TX_CTL PRU_ICSSG RGMII Transmit Control O AC20 PRG1_RGMII1_RD0 PRU_ICSSG RGMII Receive Data I AE22 PRG1_RGMII1_RD1 PRU_ICSSG RGMII Receive Data I AG24 PRG1_RGMII1_RD2 PRU_ICSSG RGMII Receive Data I AF23 PRG1_RGMII1_RD3 PRU_ICSSG RGMII Receive Data I AD21 PRG1_RGMII1_TD0 PRU_ICSSG RGMII Transmit Data O AH20 PRG1_RGMII1_TD1 PRU_ICSSG RGMII Transmit Data O AH21 PRG1_RGMII1_TD2 PRU_ICSSG RGMII Transmit Data O AG20 PRG1_RGMII1_TD3 PRU_ICSSG RGMII Transmit Data O AD19 PRG1_RGMII2_RD0 PRU_ICSSG RGMII Receive Data I AH24 PRG1_RGMII2_RD1 PRU_ICSSG RGMII Receive Data I AH23 PRG1_RGMII2_RD2 PRU_ICSSG RGMII Receive Data I AG21 PRG1_RGMII2_RD3 PRU_ICSSG RGMII Receive Data I AH22 PRG1_RGMII2_TD0 PRU_ICSSG RGMII Transmit Data O AE20 PRG1_RGMII2_TD1 PRU_ICSSG RGMII Transmit Data O AF19 PRG1_RGMII2_TD2 PRU_ICSSG RGMII Transmit Data O AH19 PRG1_RGMII2_TD3 PRU_ICSSG RGMII Transmit Data O AG19 PRG1_UART0_CTSn PRU-ICSSG UART Clear to Send (active low) I AF26 PRG1_UART0_RTSn PRU-ICSSG UART Request to Send (active low) O AH25 PRG1_UART0_RXD PRU-ICSSG UART Receive Data I AF25 PRG1_UART0_TXD PRU-ICSSG UART Transmit Data O AF24 Table 4-40. PRU-ICSSG2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG2_ECAP0_IN_APWM_OUT PRU-ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Ouput IO AE16 PRG2_ECAP0_SYNC_IN PRU-ICSSG ECAP Sync Input I AD14 PRG2_ECAP0_SYNC_OUT PRU-ICSSG ECAP Sync Output O AG14 PRG2_IEP0_EDIO_OUTVALID PRU_ICSSG Industrial Ethernet Digital I/O Outvalid O A23

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated Table 4-40. PRU-ICSSG2 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG2_IEP0_EDC_LATCH_IN0 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AD12 PRG2_IEP0_EDC_LATCH_IN1 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AE12 PRG2_IEP0_EDC_SYNC_OUT0 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AH12 PRG2_IEP0_EDC_SYNC_OUT1 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AF12 PRG2_IEP0_EDIO_DATA_IN_OUT28 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/Output IO R23 PRG2_IEP0_EDIO_DATA_IN_OUT29 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/Output IO T24 PRG2_IEP0_EDIO_DATA_IN_OUT30 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/Output IO R25 PRG2_IEP0_EDIO_DATA_IN_OUT31 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/Output IO T27 PRG2_IEP1_EDC_LATCH_IN0 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I R23 PRG2_IEP1_EDC_LATCH_IN1 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I R25 PRG2_IEP1_EDC_SYNC_OUT0 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O T24 PRG2_IEP1_EDC_SYNC_OUT1 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O T27 PRG2_MDIO0_MDC PRU-ICSSG MDIO Clock O AE15 PRG2_MDIO0_MDIO PRU-ICSSG MDIO Data IO AC19 PRG2_PRU0_GPI0 PRU-ICSSG PRU Data Input I AF18 PRG2_PRU0_GPI1 PRU-ICSSG PRU Data Input I AE18 PRG2_PRU0_GPI2 PRU-ICSSG PRU Data Input I AH17 PRG2_PRU0_GPI3 PRU-ICSSG PRU Data Input I AG18 PRG2_PRU0_GPI4 PRU-ICSSG PRU Data Input I AG17 PRG2_PRU0_GPI5 PRU-ICSSG PRU Data Input I AF17 PRG2_PRU0_GPI6 PRU-ICSSG PRU Data Input I AE17 PRG2_PRU0_GPI7 PRU-ICSSG PRU Data Input I AC19 PRG2_PRU0_GPI8 PRU-ICSSG PRU Data Input I AH16 PRG2_PRU0_GPI9 PRU-ICSSG PRU Data Input I AG16 PRG2_PRU0_GPI10 PRU-ICSSG PRU Data Input I AF16 PRG2_PRU0_GPI11 PRU-ICSSG PRU Data Input I AE16 PRG2_PRU0_GPI12 PRU-ICSSG PRU Data Input I N23 PRG2_PRU0_GPI13 PRU-ICSSG PRU Data Input I M26 PRG2_PRU0_GPI14 PRU-ICSSG PRU Data Input I P28 PRG2_PRU0_GPI15 PRU-ICSSG PRU Data Input I P27 PRG2_PRU0_GPI16 PRU-ICSSG PRU Data Input I AD16 PRG2_PRU0_GPI17 PRU-ICSSG PRU Data Input I P23 PRG2_PRU0_GPO0 PRU-ICSSG PRU Data Output IO AF18 PRG2_PRU0_GPO1 PRU-ICSSG PRU Data Output IO AE18 PRG2_PRU0_GPO2 PRU-ICSSG PRU Data Output IO AH17 PRG2_PRU0_GPO3 PRU-ICSSG PRU Data Output IO AG18 PRG2_PRU0_GPO4 PRU-ICSSG PRU Data Output IO AG17 PRG2_PRU0_GPO5 PRU-ICSSG PRU Data Output IO AF17

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated Table 4-40. PRU-ICSSG2 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG2_PRU0_GPO6 PRU-ICSSG PRU Data Output IO AE17 PRG2_PRU0_GPO7 PRU-ICSSG PRU Data Output IO AC19 PRG2_PRU0_GPO8 PRU-ICSSG PRU Data Output IO AH16 PRG2_PRU0_GPO9 PRU-ICSSG PRU Data Output IO AG16 PRG2_PRU0_GPO10 PRU-ICSSG PRU Data Output IO AF16 PRG2_PRU0_GPO11 PRU-ICSSG PRU Data Output IO AE16 PRG2_PRU0_GPO12 PRU-ICSSG PRU Data Output IO N23 PRG2_PRU0_GPO13 PRU-ICSSG PRU Data Output IO M26 PRG2_PRU0_GPO14 PRU-ICSSG PRU Data Output IO P28 PRG2_PRU0_GPO15 PRU-ICSSG PRU Data Output IO P27 PRG2_PRU0_GPO16 PRU-ICSSG PRU Data Output IO AD16 PRG2_PRU0_GPO17 PRU-ICSSG PRU Data Output IO P23 PRG2_PRU1_GPI0 PRU-ICSSG PRU Data Input I AH15 PRG2_PRU1_GPI1 PRU-ICSSG PRU Data Input I AC16 PRG2_PRU1_GPI2 PRU-ICSSG PRU Data Input I AD17 PRG2_PRU1_GPI3 PRU-ICSSG PRU Data Input I AH14 PRG2_PRU1_GPI4 PRU-ICSSG PRU Data Input I AG14 PRG2_PRU1_GPI5 PRU-ICSSG PRU Data Input I AG15 PRG2_PRU1_GPI6 PRU-ICSSG PRU Data Input I AC17 PRG2_PRU1_GPI7 PRU-ICSSG PRU Data Input I AE15 PRG2_PRU1_GPI8 PRU-ICSSG PRU Data Input I AD15 PRG2_PRU1_GPI9 PRU-ICSSG PRU Data Input I AF14 PRG2_PRU1_GPI10 PRU-ICSSG PRU Data Input I AC15 PRG2_PRU1_GPI11 PRU-ICSSG PRU Data Input I AD14 PRG2_PRU1_GPI12 PRU-ICSSG PRU Data Input I N26 PRG2_PRU1_GPI13 PRU-ICSSG PRU Data Input I N25 PRG2_PRU1_GPI14 PRU-ICSSG PRU Data Input I P24 PRG2_PRU1_GPI15 PRU-ICSSG PRU Data Input I R27 PRG2_PRU1_GPI16 PRU-ICSSG PRU Data Input I AE14 PRG2_PRU1_GPI17 PRU-ICSSG PRU Data Input I T23 PRG2_PRU1_GPO0 PRU-ICSSG PRU Data Output IO AH15 PRG2_PRU1_GPO1 PRU-ICSSG PRU Data Output IO AC16 PRG2_PRU1_GPO2 PRU-ICSSG PRU Data Output IO AD17 PRG2_PRU1_GPO3 PRU-ICSSG PRU Data Output IO AH14 PRG2_PRU1_GPO4 PRU-ICSSG PRU Data Output IO AG14 PRG2_PRU1_GPO5 PRU-ICSSG PRU Data Output IO AG15 PRG2_PRU1_GPO6 PRU-ICSSG PRU Data Output IO AC17 PRG2_PRU1_GPO7 PRU-ICSSG PRU Data Output IO AE15 PRG2_PRU1_GPO8 PRU-ICSSG PRU Data Output IO AD15 PRG2_PRU1_GPO9 PRU-ICSSG PRU Data Output IO AF14 PRG2_PRU1_GPO10 PRU-ICSSG PRU Data Output IO AC15 PRG2_PRU1_GPO11 PRU-ICSSG PRU Data Output IO AD14 PRG2_PRU1_GPO12 PRU-ICSSG PRU Data Output IO N26 PRG2_PRU1_GPO13 PRU-ICSSG PRU Data Output IO N25 PRG2_PRU1_GPO14 PRU-ICSSG PRU Data Output IO P24 PRG2_PRU1_GPO15 PRU-ICSSG PRU Data Output IO R27 PRG2_PRU1_GPO16 PRU-ICSSG PRU Data Output IO AE14

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated Table 4-40. PRU-ICSSG2 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG2_PRU1_GPO17 PRU-ICSSG PRU Data Output IO T23 PRG2_PWM0_TZ_IN PRU_ICSSG PWM Trip Zone Input I P28 PRG2_PWM0_TZ_OUT PRU_ICSSG PWM Trip Zone Output O P24 PRG2_PWM1_TZ_IN PRU_ICSSG PWM Trip Zone Input I F18 PRG2_PWM1_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AE14 PRG2_PWM2_TZ_IN PRU_ICSSG PWM Trip Zone Input I P23 PRG2_PWM2_TZ_OUT PRU_ICSSG PWM Trip Zone Output O T23 PRG2_PWM3_TZ_IN PRU_ICSSG PWM Trip Zone Input I AE15 PRG2_PWM3_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AF14 PRG2_PWM0_A0 PRU_ICSSG PWM Output A IO AG17 PRG2_PWM0_A1 PRU_ICSSG PWM Output A IO AD16 PRG2_PWM0_A2 PRU_ICSSG PWM Output A IO AD15 PRG2_PWM0_B0 PRU_ICSSG PWM Output B IO AH16 PRG2_PWM0_B1 PRU_ICSSG PWM Output B IO AD17 PRG2_PWM0_B2 PRU_ICSSG PWM Output B IO AC15 PRG2_PWM1_A0 PRU_ICSSG PWM Output A IO R23 PRG2_PWM1_A1 PRU_ICSSG PWM Output A IO AD18 PRG2_PWM1_A2 PRU_ICSSG PWM Output A IO AE26 PRG2_PWM1_B0 PRU_ICSSG PWM Output B IO T24 PRG2_PWM1_B1 PRU_ICSSG PWM Output B IO AH18 PRG2_PWM1_B2 PRU_ICSSG PWM Output B IO AE28 PRG2_PWM2_A0 PRU_ICSSG PWM Output A IO N23 PRG2_PWM2_A1 PRU_ICSSG PWM Output A IO P27 PRG2_PWM2_A2 PRU_ICSSG PWM Output A IO N25 PRG2_PWM2_B0 PRU_ICSSG PWM Output B IO M26 PRG2_PWM2_B1 PRU_ICSSG PWM Output B IO N26 PRG2_PWM2_B2 PRU_ICSSG PWM Output B IO R27 PRG2_PWM3_A0 PRU_ICSSG PWM Output A IO AF18 PRG2_PWM3_A1 PRU_ICSSG PWM Output A IO AF17 PRG2_PWM3_A2 PRU_ICSSG PWM Output A IO AH15 PRG2_PWM3_B0 PRU_ICSSG PWM Output B IO AG18 PRG2_PWM3_B1 PRU_ICSSG PWM Output B IO AE17 PRG2_PWM3_B2 PRU_ICSSG PWM Output B IO AC16 PRG2_RGMII1_RXC PRU_ICSSG RGMII Receive Clock I AF17 PRG2_RGMII1_RX_CTL PRU_ICSSG RGMII Receive Control I AG17 PRG2_RGMII1_TXC PRU_ICSSG RGMII Transmit Clock IO AD16 PRG2_RGMII1_TX_CTL PRU_ICSSG RGMII Transmit Control O AE17 PRG2_RGMII2_RXC PRU_ICSSG RGMII Receive Clock I AG15 PRG2_RGMII2_RX_CTL PRU_ICSSG RGMII Receive Control I AG14 PRG2_RGMII2_TXC PRU_ICSSG RGMII Transmit Clock IO AE14 PRG2_RGMII2_TX_CTL PRU_ICSSG RGMII Transmit Control O AC17 PRG2_RGMII1_RD0 PRU_ICSSG RGMII Receive Data I AF18 PRG2_RGMII1_RD1 PRU_ICSSG RGMII Receive Data I AE18 PRG2_RGMII1_RD2 PRU_ICSSG RGMII Receive Data I AH17 PRG2_RGMII1_RD3 PRU_ICSSG RGMII Receive Data I AG18 PRG2_RGMII1_TD0 PRU_ICSSG RGMII Transmit Data O AH16 PRG2_RGMII1_TD1 PRU_ICSSG RGMII Transmit Data O AG16

4.3.17 SERDES

4.3.17.1 MAIN Domain

Table 4-41. SERDES0 Signal Descriptions(1) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SERDES0_REFCLKN SERDES Clock Input (negative) I AG5 SERDES0_REFCLKP SERDES Clock Input (positive) I AG6 SERDES0_REFRES SERDES Reference Resistor(2) A AC9 SERDES0_RXN SERDES Differential Receive Data (negative) I AH3 SERDES0_RXP SERDES Differential Receive Data (positive) I AG2 SERDES0_TXN SERDES Differential Transmit Data (negative) O AH4 SERDES0_TXP SERDES Differential Transmit Data (positive) O AG3 (1) The functionality of these pins is controlled by CTRLMMR_SERDES0_CTRL 1:0] LANE_FUNC_SEL. 0x0 = USB3, 0x1 = PCIe0 Lane0, 0x2 = ICSS2 SGMII Lane0. (2) The required resistor value is 3kΩ ±1%. Table 4-42. SERDES1 Signal Descriptions(1) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SERDES1_REFCLKN SERDES Clock Input (negative) I AH6 SERDES1_REFCLKP SERDES Clock Input (positive) I AH7 SERDES1_REFRES SERDES Reference Resistor(2) A AC14 SERDES1_RXN SERDES Differential Receive Data (negative) I AG9 SERDES1_RXP SERDES Differential Receive Data (positive) I AH10 SERDES1_TXN SERDES Differential Transmit Data (negative) O AH9 SERDES1_TXP SERDES Differential Transmit Data (positive) O AG8

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated (1) The functionality of these pins is controlled by CTRLMMR_SERDES1_CTRL [1:0] LANE_FUNC_SEL. 0x0 = PCIe1 Lane0, 0x1 = PCIe0 Lane1, 0x2 = ICSS2 SGMII Lane1. (2) The required resistor value is 3kΩ ±1%.

4.3.18 UART

4.3.18.1 MAIN Domain

Table 4-43. UART0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART0_CTSn UART Clear to Send (active low) I AG11 UART0_DCDn UART Data Carrier Detect (active low) I D25 UART0_DSRn UART Data Set Ready (active low) I B26 UART0_DTRn UART Data Terminal Ready (active low) O A24 UART0_RIN UART Ring Indicator I E24 UART0_RTSn UART Request to Send (active low) O AD11 UART0_RXD UART Receive Data I AF11 UART0_TXD UART Transmit Data O AE11 Table 4-44. UART1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART1_CTSn UART Clear to Send (active low) I AD22 UART1_RTSn UART Request to Send (active low) O AC21 UART1_RXD UART Receive Data I AE23 UART1_TXD UART Transmit Data O AD23 Table 4-45. UART2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART2_CTSn UART Clear to Send (active low) I Y26 UART2_RTSn UART Request to Send (active low) O W26 UART2_RXD UART Receive Data I Y27 UART2_TXD UART Transmit Data O W28

4.3.18.2 MCU Domain

Table 4-46. UART0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_UART0_CTSn UART Clear to Send (active low) I P1 MCU_UART0_RTSn UART Request to Send (active low) O N3 MCU_UART0_RXD UART Receive Data I P4 MCU_UART0_TXD UART Transmit Data O P5

4.3.18.3 WKUP Domain

Table 4-47. UART0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_UART0_CTSn UART Clear to Send (active low) I AC2 WKUP_UART0_RTSn UART Request to Send (active low) O AC1 WKUP_UART0_RXD UART Receive Data I AB1 WKUP_UART0_TXD UART Transmit Data O AB5

4.3.19 USB

4.3.19.1 MAIN Domain

Table 4-48. USB0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] USB0_DM USB 2.0 Differential Data (negative) IO AE2 USB0_DP USB 2.0 Differential Data (positive) IO AF1 USB0_DRVVBUS USB VBUS control output (active high) O AD9 USB0_ID USB 2.0 Dual-Role Device Role Select A AF7 USB0_VBUS (1) USB Level-shifted VBUS Input A AE7 (1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 7.4. Table 4-49. USB1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] USB1_DM USB 2.0 Differential Data (negative) IO AD2 USB1_DP USB 2.0 Differential Data (positive) IO AE1 USB1_DRVVBUS USB VBUS control output (active high) O AC8 USB1_ID USB 2.0 Dual-Role Device Role Select A AF5 USB1_VBUS (1) USB Level-shifted VBUS Input A AF6 (1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 7.4.

4.3.20 Emulation and Debug

4.3.20.1 MAIN Domain

Table 4-50. Emulation and Debug 0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EMU0 Emulation Control 0 IO AA2 EMU1 Emulation Control 1 IO AA1 TCK JTAG Test Clock Input I AA4 TDI JTAG Test Data Input I C20 TDO JTAG Test Data Output OZ A20 TMS JTAG Test Mode Select Input I A21 TRSTn JTAG Reset I AA3 TRC_CLK Trace Clock O AF18 TRC_CTL Trace Control O AE18 TRC_DATA0 Trace Data 0 O AH17

4.3.21 System and Miscellaneous

4.3.21.1 Boot Mode Configuration

4.3.21.1.1 MAIN Domain

Table 4-51. Sysboot Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] BOOTMODE00 Bootmode pin 00 I M27 BOOTMODE01 Bootmode pin 01 I M23 BOOTMODE02 Bootmode pin 02 I M28 BOOTMODE03 Bootmode pin 03 I M24 BOOTMODE04 Bootmode pin 04 I N24 BOOTMODE05 Bootmode pin 05 I N27 BOOTMODE06 Bootmode pin 06 I N28 BOOTMODE07 Bootmode pin 07 I M25 BOOTMODE08 Bootmode pin 08 I N23 BOOTMODE09 Bootmode pin 09 I M26 BOOTMODE10 Bootmode pin 10 I P28 BOOTMODE11 Bootmode pin 11 I P27 BOOTMODE12 Bootmode pin 12 I N26 BOOTMODE13 Bootmode pin 13 I N25 BOOTMODE14 Bootmode pin 14 I P24 BOOTMODE15 Bootmode pin 15 I R27 BOOTMODE16 Bootmode pin 16 I P25 BOOTMODE17 Bootmode pin 17 I P26 BOOTMODE18 Bootmode pin 18 I U28

4.3.21.1.2 MCU Domain

Table 4-52. Sysboot Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_BOOTMODE00 Bootmode pin 00 I AF4 MCU_BOOTMODE01 Bootmode pin 01 I AF3 MCU_BOOTMODE02 Bootmode pin 02 I AE3 MCU_BOOTMODE03(1) Bootmode pin 03 I AD1 MCU_BOOTMODE04(1) Bootmode pin 04 I AC3 MCU_BOOTMODE05(1) Bootmode pin 05 I Y2 MCU_BOOTMODE06(1) Bootmode pin 06 I Y1 MCU_BOOTMODE07(1) Bootmode pin 07 I Y3 MCU_BOOTMODE08(1) Bootmode pin 08 I AC5 MCU_BOOTMODE09 Bootmode pin 09 I AB4

ADVANCE□INFORMATION DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated (1) These signals must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level.

4.3.21.2 Clock

4.3.21.2.1 MAIN Domain

Table 4-53. Clock1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] OSC1_XI High frequency oscillator input I C22 OSC1_XO High frequency oscillator output O E22

4.3.21.2.2 WKUP Domain

Table 4-54. Clock0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_LFOSC0_XI Low frequency (32.768 KHz) oscillator input I AE4 WKUP_LFOSC0_XO Low frequency (32.768 KHz) oscillator output O AC4 WKUP_OSC0_XI High frequency oscillator input I AD5 WKUP_OSC0_XO High frequency oscillator output O AE6

4.3.21.3 System

4.3.21.3.1 MAIN Domain

Table 4-55. System0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EXT_REFCLK1 External clock input to Main Domain, routed to Timer clock muxes as one of the selectable input clock sources for Timer/WDT modules, or as reference clock to MAIN_PLL2 (PER1 PLL) I A22 NMIn External Interrupt I F18 OBSCLK0 Observation clock output for test and debug purposes only O C23 PORz Main Domain cold reset I E19 PORz_OUT Main Domain POR status output O C19 REFCLK0N SERDES Differential Clock Output (negative) O AF9 REFCLK0P SERDES Differential Clock Output (positive) O AF10 REFCLK1N SERDES Differential Clock Output (negative) O AE8 REFCLK1P SERDES Differential Clock Output (positive) O AE9 RESETSTATz Main Domain warm reset status output O D19 RESETz Main Domain warm reset I F17 SOC_SAFETY_ERRORn Error signal output from Main Domain ESM IO E20 SYNC0_OUT CPTS Time Stamp Generator Bit 0 O D21 SYNC1_OUT CPTS Time Stamp Generator Bit 1 O A22 SYNC2_OUT CPTS Time Stamp Generator Bit 2 O AE18 SYNC3_OUT CPTS Time Stamp Generator Bit 3 O AH17 SYSCLKOUT0 SYSCLK0 output from Main PLL controller (divided by 6) for test and debug purposes only O B22

4.3.21.3.2 WKUP Domain

Table 4-56. System0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_BYP_POR MCU Bypass reset circuitry input. 0 = Internal POR is used, 1 = External MCU_PORz signal is used. I V5 MCU_CLKOUT0 Reference clock output for Ethernet PHYs (50MHz or 25MHz) O AB2 MCU_EXT_REFCLK0 External system clock input I AB3 MCU_OBSCLK0 Observation clock output for test and debug purposes only O AB2 MCU_PORz MCU Domain cold reset I W5 MCU_PORz_OUT MCU Domain POR status output O V2 MCU_RESETSTATz MCU Domain warm reset status output O V3 MCU_RESETz MCU Domain warm reset I W4 MCU_SAFETY_ERRORn Error signal output from MCU Domain ESM IO W3 MCU_SYSCLKOUT0 MCU Domain system clock output for test and debug purposes only O AB3 PMIC_POWER_EN0 Power enable output for MAIN Domain supplies O Y5 PMIC_POWER_EN1 Power enable output for MAIN Domain supplies O AA5

4.3.21.4 Miscellaneous

4.3.21.4.1 WKUP Domain

Table 4-57. Miscellaneous0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] TEMP_DIODE_P Temperature Sensor Diode A W6

4.3.21.5 EFUSE

4.3.21.5.1 MAIN Domain

Table 4-58. EFUSE0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] VPP_CORE (1) Programming voltage for MAIN Domain efuses PWR F21 (1) This signal is valid only for High-Security devices. For more details, see Section 5.8, VPP Specification for One-Time Programmable (OTP) eFUSEs. For General Purpose devices do not connect any signal, test point, or board trace to this signal.

4.3.21.5.2 MCU Domain

Table 4-59. EFUSE0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] VPP_MCU (1) Programming voltage for MCU Domain efuses PWR T6 (1) This signal is valid only for High-Security devices. For more details, see Section 5.8, VPP Specification for One-Time Programmable (OTP) eFUSEs. For General Purpose devices do not connect any signal, test point, or board trace to this signal.

4.3.22 Power Supply

Table 4-60. Power Supply Signal Description SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] CAP_VDDAR_CORE0(1) External capacitor connection for CORE SRAM LDOs CAP P17 CAP_VDDAR_CORE1(1) External capacitor connection for CORE SRAM LDOs CAP V17 CAP_VDDAR_CORE2(1) External capacitor connection for CORE SRAM LDOs CAP W16 CAP_VDDAR_CORE3(1) External capacitor connection for MSMC SRAM LDOs CAP M14 CAP_VDDAR_CORE4(1) External capacitor connection for MSMC SRAM LDOs CAP L15 CAP_VDDAR_MCU(1) External capacitor connection for MCU SRAM LDO CAP U10 CAP_VDDAR_MPU0_0(1) External capacitor connection for MPU SRAM LDOs CAP M12 CAP_VDDAR_MPU0_1(1) External capacitor connection for MPU SRAM LDOs CAP N12 CAP_VDDAR_MPU1_0(1) External capacitor connection for MPU SRAM LDOs CAP N18 CAP_VDDAR_MPU1_1(1) External capacitor connection for MPU SRAM LDOs CAP N15 CAP_VDDAR_WKUP(1) External capacitor connection for WKUP SRAM LDO CAP Y10 CAP_VDDA_1P8_IOLDO_WKUP(1) External capacitor connection for IO Bias LDO in WKUP domain CAP AA8 CAP_VDDA_1P8_SDIO(2) External capacitor connection for SDIO LDO CAP J17 CAP_VDDA_1P8_IOLDO0(1) External capacitor connection for IO Bias LDO CAP G19 CAP_VDDA_1P8_IOLDO1(1) External capacitor connection for IO Bias LDO CAP Y19 CAP_VDDSHV_SDIO(3) External capacitor connection for SDIO LDO CAP H18 CAP_VDD_WKUP(1) External capacitor connection for WKUP LDO CAP V9 VDDA_1P8_MON_WKUP Supply monitor in WKUP domain PWR AB6 VDDA_1P8_SDIO SDIO LDO analog power supply PWR G17 VDDA_1P8_CSI0 CSI PHY analog power supply PWR L20, M21 VDDA_1P8_MON0 Supply monitor in MAIN domain PWR AC6 VDDA_1P8_OLDI0 OLDI analog power supply PWR L22 VDDA_1P8_SERDES0 SERDES0/1 (USB, PCIE) analog power supply PWR AA14, AB13, AB15 VDDA_3P3_IOLDO_WKUP WKUP IO Bias LDO analog power supply PWR AB9 VDDA_3P3_MON_WKUP Supply monitor in WKUP domain PWR U6 VDDA_3P3_SDIO SDIO LDO analog power supply PWR H17 VDDA_3P3_USB USB analog power supply PWR AC12 VDDA_3P3_IOLDO0 IO Bias LDO analog power supply PWR G18 VDDA_3P3_IOLDO1 IO Bias LDO analog power supply PWR AA21 VDDA_3P3_MON0 Supply monitor in MAIN domain PWR AC10 VDDA_ADC_MCU ADC0, ADC1 analog power supply PWR M7, M9 VDDA_LDO_WKUP WKUP LDO analog power supply PWR AB8 VDDA_MCU MCU SRAM LDO, MCU DPLL, CPSW DPLL analog power supply PWR U12 VDDA_PLL0_DDR DDR DPLL analog power supply PWR H15 VDDA_PLL1_DDR DDR De-skew DPLL analog power supply PWR H11

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated Table 4-60. Power Supply Signal Description (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] VDDA_PLL_CORE CORE DPLL, PER1 DPLL analog power supply PWR Y17 VDDA_PLL_DSS DSS DPLL analog power supply PWR L21 VDDA_PLL_MPU0 MPU0 DPLL analog power supply PWR L12 VDDA_PLL_MPU1 MPU1 DPLL analog power supply PWR K15 VDDA_PLL_PER0 PER0 DPLL analog power supply PWR AB7 VDDA_POR_WKUP(5) WKUP POR/POK analog power supply PWR Y9 VDDA_SRAM_CORE0 CORE SRAM LDOs analog power supply PWR M19 VDDA_SRAM_CORE1 CORE SRAM LDOs analog power supply PWR V16 VDDA_SRAM_MPU0 MPU SRAM LDOs analog power supply PWR K7 VDDA_SRAM_MPU1 MPU SRAM LDOs analog power supply PWR L18 VDDA_VSYS_MON Supply monitor for system PWR AC11 VDDA_WKUP WKUP High/Low Frequency Oscillator (WKUP_LFOSC0 / WKUP_OSC0), SRAM LDO analog power supply PWR AA9 VDDS0 IO bias supply for VDDSHV0 PWR G12 VDDS0_WKUP IO bias supply for VDDSHV0_WKUP PWR V8 VDDS1 IO bias supply for VDDSHV1 PWR AA16 VDDS1_WKUP IO bias supply for VDDSHV1_WKUP PWR T9 VDDS2 IO bias supply for VDDSHV2 PWR P20 VDDS2_WKUP IO bias supply for VDDSHV2_WKUP PWR N8 VDDS3 IO bias supply for VDDSHV3 PWR T20 VDDS4 IO bias supply for VDDSHV4 PWR Y20 VDDS5 IO bias supply for VDDSHV5 PWR AC18 VDDS6 IO bias supply for VDDSHV6 PWR F20 VDDS7 IO bias supply for VDDSHV7 PWR K20 VDDS8 IO bias supply for VDDSHV8 PWR AA10 VDDSHV0 Dual-voltage IO domain power supply PWR G15, H16 VDDSHV0_WKUP Dual-voltage IO domain power supply PWR U8, V7, W8, Y7 VDDSHV1 Dual-voltage IO domain power supply PWR AA18, AB17 VDDSHV1_WKUP Dual-voltage IO domain power supply PWR R6, R8, T7 VDDSHV2 Dual-voltage IO domain power supply PWR N20, N22, P21, R20, R22 VDDSHV2_WKUP Dual-voltage IO domain power supply PWR N6, P7, P9 VDDSHV3 Dual-voltage IO domain power supply PWR T21, U20, U22, V21, V23 VDDSHV4 Dual-voltage IO domain power supply PWR AA22, W20, W22, Y21, Y23 VDDSHV5 Dual-voltage IO domain power supply PWR AA20, AB19, AB21, AB23 VDDSHV6 Dual-voltage IO domain power supply PWR G20, H19, H21 VDDSHV7 Dual-voltage IO domain power supply PWR J20, J22, K21 VDDSHV8 Dual-voltage IO domain power supply PWR AB11 VDDS_DDR DDR IO domain power supply PWR G10, G14, G8, H13, H7, H9 VDDS_OSC1 MAIN High Frequency Oscillator (OSC1) analog power supply PWR J16

ADVANCE□INFORMATION DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated (1) This pin must always be connected via a 1-uF capacitor to vss. (2) The net connecting CAP_VDDA_1P8_SDIO and VDDA_1P8_SDIO to VDDS6 or VDDS7 must be connected to a 3.3-uF decoupling capacitor. When SDIO LDO is not used, this pin should be connected to VDDA_1P8_SDIO and an external capacitor in the range of 1uF to 3.3uF. Additionally, VDDA_3P3_SDIO should be connected to 3.3V, even when SDIO LDO is not used. (3) When CAP_VDDSHV_SDIO is connected to VDDSHV6 or VDDSHV7, the entire net which connects these pins should not exceed TBD- uF of decoupling capacitance. When SDIO LDO is not used, this pin should be left unconnected. (4) These power rails should be connected together on the board level. (5) VDDA_WKUP_POR is preferred to be connected to CAP_VDDA_1P8_IOLDO_WKUP when using internal POR feature.

4.4 Pin Multiplexing

Table 4-61 describes the device pin multiplexing associated with pins. NOTE Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins. Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are associated with peripheral logic functions. Table 4-61, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see section Pad Configuration Registers in section Control Module (CTRL_MMR) of chapter Device Configuration of the Device TRM. Refer to the respective peripheral chapter of the Device TRM for information associated with peripheral signal multiplexing. NOTE When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided. NOTE Table 4-61, Pin Multiplexing does not include SerDes signal functions. For more information, refer to the Serializer/Deserializer (SerDes) chapter in the Device TRM. NOTE The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in the device TRM. For more information on the I/O cell configurations, see section Pad Configuration Registers in section Control Module (BOOT_CFG) of chapter Device Configuration of the Device TRM. Table 4-61. Pin Multiplexing ADDRESS REGISTER NAME BALL NUMBER MUXMODE[7:0] SETTINGS 0 1 2 3 4 5 6 7 Bootstrap 0x0011C000 PADCONFIG0 M27 GPMC0_AD0 GPIO0_0 BOOTMODE00 0x0011C004 PADCONFIG1 M23 GPMC0_AD1 GPIO0_1 BOOTMODE01 0x0011C008 PADCONFIG2 M28 GPMC0_AD2 GPIO0_2 BOOTMODE02 0x0011C00C PADCONFIG3 M24 GPMC0_AD3 GPIO0_3 BOOTMODE03 0x0011C010 PADCONFIG4 N24 GPMC0_AD4 GPIO0_4 BOOTMODE04 0x0011C014 PADCONFIG5 N27 GPMC0_AD5 GPIO0_5 BOOTMODE05

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Table 4-61. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMBER MUXMODE[7:0] SETTINGS 0 1 2 3 4 5 6 7 Bootstrap 0x0011C018 PADCONFIG6 N28 GPMC0_AD6 GPIO0_6 BOOTMODE06 0x0011C01C PADCONFIG7 M25 GPMC0_AD7 GPIO0_7 BOOTMODE07 0x0011C020 PADCONFIG8 N23 GPMC0_AD8 PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_PWM2_A0 GPIO0_8 BOOTMODE08 0x0011C024 PADCONFIG9 M26 GPMC0_AD9 PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_PWM2_B0 GPIO0_9 BOOTMODE09 0x0011C028 PADCONFIG10 P28 GPMC0_AD10 PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_PWM0_TZ_I N GPIO0_10 BOOTMODE10 0x0011C02C PADCONFIG11 P27 GPMC0_AD11 PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_PWM2_A1 GPIO0_11 BOOTMODE11 0x0011C030 PADCONFIG12 N26 GPMC0_AD12 PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_PWM2_B1 GPIO0_12 BOOTMODE12 0x0011C034 PADCONFIG13 N25 GPMC0_AD13 PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_PWM2_A2 GPIO0_13 BOOTMODE13 0x0011C038 PADCONFIG14 P24 GPMC0_AD14 PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_PWM0_TZ_ OUT GPIO0_14 BOOTMODE14 0x0011C03C PADCONFIG15 R27 GPMC0_AD15 PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_PWM2_B2 GPIO0_15 BOOTMODE15 0x0011C040 PADCONFIG16 R28 GPMC0_CLK GPIO0_16 0x0011C044 PADCONFIG17 P25 GPMC0_ADVn_AL E GPIO0_17 BOOTMODE16 0x0011C048 PADCONFIG18 P26 GPMC0_OEn_REn GPIO0_18 BOOTMODE17 0x0011C04C PADCONFIG19 U28 GPMC0_WEn GPIO0_19 BOOTMODE18 0x0011C050 PADCONFIG20 T28 GPMC0_BE0n_CL E GPIO0_20 0x0011C054 PADCONFIG21 P23 GPMC0_BE1n PRG2_PRU0_GPO PRG2_PRU0_GPI1 TIMER_IO2 PRG2_PWM2_TZ_I N GPIO0_21 0x0011C058 PADCONFIG22 R26 GPMC0_WAIT0 GPIO0_22 0x0011C05C PADCONFIG23 R23 GPMC0_WAIT1 PRG2_PWM1_A0 PRG2_IEP1_EDC_ LATCH_IN0 TIMER_IO3 PRG2_IEP0_EDIO _DATA_IN_OUT28 GPIO0_23 0x0011C060 PADCONFIG24 T25 GPMC0_WPn GPIO0_24 0x0011C064 PADCONFIG25 T24 GPMC0_DIR PRG2_PWM1_B0 PRG2_IEP1_EDC_ SYNC_OUT0 TIMER_IO6 PRG2_IEP0_EDIO _DATA_IN_OUT29 GPIO0_25 0x0011C068 PADCONFIG26 R24 GPMC0_CSn0 GPIO0_26 0x0011C06C PADCONFIG27 T23 GPMC0_CSn1 PRG2_PRU1_GPO PRG2_PRU1_GPI1 TIMER_IO7 PRG2_PWM2_TZ_ OUT GPIO0_27 0x0011C070 PADCONFIG28 R25 GPMC0_CSn2 GPMC0_A27 PRG2_IEP1_EDC_ LATCH_IN1 I2C2_SDA PRG2_IEP0_EDIO _DATA_IN_OUT30 GPIO0_28 0x0011C074 PADCONFIG29 T27 GPMC0_CSn3 GPMC0_A26 PRG2_IEP1_EDC_ SYNC_OUT1 I2C2_SCL PRG2_IEP0_EDIO _DATA_IN_OUT31 GPIO0_29 0x0011C078 PADCONFIG30 AF18 PRG2_PRU0_GPO PRG2_PRU0_GPI0 PRG2_RGMII1_RD GPMC0_A25 TRC_CLK PRG2_PWM3_A0 GPIO0_30 0x0011C07C PADCONFIG31 AE18 PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_RGMII1_RD GPMC0_A24 TRC_CTL SYNC2_OUT GPIO0_31 0x0011C080 PADCONFIG32 AH17 PRG2_PRU0_GPO PRG2_PRU0_GPI2 PRG2_RGMII1_RD GPMC0_A23 TRC_DATA0 SYNC3_OUT GPIO0_32

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M 100 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-61. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMBER MUXMODE[7:0] SETTINGS 0 1 2 3 4 5 6 7 Bootstrap 0x0011C084 PADCONFIG33 AG18 PRG2_PRU0_GPO PRG2_PRU0_GPI3 PRG2_RGMII1_RD GPMC0_A22 TRC_DATA1 PRG2_PWM3_B0 GPIO0_33 0x0011C088 PADCONFIG34 AG17 PRG2_PRU0_GPO PRG2_PRU0_GPI4 PRG2_RGMII1_RX _CTL GPMC0_A21 TRC_DATA2 PRG2_PWM0_A0 GPIO0_34 0x0011C08C PADCONFIG35 AF17 PRG2_PRU0_GPO PRG2_PRU0_GPI5 PRG2_RGMII1_RX C GPMC0_A20 TRC_DATA3 PRG2_PWM3_A1 GPIO0_35 0x0011C090 PADCONFIG36 AE17 PRG2_PRU0_GPO PRG2_PRU0_GPI6 PRG2_RGMII1_TX _CTL GPMC0_A19 TRC_DATA4 PRG2_PWM3_B1 GPIO0_36 0x0011C094 PADCONFIG37 AC19 PRG2_PRU0_GPO PRG2_PRU0_GPI7 PRG2_MDIO0_MDI O GPMC0_A18 TRC_DATA5 GPIO0_37 0x0011C098 PADCONFIG38 AH16 PRG2_PRU0_GPO PRG2_PRU0_GPI8 PRG2_RGMII1_TD GPMC0_A17 TRC_DATA6 PRG2_PWM0_B0 GPIO0_38 0x0011C09C PADCONFIG39 AG16 PRG2_PRU0_GPO PRG2_PRU0_GPI9 PRG2_RGMII1_TD GPMC0_A16 TRC_DATA7 GPIO0_39 0x0011C0A0 PADCONFIG40 AF16 PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_RGMII1_TD GPMC0_A15 TRC_DATA8 GPIO0_40 0x0011C0A4 PADCONFIG41 AE16 PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_RGMII1_TD GPMC0_A14 TRC_DATA9 PRG2_ECAP0_IN_ APWM_OUT GPIO0_41 0x0011C0A8 PADCONFIG42 AD16 PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_RGMII1_TX C GPMC0_A13 TRC_DATA10 PRG2_PWM0_A1 GPIO0_42 0x0011C0AC PADCONFIG43 AH15 PRG2_PRU1_GPO PRG2_PRU1_GPI0 PRG2_RGMII2_RD GPMC0_A12 TRC_DATA11 PRG2_PWM3_A2 GPIO0_43 0x0011C0B0 PADCONFIG44 AC16 PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_RGMII2_RD GPMC0_A11 TRC_DATA12 PRG2_PWM3_B2 GPIO0_44 0x0011C0B4 PADCONFIG45 AD17 PRG2_PRU1_GPO PRG2_PRU1_GPI2 PRG2_RGMII2_RD GPMC0_A10 TRC_DATA13 PRG2_PWM0_B1 GPIO0_45 0x0011C0B8 PADCONFIG46 AH14 PRG2_PRU1_GPO PRG2_PRU1_GPI3 PRG2_RGMII2_RD GPMC0_A9 TRC_DATA14 GPIO0_46 0x0011C0BC PADCONFIG47 AG14 PRG2_PRU1_GPO PRG2_PRU1_GPI4 PRG2_RGMII2_RX _CTL GPMC0_A8 TRC_DATA15 PRG2_ECAP0_SY NC_OUT GPIO0_47 0x0011C0C0 PADCONFIG48 AG15 PRG2_PRU1_GPO PRG2_PRU1_GPI5 PRG2_RGMII2_RX C GPMC0_A7 TRC_DATA16 GPIO0_48 0x0011C0C4 PADCONFIG49 AC17 PRG2_PRU1_GPO PRG2_PRU1_GPI6 PRG2_RGMII2_TX _CTL GPMC0_A6 TRC_DATA17 GPIO0_49 0x0011C0C8 PADCONFIG50 AE15 PRG2_PRU1_GPO PRG2_PRU1_GPI7 PRG2_MDIO0_MD C GPMC0_A5 TRC_DATA18 PRG2_PWM3_TZ_I N GPIO0_50 0x0011C0CC PADCONFIG51 AD15 PRG2_PRU1_GPO PRG2_PRU1_GPI8 PRG2_RGMII2_TD GPMC0_A4 TRC_DATA19 PRG2_PWM0_A2 GPIO0_51 0x0011C0D0 PADCONFIG52 AF14 PRG2_PRU1_GPO PRG2_PRU1_GPI9 PRG2_RGMII2_TD GPMC0_A3 TRC_DATA20 PRG2_PWM3_TZ_ OUT GPIO0_52 0x0011C0D4 PADCONFIG53 AC15 PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_RGMII2_TD GPMC0_A2 TRC_DATA21 PRG2_PWM0_B2 GPIO0_53 0x0011C0D8 PADCONFIG54 AD14 PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_RGMII2_TD GPMC0_A1 TRC_DATA22 PRG2_ECAP0_SY NC_IN GPIO0_54 0x0011C0DC PADCONFIG55 AE14 PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_RGMII2_TX C GPMC0_A0 TRC_DATA23 PRG2_PWM1_TZ_ OUT GPIO0_55 0x0011C0E0 PADCONFIG56 AE22 PRG1_PRU0_GPO PRG1_PRU0_GPI0 PRG1_RGMII1_RD PRG1_PWM3_A0 GPIO0_56

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M 101 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Table 4-61. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMBER MUXMODE[7:0] SETTINGS 0 1 2 3 4 5 6 7 Bootstrap 0x0011C0E4 PADCONFIG57 AG24 PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_RD PRG1_PWM3_B0 GPIO0_57 0x0011C0E8 PADCONFIG58 AF23 PRG1_PRU0_GPO PRG1_PRU0_GPI2 PRG1_RGMII1_RD PRG1_PWM2_A0 GPIO0_58 0x0011C0EC PADCONFIG59 AD21 PRG1_PRU0_GPO PRG1_PRU0_GPI3 PRG1_RGMII1_RD PRG1_PWM3_A2 GPIO0_59 0x0011C0F0 PADCONFIG60 AG23 PRG1_PRU0_GPO PRG1_PRU0_GPI4 PRG1_RGMII1_RX _CTL PRG1_PWM2_B0 GPIO0_60 0x0011C0F4 PADCONFIG61 AF27 PRG1_PRU0_GPO PRG1_PRU0_GPI5 PRG1_PWM3_B2 GPIO0_61 0x0011C0F8 PADCONFIG62 AF22 PRG1_PRU0_GPO PRG1_PRU0_GPI6 PRG1_RGMII1_RX C PRG1_PWM3_A1 GPIO0_62 0x0011C0FC PADCONFIG63 AG27 PRG1_PRU0_GPO PRG1_PRU0_GPI7 PRG1_IEP0_EDC_ LATCH_IN1 PRG1_PWM3_B1 GPIO0_63 0x0011C100 PADCONFIG64 AF28 PRG1_PRU0_GPO PRG1_PRU0_GPI8 PRG1_PWM2_A1 GPIO0_64 0x0011C104 PADCONFIG65 AF26 PRG1_PRU0_GPO PRG1_PRU0_GPI9 PRG1_UART0_CT Sn PRG1_PWM3_TZ_I N SPI2_CS1 PRG1_IEP0_EDIO _DATA_IN_OUT28 GPIO0_65 0x0011C108 PADCONFIG66 AH25 PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_UART0_RT Sn PRG1_PWM2_B1 SPI2_CS2 PRG1_IEP0_EDIO _DATA_IN_OUT29 GPIO0_66 0x0011C10C PADCONFIG67 AF21 PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_TX _CTL PRG1_PWM3_TZ_ OUT GPIO0_67 0x0011C110 PADCONFIG68 AH20 PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_TD PRG1_PWM0_A0 GPIO0_68 0x0011C114 PADCONFIG69 AH21 PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_TD PRG1_PWM0_B0 GPIO0_69 0x0011C118 PADCONFIG70 AG20 PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_TD PRG1_PWM0_A1 GPIO0_70 0x0011C11C PADCONFIG71 AD19 PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_TD PRG1_PWM0_B1 GPIO0_71 0x0011C120 PADCONFIG72 AD20 PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_TX C PRG1_PWM0_A2 GPIO0_72 0x0011C124 PADCONFIG73 AH26 PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_IEP0_EDC_ SYNC_OUT1 PRG1_PWM0_B2 GPIO0_73 0x0011C128 PADCONFIG74 AG25 PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_IEP0_EDC_ LATCH_IN0 PRG1_PWM0_TZ_I N GPIO0_74 0x0011C12C PADCONFIG75 AG26 PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_IEP0_EDC_ SYNC_OUT0 PRG1_PWM0_TZ_ OUT GPIO0_75 0x0011C130 PADCONFIG76 AH24 PRG1_PRU1_GPO PRG1_PRU1_GPI0 PRG1_RGMII2_RD GPIO0_76 0x0011C134 PADCONFIG77 AH23 PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_RD GPIO0_77 0x0011C138 PADCONFIG78 AG21 PRG1_PRU1_GPO PRG1_PRU1_GPI2 PRG1_RGMII2_RD PRG1_PWM2_A2 GPIO0_78 0x0011C13C PADCONFIG79 AH22 PRG1_PRU1_GPO PRG1_PRU1_GPI3 PRG1_RGMII2_RD GPIO0_79 0x0011C140 PADCONFIG80 AE21 PRG1_PRU1_GPO PRG1_PRU1_GPI4 PRG1_RGMII2_RX _CTL PRG1_PWM2_B2 GPIO0_80

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M 102 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-61. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMBER MUXMODE[7:0] SETTINGS 0 1 2 3 4 5 6 7 Bootstrap 0x0011C144 PADCONFIG81 AC22 PRG1_PRU1_GPO PRG1_PRU1_GPI5 GPIO0_81 0x0011C148 PADCONFIG82 AG22 PRG1_PRU1_GPO PRG1_PRU1_GPI6 PRG1_RGMII2_RX C GPIO0_82 0x0011C14C PADCONFIG83 AD23 PRG1_PRU1_GPO PRG1_PRU1_GPI7 PRG1_IEP1_EDC_ LATCH_IN1 SPI2_CS0 UART1_TXD GPIO0_83 0x0011C150 PADCONFIG84 AE24 PRG1_PRU1_GPO PRG1_PRU1_GPI8 PRG1_PWM2_TZ_ OUT GPIO0_84 0x0011C154 PADCONFIG85 AF25 PRG1_PRU1_GPO PRG1_PRU1_GPI9 PRG1_UART0_RX D PRG1_IEP0_EDIO _DATA_IN_OUT30 GPIO0_85 0x0011C158 PADCONFIG86 AF24 PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_UART0_TX D PRG1_PWM2_TZ_I N SPI2_CS3 PRG1_IEP0_EDIO _DATA_IN_OUT31 GPIO0_86 0x0011C15C PADCONFIG87 AC20 PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_TX _CTL GPIO0_87 0x0011C160 PADCONFIG88 AE20 PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_TD PRG1_PWM1_A0 GPIO0_88 0x0011C164 PADCONFIG89 AF19 PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_TD PRG1_PWM1_B0 GPIO0_89 0x0011C168 PADCONFIG90 AH19 PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_TD PRG1_PWM1_A1 GPIO0_90 0x0011C16C PADCONFIG91 AG19 PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_TD PRG1_PWM1_B1 GPIO0_91 0x0011C170 PADCONFIG92 AE19 PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_TX C PRG1_PWM1_A2 GPIO0_92 0x0011C174 PADCONFIG93 AE23 PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_IEP1_EDC_ SYNC_OUT1 PRG1_PWM1_B2 SPI2_CLK PRG1_ECAP0_SY NC_OUT UART1_RXD GPIO0_93 0x0011C178 PADCONFIG94 AD22 PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_IEP1_EDC_ LATCH_IN0 PRG1_PWM1_TZ_I N SPI2_D0 PRG1_ECAP0_SY NC_IN UART1_CTSn GPIO0_94 0x0011C17C PADCONFIG95 AC21 PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_IEP1_EDC_ SYNC_OUT0 PRG1_PWM1_TZ_ OUT SPI2_D1 PRG1_ECAP0_IN_ APWM_OUT UART1_RTSn GPIO0_95 0x0011C180 PADCONFIG96 AD18 PRG1_MDIO0_MDI O SPI1_CS2 PRG2_PWM1_A1 GPIO1_0 0x0011C184 PADCONFIG97 AH18 PRG1_MDIO0_MD C SPI1_CS3 PRG2_PWM1_B1 GPIO1_1 0x0011C188 PADCONFIG98 D25 MMC0_DAT7 UART0_DCDn GPIO1_2 0x0011C18C PADCONFIG99 B26 MMC0_DAT6 UART0_DSRn GPIO1_3 0x0011C190 PADCONFIG100 A24 MMC0_DAT5 UART0_DTRn GPIO1_4 0x0011C194 PADCONFIG101 E24 MMC0_DAT4 UART0_RIN GPIO1_5 0x0011C198 PADCONFIG102 A25 MMC0_DAT3 GPIO1_6 0x0011C19C PADCONFIG103 C26 MMC0_DAT2 GPIO1_7 0x0011C1A0 PADCONFIG104 E25 MMC0_DAT1 GPIO1_8 0x0011C1A4 PADCONFIG105 A26 MMC0_DAT0 GPIO1_9 0x0011C1A8 PADCONFIG106 B25 MMC0_CLK GPIO1_10 0x0011C1AC PADCONFIG107 B27 MMC0_CMD GPIO1_11 0x0011C1B0 PADCONFIG108 C25 MMC0_DS GPIO1_12

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M 103 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Table 4-61. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMBER MUXMODE[7:0] SETTINGS 0 1 2 3 4 5 6 7 Bootstrap 0x0011C1B4 PADCONFIG109 A23 MMC0_SDCD PRG2_IEP0_EDIO _OUTVALID GPIO1_13 0x0011C1B8 PADCONFIG110 B23 MMC0_SDWP GPIO1_14 0x0011C1BC PADCONFIG111 AG13 SPI0_CS0 GPIO1_15 0x0011C1C0 PADCONFIG112 AF13 SPI0_CS1 CPTS0_TS_COMP I2C3_SCL PRG1_IEP0_EDIO _OUTVALID GPIO1_16 0x0011C1C4 PADCONFIG113 AH13 SPI0_CLK GPIO1_17 0x0011C1C8 PADCONFIG114 AE13 SPI0_D0 GPIO1_18 0x0011C1CC PADCONFIG115 AD13 SPI0_D1 GPIO1_19 0x0011C1D0 PADCONFIG116 AD12 SPI1_CS0 PRG2_IEP0_EDC_ LATCH_IN0 PRG2_UART0_CT Sn PRG0_IEP0_EDIO _OUTVALID GPIO1_20 0x0011C1D4 PADCONFIG117 AG12 SPI1_CS1 CPTS0_TS_SYNC I2C3_SDA GPIO1_21 0x0011C1D8 PADCONFIG118 AH12 SPI1_CLK PRG2_IEP0_EDC_ SYNC_OUT0 PRG2_UART0_RT Sn GPIO1_22 0x0011C1DC PADCONFIG119 AE12 SPI1_D0 PRG2_IEP0_EDC_ LATCH_IN1 PRG2_UART0_RX D GPIO1_23 0x0011C1E0 PADCONFIG120 AF12 SPI1_D1 PRG2_IEP0_EDC_ SYNC_OUT1 PRG2_UART0_TX D GPIO1_24 0x0011C1E4 PADCONFIG121 AF11 UART0_RXD GPIO1_25 0x0011C1E8 PADCONFIG122 AE11 UART0_TXD GPIO1_26 0x0011C1EC PADCONFIG123 AG11 UART0_CTSn TIMER_IO4 SPI0_CS2 GPIO1_27 0x0011C1F0 PADCONFIG124 AD11 UART0_RTSn TIMER_IO5 SPI0_CS3 GPIO1_28 0x0011C1F4 PADCONFIG125 V24 PRG0_PRU0_GPO PRG0_PRU0_GPI0 PRG0_RGMII1_RD PRG0_PWM3_A0 MCASP0_ACLKX GPIO1_29 0x0011C1F8 PADCONFIG126 W25 PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_RD PRG0_PWM3_B0 MCASP0_AFSX GPIO1_30 0x0011C1FC PADCONFIG127 W24 PRG0_PRU0_GPO PRG0_PRU0_GPI2 PRG0_RGMII1_RD PRG0_PWM2_A0 MCASP0_ACLKR GPIO1_31 0x0011C200 PADCONFIG128 AA27 PRG0_PRU0_GPO PRG0_PRU0_GPI3 PRG0_RGMII1_RD PRG0_PWM3_A2 MCASP0_AFSR GPIO1_32 0x0011C204 PADCONFIG129 Y24 PRG0_PRU0_GPO PRG0_PRU0_GPI4 PRG0_RGMII1_RX _CTL PRG0_PWM2_B0 MCASP0_AXR0 GPIO1_33 0x0011C208 PADCONFIG130 V28 PRG0_PRU0_GPO PRG0_PRU0_GPI5 PRG0_PWM3_B2 MCASP0_AXR1 GPIO1_34 0x0011C20C PADCONFIG131 Y25 PRG0_PRU0_GPO PRG0_PRU0_GPI6 PRG0_RGMII1_RX C PRG0_PWM3_A1 MCASP0_AXR2 GPIO1_35 0x0011C210 PADCONFIG132 U27 PRG0_PRU0_GPO PRG0_PRU0_GPI7 PRG0_IEP0_EDC_ LATCH_IN1 PRG0_PWM3_B1 PRG0_ECAP0_SY NC_IN MCASP0_AXR3 GPIO1_36 0x0011C214 PADCONFIG133 V27 PRG0_PRU0_GPO PRG0_PRU0_GPI8 PRG0_PWM2_A1 MCASP0_AXR4 GPIO1_37 0x0011C218 PADCONFIG134 V26 PRG0_PRU0_GPO PRG0_PRU0_GPI9 PRG0_UART0_CT Sn PRG0_PWM3_TZ_I N SPI3_CS1 MCASP0_AXR5 PRG0_IEP0_EDIO _DATA_IN_OUT28 GPIO1_38 0x0011C21C PADCONFIG135 U25 PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_UART0_RT Sn PRG0_PWM2_B1 SPI3_CS2 MCASP0_AXR6 PRG0_IEP0_EDIO _DATA_IN_OUT29 GPIO1_39

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M 104 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-61. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMBER MUXMODE[7:0] SETTINGS 0 1 2 3 4 5 6 7 Bootstrap 0x0011C220 PADCONFIG136 AB25 PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_TX _CTL PRG0_PWM3_TZ_ OUT MCASP0_AXR7 GPIO1_40 0x0011C224 PADCONFIG137 AD27 PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_TD PRG0_PWM0_A0 MCASP0_AXR8 GPIO1_41 0x0011C228 PADCONFIG138 AC26 PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_TD PRG0_PWM0_B0 MCASP0_AXR9 GPIO1_42 0x0011C22C PADCONFIG139 AD26 PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_TD PRG0_PWM0_A1 MCASP0_AXR10 GPIO1_43 0x0011C230 PADCONFIG140 AA24 PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_TD PRG0_PWM0_B1 MCASP0_AXR11 GPIO1_44 0x0011C234 PADCONFIG141 AD28 PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_TX C PRG0_PWM0_A2 MCASP0_AXR12 MCASP1_AHCLKR GPIO1_45 0x0011C238 PADCONFIG142 U26 PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_IEP0_EDC_ SYNC_OUT1 PRG0_PWM0_B2 PRG0_ECAP0_SY NC_OUT MCASP0_AXR13 MCASP1_AHCLKX GPIO1_46 0x0011C23C PADCONFIG143 V25 PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_IEP0_EDC_ LATCH_IN0 PRG0_PWM0_TZ_I N PRG0_ECAP0_IN_ APWM_OUT MCASP0_AXR14 MCASP2_AHCLKR GPIO1_47 0x0011C240 PADCONFIG144 U24 PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_IEP0_EDC_ SYNC_OUT0 PRG0_PWM0_TZ_ OUT MCASP0_AXR15 MCASP2_AHCLKX GPIO1_48 0x0011C244 PADCONFIG145 AB28 PRG0_PRU1_GPO PRG0_PRU1_GPI0 PRG0_RGMII2_RD MCASP1_ACLKX GPIO1_49 0x0011C248 PADCONFIG146 AC28 PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_RD MCASP1_AFSX GPIO1_50 0x0011C24C PADCONFIG147 AC27 PRG0_PRU1_GPO PRG0_PRU1_GPI2 PRG0_RGMII2_RD PRG0_PWM2_A2 MCASP1_ACLKR GPIO1_51 0x0011C250 PADCONFIG148 AB26 PRG0_PRU1_GPO PRG0_PRU1_GPI3 PRG0_RGMII2_RD MCASP1_AFSR GPIO1_52 0x0011C254 PADCONFIG149 AA25 PRG0_PRU1_GPO PRG0_PRU1_GPI4 PRG0_RGMII2_RX _CTL PRG0_PWM2_B2 MCASP1_AXR0 MCASP0_AHCLKR GPIO1_53 0x0011C258 PADCONFIG150 U23 PRG0_PRU1_GPO PRG0_PRU1_GPI5 MCASP1_AXR1 MCASP0_AHCLKX GPIO1_54 0x0011C25C PADCONFIG151 AB27 PRG0_PRU1_GPO PRG0_PRU1_GPI6 PRG0_RGMII2_RX C MCASP1_AXR2 GPIO1_55 0x0011C260 PADCONFIG152 W28 PRG0_PRU1_GPO PRG0_PRU1_GPI7 PRG0_IEP1_EDC_ LATCH_IN1 SPI3_CS0 MCASP1_AXR3 UART2_TXD GPIO1_56 0x0011C264 PADCONFIG153 W27 PRG0_PRU1_GPO PRG0_PRU1_GPI8 PRG0_PWM2_TZ_ OUT MCASP1_AXR4 GPIO1_57 0x0011C268 PADCONFIG154 Y28 PRG0_PRU1_GPO PRG0_PRU1_GPI9 PRG0_UART0_RX D SPI3_CS3 MCASP1_AXR5 PRG0_IEP0_EDIO _DATA_IN_OUT30 GPIO1_58 0x0011C26C PADCONFIG155 AA28 PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_UART0_TX D PRG0_PWM2_TZ_I N MCASP1_AXR6 PRG0_IEP0_EDIO _DATA_IN_OUT31 GPIO1_59 0x0011C270 PADCONFIG156 AB24 PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_TX _CTL MCASP1_AXR7 GPIO1_60 0x0011C274 PADCONFIG157 AC25 PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_TD PRG0_PWM1_A0 MCASP1_AXR8 GPIO1_61 0x0011C278 PADCONFIG158 AD25 PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_TD PRG0_PWM1_B0 MCASP1_AXR9 GPIO1_62 0x0011C27C PADCONFIG159 AD24 PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_TD PRG0_PWM1_A1 MCASP2_AFSR GPIO1_63

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M 105 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Table 4-61. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMBER MUXMODE[7:0] SETTINGS 0 1 2 3 4 5 6 7 Bootstrap 0x0011C280 PADCONFIG160 AE27 PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_TD PRG0_PWM1_B1 MCASP2_ACLKR GPIO1_64 0x0011C284 PADCONFIG161 AC24 PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_TX C PRG0_PWM1_A2 MCASP2_AXR0 GPIO1_65 0x0011C288 PADCONFIG162 Y27 PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_IEP1_EDC_ SYNC_OUT1 PRG0_PWM1_B2 SPI3_CLK MCASP2_AXR1 UART2_RXD GPIO1_66 0x0011C28C PADCONFIG163 Y26 PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_IEP1_EDC_ LATCH_IN0 PRG0_PWM1_TZ_I N SPI3_D0 MCASP2_AFSX UART2_CTSn GPIO1_67 0x0011C290 PADCONFIG164 W26 PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_IEP1_EDC_ SYNC_OUT0 PRG0_PWM1_TZ_ OUT SPI3_D1 MCASP2_ACLKX UART2_RTSn GPIO1_68 0x0011C294 PADCONFIG165 AE26 PRG0_MDIO0_MDI O PRG2_PWM1_A2 MCASP2_AXR2 GPIO1_69 0x0011C298 PADCONFIG166 AE28 PRG0_MDIO0_MD C PRG2_PWM1_B2 MCASP2_AXR3 GPIO1_70 0x0011C29C PADCONFIG167 F18 NMIn PRG2_PWM1_TZ_I N 0x0011C2A0 PADCONFIG168 F17 RESETz 0x0011C2A4 PADCONFIG169 D19 RESETSTATz 0x0011C2A8 PADCONFIG170 C19 PORz_OUT 0x0011C2AC PADCONFIG171 E20 SOC_SAFETY_ER RORn 0x0011C2B0 PADCONFIG172 C20 TDI 0x0011C2B4 PADCONFIG173 A20 TDO 0x0011C2B8 PADCONFIG174 A21 TMS 0x0011C2BC PADCONFIG175 AD9 USB0_DRVVBUS GPIO1_71 0x0011C2C0 PADCONFIG176 AC8 USB1_DRVVBUS GPIO1_72 0x0011C2C4 PADCONFIG177 D27 MMC1_DAT3 GPIO1_73 0x0011C2C8 PADCONFIG178 D26 MMC1_DAT2 GPIO1_74 0x0011C2CC PADCONFIG179 E27 MMC1_DAT1 GPIO1_75 0x0011C2D0 PADCONFIG180 D28 MMC1_DAT0 GPIO1_76 0x0011C2D4 PADCONFIG181 C27 MMC1_CLK GPIO1_77 0x0011C2D8 PADCONFIG182 C28 MMC1_CMD GPIO1_78 0x0011C2DC PADCONFIG183 B24 MMC1_SDCD GPIO1_79 0x0011C2E0 PADCONFIG184 C24 MMC1_SDWP GPIO1_80 0x0011C2E8 PADCONFIG186 D20 I2C0_SCL 0x0011C2EC PADCONFIG187 C21 I2C0_SDA 0x0011C2F0 PADCONFIG188 B21 I2C1_SCL CPTS0_HW1TSPU SH 0x0011C2F4 PADCONFIG189 E21 I2C1_SDA CPTS0_HW2TSPU SH 0x0011C2F8 PADCONFIG190 D21 SYNC0_OUT CPTS0_RFT_CLK GPIO1_86 0x0011C2FC PADCONFIG191 A22 EXT_REFCLK1 SYNC1_OUT GPIO1_87 0x0011C300 PADCONFIG192 B22 TIMER_IO0 SYSCLKOUT0 GPIO1_88

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M 106 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-61. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMBER MUXMODE[7:0] SETTINGS 0 1 2 3 4 5 6 7 Bootstrap 0x0011C304 PADCONFIG193 C23 TIMER_IO1 OBSCLK0 GPIO1_89 0x0011C308 PADCONFIG194 E19 PORz 0x4301C000 WKUP_PADCONFIG0 V1 MCU_OSPI0_CLK MCU_HYPERBUS0 _CK WKUP_GPIO0_12 0x4301C004 WKUP_PADCONFIG1 U1 MCU_OSPI0_LBCL KO MCU_HYPERBUS0 _CKn WKUP_GPIO0_13 0x4301C008 WKUP_PADCONFIG2 U2 MCU_OSPI0_DQS MCU_HYPERBUS0 _RWDS WKUP_GPIO0_14 0x4301C00C WKUP_PADCONFIG3 U4 MCU_OSPI0_D0 MCU_HYPERBUS0 _DQ0 WKUP_GPIO0_15 0x4301C010 WKUP_PADCONFIG4 U5 MCU_OSPI0_D1 MCU_HYPERBUS0 _DQ1 WKUP_GPIO0_16 0x4301C014 WKUP_PADCONFIG5 T2 MCU_OSPI0_D2 MCU_HYPERBUS0 _DQ2 WKUP_GPIO0_17 0x4301C018 WKUP_PADCONFIG6 T3 MCU_OSPI0_D3 MCU_HYPERBUS0 _DQ3 WKUP_GPIO0_18 0x4301C01C WKUP_PADCONFIG7 T4 MCU_OSPI0_D4 MCU_HYPERBUS0 _DQ4 WKUP_GPIO0_19 0x4301C020 WKUP_PADCONFIG8 T5 MCU_OSPI0_D5 MCU_HYPERBUS0 _DQ5 WKUP_GPIO0_20 0x4301C024 WKUP_PADCONFIG9 R2 MCU_OSPI0_D6 MCU_HYPERBUS0 _DQ6 WKUP_GPIO0_21 0x4301C028 WKUP_PADCONFIG10 R3 MCU_OSPI0_D7 MCU_HYPERBUS0 _DQ7 WKUP_GPIO0_22 0x4301C02C WKUP_PADCONFIG11 R4 MCU_OSPI0_CSn0 MCU_HYPERBUS0 _CSn0 WKUP_GPIO0_23 0x4301C030 WKUP_PADCONFIG12 R5 MCU_OSPI0_CSn1 MCU_HYPERBUS0 _RESETn WKUP_GPIO0_24 0x4301C034 WKUP_PADCONFIG13 T1 MCU_OSPI1_CLK WKUP_GPIO0_25 0x4301C038 WKUP_PADCONFIG14 R1 MCU_OSPI1_LBCL KO MCU_OSPI0_CSn2 MCU_HYPERBUS0 _RESETOn WKUP_GPIO0_26 0x4301C03C WKUP_PADCONFIG15 P2 MCU_OSPI1_DQS MCU_OSPI0_CSn3 MCU_HYPERBUS0 _INTn WKUP_GPIO0_27 0x4301C040 WKUP_PADCONFIG16 P3 MCU_OSPI1_D0 WKUP_GPIO0_28 0x4301C044 WKUP_PADCONFIG17 P4 MCU_OSPI1_D1 MCU_UART0_RXD MCU_SPI1_CS1 WKUP_GPIO0_29 0x4301C048 WKUP_PADCONFIG18 P5 MCU_OSPI1_D2 MCU_UART0_TXD MCU_SPI1_CS2 WKUP_GPIO0_30 0x4301C04C WKUP_PADCONFIG19 P1 MCU_OSPI1_D3 MCU_UART0_CTS n MCU_SPI0_CS1 WKUP_GPIO0_31 0x4301C050 WKUP_PADCONFIG20 N2 MCU_OSPI1_CSn0 WKUP_GPIO0_32 0x4301C054 WKUP_PADCONFIG21 N3 MCU_OSPI1_CSn1 MCU_HYPERBUS0 _WPn MCU_TIMER_IO0 MCU_HYPERBUS0 _CSn1 MCU_UART0_RTS n MCU_SPI0_CS2 WKUP_GPIO0_33 0x4301C058 WKUP_PADCONFIG22 N4 MCU_RGMII1_TX_ CTL MCU_RMII1_CRS_ DV WKUP_GPIO0_34 0x4301C05C WKUP_PADCONFIG23 N5 MCU_RGMII1_RX_ CTL MCU_RMII1_RX_E R WKUP_GPIO0_35 0x4301C060 WKUP_PADCONFIG24 M2 MCU_RGMII1_TD3 WKUP_GPIO0_36

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M 107 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Table 4-61. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMBER MUXMODE[7:0] SETTINGS 0 1 2 3 4 5 6 7 Bootstrap 0x4301C064 WKUP_PADCONFIG25 M3 MCU_RGMII1_TD2 WKUP_GPIO0_37 0x4301C068 WKUP_PADCONFIG26 M4 MCU_RGMII1_TD1 MCU_RMII1_TXD1 WKUP_GPIO0_38 0x4301C06C WKUP_PADCONFIG27 M5 MCU_RGMII1_TD0 MCU_RMII1_TXD0 WKUP_GPIO0_39 0x4301C070 WKUP_PADCONFIG28 N1 MCU_RGMII1_TXC MCU_RMII1_TX_E N WKUP_GPIO0_40 0x4301C074 WKUP_PADCONFIG29 M1 MCU_RGMII1_RXC MCU_RMII1_REF_ CLK WKUP_GPIO0_41 0x4301C078 WKUP_PADCONFIG30 L2 MCU_RGMII1_RD3 WKUP_GPIO0_42 0x4301C07C WKUP_PADCONFIG31 L5 MCU_RGMII1_RD2 WKUP_GPIO0_43 0x4301C080 WKUP_PADCONFIG32 M6 MCU_RGMII1_RD1 MCU_RMII1_RXD1 WKUP_GPIO0_44 0x4301C084 WKUP_PADCONFIG33 L6 MCU_RGMII1_RD0 MCU_RMII1_RXD0 WKUP_GPIO0_45 0x4301C088 WKUP_PADCONFIG34 L4 MCU_MDIO0_MDI O WKUP_GPIO0_46 0x4301C08C WKUP_PADCONFIG35 L1 MCU_MDIO0_MDC WKUP_GPIO0_47 0x4301C090 WKUP_PADCONFIG36 Y1 MCU_SPI0_CLK WKUP_GPIO0_48 MCU_BOOTMODE 0x4301C094 WKUP_PADCONFIG37 Y3 MCU_SPI0_D0 WKUP_GPIO0_49 MCU_BOOTMODE 0x4301C098 WKUP_PADCONFIG38 Y2 MCU_SPI0_D1 WKUP_GPIO0_50 MCU_BOOTMODE 0x4301C09C WKUP_PADCONFIG39 Y4 MCU_SPI0_CS0 WKUP_GPIO0_51 0x4301C0A0 WKUP_PADCONFIG40 AB1 WKUP_UART0_RX D WKUP_GPIO0_52 0x4301C0A4 WKUP_PADCONFIG41 AB5 WKUP_UART0_TX D WKUP_GPIO0_53 0x4301C0A8 WKUP_PADCONFIG42 W1 MCU_MCAN0_TX WKUP_GPIO0_54 0x4301C0AC WKUP_PADCONFIG43 W2 MCU_MCAN0_RX WKUP_GPIO0_55 0x4301C0B0 WKUP_PADCONFIG44 AF4 WKUP_GPIO0_0 MCU_SPI1_CLK WKUP_GPIO0_0 MCU_BOOTMODE 0x4301C0B4 WKUP_PADCONFIG45 AF3 WKUP_GPIO0_1 MCU_SPI1_D0 WKUP_GPIO0_1 MCU_BOOTMODE 0x4301C0B8 WKUP_PADCONFIG46 AE3 WKUP_GPIO0_2 MCU_SPI1_D1 WKUP_GPIO0_2 MCU_BOOTMODE 0x4301C0BC WKUP_PADCONFIG47 AD1 WKUP_GPIO0_3 MCU_SPI1_CS0 WKUP_GPIO0_3 MCU_BOOTMODE 0x4301C0C0 WKUP_PADCONFIG48 AC3 WKUP_GPIO0_4 MCU_MCAN1_TX MCU_SPI0_CS3 MCU_ADC_EXT_T RIGGER0 WKUP_GPIO0_4 MCU_BOOTMODE 0x4301C0C4 WKUP_PADCONFIG49 AD3 WKUP_GPIO0_5 MCU_MCAN1_RX MCU_SPI1_CS3 MCU_ADC_EXT_T RIGGER1 WKUP_GPIO0_5 0x4301C0C8 WKUP_PADCONFIG50 AC2 WKUP_GPIO0_6 WKUP_UART0_CT Sn MCU_CPTS0_HW1 TSPUSH WKUP_GPIO0_6 0x4301C0CC WKUP_PADCONFIG51 AC1 WKUP_GPIO0_7 WKUP_UART0_RT Sn MCU_CPTS0_HW2 TSPUSH WKUP_GPIO0_7 0x4301C0D0 WKUP_PADCONFIG52 AC5 WKUP_GPIO0_8 MCU_CPTS0_TS_ SYNC WKUP_GPIO0_8 MCU_BOOTMODE

ADVANCE□INFORMATION Copyright © 2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: DRA80M 108 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Table 4-61. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMBER MUXMODE[7:0] SETTINGS 0 1 2 3 4 5 6 7 Bootstrap 0x4301C0D4 WKUP_PADCONFIG53 AB4 WKUP_GPIO0_9 MCU_CPTS0_TS_ COMP WKUP_GPIO0_9 MCU_BOOTMODE 0x4301C0D8 WKUP_PADCONFIG54 AB3 WKUP_GPIO0_10 MCU_EXT_REFCL MCU_CPTS0_RFT _CLK MCU_SYSCLKOUT WKUP_GPIO0_10 0x4301C0DC WKUP_PADCONFIG55 AB2 WKUP_GPIO0_11 MCU_OBSCLK0 MCU_TIMER_IO1 MCU_CLKOUT0 WKUP_GPIO0_11 0x4301C0E0 WKUP_PADCONFIG56 AC7 WKUP_I2C0_SCL 0x4301C0E4 WKUP_PADCONFIG57 AD6 WKUP_I2C0_SDA 0x4301C0E8 WKUP_PADCONFIG58 AD8 MCU_I2C0_SCL 0x4301C0EC WKUP_PADCONFIG59 AD7 MCU_I2C0_SDA 0x4301C0F0 WKUP_PADCONFIG60 AA5 PMIC_POWER_EN 0x4301C0F4 WKUP_PADCONFIG61 W3 MCU_SAFETY_ER RORn 0x4301C0F8 WKUP_PADCONFIG62 W4 MCU_RESETz 0x4301C0FC WKUP_PADCONFIG63 V3 MCU_RESETSTAT z 0x4301C100 WKUP_PADCONFIG64 V2 MCU_PORz_OUT 0x4301C104 WKUP_PADCONFIG65 AA4 TCK 0x4301C108 WKUP_PADCONFIG66 AA3 TRSTn 0x4301C10C WKUP_PADCONFIG67 AA2 EMU0 0x4301C110 WKUP_PADCONFIG68 AA1 EMU1 0x4301C114 WKUP_PADCONFIG69 Y5 PMIC_POWER_EN

ADVANCE□INFORMATION 109 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Terminal Configuration and FunctionsCopyright © 2018, Texas Instruments Incorporated

4.5 Connections for Unused Pins

This section describes the Unused/Reserved balls connection requirements. NOTE All power balls must be supplied with the voltages specified in Section 5.4, Recommended Operating Conditions, unless otherwise specified in Section 4.3, Signal Descriptions. Table 4-62. Unused Balls Specific Connection Requirements Balls Connection Requirements AD5, C22, AE4, AA3 K2, K3, V5, H2, H3, K5, J3, J1, J5, K4, J4, J2, J6, F4, G6, G4, H5, F5, G5, G3, H4 Each of these balls must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level if unused F17, W4, W5, E19, AA4, A21, AC7, AD6, AD7, AD8, F18, C20, A20, AA1, AA2 Each of these balls must be connected to the corresponding power supply through a separate external pull resistor to ensure these balls are held to a valid logic high level if unused(1) F21, T6, F23, D24 This ball must be left unconnected if unused (1) To determine which power supply is associated with any IO refer to Table 4-1, Pin Attributes. NOTE The following balls are reserved: AC23 (RSV4), B1 (RSV3), AA6 (RSV2), C12 (RSV5), F9 (RSV6), F10 (RSV7), AD10 (RSV8), AC13 (RSV9), B28 (RSV10), A27 (RSV11), D23 (RSV12), E23 (RSV13). These balls must be left unconnected. NOTE The following balls are reserved: V4 (RSV1) These balls must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level. NOTE All other unused signal balls with a Pad Configuration Register can be left unconnected with their multiplexing mode set to GPIO input and internal pulldown resistor enabled. Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case where internal pull resistors are allowed as the only source/sink to hold a valid logic level. Any balls connected to a via, test point, or PCB trace are considered used and must not depend on the internal pull resistor to hold a valid logic level. Internal pull resistors are weak and may not source enough current to maintain a valid logic level for some operating conditions. This may be the case when connected to components with leakage to the opposite logic level, or when external noise sources couple to signal traces attached to balls which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be required to hold a valid logic level on balls with external connections. If balls are allowed to float between valid logic levels, the input buffer may enter a high- current state which could damage the IO cell.

ADVANCE□INFORMATION 110 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3) PARAMETERS MIN MAX UNIT VDD_CORE Supply voltage range for CORE domain TBD TBD V VDD_MCU Supply voltage range for R5F MCU domain TBD TBD V VDD_MPU0 Supply voltage range for A53 MPU0 domain TBD TBD V VDD_MPU1 Supply voltage range for A53 MPU1 domain TBD TBD V VDD_WKUP0 Supply voltage range for WKUP domain TBD TBD V VDD_WKUP1 Supply voltage range for WKUP domain TBD TBD V VDD_DLL_MMC0 Supply voltage range for MMC0 DLL TBD TBD V VDD_DLL_MMC1 Supply voltage range for MMC1 DLL TBD TBD V VDDA_1P8_CSI0 Supply voltage range for CSI PHY, Analog, 1.8 V TBD TBD V VDDA_1P8_OLDI0 Supply voltage range for OLDI, Analog, 1.8 V TBD TBD V VDDA_1P8_SDIO Supply voltage range for SDIO LDO, Analog, 1.8 V TBD TBD V VDDA_1P8_SERDES0 Supply voltage range for USB, PCIE, Analog, 1.8 V TBD TBD V VDDA_3P3_IOLDO_WKUP Supply voltage range for WKUP IO Bias LDO, Analog, 3.3 V TBD TBD V VDDA_3P3_IOLDO0 Supply voltage range for IO Bias LDO, Analog 3.3 V TBD TBD V VDDA_3P3_IOLDO1 Supply voltage range for IO Bias LDO, Analog 3.3 V TBD TBD V VDDA_3P3_SDIO Supply voltage range for SDIO LDO, Analog, 3.3 V TBD TBD V VDDA_3P3_USB Supply voltage range for USBPHY, Analog, 3.3 V TBD TBD V VDDA_ADC_MCU Supply voltage range for ADC0, ADC1, Analog TBD TBD V VDDA_PLL0_DDR Supply voltage range for DDR DPLL, Analog TBD TBD V VDDA_PLL1_DDR Supply voltage range for DDR De-skew DPLL, Analog TBD TBD V VDDA_LDO_WKUP Supply voltage range for WKUP LDO, Analog TBD TBD V VDDA_MCU Supply voltage range for MCU SRAM LDO, MCU DPLL, CPSW DPLL, Analog TBD TBD V VDDA_PLL_CORE Supply voltage range for CORE DPLL, PER1 DPLL, Analog TBD TBD V VDDA_PLL_DSS Supply voltage range for DSS DPLL, Analog TBD TBD V VDDA_PLL_MPU0 Supply voltage range for MPU0 DPLL, Analog TBD TBD V VDDA_PLL_MPU1 Supply voltage range for MPU1 DPLL, Analog TBD TBD V VDDA_PLL_PER0 Supply voltage range for PER0 DPLL, Analog TBD TBD V VDDA_POR_WKUP Supply voltage range for WKUP POR, Analog TBD TBD V VDDA_SRAM_CORE0 Supply voltage range for CORE SRAM LDOs, Analog TBD TBD V VDDA_SRAM_CORE1 Supply voltage range for CORE SRAM LDOs, Analog TBD TBD V VDDA_SRAM_MPU0 Supply voltage range for MPU SRAM LDOs, Analog TBD TBD V VDDA_SRAM_MPU1 Supply voltage range for MPU SRAM LDOs, Analog TBD TBD V VDDA_WKUP Supply voltage range for WKUP OSC, SRAM LDO, Analog TBD TBD V VDDS_DDR Supply voltage range for DDR IO domain TBD TBD V VDDS_OSC1 Supply voltage range for CORE HFOSC, Analog TBD TBD V VDDS0 Supply voltage range for dual-voltage IO domain TBD TBD V VDDS0_WKUP Supply voltage range for dual-voltage IO domain TBD TBD V VDDS1 Supply voltage range for dual-voltage IO domain TBD TBD V VDDS1_WKUP Supply voltage range for dual-voltage IO domain TBD TBD V VDDS2 Supply voltage range for dual-voltage IO domain TBD TBD V VDDS2_WKUP Supply voltage range for dual-voltage IO domain TBD TBD V VDDS3 Supply voltage range for dual-voltage IO domain TBD TBD V VDDS4 Supply voltage range for dual-voltage IO domain TBD TBD V

ADVANCE□INFORMATION 111 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Absolute Maximum Ratings (continued) over operating free-air temperature range (unless otherwise noted)(1)(2)(3) PARAMETERS MIN MAX UNIT VDDS5 Supply voltage range for dual-voltage IO domain TBD TBD V VDDS6 Supply voltage range for dual-voltage IO domain TBD TBD V VDDS7 Supply voltage range for dual-voltage IO domain TBD TBD V VDDS8 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV0 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV0_WKUP Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV1 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV1_WKUP Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV2 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV2_WKUP Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV3 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV4 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV5 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV6 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV7 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV8 Supply voltage range for dual-voltage IO domain TBD TBD V VPP_CORE Supply voltage range for CORE EFUSE domain TBD TBD V VPP_MCU Supply voltage range for MCU EFUSE domain TBD TBD V USB0_VBUS Voltage range for USB VBUS comparator input TBD TBD V USB1_VBUS Voltage range for USB VBUS comparator input TBD TBD V Steady State Max. Voltage at all IO pins (4) TBD V Transient Overshoot and Undershoot specification at IO terminal (5) TBD V Latch-up Performance (6) Class II (105°C) Latch-up I-test performance current-pulse injection on each IO pin TBD TBD mA Latch-up overvoltage performance voltage injection on each IO pin TBD TBD mA TSTG Storage temperature after soldered onto PC board TBD TBD °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.4, Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted. (3) To determine which power supply is associated with any IO refer to Table 4-1, Pin Attributes. (4) This parameter applies to all IO terminals which are not fail-safe and the requirement applies to all values of IO supply voltage. For example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be –TBD to +IO supply + TBD volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences. (5) Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8 V LVCMOS signals is VDDS18V6/9 + (0.20 × VDDS18V6/9) and maximum undershoot value would be VSS - (0.20 × VDDS18V6/9). (6) For current pulse injection: Pins stressed per JEDEC JESD78D (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage. For overvoltage performance: Supplies stressed per JEDEC JESD78D (Class II) and passed specified voltage injection. Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO power supplies are turned off. The I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, DDR_FS_RESETn, and NMIn are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Section 5.1, Absolute Maximum Ratings.

ADVANCE□INFORMATION Tovershoot Tundershoot Tperiod Overshoot = 20% of nominal IO supply voltage Undershoot = 20% of nominal IO supply voltage 112 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-1. Tovershoot + Tundershoot < 20% of Tperiod

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) TBD VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) TBD (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Power-On-Hour (POH) Limits(1)(2)(3)

TEMP (Tj) LIFETIME (POH) JUNCTION TEMP (Tj) LIFETIME (POH) JUNCTION TEMP (Tj) LIFETIME (POH) OPP_NOM 0°C to 90°C 100k -40°C to 105°C 100k Automotive Profile(4) TBD OPP_OD 100k 100k TBD OPP_TURBO TBD TBD TBD (1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products. (2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted temperatures. (3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH. (4) Automotive profile is defined as 20000 power on hours with a junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C, and 10%@125°C.

ADVANCE□INFORMATION 113 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated

5.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) SUPPLY NAME DESCRIPTION MIN(1) NOM MAX(1) UNIT VDD_CORE(3) CORE voltage domain supply 0.95 1 1.05 V VDD_MCU(3) MCU voltage domain supply 0.95 1 1.05 V VDD_MPU0(3) MPU0 voltage domain supply OPP_NOM 0.95 1 1.05 V OPP_OD 1.05 1.1 1.15 V OPP_TURBO 1.16 1.22 1.28 V VDD_MPU1(3) MPU1 voltage domain supply OPP_NOM 0.95 1 1.05 V OPP_OD 1.05 1.1 1.15 V OPP_TURBO 1.16 1.22 1.28 V VDD_WKUP0 WKUP voltage domain supply 0.95 1 1.05 V VDD_WKUP1 WKUP voltage domain supply 0.95 1 1.05 V VDD_DLL_MMC0 MMC0 PHY DLL voltage supply 0.95 1 1.05 V VDD_DLL_MMC1 MMC1 PHY DLL voltage supply 0.95 1 1.05 V VDDA_1P8_CSI0 CSI PHY analog power supply 1.71 1.8 1.89 V VDDA_1P8_SDIO SDIO LDO analog power supply 1.71 1.8 1.89 V VDDA_1P8_OLDI0 OLDI analog power supply 1.71 1.8 1.89 V VDDA_1P8_SERDES0 SERDES0/1 (USB, PCIE, SGMII) analog power supply 1.71 1.8 1.89 V VDDA_3P3_IOLDO_WKUP WKUP IO Bias LDO analog power supply 3.14 3.3 3.46 V VDDA_3P3_IOLDO0 IO Bias LDO analog power supply 3.14 3.3 3.46 V VDDA_3P3_IOLDO1 IO Bias LDO analog power supply 3.14 3.3 3.46 V VDDA_3P3_SDIO SDIO LDO analog power supply 3.14 3.3 3.46 V VDDA_3P3_USB USB analog power supply 3.14 3.3 3.46 V VDDA_1P8_MON_WKUP 1.8V supply monitor in WKUP domain 1.71 1.8 1.89 V VDDA_1P8_MON0 1.8V supply monitor in MAIN domain 1.71 1.8 1.89 V VDDA_3P3_MON_WKUP 3.3V supply monitor in WKUP domain 3.14 3.3 3.46 V VDDA_3P3_MON0 3.3V supply monitor in MAIN domain 3.14 3.3 3.46 V VDDA_VSYS_MON Supply monitor for system TBD TBD TBD V VDDA_ADC_MCU ADC0, ADC1 analog power supply 1.71 1.8 1.89 V VDDA_LDO_WKUP WKUP LDO analog power supply 1.71 1.8 1.89 V VDDA_MCU MCU SRAM LDO, MCU DPLL, CPSW DPLL analog power supply 1.71 1.8 1.89 V VDDA_PLL_CORE CORE DPLL, PER1 DPLL analog power supply 1.71 1.8 1.89 V VDDA_PLL0_DDR DDR DPLL analog power supply 1.71 1.8 1.89 V VDDA_PLL1_DDR DDR De-skew DPLL analog power supply 1.71 1.8 1.89 V VDDA_PLL_DSS DSS DPLL analog power supply 1.71 1.8 1.89 V VDDA_PLL_MPU0 MPU0 DPLL analog power supply 1.71 1.8 1.89 V VDDA_PLL_MPU1 MPU1 DPLL analog power supply 1.71 1.8 1.89 V VDDA_PLL_PER0 PER0 DPLL analog power supply 1.71 1.8 1.89 V VDDA_POR_WKUP WKUP POR/POK analog power supply 1.71 1.8 1.89 V VDDA_SRAM_CORE0 CORE SRAM LDOs analog power supply 1.71 1.8 1.89 V VDDA_SRAM_CORE1 CORE SRAM LDOs analog power supply 1.71 1.8 1.89 V VDDA_SRAM_MPU0 MPU SRAM LDOs analog power supply 1.71 1.8 1.89 V VDDA_SRAM_MPU1 MPU SRAM LDOs analog power supply 1.71 1.8 1.89 V VDDA_WKUP WKUP High/Low Frequency Oscillator (WKUP_LFOSC0 / WKUP_OSC0), SRAM LDO analog power supply 1.71 1.8 1.89 V VDDS_DDR(4) DDR IO domain power supply (DDR3L) 1.28 1.35 1.42 V DDR IO domain power supply (DDR4) 1.14 1.2 1.26 V DDR IO domain power supply (LPDDR4) 1.05 1.1 1.15 V

ADVANCE□INFORMATION 114 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) SUPPLY NAME DESCRIPTION MIN(1) NOM MAX(1) UNIT VDDS_OSC1 MAIN High Frequency Oscillator (OSC1) analog power supply 1.71 1.8 1.89 V VDDS0 IO bias supply for VDDSHV0 1.71 1.8 1.89 V VDDS0_WKUP IO bias supply for VDDSHV0_WKUP 1.71 1.8 1.89 V VDDS1 IO bias supply for VDDSHV1 1.71 1.8 1.89 V VDDS1_WKUP IO bias supply for VDDSHV1_WKUP 1.71 1.8 1.89 V VDDS2 IO bias supply for VDDSHV2 1.71 1.8 1.89 V VDDS2_WKUP IO bias supply for VDDSHV2_WKUP 1.71 1.8 1.89 V VDDS3 IO bias supply for VDDSHV3 1.71 1.8 1.89 V VDDS4 IO bias supply for VDDSHV4 1.71 1.8 1.89 V VDDS5 IO bias supply for VDDSHV5 1.71 1.8 1.89 V VDDS6 IO bias supply for VDDSHV6 1.71 1.8 1.89 V VDDS7 IO bias supply for VDDSHV7 1.71 1.8 1.89 V VDDS8 IO bias supply for VDDSHV8 1.71 1.8 1.89 V VDDSHV0 Dual-voltage IO domain power supply 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV0_WKUP Dual-voltage IO domain power supply 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV1 Dual-voltage IO domain power supply 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV1_WKUP Dual-voltage IO domain power supply 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV2 Dual-voltage IO domain power supply 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV2_WKUP Dual-voltage IO domain power supply 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV3 Dual-voltage IO domain power supply 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV4 Dual-voltage IO domain power supply 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV5 Dual-voltage IO domain power supply 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV6 Dual-voltage IO domain power supply 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV7 Dual-voltage IO domain power supply 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV8 Dual-voltage IO domain power supply 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V USB0_VBUS Voltage range for USB VBUS comparator input 0 TBD TBD V USB1_VBUS Voltage range for USB VBUS comparator input 0 TBD TBD V USB0_ID Voltage range for the USB ID input (5) V USB1_ID Voltage range for the USB ID input (5) V VSS Ground 0 V TJ Operating junction temperature range Automotive -40 125 °C Extended -40 105 °C Commercial 0 90 °C (1) The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement

ADVANCE□INFORMATION 115 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth. (2) Refer to Section 5.3, Power-On-Hour (POH) Limits for limitations. (3) This value is without AVS. The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the STD_FUSE_OPP. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the Device TRM. The power supply should be adjustable over the following ranges for each required OPP: – OPP_NOM: TBD – OPP_OD: TBD – OPP_TURBO: TBD The AVS Voltages will be within the above specified ranges. (4) VDDS_DDR is required to still be powered with either DDR3L, DDR4, or LPDDR4 voltage ranges, even If DDR interface is unused. (5) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the voltage to determine if the terminal is connected to VSS with a resistance less than 10 Ω or greater than 100 kΩ. The terminal should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any external voltage source.

5.5 Operating Performance Points

This section describes the operating conditions of the device. This section also contains the description of each operating performance point for processor clocks and device core clocks. CAUTION The OPP voltage and frequency values may change following the silicon characterization result. Table 5-1 describes the maximum supported frequency per speed grade for the device. Table 5-1. Speed Grade Maximum Frequency Device Speed Maximum frequency (MHz) MPU MCU DMSC GPU CBASS0 DDR3L/DDR4 LPDDR4 DRA80xM X 1100 400 200 N/A 250 800 (DDR-1600) 667 (DDR-1333) (1) N/A in this table stands for Not Applicable.

5.5.1 Core Clock Specifications

Table 5-2 describes the standard processor clocks speed characteristics vs OPP of the device. Table 5-2. Supported OPP vs Max Frequency (2) DESCRIPTION OPP_NOM OPP_OD OPP_TURBO Max Freq. (MHz) Max Freq. (MHz) Max Freq. (MHz) VD_CORE DDR3L/DDR4 800 (DDR-1600) N/A N/A LPDDR4 667 (DDR-1333) N/A N/A CBASS0 250 N/A N/A VD_MPU0 MPU0 800 1000 1100 VD_MPU1 MPU1 800 1000 1100 VD_MCU MCU 400 N/A N/A

ADVANCE□INFORMATION 116 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-2. Supported OPP vs Max Frequency (2) (continued) DESCRIPTION OPP_NOM OPP_OD OPP_TURBO Max Freq. (MHz) Max Freq. (MHz) Max Freq. (MHz) VD_WKUP DMSC 200 N/A N/A (1) N/A in this table stands for Not Applicable. (2) Maximum supported frequency is limited according to the Device Speed Grade (see Table 5-1).

5.6 Power Consumption Summary

For information on the device power consumption, see the Power Estimation SpreadSheet provided in DRA80x Power Consumption Model.

5.7 Electrical Characteristics

The interfaces or signals described in Table 5-3 through Table 5-8 correspond to the interfaces or signals available in multiplexing mode 0 (Primary Function). All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC electrical characteristics are specified for the different multiplexing modes (Functions). Table 5-3. I2C OPEN DRAIN DC Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT BALL NAMES in Mode 0: WKUP_I2C0_SCL / WKUP_I2C0_SDA / MCU_I2C0_SCL / MCU_I2C0_SDA BALL NUMBERS: AC7 / AD6 / AD7 / AD8 I2C STANDARD MODE / FAST MODE - VDDSHV0_WKUP = 1.8 V VIH High-level input threshold 0.7 × VDDSHV0_WKUP V VIL Low-level input threshold 0.3 × VDDSHV0_WKUP V VHYS Hysteresis 0.1 × VDDSHV0_WKUP V IIN Input leakage current. This value represents the maximum current flowing in or out of the pin while the output driver is disabled and the input is swept from VSS to VDD. 12 µA IOZ Total leakage current through the driver/receiver combination, which may include an internal pull-up or pull-down. This value represents the maximum current flowing in or out of the pin while the output driver is disabled, the pull-up or pull-down is inhibited, and the input is swept from VSS to VDD. 12 µA VOL Low-level output voltage at 3-mA sink current 0.2 × VDDSHV0_WKUP V I2C STANDARD MODE / FAST MODE - VDDSHV0_WKUP = 3.3 V VIH High-level input voltage 0.7 × VDDSHV0_WKUP V VIL Low-level input voltage 0.3 × VDDSHV0_WKUP V VHYS Hysteresis 0.05 × VDDSHV0_WKUP V

ADVANCE□INFORMATION 117 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-3. I2C OPEN DRAIN DC Electrical Characteristics (continued) over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT IIN Input leakage current. This value represents the maximum current flowing in or out of the pin while the output driver is disabled and the input is swept from VSS to VDD. 80 µA IOZ Total leakage current through the driver/receiver combination, which may include an internal pull-up or pull-down. This value represents the maximum current flowing in or out of the pin while the output driver is disabled, the pull-up or pull-down is inhibited, and the input is swept from VSS to VDD. 80 µA VOL Low-level output voltage at 3-mA sink current 0.4 V (1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [9] column. Table 5-4. Analog OSC Buffers DC Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT 1.8-V MODE High Frequency Oscillator BALL NAMES in Mode 0: WKUP_OSC0_XI / WKUP_OSC0_XO / OSC1_XI / OSC1_XO BALL NUMBERS: C22 / E22 / AD5 / AE6 VIH Input high-level threshold 0.65 × VDDS V VIL Input low-level threshold 0.35 × VDDS V COSC Crystal Shunt capacitance 4 pF CLC Load Capacitance 12 24 pF TDC Output duty cycle on core port 40 50 60 % 1.8-V MODE Low Frequency Oscillator BALL NAMES in Mode 0: WKUP_LFOSC0_XI, WKUP_LFOSC0_XO BALL NUMBERS: AC4 / AE4 VIH Input high-level threshold 0.65 × VDDS V VIL Input low-level threshold 0.35 × VDDS V COSC Crystal Shunt capacitance 1.35 pF CLC Load Capacitance 12 24 µF TDC Output duty cycle on core port 45 50 55 % (1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [9] column. Table 5-5. UHS-I MMC (8bit PHY) Buffers DC Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT BALL NAMES in Mode 0: MMC0_CLK / MMC0_CMD / MMC0_DS / MMC0_DAT[7:0] / MMC1_CLK / MMC1_CMD / MMC1_DAT[3:0] / MMC0_CALPAD / MMC1_CALPAD BALL NUMBERS: A24 / A25 / A26 / B25 / B26 / B27 / C25 / C26 / C27 / C28 / D24 / D25 / D26 / D27 / D28 / E24 / E25 / E27 / F23 1.8-V Mode VIH Input high-level voltage 0.65 × VDDS VDDS VDDS+0.3 V

ADVANCE□INFORMATION 118 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-5. UHS-I MMC (8bit PHY) Buffers DC Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT VIL Input low-level voltage VDDS-0.3 VSSQ 0.35 × VDDS V VHYS Input hysteresis voltage 50 mV IIN Input current at each I/O pin 30 µA IOZ IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ 30 µA IIN with pulldown enabled Input current at each I/O pin with weak pulldown enabled measured when PAD = VDDS 50 120 210 µA IIN with pullup enabled Input current at each I/O pin with weak pullup enabled measured when PAD = 0 60 120 200 µA CPAD Pad capacitance (including package capacitance) 5 pF VOH Output high-level threshold (IOH = 2 mA) 0.75 × VDDS V VOL Output low-level threshold (IOL = 2 mA) 0.125 × VDDS V 3.3-V Mode VIH Input high-level threshold 0.65 × VDDS VDDS VDDS+0.3 V VIL Input low-level threshold VDDS-0.3 VDDS 0.35 × VDDS V VHYS Input hysteresis voltage 40 mV IIN Input current at each I/O pin 110 µA IOZ IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ 110 µA IIN with pulldown enabled Input current at each I/O pin with weak pulldown enabled measured when PAD = VDDS 40 100 290 µA IIN with pullup enabled Input current at each I/O pin with weak pullup enabled measured when PAD = 0 10 100 290 µA CPAD Pad capacitance (including package capacitance) 5 pF VOH Output high-level threshold (IOH = 2 mA) 0.75 × VDDS V VOL Output low-level threshold (IOL = 2 mA) 0.125 × VDDS V (1) VDDS in this table stands for corresponding power supply (i.e. vddshv8). For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [9] column. Table 5-6. Analog ADC Buffers DC Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER CONDITIONS MIN NOM MAX UNIT BALL NAMES in Mode 0: MCU_ADC0_AIN[7:0] / MCU_ADC0_REFP/N / MCU_ADC1_AIN[7:0] / MCU_ADC1_REFP/N BALL NUMBERS: F4 / F5 / G3 / G4 / G5 / G6 / H2 / H3 / H4 / H5 / J1 / J2 / J3 / J4 / J5 / J6 / K2 / K3 / K4 / K5 Analog Input VIN Full-scale Input Range Single Ended mode 0.5 1.8 V Differential Mode 1 3.6 V VREF Voltage reference Should be less than or equal to VDDA_MCU_ADC0/1. 1.8 V DNL Differential Non-Linearity -1 0.5 1 LSB

ADVANCE□INFORMATION 119 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-6. Analog ADC Buffers DC Electrical Characteristics (continued) over recommended operating conditions (unless otherwise noted) PARAMETER CONDITIONS MIN NOM MAX UNIT INL Integral Non-Linearity MCU_ADC0/1_REFP = VDDA_MCU_ADC0/1 ±1 ±2 LSB LSBGAIN-ERROR Gain Error MCU_ADC0/1_REFP = VDDA_MCU_ADC0/1 ±2 LSB LSBOFFSET-ERROR Offset Error MCU_ADC0/1_REFP = VDDA_MCU_ADC0/1 ±2 LSB CIN Input Sampling Capacitance 5.5 pF FC Input Frequency MCU_ADC0/1_AIN[7:0] TBD TBD kHz SNR Signal-to-Noise Ratio Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 70 dB THD Total Harmonic Distortion 1.7 Vpp, 200 kHz sine wave 75 dB SFDR Spurious Free Dynamic Range 1.7 Vpp, 200 kHz sine wave 80 dB SNR(PULSE) Signal-to-Noise Plus Distortion 1.7 Vpp, 200 kHz sine wave 69 dB RVREF VREF Input Impedance 2.2 kΩ Sampling Dynamics tSS Time from Start to Start TBD Clock Cycles tC Conversion Time 14 15 Clock Cycles tACQ Acquisition time TBD Clock Cycles TR Throughput Rate CLK = 60 MHz 4 MSPS CCISO Channel to Channel Isolation 100 dB F ADC ADC Clock Frequency 60 60 MHz Table 5-7. OLDI LVDS Buffers DC Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER Test Conditions MIN TYP MAX UNIT 1.8-V MODE BALL NAMES in Mode 0: OLDI0_A0P/N / OLDI0_A1P/N / OLDI0_A2P/N / OLDI0_A3P/N / OLDI0_CLKP/N BALL NUMBERS: J24 / J26 / J28 / K24 / K25 / K26 / K27 / K28 / L25 / L27 OLDI LVDS TRANSMITTER VOH High Level Output Voltage RL=100Ω 1.3 1.6 V VOL Low Level Output Voltage 0.9 1.01 V VCM Common Mode Voltage (OLDI) 1.125 1.25 1.375 V Common Mode Voltage (sub-LVDS) 0.9 V VOD Differential Output Voltage 250 380 450 mV Reduced Differential Output Voltage 100 200 300 mV IOS Output Short Circuit Current PAD/PADN=0, RL=100Ω -5 mA IOZ Output Tri-State Current PAD/PADN = 0/VDDS -10 4 40 µA TRF Rise/Fall Delay Time from 20% to 80% 100 ns RTERM Internal termination impedance VCM=1.25 V 45 95 125 Ω OLDI LVDS RECEIVER VID Differential input Voltage 50 mV VCM Common Mode Voltage 1.125 1.25 1.375 V FC Operating Frequency 100 kHz (1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [9] column.

ADVANCE□INFORMATION 120 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-8. LVCMOS Buffers DC Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER SPECIFIC BALL MIN TYP MAX UNIT BALL NAMES: ALL other IOs BALL NUMBERS: ALL other IOs 1.8-V MODE VIH Input high-level threshold TCK ( AA4) 0.60 * VDDS(1) V All other IOs 0.65 * VDDS(1) VIL Input low-level threshold TCK ( AA4) 0.30 * VDDS(1) V All other IOs 0.35 * VDDS(1) VHYS Input hysteresis voltage TCK ( AA4) 400 mV PORz ( E19), MCU_PORz ( W5), MCU_BYP_POR ( V5) All other IOs 100 VOH Output high-level threshold IOH = 100µA VDDS(1)-0.1 V IOH = 2mA VDDS(1)-0.2 IOH = 4mA VDDS(1)-0.3 IOH = 6mA VDDS(1)-0.4 VOL Output low-level threshold IOL = 100µA 0.1 V IOL = 2mA 0.2 IOL = 4mA 0.3 IOL = 6mA 0.4 IIN Input leakage current, pull-up or pull-down inhibited 11.5 µA Input leakage current, pull- down enabled, VI = VDDS(1) 65 96 153 Input leakage current, pull-up enabled, VI = VSS 64 97 154 IOZ Total leakage current through the driver/receiver combination, which may include an internal pull-up or pull-down. This value represents the maximum current flowing in or out of the pin while the output driver is disabled, the pull-up or pull- down is inhibited, and the input is swept from VSS to VDD. 11.5 µA 3.3-V MODE VIH Input high-level threshold TCK ( AA4) 2 V All other IOs 2 VIL Input low-level threshold TCK ( AA4) 0.8 V All other IOs 0.8 VHYS Input hysteresis voltage TCK ( AA4) 400 mV PORz ( E19), MCU_PORz ( W5), MCU_BYP_POR ( V5) All other IOs 100

ADVANCE□INFORMATION 121 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-8. LVCMOS Buffers DC Electrical Characteristics (continued) over recommended operating conditions (unless otherwise noted) PARAMETER SPECIFIC BALL MIN TYP MAX UNIT VOH Output high-level threshold IOH = 100µA VDDS(1)-0.1 V IOH = 2mA VDDS(1)-0.2 IOH = 4mA VDDS(1)-0.3 IOH = 6mA VDDS(1)-0.45 VOL Output low-level threshold IOL = 100µA 0.1 V IOL = 2mA 0.2 IOL = 4mA 0.3 IOL = 6mA 0.45 IIN Input leakage current, pull-up or pull-down inhibited 64 µA Input leakage current, pull- down enabled, VI = VDDS(1) 67 100.7 198 Input leakage current, pull-up enabled, VI = VSS 63 100.3 160 IOZ Total leakage current through the driver/receiver combination, which may include an internal pull-up or pull-down. This value represents the maximum current flowing in or out of the pin while the output driver is disabled, the pull-up or pull- down is inhibited, and the input is swept from VSS to VDD. 64 µA (1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [9] column.

5.7.1 USBHS Buffers DC Electrical Characteristics

USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0 Specification dated April 27, 2000 including ECNs and Errata as applicable.

5.7.2 SERDES Buffers DC Electrical Characteristics

The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base Specification Revision 4.0, February 19, 2014. NOTE USB0 instance is compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0, July 26, 2013.

5.8 VPP Specifications for One-Time Programmable (OTP) eFuses

This section specifies the operating conditions required for programming the OTP eFuses and is applicable only for High-Security Devices.

ADVANCE□INFORMATION 122 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-9. Recommended Operating Conditions for OTP eFuse Programming over operating free-air temperature range (unless otherwise noted) PARAMETER DESCRIPTION MIN NOM MAX UNIT VDD_CORE Supply voltage range for the core domain during OTP operation; OPP NOM (BOOT) See Section 5.4 V VDD_MCU Supply voltage range for the core domain during OTP operation; OPP NOM (BOOT) See Section 5.4 V VPP_CORE Supply voltage range for the eFuse ROM domain during normal operation N/A Supply voltage range for the eFuse ROM domain during OTP programming (1) 1.71 1.8 1.89 V VPP_MCU Supply voltage range for the eFuse ROM domain during normal operation N/A Supply voltage range for the eFuse ROM domain during OTP programming (1) 1.71 1.8 1.89 V I(VPP_CORE) TBD mA I(VPP_MCU) TBD mA Tj Temperature (ambient) 0 25 85 ºC (1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70718 from the TLV707x family meet the supply voltage range needed for VPP_CORE and VPP_MCU. (2) N/A in this table stands for Not Applicable.

5.8.1 Hardware Requirements

The following hardware requirements must be met when programming keys in the OTP eFuses:

The VPP_CORE and VPP_MCU power supplies must be disabled when not programming OTP registers.
The VPP_CORE and VPP_MCU power supplies must be ramped up after the proper device power-up sequence (for more details, see Section 5.11.2).

5.8.2 Programming Sequence

Programming sequence for OTP eFuses:

Power on the board per the power-up sequencing. No voltage should be applied on the VPP_CORE and VPP_MCU terminals during power up and normal operation.
Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP software package).
Apply the voltage on the VPP_CORE and VPP_MCU terminals according to the specification in Table 5-9.
Run the software that programs the OTP registers.
After validating the content of the OTP registers, remove the voltage from the VPP_CORE and VPP_MCU terminals.

5.8.3 Impact to Your Hardware Warranty

You recognize and accept at your own risk that your use of eFuse permanently alters the TI device. You acknowledge that eFuse can fail due to incorrect operating conditions or programming sequence. Such a failure may render the TI device inoperable and TI will be unable to confirm the TI device conformed to TI device specifications prior to the attempted eFuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY FOR ANY TI DEVICES THAT HAVE BEEN eFUSED.

ADVANCE□INFORMATION 123 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated

5.9 Thermal Resistance Characteristics

This section provides the thermal resistance characteristics used on this device. For reliability and operability concerns, the maximum junction temperature of the Device has to be at or below the TJ value identified in Section 5.4, Recommended Operating Conditions.

5.10 Thermal Resistance Characteristics

It is recommended to perform thermal simulations at the system level with the worst case device power consumption. NO. NAME DESCRIPTION ACD °C/W AIR FLOW (m/s) T1 RΘJC Junction-to-case 0.2 N/A T2 RΘJB Junction-to-board 3.1 N/A RΘJA Junction-to-free air 12.8 0 Junction-to-moving air 7.4 1 T5 6.5 2 T6 6 3 ΨJT Junction-to-package top 0.1 0 T8 0.1 1 T9 0.1 2 T10 0.1 3 T11 ΨJB Junction-to-board 2.9 0 T12 2.4 1 T13 2.3 2 T14 2.3 3 (1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: – JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) – JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages – JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air) – JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages – JESD51-9, Test Boards for Area Array Surface Mount Packages (2) m/s = meters per second. (3) °C/W = degrees Celsius per watt.

ADVANCE□INFORMATION 124 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated

5.11 Timing and Switching Characteristics

The Timing Requirements and Switching Characteristics values may change following the silicon characterization result.

5.11.1 Timing Parameters and Information

The timing parameter symbols used in Section 5.11 are created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies have been abbreviated in Table 5-10: Table 5-10. Timing Parameters Subscripts SYMBOL PARAMETER c Cycle time (period) d Delay time dis Disable time en Enable time h Hold time su Setup time START Start bit t Transition time v Valid time w Pulse duration (width) X Unknown, changing, or don't care level F Fall time H High L Low R Rise time V Valid IV Invalid AE Active Edge FE First Edge LE Last Edge Z High impedance

ADVANCE□INFORMATION t slew rate < 1E + 5 V/s slew > (supply value) / (1E + 5V/s) supply value x 10 µs Supply value SPRSP08_ELCH_06 125 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated

5.11.2 Power Supply Sequencing

This section describes the power-up sequence required to ensure proper device operation. The power supply names described in this section comprise a superset of a family of compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. NOTE All timing requirements and switching characteristics in Section 5.11.3 should be strictly followed unless otherwise specified.

5.11.2.1 Power Supply Slew Rate Requirement

To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the maximum slew rate of supplies to be less than 1.0E + 5 V/s. For instance, as shown in Figure 5-2, TI recommends having the supply ramp slew for a 1.8-V supply of more than 18 μs. Figure 5-2 describes the Power Supply Slew Rate Requirement of the device. Figure 5-2. Power Supply Slew and Slew Rate

5.11.2.2 Power-Up Sequencing

Figure 5-3 describes the Power-Up Sequencing using On Chip Power-on-reset (POR) of the device.

ADVANCE□INFORMATION Note 6 SPRSP08_ELCH_03 Note 7 Note 8 (2) (2) (2) (2) (2) VDDS1_WKUP , VDDS2_WKUP VDDS1 ,VDDS2 , VDDS3 , VDDS4 , VDDS5 , VDDS6 , VDDS7 , VDDS8 VDDA_1P8_CSI0, VDDA_PLL1_DDR, VDDA_PLL_MPU1 VDDA_SRAM_CORE1 VDDA_SRAM_MPU1 VDDS0_WKUP , , VDDS0 , , VDDA_1P8_OLDI0, VDDA_1P8_SERDES0, VDDA_MCU, VDDA_PLL_CORE, VDDA_PLL0_DDR, VDDA_PLL_DSS, VDDA_PLL_MPU0, , VDDA_PLL_PER0, VDDA_SRAM_CORE0, , VDDA_SRAM_MPU0, , VDDA_WKUP, VDDS_OSC1 (2) VDDA_ADC_MCU, VDDA_LDO_WKUP, VDDA_POR_WKUP, VDDA_3P3_IOLDO_WKUP, VDDA_3P3_SDIO, VDDA_3P3_USB VDDA_3P3_IOLDO0, VDDA_3P3_IOLDO1, VDDS_DDR VDD_MPU0, VDD_MPU1 WKUP_OSC0_XI, WKUP_OSC0_XO RESETz, MCU_RESETz RESETSTATz, MCU_RESETSTATz WKUP_LFOSC0_XI, WKUP_LFOSC0_XO (optional) (3) OSC1_XI, OSC1_XO (optional) (9) PORz_OUT, MCU_PORz_OUT MCU_BYP_POR PORz, MCU_PORz (4) VDDSHV0_WKUP,VDDSHV1_WKUP, VDDSHV2_WKUP, VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5, VDDSHV6, VDDSHV7, VDDSHV8 VDD_CORE, VDD_DLL_MMC0, VDD_DLL_MMC1 VDD_MCU VDD_WKUP0, VDD_WKUP1 Note 10 126 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-3. Power-Up Sequencing using On Chip Power-on-reset (POR) (1) Grey shaded areas are windows where it is valid to ramp the voltage rail. (2) The VDDS[2:0]_WKUP, VDDS[8:0] are sourced from the same 1.8 V VDDSHV[2:0]_WKUP, VDDSHV[8:0] supply. If VDDSHV[2:0]_WKUP, VDDSHV[8:0] is configured as 3.3 V, VDDS[2:0]_WKUP, VDDS[8:0] should be sourced from the internal IO bias LDO. (3) WKUP_LFOSC0 crystal clock source is disabled until software configures the oscillator and should be enabled after PORz_OUT, MCU_PORz_OUT reset release. WKUP_LFOSC0 square-wave clock source is not dependent on PORz_OUT, MCU_PORz_OUT. (4) PORz should be pulled to VDDSHV0. MCU_PORz should be pulled to VDDSHV0_WKUP. (5) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note. (6) If any of the VDDSHV[0-8], VDDSHV[2:0]_WKUP rails are used as 3.3 V only, then these rails must be ramped-up with the 3.3 V power supplies. (7) If any of the PORz, MCU_PORz signals are configured at 3.3 V only, then these signals must be ramped-up at the same time with the 3.3 V power supplies. (8) If any of the RESETz, MCU_RESETz signals are configured at 3.3 V only, then these signals must be ramped-up at the same time with the 3.3 V power supplies.

ADVANCE□INFORMATION 128 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated (5) MCU_BYP_POR should be pulled to VDDSHV0_WKUP. (6) If any of the VDDSHV[0-8] rails are used as 3.3 V only, then these rails must be ramped-up with the 3.3 V power supplies. (7) If MCU_BYP_POR is configured at 3.3 V only, then this signal must be ramped-up at the same time with the 3.3 V power supplies. (8) If any of the RESETz, MCU_RESETz signals are configured at 3.3 V only, then these signals must be ramped-up at the same time with the 3.3 V power supplies. (9) OSC1 crystal and square-wave clock sources are disabled until software configures the oscillator. Software should enable oscillator after PORz_OUT, MCU_PORz_OUT reset release. (10) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note. (11) If WKUP LDO is used to power the WKUP domain, connect CAP_VDD_WKUP pin to VDD_WKUP0/1 pin. VDD_WKUP0/1 will start ramping after VDDA_LDO_WKUP reaches a certain threshold. If WKUP LDO is bypassed, connect VDD_WKUP0/1 with VDD_MCU.

5.11.2.3 Power-Down Sequencing

A typical power down sequence is to have the Power-on-Reset asserted, clock shut down, and ramp down all the power supplies sequentially in the exact reverse order of the power-up sequencing. In other words, the power supply that has been ramped up first should be the last one that is ramped down. For DRA80x, there are no specific power-down sequencing requirements, except for asserting Power-on- Reset before ramping down the rails while bypassing internal POR.

ADVANCE□INFORMATION 129 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated

5.11.3 Reset Timing

5.11.3.1 Reset Electrical Data/Timing

For more details about features and additional description information on the subsystem multiplexing signals, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-11, Table 5-12, Figure 5-5, and Figure 5-6 present the reset timing requirements and switching characteristics. Table 5-11. Reset Timing Requirements NO. PARAMETER DESCRIPTION MIN MAX UNIT PORz Pin RST1 tw(PORzL) Pulse Width minimum, PORz low 2000 ns RST2 th(SUPPLIES VALID - PORz) Hold time, PORz active (low) after all supplies valid 2000000 ns RESETz Pin RST5 tw(RESETzL) Pulse Width minimum, RESETz low 400 ns MCU_PORz Pin RST13 tw(MCU_PORzL) Pulse Width minimum, MCU_PORz 2000 ns RST8 th(SUPPLIES VALID - MCU_PORz) Hold time, MCU_PORz active (low) after all supplies valid 2000000 ns MCU_RESETz Pin RST9 tw(MCU_RESETzL) Pulse Width minimum, MCU_RESETz 400 ns MCU_BYP_POR Pin RST12 tsu(MCU_BYP_POR-MCU_PORz) Setup time, MCU_BYP_POR active (high) before all supplies are valid 1000000 ns Table 5-12. Reset Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT PORz Pin RST3 td(PORz-PORz_OUT low) Delay time, PORz active (low) to PORz_OUT active (low) 0 ns RST4 td(PORz-PORz_OUT high) Delay time, PORz inactive (high) to PORz_OUT inactive (high) 0 ns RESETz Pin RST6 td(RESETz-RESETSTATz low) Delay time, RESETz active (low) to RESETSTATz active (low) 4106 ns RST7 td(RESETz-RESETSTATz high) Delay time, RESETz inactive (high) to RESETSTATz inactive (high) 380000 ns MCU_RESETSTATz Pin RST10 td(MCU_RESETz- MCU_RESETSTATz low) Delay time, MCU_RESETz active (low) to MCU_RESETSTATz active (low) 4106 ns RST11 td(MCU_RESETz- MCU_RESETSTATz high) Delay time, MCU_RESETz inactive (high) to MCU_RESETSTATz inactive (high) 289000 ns MCU_PORz Pin RST14 td(MCU_PORz-MCU_PORz_OUT low) Delay time, MCU_PORz active (low) to MCU_PORz_OUT active (low) 0 ns RST15 td(MCU_PORz-MCU_PORz_OUT high) Delay time, MCU_PORz inactive (high) to MCU_PORz_OUT inactive (high) 0 ns

ADVANCE□INFORMATION BC1 PORz BOOTMODE[18:00] BC2 BC3 MCU_PORz MCU_BOOTMODE[09:00] B 4 C 131 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-13. Boot Configuration Timing Requirements (continued) NO. PARAMETER MIN MAX UNIT BC4 th(MCU_PORz - MCU_BOOTMODE) Hold time, All Bootmode pins active after MCU_PORz inactive (high) 0 ns Figure 5-8. Boot Configuration Timing

5.11.4 Clock Specifications

5.11.4.1 Input Clocks / Oscillators

Various external clock inputs are needed to drive the device. Summary of these input clock signals are:

OSC1_XO/OSC1_XI — Еxternal main crystal interface pins connected to internal oscillator which sources reference clock and provides reference clock to PLLs within MAIN domain. Also, for audio applications, high-frequency oscillator 0 is used to provide audio clock frequencies to MCASPs.
WKUP_OSC0_XO/WKUP_OSC0_XI — Еxternal main crystal interface pins connected to internal oscillator which sources reference clock and provides reference clock to PLLs within MCU domain and MAIN domain.
WKUP_LFOSC_XO/WKUP_LFOSC_XI — External main crystal interface pins connected to internal oscillator which sources reference clock provides a clock for low power operation in deeper sleep modes.
MCU_EXT_REFCLK0 — Optional external system clock input (MCU domain).
EXT_REFCLK1— Optional external System clock input (MAIN domain). Optionally PLL2 (PER1) and MCASP can be sourced by EXT_REFCLK1 (sourced externally).
SERDES0_REFCLK P/N and SERDES1_REFCLK P/N — SerDes reference clock for PCIe or Optional USB3.0 PHY.
MCU_CPTS0_RFT_CLK — CPTS reference clock inputs for MCU_CPTS0_RFT_CLK.
CPTS_RFT0_CLK — CPTS reference clock inputs for CPTS0_RFT_CLK.
VOUT1_EXTPCLKIN — Optional for the DPI1 Port of DSS.
REFCLK0 P/N and REFCLK1 P/N — There are 2 differential clock output pins to support 2 PCIe devices. Figure 5-9 shows the external input clock sources to peripherals.

ADVANCE□INFORMATION DEVICE MCU_PORz / PORz MCU_SYSCLKOUT0 REFCLK0 P/N SERDES0_REFCLK P/N Selects Main PLL output divide-by-4 External main crystal interface pins connected to internal oscillator which provides reference clock to PLLs within MCU domain and MAIN domain. MCU_RESETz/ RESETz MCU_OBSCLK0 Optional pins to provide reference clock input to the PLLs. OSC1_XI OSC1_XO MCU Warm Reset Input / Device Warm Reset Input BOOTMODE[18:00] REFCLK1 P/N OBSCLK0 SYSCLK0 MCU Power ON Reset / Device Power ON Reset SPRSP08_CLOCK_01 There are 2 differential clock output pins to support 2 PCIe devices Boot Mode Configuration / devices select SerDes reference clock input for PCIe or Optional USB3SS0 PHY SERDES1_REFCLK P/N MCU_CPTS0_RFT_CLK MCU_EXT_REFCLK0 Optional for the DPI1 Port of DSSVOUT1_EXTPCLKIN External Low frequency crystal interface pins connected to internal oscillator which provides 32.768 KHza clock for low power operation in deeper sleep modes. WKUP_LFOSC0_XI WKUP_LFOSC0_XO External Wake-up crystal interface pins connected to internal oscillator which provides reference clock to PLLs within MAIN domain, and audio clock frequencies to MCASPs. WKUP_OSC0_XI WKUP_OSC0_XO CPTS reference clock input for CPTS_RFT_CLKCPTS0_RFT_CLK TCK EXT_REFCLK1 Optional external system clock input (MCU domain) CPTS reference clock input for MCU_CPTS_RFT_CLK Optional external System clock input (MAIN domain) Observation clock output for MCU Domain clocks Observation clock output for MAIN and MCU Domain clocks JTAG Clock Input MCU_BOOTMODE[09:00] MCU Boot Mode system clock speed and fail-safe boot device DDR_CK0P/DDR_CK0N DDR Differential Clock outputs DDR_CK1P/DDR_CK1N 132 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-9. Input Clocks Interface

ADVANCE□INFORMATION CL= C Cf1 2 f (C +C )f1 f2 SPRS932_CLOCK_03 Device WKUP_OSC0_XOWKUP_OSC0_XI Cf1 Crystal Rd Cf2 (Optional) SPRSP08_PCB_CLK_OSC_2 Rbias(Optional) PCB Ground 133 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated For more information about Input clock interfaces, see section Clocking in chapter Device Configuration of the device TRM.

5.11.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source

Figure 5-10 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board (PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on preproduction PCBs. Figure 5-10. WKUP_OSC0 Crystal Implementation NOTE The load capacitors, Cf1 and Cf2 in Figure 5-11, should be chosen such that the below equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator WKUP_OSC0_XI, WKUP_OSC0_XO, and VSS pins. Figure 5-11. Load Capacitance Equation The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-14 summarizes the required electrical constraints. Table 5-14. WKUP_OSC0 Crystal Electrical Characteristics NAME DESCRIPTION MIN TYP MAX UNIT fp Parallel resonance crystal frequency 19.2, 20, 24, 25, 26, 27 MHz Cf1 Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF Cf2 Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF

ADVANCE□INFORMATION VDDA_WKUP WKUP_OSC0_XO tsX Time Voltage VSS VDDA_WKUP (min.) VDD_WKUP (min.) VSS VDD_WKUP 134 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-14. WKUP_OSC0 Crystal Electrical Characteristics (continued) NAME DESCRIPTION MIN TYP MAX UNIT ESR(Cf1,Cf2) Crystal ESR 100 Ω CO Crystal shunt capacitance ESR = 30 Ω ESR = 40 Ω

19.2 MHz, 20 MHz, 24

MHz, 25 MHz, 26 MHz, 27 MHz 7 pF ESR = 50 Ω

19.2 MHz, 20 MHz 7 pF

24 MHz, 25 MHz, 26 MHz,

27 MHz 5 pF

ESR = 60 Ω

27 MHz Not Supported -

ESR = 80 Ω

19.2 MHz, 20 MHz 5 pF

ESR = 100 Ω

19.2 MHz, 20 MHz 3 pF

LM Crystal motional inductance for fp = 20 MHz 10.16 mH CM Crystal motional capacitance 3.42 fF fj(WKUP_OSC0_XI) Frequency accuracy, WKUP_OSC0_XI Ethernet RGMII and RMII not used ±100 ppm Ethernet RGMII and RMII using derived clock ±50 When selecting a crystal, the system design must consider the temperature and aging characteristics of a based on the worst case environment and expected life expectancy of the system. Table 5-15 details the switching characteristics of the oscillator and the requirements of the input clock. Table 5-15. WKUP_OSC0 Switching Characteristics – Crystal Mode NAME DESCRIPTION MIN TYP MAX UNIT fp Oscillation frequency 19.2, 20, 24, 25, 26, 27 MHz tsX Start-up time 2(1) ms (1) In order to meet the start-up time defined in this table, the crystal needs to be selected according to the following equation: Tsu = K*Lm/ (Ro-ESR) + Δt where Lm is crystal motional inductance, RO is the negative resistance of amplifier, ESR is the crystal Effective series resistance and K is a constant which represents the initial conditions. Δt is the time amplifier takes to reach its bias point after power down is released. Figure 5-12. WKUP_OSC0 Start-up Time

ADVANCE□INFORMATION WKUP_OSC0_XI CK0 CK1 CK1 VSS Device WKUP_OSC0_XOWKUP_OSC0_XI NC SPRSP08_CLK_02 NC PCB Ground 135 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated

5.11.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source

Figure 5-13 shows the recommended oscillator connections when WKUP_OSC0 is connected to an LVCMOS square-wave digital clock source The 1.8-V LVCMOS-Compatible clock source is connected to the WKUP_OSC0_XI pin. In this mode of operation, the WKUP_OSC0_XO pin is left unconnected and should not be used to source any external components. Figure 5-13. 1.8-V LVCMOS-Compatible Clock Input Table 5-16 summarizes the WKUP_OSC0 input clock electrical characteristics Table 5-16. WKUP_OSC0 Switching Characteristics – Crystal Mode NAME DESCRIPTION MIN TYP MAX UNIT f Frequency 19.2, 20, 24, 25, 26, 27 MHz CIN Input capacitance 2.184 2.384 2.584 pF IIN Input current (3.3V mode) 4 6 10 µA Table 5-17 details the WKUP_OSC0 input clock timing requirements. Table 5-17. WKUP_OSC0 Input Clock Timing Requirements NAME DESCRIPTION MIN TYP MAX UNIT CK0 1 / tc(WKUP_OSC0_XI) Frequency, WKUP_OSC0_XI 19.2, 20, 24, 25, 26, 27 MHz CK1 tw(WKUP_OSC0_XI) Pulse duration, WKUP_OSC0_XI low or high 0.45 × tc(WKUP_OSC0_XI) 0.55 × tc(WKUP_OSC0_XI) ns tj(WKUP_OSC0_XI) Period jitter, WKUP_OSC0_XI 0.01 × tc(WKUP_OSC0_XI) ns tR(WKUP_OSC0_XI) Rise time, WKUP_OSC0_XI 5 ns tF(WKUP_OSC0_XI) Fall time, WKUP_OSC0_XI 5 ns tj(WKUP_OSC0_XI) Frequency accuracy, WKUP_OSC0_XI Ethernet RGMII and RMII not used ±100 ppm Ethernet RGMII and RMII using derived clock ±50 Figure 5-14. WKUP_OSC0_XI Input Clock

ADVANCE□INFORMATION CL= C Cf1 2 f (C +C )f1 f2 SPRS932_CLOCK_03 Device OSC1_XOOSC1_XI Cf1 Crystal Rd Cf2 (Optional) SPRSP08_PCB_CLK_OSC_1 Rbias(Optional) PCB Ground 136 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated

5.11.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source

Figure 5-15 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board (PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on preproduction PCBs. Figure 5-15. OSC1 Crystal Implementation NOTE The load capacitors, Cf1 and Cf2 in Figure 5-16, should be chosen such that the below equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator OSC1_XI, OSC1_XO, and VSS pins. Figure 5-16. Load Capacitance Equation The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-18 summarizes the required electrical constraints. Table 5-18. OSC1 Crystal Electrical Characteristics NAME DESCRIPTION MIN TYP MAX UNIT fp Parallel resonance crystal frequency 19.2, 20, 24, 25, 26, 27 MHz Cf1 Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF Cf2 Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF ESR(Cf1,Cf2) Crystal ESR 100 Ω

ADVANCE□INFORMATION VDDS_OSC1 OSC1_XO tsX Time Voltage VSS VDDS_OSC1 (min.) VDD_CORE (min.) VSS VDD_CORE 137 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-18. OSC1 Crystal Electrical Characteristics (continued) NAME DESCRIPTION MIN TYP MAX UNIT CO Crystal shunt capacitance ESR = 30 Ω ESR = 40 Ω MHz, 25 MHz, 26 MHz, 27 MHz 7 pF ESR = 50 Ω ESR = 60 Ω ESR = 80 Ω ESR = 100 Ω LM Crystal motional inductance for fp = 20 MHz 10.16 mH CM Crystal motional capacitance 3.42 fF fj(OSC1_XI) Frequency accuracy, OSC1_XI Ethernet RGMII and RMII not used ±100 ppm Ethernet RGMII and RMII using derived clock ±50 When selecting a crystal, the system design must consider the temperature and aging characteristics of a based on the worst case environment and expected life expectancy of the system. Table 5-19 details the switching characteristics of the oscillator and the requirements of the input clock. Table 5-19. OSC1 Switching Characteristics – Crystal Mode NAME DESCRIPTION MIN TYP MAX UNIT fp Oscillation frequency 19.2, 20, 24, 25, 26, 27 MHz tsX Start-up time 2(1) ms (1) In order to meet the start-up time defined in this table, the crystal needs to be selected according to the following equation: Tsu = K*Lm/ (Ro-ESR) + Δt where Lm is crystal motional inductance, RO is the negative resistance of amplifier, ESR is the crystal Effective series resistance and K is a constant which represents the initial conditions. Δt is the time amplifier takes to reach its bias point after power down is released. Figure 5-17. OSC1 Start-up Time

ADVANCE□INFORMATION OSC1_XI CK0 CK1 CK1 VSS Device OSC1_XOOSC1_XI NC SPRSP08_CLK_01 PCB Ground 138 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated

5.11.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source

Figure 5-18 shows the recommended oscillator connections when OSC1 is connected to an LVCMOS square-wave digital clock source The 1.8-V LVCMOS-Compatible clock source is connected to the OSC1_XI pin. In this mode of operation, the OSC1_XO pin is left unconnected and should not be used to source any external components. Figure 5-18. 1.8-V LVCMOS-Compatible Clock Input Table 5-20 summarizes the OSC1 input clock electrical characteristics. Table 5-20. OSC1 Switching Characteristics – Crystal Mode NAME DESCRIPTION MIN TYP MAX UNIT f Frequency 19.2, 20, 24, 25, 26, 27 MHz CIN Input capacitance 2.184 2.384 2.584 pF IIN Input current (3.3V mode) 4 6 10 µA Table 5-21 details the OSC1 input clock timing requirements. Table 5-21. OSC1 Input Clock Timing Requirements NAME DESCRIPTION MIN TYP MAX UNIT CK0 1 / tc(OSC1_XI) Frequency, OSC1_XI 19.2, 20, 24, 25, 26, 27 MHz CK1 tw(OSC1_XI) Pulse duration, OSC1_XI low or high 0.45 × tc(OSC1_XI) 0.55 × tc(OSC1_XI) ns tj(OSC1_XI) Period jitter, OSC1_XI 0.01 × tc(OSC1_XI) ns tR(OSC1_XI) Rise time, OSC1_XI 5 ns tF(OSC1_XI) Fall time, OSC1_XI 5 ns tj(OSC1_XI) Frequency accuracy, OSC1_XI Ethernet RGMII and RMII not used ±100 ppm Ethernet RGMII and RMII using derived clock ±50 Figure 5-19. OSC1_XI Input Clock

ADVANCE□INFORMATION Device WKUP_LFOSC0_XOWKUP_LFOSC0_XI Cf1 Crystal Rd Cf2 (Optional) SPRSP08_PCB_CLK_OSC_3 Rbias(Optional) PCB Ground Device OSC1_XOOSC1_XI SPRSP08_PCB_CLK_OSC_NU1 Rpd PCB Ground NC 139 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated

5.11.4.1.5 Auxiliary OSC1 Not Used

Figure 5-20 shows the recommended oscillator connections when OSC1 is not used. OSC1_XI must be connected to VSS through an external pull resistor (Rpd) to ensure this input is held to a valid low level when unused since the internal pull-down resistor is disabled by default. Figure 5-20. OSC1 Not Used

5.11.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source

Figure 5-21 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board (PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd is a 0 ohm resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on preproduction PCBs. Figure 5-21. WKUP_LFOSC0 Crystal Implementation

ADVANCE□INFORMATION CL= C Cf1 2 f (C +C )f1 f2 SPRS932_CLOCK_03 140 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated NOTE The load capacitors, Cf1 and Cf2 in Figure 5-22, should be chosen such that the below equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator WKUP_LFOSC0_XI, WKUP_LFOSC0_XO, and VSS pins. Figure 5-22. Load Capacitance Equation The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-22 summarizes the required electrical constraints Table 5-22. WKUP_LFOSC0 Crystal Electrical Characteristics NAME DESCRIPTION MIN TYP MAX UNIT fp Parallel resonance crystal frequency 32768 Hz Cf1 Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF Cf2 Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF Cshunt Shunt capacitance TBD pF ESR Crystal effective series resistance TBD kΩ When selecting a crystal, the system design must consider the temperature and aging characteristics of a based on the worst case environment and expected life expectancy of the system. Table 5-23 details the switching characteristics of the oscillator and the requirements of the input clock. Table 5-23. WKUP_LFOSC0 Switching Characteristics – Crystal Mode NAME DESCRIPTION MIN TYP MAX UNIT fxtal Oscillation frequency 32768 Hz tSX Start-up time (1) s

ADVANCE□INFORMATION Device WKUP_LFOSC0_XOWKUP_LFOSC0_XI SPRSP08_PCB_CLK_OSC_NU3 NC NC VDDA_WKUP WKUP_LFOSC0_XO tsX Time Voltage VSS VDDA_WKUP (min.) VDD_WKUP (min.) VSS VDD_WKUP 141 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated (1) In order to meet the start-up time defined in this table, the crystal needs to be selected according to the following equation: Tsu = K*Lm/ (Ro-ESR) + Δt where Lm is crystal motional inductance, RO is the negative resistance of amplifier, ESR is the crystal Effective series resistance and K is a constant which represents the initial conditions. Δt is the time amplifier takes to reach its bias point after power down is released. Figure 5-23. WKUP_LFOSC0 Start-up Time

5.11.4.1.7 WKUP_LFOSC0 Not Used

Figure 5-24 shows the recommended oscillator connections when WKUP_LFOSC0 is not used. WKUP_LFOSC0 may be a no-connect while the oscillator remains disabled since the internal pull-down resistor is enabled by default. Figure 5-24. WKUP_LFOSC0 Not Used

5.11.4.2 Output Clocks

The device provides several system clock outputs. Summary of these output clocks are as follows:

MCU_SYSCLKOUT0 – SYSCLK0 of WKUP_PLLCTRL0 is divided by 6 and then sent out of the device as a LVCMOS clock signal (MCU_SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not.
MCU_OBSCLK0 – On the clock output MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.
SYSCLKOUT0 – SYSCLK0 from the MAIN_PLL controller is divided by 6 and then sent out of the device as a LVCMOS clock signal (SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not.

ADVANCE□INFORMATION 142 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated

OBSCLK0 – On the clock output OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.

ADVANCE□INFORMATION 143 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated

5.11.4.3 PLLs

Power is supplied to the PLL by internal regulators that derive power from the off-chip power-supply. There are total nine Phase Locked Loops (PLLs) in the device:

MCU_PLL0 (MCU PLL) with WKUP_PLL_CTRL0: The MCU PLL — which is used to drive the switch fabrics, accelerators, and a majority of the peripheral clocks — requires a PLL controller to manage the various clock divisions, gating, and synchronization in WKUP domain and MCU domain.
MCU_PLL1 (CPSW PLL): The MCU_PLL1, which is used to drive the CPSW.
PLL0 (MAIN PLL) with PLL_CTRL0: The Main PLL — which is used to drive the switch fabrics, accelerators, and a majority of the peripheral clocks — requires a PLL controller to manage the various clock divisions, gating, and synchronization in MAIN domain.
PLL1 (PER0 PLL): The PER0 PLL, which is used to drive the Peripherals in MAIN Domain.
PLL2 (PER1 PLL): The PER1 PLL, which is used to drive the PRU-ICSSG.
PLL3 (DDR PLL): The DDR PLL is used to drive the DDR PHY for the DDRSS.
PLL4 (DSS PLL): The DSS PLL, which is used to drive the Display Subsystem.
PLL6 (ARM0 PLL): The ARM0 PLL, which is used to drive the ARM0.
PLL7 (ARM1 PLL): The ARM1 PLL, which is used to drive the ARM1. Most of the Device is driven by the output from the main PLL except the following items:
Arm subsystem has its own dedicated PLL.
MCU subsystem has its own dedicated PLL
EMIF DDR subsystem has its own dedicated PLL to drive DDR PHY and DDRSS.
PRU-ICSSG has clocks sourced from several PLLs: – PER0 PLL to generate UART clock, – PER1 PLL to generate Core clock, – MAIN PLL to generate Industrial Ethernet Peripheral clock, – CPSW PLL to generate Ethernet clocks.
DSS has its own dedicated PLL, to generate Pixel Clock.
PCIESS require separate reference clocks to drive SERDES PHYs. NOTE For more information, see:
Device Configuration / Clocking / PLLs section of the device TRM
Peripherals / Display Subsystem Overview section of the device TRM
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) section of the device TRM NOTE The input reference clock (OSC1_XI/OSC1_XO) are specified and the lock time is guaranteed by the PLL controller, as documented in the Device Configuration chapter of the device TRM.

5.11.4.3.1 PLL Characteristics

Figure 5-25 shows the power supply connectivity implemented in the device.

ADVANCE□INFORMATION MCU_PLL0 (MCU PLL) SPRSP08_PLL_PWR_01 MCU_PLL1 (CPSW PLL) PLL0 (MAIN PLL) PLL2 (PER1 PLL) PLL1 (PER0 PLL) PLL3 (DDR PLL) PLL4 (DSS PLL) PLL6 (ARM0 PLL) PLL7 (ARM1 PLL) VDDA_MCU VDDA_PLL_CORE VDDA_PLL_PER0 VDDA_PLL0_DDR VDDA_PLL_DSS VDDA_PLL_MPU0 VDDA_PLL_MPU1 144 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-25. PLL Power Supply Connectivity Table 5-24 provides the power supply requirements for the PLL. Table 5-24. PLL Power Supply Requirements SUPPLY NAME DESCRIPTION MIN NOM MAX UNIT VDD_DLL_MMC0 MMC0 PHY DLL voltage supply 0.95 1 1.05 V Max. peak-to-peak supply noise TBD mV (p-p) VDD_DLL_MMC1 MMC1 PHY DLL voltage supply 0.95 1 1.05 V Max. peak-to-peak supply noise TBD mV (p-p) VDDA_PLL_CORE CORE DPLL, PER1 DPLL analog power supply 1.71 1.8 1.89 V Max. peak-to-peak supply noise 50 mV (p-p) VDDA_PLL0_DDR DDR DPLL analog power supply 1.71 1.8 1.89 V Max. peak-to-peak supply noise 50 mV (p-p) VDDA_PLL1_DDR DDR De-skew DPLL analog power supply 1.71 1.8 1.89 V Max. peak-to-peak supply noise 50 mV (p-p) VDDA_PLL_DSS DSS DPLL analog power supply 1.71 1.8 1.89 V Max. peak-to-peak supply noise 50 mV (p-p) VDDA_PLL_MPU0 MPU0 DPLL analog power supply 1.71 1.8 1.89 V Max. peak-to-peak supply noise 50 mV (p-p) VDDA_PLL_MPU1 MPU1 DPLL analog power supply 1.71 1.8 1.89 V Max. peak-to-peak supply noise 50 mV (p-p) VDDA_PLL_PER0 PER0 DPLL analog power supply 1.71 1.8 1.89 V Max. peak-to-peak supply noise 50 mV (p-p)

5.11.4.4 System Clocks Operating Frequency Ranges

Table 5-25 lists the operating frequency ranges for the system clocks of the device. Table 5-25. System Clocks Operating Frequency Range System Clocks (1) Bypass Min (MHz) Bypass Max (MHz) Minimum Operating Frequency (MHz) PLL0 (MAIN PLL)

ADVANCE□INFORMATION 145 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-25. System Clocks Operating Frequency Range (continued) System Clocks (1) Bypass Min (MHz) Bypass Max (MHz) Minimum Operating Frequency (MHz) PLL1 (PER0 PLL) PLL2 (PER1 PLL) PLL3 (DDR PLL) PLL4 (DSS PLL) PLL6 (ARM0 PLL) PLL7 (ARM1 PLL) MCU_PLL0 MCU_PLL1 (1) Supported input reference clock frequencies to the PLL are 19.2/24/25/26 MHz only. (2) Interconnect clock on DSS is CPU/4. This will range from 100 MHz to 250 MHz. (3) When Main PLL is configured to 400 MHz mode, DSS can only support a Max Pixel clock of 74.25 MHz. For lower resolution Displays the DSS clock can be lower than 74.25 MHz.

5.11.4.5 Device Inputs and Outputs Module Clocks Frequencies

NOTE TO USERS: The content of this section is UNDER DEVELOPMENT!

5.11.4.6 Recommended Clock and Control Signal Transition Behavior

All clocks and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input transitions are more susceptible to glitches due to noise, and special care must be taken for slow input clocks.

5.11.4.7 Interface Clock Specifications

5.11.4.7.1 Interface Clock Terminology

The interface clock is used at the system level to sequence the data and to control transfers accordingly with the interface protocol.

5.11.4.7.2 Interface Clock Frequency

The two interface clock characteristics are:

The maximum clock frequency
The maximum operating frequency The interface clock frequency documented here is the maximum clock frequency, which corresponds to the maximum frequency programmable on this output clock. This frequency defines the maximum limit supported by the Device IC and does not take into account any system consideration (PCB, peripherals). The system designer must take into account these system considerations and the Device IC timing characteristics to properly define the maximum operating frequency that corresponds to the maximum frequency supported to transfer the data on this interface.

ADVANCE□INFORMATION MDIO3 MDIO1 MDIO2 MDIO7 MDIO4 MDIO5 MDIO6 MDIO6 MDIO_CLK MDIO_DA T A (input) MDIO_DA T A (output) SPRS8xx_GMAC_MDIO_07 146 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated

5.11.5 Peripherals

5.11.5.1 CPSW2G

For more details about features and additional description information on the device Gigabit Ethernet MAC, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description.

5.11.5.1.1 CPSW2G MDIO Interface Timings

Table 5-26, Table 5-27, and Figure 5-26 present timing requirements for MDIO. Table 5-26. Timing Requirements for MDIO Input NO. PARAMETER MIN MAX UNIT MDIO1 tsu(MDIO_MDC) Setup time, MDIO_DATA valid before MDIO_CLK high 90 ns MDIO2 th(MDIO_MDC) Hold time, MDIO_DATA valid after MDIO_CLK high 0 ns Table 5-27. Switching Characteristics Over Recommended Operating Conditions for MDIO Output NO. PARAMETER MIN MAX UNIT MDIO3 tc(MDC) Cycle time, MDIO_CLK 400 ns MDIO4 tw(MDCH) Pulse Duration, MDIO_CLK high 160 ns MDIO5 tw(MDCL) Pulse Duration, MDIO_CLK low 160 ns MDIO6 tt(MDC) Transition time, MDIO_CLK 5 ns MDIO7 td(MDC_MDIO) Delay time, MDIO_CLK High to MDIO_DATA valid 10 390 ns Figure 5-26. CPSW2G MDIO diagrams receive and transmit

5.11.5.1.2 CPSW2G RMII Timings

Table 5-28, Table 5-29, and Figure 5-27 present timing requirements for CPSW2G RMII receive. Table 5-28. Timing Requirements for RMII[x]_REFCLK - RMII Mode NO. PARAMETER DESCRIPTION MIN TYP MAX UNIT RMII1 tc(REF_CLK) Cycle time, REF_CLK 19.999 20.001 ns RMII2 tw(REF_CLKH) Pulse Duration, REF_CLK High 7 13 ns RMII3 tw(REF_CLKL) Pulse Duration, REF_CLK Low 7 13 ns

ADVANCE□INFORMATION RMII[x]_TXD[1:0], RMII[x]_TXEN (outputs) SPRSP08_CPSW2G_RMIITX RMII6 RMII7 RMII[x]_REFCLK (input) RMII8 148 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-29. RMII[x]_TXD[1:0], RMII[x]_TXEN Timing - RMII Mode

5.11.5.1.3 CPSW2G RGMII Timings

Table 5-31, Table 5-32, and Figure 5-30 present timing requirements for receive RGMII operation. Table 5-31. Timing Requirements for RGMII[x]_RCLK - RGMII Mode NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT RGMII1 tc(RXC) Cycle time, RXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII2 tw(RXCH) Pulse duration, RXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII3 tw(RXCL) Pulse duration, RXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII4 tt(RXC) Transition time, RXC 10Mbps 0.75 ns 100Mbps 0.75 ns 1000Mbps 0.75 ns Table 5-32. Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT RGMII5 tsu(RD-RXC) Setup time, RD[3:0] valid before RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns tsu(RX_CTL-RXC) Setup time, RX_CTL valid before RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII6 th(RXC-RD) Hold time, RD[3:0] valid after RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns th(RXC-RX_CTL) Hold time, RX_CTL valid after RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns

ADVANCE□INFORMATION RGMII[x] RXD_ [3:0] (B) RGMII[x] RCTL_ (B) RGMII[x] RXC_ (A) RGMII5 RXERRRXDV 1st Half-byte 2nd Half-byte RGRXD[7:4]RGRXD[3:0] RGMII2 RGMII3 RGMII1 RGMII4 RGMII4 RGMII6 SPRSP08_CPSW2G_RGMIIRX 149 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-32. Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode (continued) NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT RGMII7 tt(RD) Transition time, RD 10Mbps 0.75 ns 100Mbps 0.75 ns 1000Mbps 0.75 ns tt(RX_CTL) Transition time, RX_CTL 10Mbps 0.75 ns 100Mbps 0.75 ns 1000Mbps 0.75 ns A. RGMII_RXC must be externally delayed relative to the data and control pins. B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC and RXERR on falling edge of RGMII_RXC. Figure 5-30. CPSW2G Receive Interface Timing, RGMII operation Table 5-33, Table 5-34, and Figure 5-31 present switching characteristics for transmit - RGMII for 10 Mbps, 100 Mbps, and 1000 Mbps. Table 5-33. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT RGMII1 tc(TXC) Cycle time, TXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII2 tw(TXCH) Pulse duration, TXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII3 tw(TXCL) Pulse duration, TXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII4 tt(TXC) Transition time, TXC 10Mbps 0.75 ns 100Mbps 0.75 ns 1000Mbps 0.75 ns

ADVANCE□INFORMATION RGMII[x]_TXC (A) RGMII[x]_TXD[3:0] (B) RGMII[x] TCTL_ (B) RGMII5 1st Half-byte TXERRTXEN 2nd Half-byte RGMII4 RGMII4 RGMII2 RGMII3 RGMII1 RGMII5 SPRSP08_CPSW2G_RGMIITX 150 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-34. Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT RGMII5 tsk(TD-TXC) TD to TXC output skew 10Mbps TBD TBD ns 100Mbps TBD TBD ns 1000Mbps TBD TBD ns tsk(TX_CTL-TXC) TX_CTL to TXC output skew 10Mbps TBD TBD ns 100Mbps TBD TBD ns 1000Mbps TBD TBD ns RGMII6 tt(TD) Transition time, TD 10Mbps 0.75 ns 100Mbps 0.75 ns 1000Mbps 0.75 ns tt(TX_CTL) Transition time, TX_CTL 10Mbps 0.75 ns 100Mbps 0.75 ns 1000Mbps 0.75 ns A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled. B. Data and control information is received using both edges of the clocks. RGMII_TXD[3:0] carries data bits 3-0 on the rising edge of RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TXCTL carries TXDV on rising edge of RGMII_TXC and RTXERR on falling edge of RGMII_TXC. Figure 5-31. CPSW2G Transmit Interface Timing RGMII Mode For more information, see section Networking Subsystem (NSS) in chapter Peripherals of the device TRM.

5.11.5.2 DDRSS

For more details about features and additional description information on the device DDR3L, DDR4, and LPDDR4 Memory Interfaces, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. The device has dedicated interfaces to DDR3L, DDR4, and LPDDR4 SDRAM. It supports JEDEC JESD79-3-1, JESD79-4B, and JESD209-4B standards compliant DDR3L, DDR4, and LPDDR4 SDRAM devices with the following features:

16-bit or 32-bit data path to external SDRAM memory
Memory device capacity: Up to 32 GB address space available over one chip select

5.11.5.3 GPIO

The device has three instances of GPIO144 modules. The GPIO pins are grouped into banks (16 pins per bank), which means that each GPIO module provides up to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIO0_[56:143], GPIO0_[96:143], and GPIO1_[90:143] are reserved in this Device, general purpose interface supports up to 242 pins.

ADVANCE□INFORMATION 151 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated For more details about features and additional description information on the device General-Purpose Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. NOTE The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi. Table 5-35 and Table 5-36 present timings and switching characteristics of the GPIO Interface. Table 5-35. GPIO Timing Requirements NO. PARAMETER DESCRIPTION MIN MAX UNIT GP2 tw(GPIO_IN) Minimum Input Pulse Width 3.6 + 2P(1) ns (1) P = functional clock period in ns. Table 5-36. GPIO Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT GP1 tw(GPIO_OUT) Minimum Output Pulse Width -4.6 + 0.975P(1) ns (1) P = functional clock period in ns. For more information, see section General-Purpose Interface (GPIO) in chapter Peripherals of the device TRM.

5.11.5.4 GPMC

For more details about features and additional description information on the device General-Purpose Memory Controller, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description.

5.11.5.4.1 GPMC and NOR Flash— Synchronous Mode

Table 5-37 and Table 5-38 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-32 through Figure 5-36). Table 5-37. GPMC and NOR Flash Timing Requirements— Synchronous Mode NO. PARAMETER DESCRIPTION MODE(3) MIN MAX UNIT F12 tsu(dV-clkH) Setup time, input data GPMC_AD[15:0] valid before output clock GPMC_CLK high div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 0.59 ns not_div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 0.34 ns F13 th(clkH-dV) Hold time, input data GPMC_AD[15:0] valid after output clock GPMC_CLK high div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 1.78 ns not_div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 1.78 ns F21 tsu(waitV-clkH) Setup time, input wait GPMC_WAIT[x] valid before output clock GPMC_CLK high (1) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 0.59 ns not_div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 0.34 ns

ADVANCE□INFORMATION 152 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-37. GPMC and NOR Flash Timing Requirements— Synchronous Mode (continued) NO. PARAMETER DESCRIPTION MODE(3) MIN MAX UNIT F22 th(clkH-waitV) Hold time, input wait GPMC_WAIT[x] valid after output clock GPMC_CLK high (1) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 1.78 ns not_div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 1.78 ns (1) In GPMC_WAIT[x], x is equal to 0 or 1. (2) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General- Purpose Memory Controller section in the Device TRM. (3) For div_by_1_mode: – GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency For not_div_by_1_mode: – GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h: – GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4) For GPMC_FCLK_MUX_100: – gpmc_fclk_sel[1:0] = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz For TIMEPARAGRANULARITY_X1: – GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS) Table 5-38. GPMC and NOR Flash Switching Characteristics— Synchronous Mode(2) NO. PARAMETER DESCRIPTION MODE(20) MIN MAX UNIT F0 1 / tc(clk) Period, output clock GPMC_CLK (18) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 10 ns F1 tw(clkH) Typical pulse duration, output clock GPMC_CLK high div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -0.3+0. 475*P (15) ns F1 tw(clkL) Typical pulse duration, output clock GPMC_CLK low div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -0.3+0. 475*P (15) ns tdc(clk) Duty cycle error, output clock GPMC_CLK div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -500 500 ps tJ(clk) Jitter standard deviation, output clock GPMC_CLK (19) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 33.33 ps tR(clk) Rise time, output clock GPMC_CLK div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 2 ns tF(clk) Fall time, output clock GPMC_CLK div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 2 ns tR(do) Rise time, output data GPMC_AD[15:0] div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 2 ns tF(do) Fall time, output data GPMC_AD[15:0] div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 2 ns F2 td(clkH-csnV) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[x] transition (14) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1; no extra_delay -2.2+F (6) 4.5+F (6) ns

ADVANCE□INFORMATION 153 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-38. GPMC and NOR Flash Switching Characteristics— Synchronous Mode(2) (continued) NO. PARAMETER DESCRIPTION MODE(20) MIN MAX UNIT F3 td(clkH-csnIV) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[x] invalid (14) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1; no extra_delay -2.2+E (5) 4.5+E (5) ns F4 td(aV-clk) Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edge div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -2.3+B (2) 4.5+B (2) ns F5 td(clkH-aIV) Delay time, output clock GPMC_CLK rising edge to output address GPMC_A[27:1] invalid div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -2.3 4.5 ns F6 td(be[x]nV-clk) Delay time, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n valid to output clock GPMC_CLK first edge div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -2.3+B (2) 1.9+B (2) ns F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n invalid (11) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -2.3+D (4) 1.9+D (4) ns F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid (12) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -2.3+D (4) 1.9+D (4) ns F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid (13) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -2.3+D (4) 1.9+D (4) ns F8 td(clkH-advn) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transition div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1; no extra_delay -2.3+G (7) 4.5+G (7) ns F9 td(clkH-advnIV) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invalid div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1; no extra_delay -2.3+D (4) 4.5+D (4) ns F10 td(clkH-oen) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transition div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1; no extra_delay F11 td(clkH-oenIV) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invalid div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1; no extra_delay -2.3+E (8) 3.5+E (8) ns F14 td(clkH-wen) Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transition div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1; no extra_delay F15 td(clkH-do) Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition (11) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -2.3+J (10) 2.7+J (10) ns F15 td(clkL-do) Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition (12) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -2.3+J (10) 2.7+J (10) ns F15 td(clkL-do). Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition (13) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -2.3+J (10) 2.7+J (10) ns F17 td(clkH-be[x]n) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition (11) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -2.3+J (10) 1.9+J (10) ns F17 td(clkL-be[x]n) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition (12) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -2.3+J (10) 1.9+J (10) ns

ADVANCE□INFORMATION 154 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-38. GPMC and NOR Flash Switching Characteristics— Synchronous Mode(2) (continued) NO. PARAMETER DESCRIPTION MODE(20) MIN MAX UNIT F17 td(clkL-be[x]n). Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition (13) div_by_1_mode; GPMC_FCLK_MUX_100; TIMEPARAGRANULARITY_X1 -2.3+J (10) 1.9+J (10) ns F18 tw(csnV) Pulse duration, output chip select GPMC_CSn[x] low (14) Read A (1) ns Write A (1) ns F19 tw(be[x]nV) Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n low Read C (3) ns Write C (3) ns F20 tw(advnV) Pulse duration, output address valid and address latch enable GPMC_ADVn_ALE low Read K (16) ns Write K (16) ns (1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) With n being the page burst access number. (2) B = ClkActivationTime × GPMC_FCLK(17) (3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) With n being the page burst access number. (4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) (5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) (6) For csn falling edge (CS activated): – Case GpmcFCLKDivider = 0: – F = 0.5 × CSExtraDelay × GPMC_FCLK(17) – Case GpmcFCLKDivider = 1: – F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even) – F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime) is a multiple of 3) – F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3) – F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3) (7) For ADV falling edge (ADV activated): – Case GpmcFCLKDivider = 0: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) – Case GpmcFCLKDivider = 1: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Reading mode: – Case GpmcFCLKDivider = 0: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) – Case GpmcFCLKDivider = 1: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Writing mode: – Case GpmcFCLKDivider = 0: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)

ADVANCE□INFORMATION 155 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated – Case GpmcFCLKDivider = 1: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3) (8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction): – Case GpmcFCLKDivider = 0: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) – Case GpmcFCLKDivider = 1: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3) – H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3) For OE rising edge (OE deactivated): – Case GpmcFCLKDivider = 0: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) – Case GpmcFCLKDivider = 1: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3) – H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3) (9) For WE falling edge (WE activated): – Case GpmcFCLKDivider = 0: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) – Case GpmcFCLKDivider = 1: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3) – I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3) For WE rising edge (WE deactivated): – Case GpmcFCLKDivider = 0: – I = 0.5 × WEExtraDelay × GPMC_FCLK (17) – Case GpmcFCLKDivider = 1: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise – Case GpmcFCLKDivider = 2: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3) – I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3) (10) J = GPMC_FCLK(17) (11) First transfer only for CLK DIV 1 mode. (12) Half cycle; for all data after initial transfer for CLK DIV 1 mode. (13) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK. (14) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. (15) P = GPMC_CLK period in ns (16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) (17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider. (19) The jitter probability density can be approximated by a Gaussian function.

ADVANCE□INFORMATION GPMC_CLK GPMC_CSn[x] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[x] Valid Address D 0 F12 F13 F11 F19 F18 F20 F10 F19 F12 F12 GPMC_01 156 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated (20) For div_by_1_mode: – GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency For GPMC_FCLK_MUX_100: – gpmc_fclk_sel[1:0] = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz For TIMEPARAGRANULARITY_X1: – GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS) For no extra_delay: – GPMC_CONFIG2_i Register : CSEXTRADELAY = 0h = CS i Timing control signal is not delayed – GPMC_CONFIG4_i Register : WEEXTRADELAY = 0h = nWE timing control signal is not delayed – GPMC_CONFIG4_i Register : OEEXTRADELAY = 0h = nOE timing control signal is not delayed – GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. B. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-32. GPMC and NOR Flash— Synchronous Single Read— (GpmcFCLKDivider = 0)

ADVANCE□INFORMATION GPMC_CLK GPMC_CSn[x] GPMCA[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[x] Valid Address D 0 D 1 D 2 F12 F13 F13 F12 F8 F8 F9 F10 F11 F21 F22 D 3 GPMC_02 157 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. B. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-33. GPMC and NOR Flash— Synchronous Burst Read— 4x16-bit (GpmcFCLKDivider = 0)

ADVANCE□INFORMATION GPMC_CLK GPMC_CSn[x] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_WEn GPMC_AD[15:0] GPMC_WAIT[x] D 0 D 1 D 2 D 3 F15 F15 F15 F8F8 F14F14 F17 F17 F17 F9F6 F17 F17 F17 Valid Address GPMC_03 158 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. B. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-34. GPMC and NOR Flash— Synchronous Burst Write— (GpmcFCLKDivider > 0)

ADVANCE□INFORMATION GPMC_CLK GPMC_CSn[x] GMPC_BE0n_CLE GPMC_BE1n GPMC_A[27:17] GPMC_AD[15:0] GPMC_ADVn_ALE GPMC_OEn_REn GPMC_WAIT[x] Valid Valid Address (MSB) Address (LSB) D0 D1 D2 D3 F8 F8 F10 F13 F12 F12 F11 F0 F1 F6 F7 GPMC_04 159 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. B. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-35. GPMC and Multiplexed NOR Flash— Synchronous Burst Read

ADVANCE□INFORMATION GPMC_CLK GPMC_CSn[x] GPMC_A[27:17] GPMC_BE1n BPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_WEn GPMC_WAIT[x] Address (LSB) D 0 D 1 D 2 D 3 F15 F15 F15 F8F8 F17 F17 F17 F6 F17 F17 F17 F18 F20 F14 F22 F21 Address (MSB) GPMC_AD[15:0] F14 GPMC_05 160 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. B. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-36. GPMC and Multiplexed NOR Flash— Synchronous Burst Write

5.11.5.4.2 GPMC and NOR Flash— Asynchronous Mode

Table 5-39 and Table 5-40 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-37 through Figure 5-42). Table 5-39. GPMC and NOR Flash Timing Requirements— Asynchronous Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT FA5(1) tacc(d) Data access time div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 H (5) ns FA20(2) tacc1-pgmode(d) Page mode successive data access time div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 P (4) ns FA21(1) tacc2-pgmode(d) Page mode first data access time div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 H (5) ns (1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field. (2) The FA20 prameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field. (3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by active functional clock edge. FA21 value must be stored inside the AccessTime register bit field. (4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6) (5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)

ADVANCE□INFORMATION 161 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated (6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (7) For div_by_1_mode: – GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency For GPMC_FCLK_MUX_133: – gpmc_fclk_sel[1:0] = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz For TIMEPARAGRANULARITY_X1: – GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS) Table 5-40. GPMC and NOR Flash Switching Characteristics— Asynchronous Mode NO. PARAMETER DESCRIPTION MODE(15) MIN MAX UNIT tR(d) Rise time, output data GPMC_AD[15:0] div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 2 ns tF(d) Fall time, output data GPMC_AD[15:0] div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 2 ns FA0 tw(be[x]nV) Pulse duration, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid time Read N (12) ns Write N (12) FA1 tw(csnV) Pulse duration, output chip select GPMC_CSnx low Read A (1) ns Write A (1) FA3 td(csnV-advnIV) Delay time, output chip select GPMC_CSnx valid to output address valid and address latch enable GPMC_ADVn_ALE invalid Read -2+B (2) 2+B (2) ns Write -2+B (2) 2+B (2) FA4 td(csnV-oenIV) Delay time, output chip select GPMC_CSnx valid to output enable GPMC_OEn_REn invalid (Single read) div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 FA9 td(aV-csnV) Delay time, output address GPMC_A[27:1] valid to output chip select GPMC_CSnx valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 FA10 td(be[x]nV-csnV) Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid to output chip select GPMC_CSnx valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 FA12 td(csnV-advnV) Delay time, output chip select GPMC_CSnx valid to output address valid and address latch enable GPMC_ADVn_ALE valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 FA13 td(csnV-oenV) Delay time, output chip select GPMC_CSnx valid to output enable GPMC_OEn_REn valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 FA16 tw(aIV) Pulse duration output address GPMC_A[26:1] invalid between 2 successive read and write accesses div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 G (7) ns FA18 td(csnV-oenIV) Delay time, output chip select GPMC_CSnx valid to output enable GPMC_OEn_REn invalid (Burst read) div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 FA20 tw(aV) Pulse duration, output address GPMC_A[27:1] valid - 2nd, 3rd, and 4th accesses div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 D (4) ns FA25 td(csnV-wenV) Delay time, output chip select GPMC_CSnx valid to output write enable GPMC_WEn valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 FA27 td(csnV-wenIV) Delay time, output chip select GPMC_CSnx valid to output write enable GPMC_WEn invalid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1

ADVANCE□INFORMATION 162 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-40. GPMC and NOR Flash Switching Characteristics— Asynchronous Mode (continued) NO. PARAMETER DESCRIPTION MODE(15) MIN MAX UNIT FA28 td(wenV-dV) Delay time, output write enable GPMC_WEn valid to output data GPMC_AD[15:0] valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 2.8 ns FA29 td(dV-csnV) Delay time, output data GPMC_AD[15:0] valid to output chip select GPMC_CSnx valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 FA37 td(oenV-aIV) Delay time, output enable GPMC_OEn_REn valid to output address GPMC_AD[15:0] phase end div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 2.8 ns (1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) with n being the page burst access number (2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14) (5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (7) G = Cycle2CycleDelay × GPMC_FCLK(14) (8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14) (10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14) For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) (13) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. (14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (15) For div_by_1_mode: – GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency For GPMC_FCLK_MUX_133: – gpmc_fclk_sel[1:0] = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz For TIMEPARAGRANULARITY_X1: – GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)

ADVANCE□INFORMATION GPMC_FCLK GPMC_CLK GPMC_CSn[x] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[x] Valid Address Valid Valid Data IN 0 Data IN 0 FA0 FA9 FA10 FA3 FA1 FA4 FA12 FA13 FA0 FA10 FA5 GPMC_06 163 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 5-37. GPMC and NOR Flash— Asynchronous Read— Single Word

ADVANCE□INFORMATION GPMC_FCLK GPMC_CLK GPMC_CSn[x] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADCn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[x] Address 0 Address 1 Valid Valid Valid Valid Data Upper FA9 FA10 FA3 FA9 FA3 FA13 FA13 FA1 FA1 FA4 FA4 FA12 FA12 FA10 FA0 FA0 FA16 FA0 FA0 FA10 FA10 FA5 FA5 GPMC_07 164 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 5-38. GPMC and NOR Flash— Asynchronous Read— 32-Bit

ADVANCE□INFORMATION GPMC_FCLK GPMC_CLK GPMC_CSn[x] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[x] Add0 Add1 Add2 Add3 Add4 D0 D1 D2 D3 D3 FA1 FA0 FA18 FA13 FA12 FA0 FA9 FA10 FA10 FA21 FA20 FA20FA20 GPMC_08 165 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field. C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input page data). FA20 value must be stored in PageBurstAccessTime register bits field. D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 5-39. GPMC and NOR Flash— Asynchronous Read— Page Mode 4x16-Bit

ADVANCE□INFORMATION GPMC_FCLK GPMC_CLK GPMC_CSn[x] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_WEn GPMC_AD[15:0] GPMC_WAIT[x] Valid Address Data OUT FA0 FA1 FA10 FA3 FA25 FA29 FA9 FA12 FA27 FA0 FA10 GPMC_09 166 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-40. GPMC and NOR Flash— Asynchronous Write— Single Word

ADVANCE□INFORMATION GPMC_FCLK GPMC_CLK GPMC_CSn[x] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_WAIT[x] Address (MSB) Valid Valid Address (LSB) Data IN Data IN FA0 FA9 FA10 FA3 FA13 FA29 FA1 FA37 FA12 FA4 FA10 FA0 FA5 GPMC_A[27:17] GPMC_AD[15:0] GPMC_10 167 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 5-41. GPMC and Multiplexed NOR Flash— Asynchronous Read— Single Word

ADVANCE□INFORMATION GPMC_FCLK GPMC_CLK GPMC_CSn[x] GPMC_A[27:17] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_WEn GPMC_AD[15:0] GPMC_WAIT[x] Address (MSB) Valid Address (LSB) Data OUT FA0 FA1 FA9 FA10 FA3 FA25 FA29 FA12 FA27 FA28 FA0 FA10 GPMC_11 168 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-42. GPMC and Multiplexed NOR Flash— Asynchronous Write— Single Word

ADVANCE□INFORMATION 169 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated

5.11.5.4.3 GPMC and NAND Flash— Asynchronous Mode

Table 5-41 and Table 5-42 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-43 through Figure 5-46). Table 5-41. GPMC and NAND Flash Timing Requirements— Asynchronous Mode NO. PARAMETER DESCRIPTION MODE(4) MIN MAX UNIT GNF12(1) tacc(d) Access time, input data GPMC_AD[15:0] (3) div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 J (2) ns (1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field. (2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3) (3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (4) For div_by_1_mode: – GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency For GPMC_FCLK_MUX_133: – gpmc_fclk_sel[1:0] = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz For TIMEPARAGRANULARITY_X1: – GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS) Table 5-42. GPMC and NAND Flash Switching Characteristics— Asynchronous Mode NO. PARAMETER MODE(15) MIN MAX UNIT tR(d) Rise time, output data GPMC_AD[15:0] div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 2 ns tF(d) Fall time, output data GPMC_AD[15:0] div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 2 ns GNF0 tw(wenV) Pulse duration, output write enable GPMC_WEn valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 A(1) ns GNF1 td(csnV-wenV) Delay time, output chip select GPMC_CSnx valid to output write enable GPMC_WEn valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 GNF2 tw(cleH-wenV) Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE high to output write enable GPMC_WEn valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 GNF3 tw(wenV-dV) Delay time, output data GPMC_AD[15:0] valid to output write enable GPMC_WEn valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 GNF4 tw(wenIV-dIV) Delay time, output write enable GPMC_WEn invalid to output data GPMC_AD[15:0] invalid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 GNF5 tw(wenIV-cleIV) Delay time, output write enable GPMC_WEn invalid to output lower-byte enable and command latch enable GPMC_BE0n_CLE invalid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 GNF6 tw(wenIV-csnIV) Delay time, output write enable GPMC_WEn invalid to output chip select GPMC_CSnx invalid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 GNF7 tw(aleH-wenV) Delay time, output address valid and address latch enable GPMC_ADVn_ALE high to output write enable GPMC_WEn valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1

ADVANCE□INFORMATION 170 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-42. GPMC and NAND Flash Switching Characteristics— Asynchronous Mode (continued) NO. PARAMETER MODE(15) MIN MAX UNIT GNF8 tw(wenIV-aleIV) Delay time, output write enable GPMC_WEn invalid to output address valid and address latch enable GPMC_ADVn_ALE invalid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 GNF9 tc(wen) Cycle time, write div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 H (8) ns GNF1 td(csnV-oenV) Delay time, output chip select GPMC_CSnx valid to output enable GPMC_OEn_REn valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 GNF1 tw(oenV) Pulse duration, output enable GPMC_OEn_REn valid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 K (10) ns GNF1 tc(oen) Cycle time, read div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 L (11) ns GNF1 tw(oenIV-csnIV) Delay time, output enable GPMC_OEn_REn invalid to output chip select GPMC_CSnx invalid div_by_1_mode; GPMC_FCLK_MUX_133; TIMEPARAGRANULARITY_X1 (1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) (2) B = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (3) C = ((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay)) × GPMC_FCLK(14) (4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14) (5) E = ((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK(14) (6) F = ((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay)) × GPMC_FCLK(14) (7) G = ((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay)) × GPMC_FCLK(14) (8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14) (9) I = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (10) K = (OEOffTime - OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14) (11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14) (12) M = ((CSRdOffTime - OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - OEExtraDelay)) × GPMC_FCLK(14) (13) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. (14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (15) For div_by_1_mode: – GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency For GPMC_FCLK_MUX_133: – gpmc_fclk_sel[1:0] = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz For TIMEPARAGRANULARITY_X1: – GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)

ADVANCE□INFORMATION GPMC_FCLK GPMC_CSn[x] GPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_OEn_REn GPMC_WEn DA T A GNF0 GNF1 GNF4 GNF9 GNF3 GNF6 GPMC_AD[15:0] GPMC_15 GPMC_CSn[x] GPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_OEn_REn GPMC_FCLK GPMC_WAIT[x] GNF10 GNF14 GNF15 GNF12 GNF13 DA T AGPMC_AD[15:0] GPMC_14 172 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated (1) GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional clock edge. GNF12 value must be stored inside AccessTime register bits field. (2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. (3) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1. Figure 5-45. GPMC and NAND Flash— Data Read Cycle (1) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. Figure 5-46. GPMC and NAND Flash— Data Write Cycle For more information, see section General-Purpose Memory Controller (GPMC) in chapter Memory Interface of the device TRM.

5.11.5.5 HYPERBUS

For more details about features and additional description information on the device Hyperbus, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-43, Table 5-44, and Table 5-45 assume testing over the recommended operating conditions and electrical characteristic conditions (see Figure 5-47, Figure 5-48, and Figure 5-49).

ADVANCE□INFORMATION HYPERBUS_TIMING_01 CK, CK# CS# D8/LFD8 D2 RWDS DQ[7:0] D9/LFD9 Command-Address Host drives DQ[7:0] and Memory drives RWDS CK and Data are center aligned Host drives DQ[7:0] and RWDS 39:32 31:24 23:16 15:8 7:047:40 Dn Dn Dn+1 Dn+1 A B A B D7/LFD7 D6/LFD6 D11/LFD11 D10/LFD10 D12/LFD12 D12/LFD12 173 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-43. Timing Requirements for HyperBus Initialization NO. PARAMETER DESCRIPTION MIN MAX UNIT D1 tw(RESETn) RESETn Pulse Width 200 ns D2 tw(csL) Chip Select Pulse Width 1000 ns D3 td(RESETnH-csL) Delay time, RESETn inactive to CSn active 200.34 ns D4 td(csL-RWDSL) Delay time, CSn active to RWDS falling 115 ns Table 5-44. HyperBus 166 MHz Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT D5 tskn(rwdsX-dV) Input skew, RWDS transitioning to D0:D7 valid -0.46 0.46 ns D6 tc(clk/clkn) CLK period, CLK/CLKn 6 ns D7 tw(clk/clkn) Pulse width, CLK/CLKn 2.7 ns D8 tw(csIV) Pulse width, CS0 invalid between operations 6 ns D9 td(clkH-csL) Delay time, CS0 active to CLK rising/ CLKn falling -3.41 ns D10 td(clkL[LE]-csH) Delay time, last falling CLK/ rising CLKn edge to CS0 inactive 0.66 ns D11 td(clkX-rwdsV) Delay time, CLK transition to RWDS valid 1.01 2.02 ns D12 td(clkX-d[0:7]V) Delay time, CLK transitioning to D0:7 valid 0.84 2.2 ns Table 5-45. HyperBus 100 MHz Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT LFD5 tskn(rwdsX-dV) Input skew, RWDS transitioning to D0:D7 valid -0.81 0.81 ns LFD6 tc(clk) CLK period, CLK 10 ns LFD7 tw(clk) Pulse width, CLK 4.5 ns LFD8 tw(csIV) Pulse width, CS0 invalid between operations 10 ns LFD9 td(clkH-csL) Delay time, CS0 active to CLK rising -3.76 ns LFD10 td(clkL[LE]-csH) Delay time, last falling CLK edge to CS0 inactive 1.77 ns LFD11 td(clkX-rwdsV) Delay time, CLK transition to RWDS valid 2.05 3.24 ns LFD12 td(clkX-d[0:7]V) Delay time, CLK transitioning to D0:7 valid 1.87 3.41 ns Figure 5-47. HyperBus Timing Diagrams - Transmitter Mode

ADVANCE□INFORMATION CS# RESET# HYPERBUS_TIMING_03 HYPERBUS_TIMING_02 RWDS DQ[7:0] Command-Address Host drives DQ[7:0] and Memory drives RWDS CK and Data are center aligned Host drives DQ[7:0] and RWDS 39:32 31:24 23:16 15:8 7:047:40 Dn Dn Dn+1 Dn+1 A B A B CK, CK# CS# D8/LFD8 D2 D9/LFD9 D7/LFD7 D6/LFD6 D10/LFD10 D12/LFD12 D5/LFD5 D5/LFD5 174 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-48. HyperBus Timing Diagrams - Receiver Mode Figure 5-49. HyperBus Timing Diagrams - Reset For more information, see section Hyperbus Interface in chapter Memory Interfaces of the Device TRM.

5.11.5.6 I2C

For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-46 and Figure 5-50 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-46. Timing Requirements for I2C Input Timings(1)(6) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT I1 tc(SCL) Cycle time, SCL Standard 10000 ns Fast 2500 ns I2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) Standard 4700 ns Fast 600 ns I3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) Standard 4000 ns Fast 900 ns I4 tw(SCLL) Pulse duration, SCL low Standard 4700 ns Fast 1300 ns I5 tw(SCLH) Pulse duration, SCL high Standard 4000 ns Fast 600 ns I6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high Standard 250 ns Fast 100(2) ns I7 th(SCLL-SDAV) Hold time, SDA valid after SCL low Standard 0(3) 3450(4) ns Fast 0(3) 900(4) ns

ADVANCE□INFORMATION I10 I12 I6 I14 I13 Stop Start Repeated Start Stop I2Cx_SDA I2Cx_SCL I1 1 I9 175 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-46. Timing Requirements for I2C Input Timings(1)(6) (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT I8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions Standard 4700 ns Fast 1300 ns I9 tr(SDA) Rise time, SDA Standard 1000 ns Fast 20+.1Cb(5) (7) 300(3) (7) ns I10 tr(SCL) Rise time, SCL Standard 1000 ns Fast 20+.1Cb(5) (7) 300(3) (7) ns I11 tf(SDA) Fall time, SDA Standard 300 ns Fast 20+.1Cb(5) (7) 300(3) (7) ns I12 tf(SCL) Fall time, SCL Standard 300 ns Fast 20+.1Cb 300 ns I13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) Standard 4000 ns Fast 600 ns I14 tw(SP) Pulse duration, spike (must be supressed) Standard ns Fast 0 50 ns I15 tskew Skew Standard 1 ns Fast 1 ns I16 Cb Capacitive load for each bus line Standard 400 pF Fast 400 pF (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the devive is powered down. (2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed (6) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details. (7) These timings apply only to MCU_I2C0 and WKUP_I2C0. MAIN_I2C[0:3] use standard LVCMOS buffers to emulate open-drain buffers and their rise/fall times should be referenced in the device IBIS model. Figure 5-50. I2C Receive Timing(1) (1) x in I2Cx_SDA and I2Cx_SCL is 0, 1 or 2.

ADVANCE□INFORMATION 176 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated and Figure 5-51 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-47. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT I16 tc(SCL) Cycle time, SCL Standard 10000 ns Fast 2500 ns I17 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) Standard 4700 ns Fast 600 ns I18 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) Standard 4000 ns Fast 900 ns I19 tw(SCLL) Pulse duration, SCL low Standard 4700 ns Fast 1300 ns I20 tw(SCLH) Pulse duration, SCL high Standard 4000 ns Fast 600 ns I21 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high Standard 250 ns Fast 100 (2) ns I22 th(SCLL-SDAV) Hold time, SDA valid after SCL low Standard 0 (3) 3450 (4) ns Fast 0 (3) 900 (4) ns I23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions Standard 4700 ns Fast 1300 ns I24 tr(SDA) Rise time, SDA Standard 1000 ns Fast 20+.1Cb (5) (7) 300 (3) (7) ns I25 tr(SCL) Rise time, SCL Standard 1000 ns Fast 20+.1Cb (5) (7) 300 (3) (7) ns I26 tf(SDA) Fall time, SDA Standard 300 ns Fast 20+.1Cb (5) (7) 300 (3) (7) ns I27 tf(SCL) Fall time, SCL Standard 300 ns Fast 20+.1Cb (5) (7) 300 (3) (7) ns I28 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) Standard 4000 ns Fast 600 ns I29 tskew Skew Standard 3 ns Fast 20 ns I30 Cb Capacitive load for each bus line Standard 400 pF Fast 400 pF (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the devive is powered down. (2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. (6) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details. (7) These timings apply only to MCU_I2C0 and WKUP_I2C0. MAIN_I2C[0:3] use standard LVCMOS buffers to emulate open-drain buffers and their rise/fall times should be referenced in the device IBIS model.

ADVANCE□INFORMATION I25 I23 I19 I18 I22 I27 I20 I21 I17 I18 I28 Stop Start Repeated Start Stop I2C[x]_SDA I2C[x]_SCL I16 I26 I24 177 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated NOTE I2C emulation is achieved by configuring the LVCMOS buffers to output HiZ instead of driving high when transmitting logic-1. Figure 5-51. I2C Transmit Timing(1) (1) x in I2Cx_SDA and I2Cx_SCL is 0, 1 or 2. For more information, see section Inter-Integrated Circuit (I2C) Interface in chapter Peripherals of the device TRM.

5.11.5.7 MCAN

For more details about features and additional description information on the device Controller Area Network Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-48 presents timing parameters for MCANi Interface. Table 5-48. MCAN Register to Pin Timings NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT M1 tp(MCANi_TX) Delay Time Max, Transmit Shift Register to MCANi_TX pin Normal 10 ns M2 tp(MCANi_RX) Delay Time Max, MCANi_RX pin to receive shift register Normal 10 ns (1) i in MCANi_* = 0 or 1. For more information, see section Controller Area Network (MCAN) in chapter Peripherals of the device TRM.

5.11.5.8 MCASP

For more details about features and additional description information on the device Multichannel Audio Serial Port, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-49, and Figure 5-52 present timing requirements for MCASP0 to MCASP2. Table 5-49. Timing Requirements for MCASP(1) NO. PARAMETER DESCRIPTION Mode MIN MAX UNIT ASP1 tc(AHCLKRX) Cycle time, AHCLKR/X 20 ns ASP2 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 0.5P - 2.5 (2) ns

ADVANCE□INFORMATION 178 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-49. Timing Requirements for MCASP(1) (continued) NO. PARAMETER DESCRIPTION Mode MIN MAX UNIT ASP3 tc(ACLKRX) Cycle time, ACLKR/X 20 ns ASP4 tw(ACLKRX) Pulse duration, ACLKR/X high or low 0.5R - 2.5 (3) ns ASP5 tsu(AFSRX- ACLKRX) Setup time, AFSR/X input valid before ACLKR/X ACLKR/X int 12.3 ns ACLKR/X ext in/out 4 ASP6 th(ACLKRX-AFSRX) Hold time, AFSR/X input valid after ACLKR/X ACLKR/X int -1 ns ACLKR/X ext in/out 1.6 ASP7 tsu(AXR-ACLKRX) Setup time, AXR input valid before ACLKR/X ACLKR/X int 12.3 ns ACLKR/X ext in/out 4 ASP8 th(ACLKRX-AXR) Hold time, AXR input valid after ACLKR/X ACLKR/X int -1 ns ACLKR/X ext in/out 1.6 (1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 (2) P = AHCLKR/X period in ns. (3) R = ACLKR/X period in ns.

ADVANCE□INFORMATION ASP8 ASP7 ASP4 ASP4ASP3 ASP2 ASP2ASP1 A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 MCASP[x]_ACLKR/X (Falling Edge Polarity) MCASP[x]_AHCLKR/X (Rising Edge Polarity) MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay) MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay) MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay) MCASP[x]_AXR[x] (Data In/Receive) ASP6 ASP5 MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0) (A) MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1) (B) 179 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated A. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured for falling edge (to shift data in). B. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured for rising edge (to shift data in). Figure 5-52. MCASP Input Timing (1) x in MCASP[x]_* is 0, 1 or 2

ADVANCE□INFORMATION 180 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-50 and Figure 5-53 present switching characteristics over recommended operating conditions for MCASP0 to MCASP2. Table 5-50. Switching Characteristics Over Recommended Operating Conditions for MCASP(1) NO. PARAMETER DESCRIPTION Mode MIN MAX UNIT ASP9 tc(AHCLKRX) Cycle time, AHCLKR/X 20 ns ASP10 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 0.5P - 2.5 (2) ns ASP11 tc(ACLKRX) Cycle time, ACLKR/X 20 ns ASP12 tw(ACLKRX) Pulse duration, ACLKR/X high or low 0.5R - 2.5 (3) ns ASP13 td(ACLKRX-AFSRX) Delay time, ACLKR/X transmit edge to AFSR/X output valid ACLKR/X int 0 6.5 ns ACLKR/X ext in/out 2 14 ASP14 td(ACLKX-AXR) Delay time, ACLKX transmit edge to AXR output valid ACLKR/X int 0 6.5 ns ACLKR/X ext in/out 2 14 ASP15 tdis(ACLKX-AXR) Disable time, ACLKX transmit edge to AXR output high impedance ACLKR/X int 0 6.5 ns ACLKR/X ext in/out 2 14 (1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 (2) P = AHCLKR/X period in ns. (3) R = ACLKR/X period in ns.

ADVANCE□INFORMATION ASP15 ASP14 ASP13 ASP13 ASP12 ASP12ASP11 ASP10 ASP10 ASP9 A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 ASP13 ASP13 ASP13 ASP13ASP13 MCASP[x]_ACLKR/X (Falling Edge Polarity) MCASP[x]_AHCLKR/X (Rising Edge Polarity) MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay) MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay) MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay) MCASP[x]_AXR[x] (Data Out/Transmit) MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1) (A) MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0) (B) 181 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated A. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured for rising edge (to shift data in). B. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured for falling edge (to shift data in). Figure 5-53. MCASP Output Timing (1) x in MCASP[x]_* is 0, 1 or 2 For more information, see section Multichannel Audio Serial Port (MCASP) in chapter Peripherals of the device TRM.

5.11.5.9 MCSPI

For more details about features and additional description information on the device Serial Port Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. For more information, see section Multichannel Serial Peripheral Interface (MCSPI) in chapter Peripherals of the device TRM.

5.11.5.9.1 SPI— Master Mode

Table 5-51, Figure 5-54 and Figure 5-55 present Timing Requirements for SPI - Master Mode.

ADVANCE□INFORMATION 182 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-51. Timing Requirements for SPI - Master Mode (1) (8) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SM1 tc(SPICLK) Cycle time, SPI_CLK (1) (2) 20.8(3) ns SM2 tw(SPICLKL) Typical Pulse duration, SPI_CLK low (1) -1 + 0.5P (4) ns SM3 tw(SPICLKH) Typical Pulse duration, SPI_CLK high (1) -1 + 0.5P (4) ns SM4 tsu(MISO-SPICLK) Setup time, SPI_D[x] valid before SPI_CLK active edge (1) 2 ns SM5 th(SPICLK-MISO) Hold time, SPI_D[x] valid after SPI_CLK active edge (1) 3 ns SM6 td(SPICLK-SIMO) Delay time, SPI_CLK active edge to SPI_D[x] transition (1) -3 2 ns SM7 tsk(CS-SIMO) Delay time, SPI_CS[x] active to SPI_D[x] transition 5 ns SM8 td(SPICLK-CS) Delay time, SPI_CS[x] active to SPI_CLK first edge Master_PHA0_POL0; Master_PHA0_POL1;( -4 + B (6) ns Master_PHA1_POL0; Master_PHA1_POL1;( -4 + A (7) ns SM9 td(SPICLK-CS) Delay time, SPI_CLK last edge to SPI_CS[x] inactive Master_PHA0_POL0; Master_PHA0_POL1;( -4 + A (7) ns Master_PHA1_POL0; Master_PHA1_POL1; (5) -4 + B (6) ns (1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are being used to drive output data and capture input data (2) Related to the SPI_CLK maximum frequency (3) 20 ns cycle time = 50 MHz (4) P = SPICLK period (5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register (6) B = (TCS + .5) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2. (7) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. (8) The IO timings provided in this section are applicable for all combinations of signals for SPI1 and SPI2. However, the timings are only valid for SPI3 and SPI4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.

ADVANCE□INFORMATION SPI_CS[x] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (IN) SPI_CS[x] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 PHA=1 EPOL=1 POL=0 POL=1 POL=0 POL=1 SM8 SM9 SM3 SM1 SM2 SM1 SM8 SM9SM3 SM1 SM2 SM1 SM2 SM3 SM2 SM3 SM4 SM5 SM4 SM5 SM4 SM4 SM5 SM5 SPRSP08_TIMING_McSPI_02 183 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Figure 5-54. SPI Master Mode Receive Timing

ADVANCE□INFORMATION SPI_CS[x] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (OUT) SPI_CS[x] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit0 PHA=0 EPOL=1 POL=0 POL=1 PHA=1 EPOL=1 POL=0 POL=1 SM8 SM9 SM6 SM3 SM1 SM2 SM1 SM8 SM9SM3 SM1 SM2 SM1 SM6 SM7 SM6 SM2 SM3 SM2 SM3 SM6 SM6 SM6 SPRSP08_TIMING_McSPI_01 184 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-55. SPI Master Mode Transmit Timing

5.11.5.9.2 MCSPI— Slave Mode

Table 5-52, Figure 5-56, and Figure 5-57 present Timing Requirements for SPI - Slave Mode. Table 5-52. Timing Requirements for SPI - Slave Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SS1 tc(SPICLK) Cycle time, SPI_CLK 20.8 ns SS2 tw(SPICLKL) Typical Pulse duration, SPI_CLK low 0.45P(2) ns SS3 tw(SPICLKH) Typical Pulse duration, SPI_CLK high 0.45P(2) ns SS4 tsu(SIMO-SPICLK) Setup time, SPI_D[x] valid before SPI_CLK active edge 5 ns SS5 th(SPICLK-SIMO) Hold time, SPI_D[x] valid after SPI_CLK active edge 5 ns SS6 td(SPICLK-SOMI) Delay time, SPI_CLK active edge to mcspi_somi transition 2 5 ns SS7 tsk(CS-SOMI) Delay time, SPI_CS[x] active edge to mcspi_somi transition 20.95 ns SS8 tsu(CS-SPICLK) Setup time, SPI_CS[x] valid before SPI_CLK first edge 5 ns SS9 th(SPICLK-CS) Hold time, SPI_CS[x] valid after SPI_CLK last edge 5 ns

ADVANCE□INFORMATION SPI_CS[x] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (IN) SPI_CS[x] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 POL=0 POL=1 POL=0 POL=1 PHA=1 EPOL=1 SS3 SS1 SS3 SS1 SS3 SS1 SS2 SS1 SS8 SS9 SS8 SS9 SS2 SS3 SS2 SS2 SS4 SS5 SS5 SS4 SS4 SS5 SS4 SS5 SPRSP08_TIMING_McSPI_04 185 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated (1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data. (2) P = SPICLK period. (3) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register. Figure 5-56. SPI Slave Mode Receive Timing

ADVANCE□INFORMATION SPI_CS[x] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (OUT) SPI_CS[x] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 POL=0 POL=1 POL=0 POL=1 PHA=1 EPOL=1 SS6 SS3 SS1 SS3 SS1 SS3 SS1 SS2 SS1 SS6 SS6 SS8 SS9 SS7 SS8 SS2 SS3 SS2 SS2 SS6 SS6SS6 SS9 SPRSP08_TIMING_McSPI_03 186 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-57. SPI Slave Mode Transmit Timing

5.11.5.10 MMC/SD

For more details about features and additional description information on the device Multi Media Card, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. NOTE The MMCSDi (i = 0 to 1) controller is also referred to as MMCi.

5.11.5.10.1 MMC0 - eMMC Optimized Interface

MMC0 interface supports the following eMMC applications:

Standard JC64 SDR, 8-bit data
High-speed JC64 SDR, 8-bit data
High-speed JC64 DDR, 8-bit data
High-speed HS200 JEDS84 SDR, 8-bit data

ADVANCE□INFORMATION MMC0_CLK MMC0_CMD MMC0_DA T[7:0] SSDR2L SSDR2H SSDR1 SSDR6 SSDR5 SSDR8 SSDR7 SPRSP08_MMC0_01 187 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated NOTE For more information, see the Multimedia Card/Secure Digital (MMC/SD) Interface chapter of the Device TRM. Table 5-53 and Table 5-54 present Timing requirements and Switching characteristics for MMC0 - JC64 Standard SDR in Receiver and Transmitter mode (see Figure 5-58 and Figure 5-59). Table 5-53. Timing Requirements for MMC0 - JC64 Standard SDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SSDR5 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising clock edge Positive-edge Reference Clock 9.96 ns SSDR6 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising clock edge Positive-edge Reference Clock 8.47 ns SSDR7 tsu(dV-clkH) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising clock edge Positive-edge Reference Clock 9.96 ns SSDR8 th(clkH-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising clock edge Positive-edge Reference Clock 8.47 ns Figure 5-58. MMC0 SD Card Interface - JC64 Standard SDR Receiver Mode Table 5-54. Switching Characteristics for MMC0 - JC64 Standard SDR Mode (1) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SSDR1 fop(clk) Operating frequency, MMC0_CLK Positive-edge Reference Clock

24 MHz

SSDR2H tw(clkH) Pulse duration, MMC0_CLK high Positive-edge Reference Clock 0.5*P - 1.043 (1) ns SSDR2L tw(clkL) Pulse duration, MMC0_CLK low Negative-edge Reference Clock 0.5*P - 1.043 (1) ns SSDR3 td(clkL-cmdV) Delay time, MMC0_CLK falling clock edge to MMC0_CMD transition Negative-edge Reference Clock -16.39 16.39 ns SSDR4 td(clkL-dV) Delay time, MMC0_CLK falling clock edge to MMC0_DAT[7:0] transition Negative-edge Reference Clock -16.39 16.39 ns

ADVANCE□INFORMATION MMC0_CLK MMC0_CMD MMC0_DA T[7:0] JC641 JC642L JC643 JC644 JC647 JC648 mmc0_03 JC642H SSDR2L MMC0_CLK MMC0_CMD MMC0_DA T[7:0] SSDR1 SSDR2H SSDR3 SSDR4 SPRSP08_MMC0_02 188 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated (1) P = output MMC0_CLK period in ns Figure 5-59. MMC0 SD Card Interface - JC64 Standard SDR Transmitter Mode Table 5-55 and Table 5-56 present Timing requirements and Switching characteristics for MMC0 - JC64 High speed SDR in receiver and transmitter mode (see Figure 5-60 and Figure 5-61). Table 5-55. Timing Requirements for MMC0 - JC64 High Speed SDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT JC643 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising clock edge Positive-edge Reference Clock 3.26 ns JC644 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising clock edge Positive-edge Reference Clock 2.67 ns JC647 tsu(dV-clkH) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising clock edge Positive-edge Reference Clock 3.26 ns JC648 th(clkH-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising clock edge Positive-edge Reference Clock 2.67 ns Figure 5-60. MMC0 SD Card Interface - JC64 High Speed SDR Receiver Mode Table 5-56. Switching Characteristics for MMC0 - JC64 High Speed SDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT JC641 fop(clk) Operating frequency, MMC0_CLK Positive-edge Reference Clock

48 MHz

JC642H tw(clkH) Pulse duration, MMC0_CLK high Positive-edge Reference Clock 0.5*P - 0.82 (1) ns JC642L tw(clkL) Pulse duration, MMC0_CLK low Negative-edge Reference Clock 0.5*P - 0.82 (1) ns JC645 td(clkL-cmdV) Delay time, MMC0_CLK falling clock edge to MMC0_CMD transition Negative-edge Reference Clock -6.5 6.5 ns JC646 td(clkL-dV) Delay time, MMC0_CLK falling clock edge to MMC0_DAT[7:0] transition Negative-edge Reference Clock -6.5 6.5 ns

ADVANCE□INFORMATION MMC0 CLK_ MMC0 CMD_ MMC0 DA T[7:0]_ DDR1 DDR2HDDR2L DDR3 DDR4 DDR7 DDR8 DDR7 DDR8 DDR7 DDR8 DDR7 SPRSP08_MMC0_05 MMC0_CLK MMC0_CMD MMC0_DA T[7:0] JC641 JC642L JC645 JC645 JC646 JC646 mmc0_04 JC642H 189 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated (1) P = output MMC0_CLK period in ns Figure 5-61. MMC0 SD Card Interface - JC64 High Speed SDR Transmitter Mode Table 5-57 and Table 5-58 present Timing requirements and Switching characteristics for MMC0 - JC64 High speed DDR in receiver and transmitter mode (see Figure 5-62 and Figure 5-63). Table 5-57. Timing Requirements for MMC0 - JC64 High Speed DDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DDR3 tsu(cmdV-clk) Setup time, MMC0_CMD valid before MMC0_CLK transition Positive-edge Reference Clock 6.21 ns DDR4 th(clk-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK transition Positive-edge Reference Clock 2.83 ns DDR7 tsu(dV-clk) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition Both-edge Reference Clock 1.16 ns DDR8 th(clk-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition Both-edge Reference Clock 1.67 ns Figure 5-62. MMC0 SD Card Interface - JC64 High Speed DDR Receiver Mode Table 5-58. Switching Characteristics for MMC0 - JC64 High Speed DDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DDR1 fop(clk) Operating frequency, MMC0_CLK Positive-edge Reference Clock DDR2H tw(clkH) Pulse duration, MMC0_CLK high Positive-edge Reference Clock 0.5*P - 0.82 (1) ns DDR2L tw(clkL) Pulse duration, MMC0_CLK low Negative-edge Reference Clock 0.5*P - 0.82 (1) ns DDR5 td(clk-cmdV) Delay time, MMC0_CLK transition to MMC0_CMD transition Negative-edge Reference Clock -6.5 6.5 ns DDR6 td(clk-dV) Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition Both-edge Reference Clock 3.42 7 ns

ADVANCE□INFORMATION MMC0 CLK_ MMC0 CMD_ MMC0 DA T[7:0]_ HS2005 HS2005 HS2006 HS2006 HS2001 HS2002HHS2002L SPRSP08_MMC0_07 MMC0 CLK_ MMC0 CMD_ MMC0 DA T[7:0]_ DDR1 DDR2DDR2 DDR5 DDR5 DDR6 DDR6 DDR6 DDR6 DDR5 DDR5 DDR6 DDR6 SPRSP08_MMC0_06 190 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated (1) P = output MMC0_CLK period in ns Figure 5-63. MMC0 SD Card Interface - JC64 High Speed DDR Transmitter Mode Table 5-59 presents Timing requirements and Switching characteristics for MMC0 - JEDS84 HS200 in receiver and transmitter mode (see Figure 5-64). Table 5-59. Switching Characteristics for MMC0 - JEDS84 HS200 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT HS2001 fop(clk) Operating frequency, MMC0_CLK Positive-edge Reference Clock

192 MHz

HS2002H tw(clkH) Pulse duration, MMC0_CLK high Positive-edge Reference Clock 0.5*P - 0.43 (1) ns HS2002L tw(clkL) Pulse duration, MMC0_CLK low Negative-edge Reference Clock 0.5*P - 0.43 (1) ns HS2005 td(clkL-cmdV) Delay time, MMC0_CLK falling clock edge to MMC0_CMD transition Negative-edge Reference Clock 1.33 3.28 ns HS2006 td(clkL-dV) Delay time, MMC0_CLK falling clock edge to MMC0_DAT[7:0] transition Positive-edge Reference Clock 1.33 3.28 ns (1) P = output MMC0_CLK period in ns Figure 5-64. MMC0 SD Card Interface - JEDS84 HS200 Transmitter Mode

5.11.5.10.2 MMC1— SD Card Interface

MMC1 interface is compliant with the SD Standard v3.01 and it supports the following SD Card applications:

Default speed, SD Card, 4-bit data
High speed, SD Card, 4-bit data
UHS-I SDR12, SD Card, 4-bit data
UHS-I SDR25, SD Card, 4-bit data
UHS-I SDR50, SD Card, 4-bit data

ADVANCE□INFORMATION DSSD2 DSSD1 DSSD0 DSSD6 DSSD5 DSSD8 DSSD7 MMC1_CLK MMC1_CMD MMC1_DA T[3:0] MMC1_01 191 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated

UHS-I SDR104, SD Card, 4-bit data
UHS-I DDR50, SD Card, 4-bit data NOTE For more information, see the Multimedia Card/Secure Digital (MMC/SD) Interface chapter of the Device TRM. Table 5-60 and Table 5-61 present Timing requirements and Switching characteristics for MMC1 - Default Speed in receiver and transmitter mode (see Figure 5-65 and Figure 5-66) Table 5-60. Timing Requirements for MMC1 - SD Card Default Speed Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DSSD5 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 2.44 ns DSSD6 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 0.17 ns DSSD7 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 2.44 ns DSSD8 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 0.17 ns Table 5-61. Switching Characteristics for MMC1 - SD Card Default Speed Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DSSD0 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock

DSSD1 tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 19.49 ns DSSD2 tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 19.49 ns DSSD3 td(clkL-cmdV) Delay time, MMC1_CLK falling clock edge to MMC1_CMD transition Negative-edge Reference Clock -14.39 14.39 ns DSSD4 td(clkL-dV) Delay time, MMC1_CLK falling clock edge to MMC1_DAT[3:0] transition Negative-edge Reference Clock -14.39 14.39 ns (1) P = output MMC1_CLK period in ns Figure 5-65. MMC/SD in - Default Speed - Receiver Mode

ADVANCE□INFORMATION MMC1_CLK MMC1_CMD MMC1_DA T[3:0] HSSD1 HSSD2L HSSD2H HSSD3 HSSD4 HSSD7 HSSD8 MMC1_03 DSSD2 DSSD1 DSSD0 DSSD3 DSSD4 MMC1_CLK MMC1_CMD MMC1_DA T[3:0] MMC1_02 192 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-66. MMC/SD in - Default Speed - Transmitter Mode Table 5-62 and Table 5-63 present Timing requirements and Switching characteristics for MMC1 - High Speed in receiver and transmitter mode (see Figure 5-67 and Figure 5-68). Table 5-62. Timing Requirements for MMC1 - SD Card High Speed Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT HSSD3 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 2.96 ns HSSD4 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 2.67 ns HSSD7 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 2.96 ns HSSD8 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 2.67 ns Table 5-63. Switching Characteristics for MMC1 - SD Card High Speed Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT HSSD1 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock HSSD2H tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 9.6 ns HSSD2L tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 9.6 ns HSSD5 td(clkL-cmdV) Delay time, MMC1_CLK falling clock edge to MMC1_CMD transition Negative-edge Reference Clock -7.5 3.5 ns HSSD6 td(clkL-dV) Delay time, MMC1_CLK falling clock edge to MMC1_DAT[3:0] transition Negative-edge Reference Clock -7.5 3.5 ns (1) P = output MMC1_CLK period in ns Figure 5-67. MMC/SD in - High Speed - Receiver Mode

ADVANCE□INFORMATION SDR122 SDR121 SDR120 SDR126 SDR125 SDR128 SDR127 MMC1_CLK MMC1_CMD MMC1_DA T[3:0] MMC1_05 MMC1_CLK MMC1_CMD MMC1_DA T[3:0] HSSD1 HSSD2LHSSD2H HSSD5 HSSD6 HSSD5 HSSD6 MMC1_04 193 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Figure 5-68. MMC/SD in - High Speed - Transmitter Mode Table 5-64 and Table 5-65 present Timing requirements and Switching characteristics for MMC1 - SDR12 in receiver and transmitter mode (see Figure 5-69 and Figure 5-70). Table 5-64. Timing Requirements for MMC1 - SD Card SDR12 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR125 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 23.28 ns SDR126 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 1.67 ns SDR127 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 23.28 ns SDR128 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 1.67 ns Table 5-65. Switching Characteristics for MMC1 - SD Card SDR12 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR120 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock SDR121 tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 19.49 ns SDR122 tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 19.49 ns SDR123 td(clkL-cmdV) Delay time, MMC1_CLK falling clock edge to MMC1_CMD transition Negative-edge Reference Clock -14.39 14.39 ns SDR124 td(clkL-dV) Delay time, MMC1_CLK falling clock edge to MMC1_DAT[3:0] transition Negative-edge Reference Clock -14.39 14.39 ns (1) P = output MMC1_CLK period in ns Figure 5-69. MMC/SD in - High Speed SDR12 - Receiver Mode

ADVANCE□INFORMATION MMC1_CLK MMC1_CMD MMC1_DA T[3:0] SDR254 SDR258 SDR253 SDR257 SDR251 SDR252HSDR252L MMC1_07 SDR122 SDR121 SDR120 SDR123 SDR124 MMC1_CLK MMC1_CMD MMC1_DA T[3:0] MMC1_06 194 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-70. MMC/SD in - High Speed SDR12 - Transmitter Mode Table 5-66 and Table 5-67 present Timing requirements and Switching characteristics for MMC1 - SDR25 in receiver and transmitter mode (see Figure 5-71 and Figure 5-72). Table 5-66. Timing Requirements for MMC1 - SD Card SDR25 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR253 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 2.96 ns SDR254 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 1.67 ns SDR257 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 2.96 ns SDR258 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 1.67 ns Table 5-67. Switching Characteristics for MMC1 - SD Card SDR25 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR251 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock H tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 9.6 ns SDR252 L tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 9.6 ns SDR255 td(clkL-cmdV) Delay time, MMC1_CLK falling clock edge to MMC1_CMD transition Negative-edge Reference Clock -7.5 3.5 ns SDR256 td(clkL-dV) Delay time, MMC1_CLK falling clock edge to MMC1_DAT[3:0] transition Negative-edge Reference Clock -7.5 3.5 ns (1) P = output MMC1_CLK period in ns Figure 5-71. MMC/SD in - High Speed SDR25 - Receiver Mode

ADVANCE□INFORMATION MMC1_CLK MMC1_CMD MMC1_DA T[3:0] SDR504 SDR508 SDR503 SDR507 SDR501 SDR502HSDR502L MMC1_09 MMC1_CLK MMC1_CMD MMC1_DA T[3:0] SDR251 SDR252LSDR252H HSSDR255 SDR256 SDR255 SDR256 MMC1_08 195 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Figure 5-72. MMC/SD in - High Speed SDR25 - Transmitter Mode Table 5-68 and Table 5-69 present Timing requirements and Switching characteristics for MMC1 - SDR50 in receiver and transmitter mode (see Figure 5-73 and Figure 5-74). Table 5-68. Timing Requirements for MMC1 - SD Card SDR50 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR503 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising clock edge Positive-edge Reference Clock -0.69 ns SDR504 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 1.67 ns SDR507 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising clock edge Positive-edge Reference Clock -0.69 ns SDR508 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 1.67 ns ns Table 5-69. Switching Characteristics for MMC1 - SD Card SDR50 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR501 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock

96 MHz

H tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 4.65 ns SDR502 L tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 4.65 ns SDR505 td(clkL-cmdV) Delay time, MMC1_CLK falling clock edge to MMC1_CMD transition Negative-edge Reference Clock 1.46 6.76 ns SDR506 td(clkL-dV) Delay time, MMC1_CLK falling clock edge to MMC1_DAT[3:0] transition Negative-edge Reference Clock 1.46 6.76 ns (1) P = output MMC1_CLK period in ns Figure 5-73. MMC/SD in - High Speed SDR50 - Receiver Mode

ADVANCE□INFORMATION MMC1_CLK MMC1_CMD MMC1_DA T[3:0] SDR1041 SDR1042LSDR1042H SDR1045 SDR1046 SDR1045 SDR1046 MMC1_12 MMC1_CLK MMC1_CMD MMC1_DA T[3:0] SDR1044 SDR1048 SDR1043 SDR1047 SDR1041 SDR1042HSDR1042L MMC1_1 1 MMC1_CLK MMC1_CMD MMC1_DA T[3:0] SDR501 SDR502LSDR502H SDR505 SDR506 SDR505 SDR506 MMC1_10 196 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-74. MMC/SD in - High Speed SDR50 - Transmitter Mode Table 5-70 presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver and transmitter mode (see Figure 5-75 and Figure 5-76) Table 5-70. Switching Characteristics for MMC1 - SD Card SDR104 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR104 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 2.17 ns SDR104 tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 2.17 ns SDR104 td(clkL-cmdV) Delay time, MMC1_CLK falling clock edge to MMC1_CMD transition Negative-edge Reference Clock 1.33 3.28 ns SDR104 td(clkL-dV) Delay time, MMC1_CLK falling clock edge to MMC1_DAT[3:0] transition Positive-edge Reference Clock 1.33 3.28 ns (1) P = output MMC1_CLK period in ns Figure 5-75. MMC/SD in - High Speed SDR104 - Receiver Mode Figure 5-76. MMC/SD in - High Speed SDR104 - Transmitter Mode

ADVANCE□INFORMATION MMC1 CLK_ MMC1 CMD_ MMC1 DA T_ [3:0] DDR500 DDR501 DDR502 DDR503(max) DDR503(min) DDR504(max) DDR504(min) DDR504(min) DDR504(max) MMC1_14 MMC1 CLK_ MMC1 CMD_ MMC1 DA T_ [3:0] DDR500 DDR501 DDR502 DDR505 DDR506 DDR508 DDR507 DDR507 DDR508 MMC1_13 197 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-71 and Table 5-72 present Timing requirements and Switching characteristics for MMC1 - DDR50 in receiver and transmitter mode (see Figure 5-77 and Figure 5-78). Table 5-71. Timing Requirements for MMC1 - SD Card DDR50 Mode NO. PARAME TER DESCRIPTION MODE MIN MAX UNIT DDR505 tsu(cmdV-clk) Setup time, MMC1_CMD valid before MMC1_CLK transition Positive-edge Reference Clock 6.21 ns DDR506 th(clk-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK transition Positive-edge Reference Clock 1.53 ns DDR507 tsu(dV-clk) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK transition Both-edge Reference Clock -0.45 ns DDR508 th(clk-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK transition Both-edge Reference Clock 1.67 ns Table 5-72. Switching Characteristics for MMC1 - SD Card DDR50 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DDR500 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock DDR501 tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 9.6 ns DDR502 tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 9.6 ns DDR503 td(clk-cmdV) Delay time, MMC1_CLK transition to MMC1_CMD transition Negative-edge Reference Clock 1.72 13.91 ns DDR504 td(clk-dV) Delay time, MMC1_CLK transition to MMC1_DAT[3:0] transition Both-edge Reference Clock 1.72 6.5 ns (1) P = output MMC1_CLK period in ns Figure 5-77. MMC/SD - High Speed SD - DDR - Data/Command Receive Figure 5-78. MMC/SD - High Speed SD - DDR - Data/Command Transmit

ADVANCE□INFORMATION CPTS_RFT_CLK T3 T4 T5 CPTS_HWTSPUSH T1 T2 198 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated

5.11.5.11 NAVSS

Table 5-73, Table 5-74, Figure 5-79, and Figure 5-80 present timing requirement and switching characteristics of the CPTS interface. Table 5-73. Timing Requirements for CPTS Input NO. PARAMETER DESCRIPTION MIN MAX UNIT T1 tw(HWTSPUSHH) HWTSPUSH Pulse duration, high 6 + 12P(1) ns T2 tw(HWTSPUSHL) HWTSPUSH pulse duration, low 6 + 12P(1) ns T3 tc(RFT_CLK) RFT_CLK cycle time 5 8 ns T4 tw(RFT_CLKH) RFT_CLK pulse duration, high 0.45 × tc(RFT_CLK) ns T5 tw(RFT_CLKL) RFT_CLK pulse duration, low 0.45 × tc(RFT_CLK) ns (1) P = functional clock period in ns. Figure 5-79. CPTS Input Timing Table 5-74. Switching Characteristics for CPTS Output NO. PARAMETER DESCRIPTION MIN MAX UNIT T6 tw(TS_COMPH) NAVSS-CPTS TS_COMP, high -6+36P (1) ns T7 tw(TS_COMPL) NAVSS-CPTS TS_COMP, low -6+36P (1) ns T8 tw(TS_COMPH) CPSW-CPTS TS_COMP, high -6+36P (1) ns T9 tw(TS_COMPL) CPSW-CPTS TS_COMP, low -6+36P (1) ns T10 tw(TS_SYNCH) NAVSS-CPTS TS_SYNC, high -6+36P (1) ns T11 tw(TS_SYNCL) NAVSS-CPTS TS_SYNC, low -6+36P (1) ns T12 tw(TS_SYNCH) CPSW-CPTS TS_SYNC, high -6+36P (1) ns T13 tw(TS_SYNCL) CPSW-CPTS TS_SYNC, low -6+36P (1) ns T14 tw(SYNC_OUTH) TS_SYNC sourcing SYNCn_OUT, high -6+36P (1) ns T15 tw(SYNC_OUTL) TS_SYNC sourcing SYNCn_OUT, low -6+36P (1) ns T16 tw(SYNC_OUTH) GENF sourcing SYNCn_OUT, high -6+5P (1) ns T17 tw(SYNC_OUTL) GENF sourcing SYNCn_OUT, low -6+5P (1) ns

ADVANCE□INFORMATION CPTS_TS_COMP T6 T7 CPTS_TS_SYNC T8 T9 CPTS_SYNC_OUT T10 T1 1 199 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated (1) P = functional clock period in ns. Figure 5-80. CPTS Output Switching Characteristics

5.11.5.12 OSPI

For more details about features and additional description information on the device Octal Serial Peripheral Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description.

5.11.5.12.1 OSPI with Data Training

Table 5-75. OSPI Switching Characteristics - Data Training PARAMETER DESCRIPTION MODE MIN MAX UNIT tc(CLK) Cycle time, CLK DDR, 1.8V 6.02 ns DDR, 3.3V 7.52 ns tc(CLK) Cycle time, CLK SDR, 1.8V 5.00 ns SDR, 3.3V 7.52 ns

5.11.5.12.2 OSPI without Data Training

The I/O Timings provided in this section are only applicable when data training is not implemented. Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL Delays are configured as described in Table 5-80 found in this section. These I\\O Timings also assume a matching skew of < 60 ps. Table 5-76, Table 5-77, Figure 5-81, and Figure 5-82 present switching characteristics for OSPI DDR and SDR Mode. Table 5-76. OSPI Switching Characteristics - DDR Mode (1) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O1 tc(CLK) Cycle time, CLK 1.8V 19 ns 3.3V 19 ns O2 tw(CLKL) Pulse duration, CLK low -0.3+0.475*P (2) ns O3 tw(CLKH) Pulse duration, CLK high -0.3+0.475*P (2) ns

ADVANCE□INFORMATION OSPI_CLK O S P I _ D [ i : 0 ] OSPI_TIMING_01 OSPI_CSn O6 O6 O4 O3 200 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-76. OSPI Switching Characteristics - DDR Mode (1) (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O4 td(CLK-CSn) Delay time, CLK rising edge to CSn active edge 1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX -7.7-0.475 * P – 0.975 * N * R (3) (4) (5) 0-0.475 * P – 0.975 * N * R (3) (4) (5) ns 3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX -8-0.475 * P – 0.975 * N * R (3) (4) (5) 0-0.475 * P – 0.975 * N * R (3) (4) (5) ns O5 td(CLK-CSn) Delay time, CLK rising edge to CSn inactive edge 1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX -7.7+0.475 * P + 0.975 * N * R (3) (4) (5) 0+0.475 * P + 0.975 * N * R (3) (4) (5) ns 3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX -8+0.475 * P + 0.975 * N * R (3) (4) (5) 0+0.475 * P + 0.975 * N * R (3) (4) (5) ns O6 td(CLK-D) Delay time, CLK active edge to D[i:0] transition 1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX -7.7 -1.56 ns 3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX -7.7 -1.56 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 (2) P = CLK cycle time (3) P = SCLK period (4) N = OSPI_DEV_DELAY_REG[D_INIT_FLD] (5) R = refclk Figure 5-81. OSPI Switching Characteristics - DDR Table 5-77. OSPI Switching Characteristics - SDR Mode (1) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O7 tc(CLK) Cycle time, CLK 1.8V 7 ns 3.3V 7.52 ns O8 tw(CLKL) Pulse duration, CLK low -0.3+0.475*P (2) ns O9 tw(CLKH) Pulse duration, CLK high -0.3+0.475*P (2) ns O10 td(CLK-CSn) Delay time, CLK rising edge to CSn active edge 1.8V -1-0.475 * P – 0.975 * N * R (3) (4) (5) 1-0.475 * P – 0.975 * N * R (3) (4) (5) ns 3.3V -1-0.475 * P – 0.975 * N * R (3) (4) (5) 1-0.475 * P – 0.975 * N * R (3) (4) (5) ns

ADVANCE□INFORMATION OSPI_CLK O S P I _ D [ i : 0 ] OSPI_TIMING_02 OSPI_CSn O10 O1 1 O9 O8 O12 201 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-77. OSPI Switching Characteristics - SDR Mode (1) (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O11 td(CLK-CSn) Delay time, CLK rising edge to CSn inactive edge 1.8V -1+0.475 * P + 0.975 * N * R (3) (4) (5) 1+0.475 * P + 0.975 * N * R (3) (4) (5) ns 3.3V -1+0.475 * P + 0.975 * N * R (3) (4) (5) 1+0.475 * P + 0.975 * N * R (3) (4) (5) ns O12 td(CLK-D) Delay time, CLK active edge to D[i:0] transition 1.8V -1.15 1.25 ns 3.3V -1.33 1.51 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 (2) P = CLK cycle time (3) P = SCLK period (4) N = OSPI_DEV_DELAY_REG[D_INIT_FLD] (5) R = refclk Figure 5-82. OSPI Switching Characteristics - SDR Table 5-78, Table 5-79, Figure 5-83, Figure 5-84, Figure 5-85, and Figure 5-86 presents timing requirements for OSPI DDR and SDR Mode. Table 5-78. OSPI Timing Requirements - DDR Mode (1) NO. PARAMETE R DESCRIPTION MODE MIN MAX UNIT O13 tsu(D-CLK) Setup time, D[i:0] valid before active CLK edge 1.8V, No Loopback Clock; 1.8V, Internal Pad Loopback Clock 5.23 ns 3.3V, No Loopback Clock; 3.3V, Internal Pad Loopback Clock 6.19 ns O14 th(CLK-D) Hold time, D[i:0] valid after active CLK edge 1.8V, No Loopback Clock; 1.8V, Internal Pad Loopback Clock 1.84 ns 3.3V, No Loopback Clock; 3.3V, Internal Pad Loopback Clock 2.34 ns O15 tsu(D-LBCLK) Setup time, D[i:0] valid before active LBCLK (DQS) edge 1.8V, External Board Loopback Clock 0.52 ns 3.3V, External Board Loopback Clock 1.97 ns O16 th(LBCLK-D) Hold time, D[i:0] valid after active LBCLK (DQS) edge 1.8V, External Board Loopback Clock 1.8 (2) ns 3.3V, External Board Loopback Clock 2.2 (2) ns

ADVANCE□INFORMATION OSPI_DQS O S P I _ D [ i : 0 ] OSPI_TIMING_06 O21 O 2 2 OSPI_CLK O S P I _ D [ i : 0 ] OSPI_TIMING_05 O 9 1 O20 203 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 Figure 5-85. OSPI Timing Requirements - SDR, No Loopback Clock and Internal Pad Loopback Clock Figure 5-86. OSPI Timing Requirements - SDR, External Loopback Clock Table 5-80. OSPI DLL Delay Mapping for Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BITFIELD DELAY VALUE 1.8V, OSPI0 DDR TX PHY_CONFIG_TX_DLL_DELAY_FLD 0x45 1.8V, OSPI1 DDR TX PHY_CONFIG_TX_DLL_DELAY_FLD 0x45 3.3V, OSPI0 DDR TX PHY_CONFIG_TX_DLL_DELAY_FLD 0x46 3.3V, OSPI1 DDR TX PHY_CONFIG_TX_DLL_DELAY_FLD 0x4C 1.8V, OSPI0 DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x14 1.8V, OSPI1 DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x16 3.3V, OSPI0 DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x3A 3.3V, OSPI1 DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x3E All other modes PHY_CONFIG_TX_DLL_DELAY_FLD, PHY_CONFIG_RX_DLL_DELAY_FLD 0x0

5.11.5.13 OLDI

Table 5-81. OLDI Switching Characteristics NO. PARAMETER MODE MIN MAX UNIT O1 LVDS Low-to-High Transition Time max IOSET1 0.18 0.5 ns O2 LVDS high-to-low Transition Time max IOSET1 0.18 0.5 ns O3 Transmitter Output Bit Width Min IOSET1 1 1 UI O4 Transmitter Pulse Positions – Normalized IOSET1 0.25 0.75 ns O5 Variation in transmitter pulse position across Bit 7:0 pulse positions IOSET1 -0.06 0.06 ns O6 TxOut Channel to Channel Skew IOSET1 110 ns O7 Transmitter Jitter Cycle-to-Cycle IOSET1 0.028 0.035 ns O8 Input Total Jitter Tolerance (Includes data to clock skew, pulse position variation.) IOSET1 0.25 ns

ADVANCE□INFORMATION +VOD -VOD VSS=2 VOD | | 80% 80% 20%20% LLHT LLHT OLDI_CLK DATA_TOL VTH VTL Ideal Data Bit End DATA_TOL Ideal Data Bit Beginning Sampling Window Ideal Center Position (t /2)BIT t (1UI)BIT OLDI_DATA[3:0] Left Right bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 T OLDI_CLK OLDI_DATA[3:0] tTPP1 tTPP2 tTPP3 tTPP4 tTPP5 tTPP6 tTPP7 1UI 2UI 3UI 4UI 5UI 6UI 7UI ΔtTPP 204 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-87. OLDI Transmitter Pulse Positions (1) tIJIT = DATA_TOL (Left+Right) Figure 5-88. OLDI Data Output Jitter Figure 5-89. LVDS Output Transition Times

5.11.5.14 PCIE

The PCI-Express Subsystem is compliant with the PCI Express Base Specification, revision 3.0. Refer to the specification for timing details. For more details about features and additional description information on the device Peripheral Component Interconnect Express, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description.

ADVANCE□INFORMATION GPI[m:0] PRDI1 SPRS91x_TIMING_PRU_01 205 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated

5.11.5.15 PRU_ICSSG

The device has integrated three identical PRU_ICSSG subsystems (PRU_ICSSG0, PRU_ICSSG1 and PRU_ICSSG2). The programmable nature of the PRU cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the device. For more details about features and additional description information on the device Programmable Real- Time Unit Subsystem and Industrial Communication Subsystem - Gigabit, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. NOTE The PRU_ICSSG_0 and PRU_ICSSG_1 support an internal wrapper multiplexing that expands the device top-level multiplexing. Signal naming in this section must match the internal wrapper multiplexing. For more information, please refer to the Device TRM, Chapter Processors and Accelerators, Section Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit (PRU_ICSSG).

5.11.5.15.1 Programmable Real-Time Unit (PRU_ICSSG PRU)

The PRU_ICSSG PRU signals have different functionality depending on the mode of operation. The signal naming in this section matches the naming used in the PRU Module Interface section in the device TRM. Table 5-82. PRU_ICSSG PRU Timing Requirements - Direct Input Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRDI1 tsk(PRU_DATAIN) PRU_DATAIN skew 2 ns Figure 5-90. PRU_ICSSG PRU Direct Input Timing (1) m in GPI[m:0] = 19. Table 5-83. PRU_ICSSG PRU Switching Characteristics - Direct Output Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRDO1 tsk(PRU_DATAOUT) PRU_DATAOUT skew 4 ns

ADVANCE□INFORMATION CLOCKIN DA T AIN PRPC1 PRPC2 PRPC3 PRPC5 SPRS91x_TIMING_PRU_04 PRPC4 CLOCKIN DA T AIN PRPC1 PRPC3 PRPC2 PRPC4 PRPC5 SPRS91x_TIMING_PRU_03 GPO[n:0] PRDO1 SPRS91x_TIMING_PRU_02 206 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Figure 5-91. PRU_ICSSG PRU Direct Output Timing (1) n in GPO[n:0] = 19. Table 5-84. PRU_ICSSG PRU Timing Requirements - Parallel Capture Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRPC1 tc(PRU_CLOCK) Cycle time, PRU_CLOCK 20 ns PRPC2 tw(PRU_CLOCKL) Pulse Duration, PRU_CLOCK Low 10 ns PRPC3 tw(PRU_CLOCKH) Pulse Duration, PRU_CLOCK High 10 ns PRPC4 tsu(PRU_DATAIN- PRU_CLOCK) Setup time, PRU_DATAIN valid before PRU_CLOCK active edge 4 ns PRPC5 th(PRU_CLOCK- PRU_DATAIN) Hold time, PRU_DATAIN valid after PRU_CLOCK active edge 0 ns Figure 5-92. PRU_ICSSG PRU Parallel Capture Timing – Rising Edge Mode Figure 5-93. PRU_ICSSG PRU Parallel Capture Timing – Falling Edge Mode

ADVANCE□INFORMATION CLOCKOUT DA T AO U T PRSO1 PRSO2H PRSO3 SPRSP08_TIMING_PRU_06 PRSO2L DA T AIN PRSI1 PRSI2 SPRSP08_TIMING_PRU_05 207 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-85. PRU_ICSSG PRU Timing Requirements - Shift In Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRSI1 tw(PRU_DATAINL) Pulse Duration, PRU_DATAIN Low 2+2*P (1) ns PRSI2 tw(PRU_DATAINH) Pulse Duration, PRU_DATAIN High 2+2*P (1) ns (1) P = Internal shift in clock period, defined by PRU0_GPI_DIV0 and PRU0_GPI_DIV1 bit fields in the GPCFGn register. Figure 5-94. PRU_ICSSG PRU Shift In Timing Table 5-86. PRU_ICSSG PRU Switching Characteristics - Shift Out Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRSO1 tc(PRU_CLKOUT) Cycle time, PRU_CLKOUT 10 ns PRSO2 tw(PRU_CLKOUTL) Pulse Duration, PRU_CLKOUT Low -0.3 + 0.475*P*Z (1)(2) ns PRSO3 tw(PRU_CLKOUTH) Pulse Duration, PRU_CLKOUT High -0.3 + 0.475*P*Y (1)(3) ns PRSO4 td(PRU_CLKOUT- PRU_DATAOUT) Delay time, PRU_CLKOUT to PRU_DATAOUT Valid 0 3 ns (1) P = Software programmable shift out clock period, defined by PRU0_GPO_DIV0 and PRU0_GPO_DIV1 bit fields in the GPCFGn register. (2) The Z parameter is defined as follows: If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are INTEGERS -or- if PRU0_GPI_DIV0 is a NON- INTEGER and PRU0_GPI_DIV1 is an EVEN INTEGER then, Z equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1). If PRU0_GPI_DIV0 is a NON-INTEGER and PRU0_GPI_DIV1 is an ODD INTEGER then, Z equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 + 0.5). If PRU0_GPI_DIV0 is an INTEGER and PRU0_GPI_DIV1 is a NON-INTEGER then, Z equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 + 0.5 * PRU0_GPI_DIV0). If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are NON-INTEGERS then, Z equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 + 0.25 * PRU0_GPI_DIV0). (3) The Y parameter is defined as follows: If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are INTEGERS -or- if PRU0_GPI_DIV0 is a NON- INTEGER and PRU0_GPI_DIV1 is an EVEN INTEGER then, Y equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1). If PRU0_GPI_DIV0 is a NON-INTEGER and PRU0_GPI_DIV1 is an ODD INTEGER then, Y equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 - 0.5). If PRU0_GPI_DIV0 is an INTEGER and PRU0_GPI_DIV1 is a NON-INTEGER then, Y equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 - 0.5 * PRU0_GPI_DIV0). If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are NON-INTEGERS then, Y1 equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 - 0.25 * PRU0_GPI_DIV0) and Y2 equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 + 0.25 * PRU0_GPI_DIV0), where Y1 is the first high pulse and Y2 is the second high pulse. Figure 5-95. PRU_ICSSG PRU Shift Out Timing

ADVANCE□INFORMATION PWM_A/B SPRSP08_TIMING_PRU_PWM_01 PRPWM1 PIF_CLK P I F _ DA T A _O U T PRPIF1 PRPIF2H PRPIF3 SPRSP08_TIMING_PIF_02 PRPIF2L PIF_DA T A_EN PRPIF4 209 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-89. PRU_ICSSG PRU Switching Characteristics - Peripheral Interface Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRPIF1 tc(PIF_CLK) Cycle time, PIF_CLK 30 ns PRPIF2H tw(PIF_DATA_INH) Pulse Duration, PIF_CLK High 0 + 0.475*P (1) ns PRPIF2L tw(PIF_DATA_INL) Pulse Duration, PIF_CLK Low 0 + 0.475*P (1) ns PRPIF3 td(PIF_CLK- PIF_DATA_OUT) Delay time, PIF_CLK fall to PIF_DATA_OUT -5 5 ns PRPIF4 td(PIF_CLK- PIF_DATA_EN) Delay time, PIF_CLK fall to PIF_DATA_EN -5 5 ns (1) P = 1x (or TX) clock period, defined by TX_DIV_FACTOR and TX_DIV_FACTOR_FRAC in the CFG_ED_Pn_TXCFG register. Figure 5-99. PRU_ICSSG PRU Peripheral Interface Switching Characteristics

5.11.5.15.2 PRU_ICSSG Pulse Width Modulation (PWM)

Table 5-90. PRU_ICSSG PWM Switching Characteristics NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRPWM tsk(PWM_A/B) PWM_A/B skew 5 ns Figure 5-100. PRU_ICSSG PRU PWM Timing

5.11.5.15.3 PRU_ICSSG Industrial Ethernet Peripheral (PRU_ICSSG IEP)

Table 5-91. PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRIEP1 tw(EDC_SYNCx_OUTL) Pulse Duration, EDC_SYNCx_OUT Low -2+20*P (1) ns

ADVANCE□INFORMATION PRUR3L Start Bit Data Bits PRG _UART0_TXDi SPRS91x_TIMING_PRU_UART_01 PRUR3H PRUR1L Data Bits Bit Start PRG _UART0_RXDi PRUR1H (1) (1) (1) i in PRG _UART0_RXD and PRG _UART0_TXD = 0, 1 or 2i i EDC_LA TCHx_IN PRLA2 SPRSP08_TIMING_PRU_IEP_02 PRLA1 211 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated (1) P = PRU-ICSS IEP clock source period. Figure 5-103. PRU_ICSSG PRU IEP LATCHx_IN Timing

5.11.5.15.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)

Table 5-94. PRU_ICSSG UART Timing Requirements NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRUR1H tw(RXH) Pulse Duration, Receive start, stop, data bit High 0+U (1) ns PRUR1L tw(RXL) Pulse Duration, Receive start, stop, data bit Low -2+U (1) ns (1) U = UART baud time = 1/programmed baud rate. Table 5-95. PRU_ICSSG UART Switching Characteristics NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRUR2 f(baud) Maximum programmable baud rate PRUR3L tw(TXH) Pulse Duration, Transmit start, stop, data bit High 0+U(1) ns PRUR3H tw(TXL) Pulse Duration, Transmit start, stop, data bit Low -2+U(1) ns (1) U = UART baud time = 1/programmed baud rate. Figure 5-104. PRU_ICSSG UART Timing

5.11.5.15.5 PRU_ICSSG Enhanced Capture Peripheral (PRU-ICSS ECAP)

Table 5-96. PRU_ICSSG ECAP Timing Requirements NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PREP1 tw(CAP) Pulse Duration, Capture input (asynchronous) 2+2*P (1) ns PREP2 tw(SYNCI) Pulse Duration, Sync input (asynchronous) 2+2*P (1) ns

ADVANCE□INFORMATION APWM PREP3 SPRSP08_TIMING_ECAP_02 SYNCO CAP PREP1 SPRSP08_TIMING_ECAP_01 SYNCI PREP2 212 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated (1) P = core_clk period Figure 5-105. PRU_ICSSG ECAP Timing Table 5-97. PRU_ICSSG ECAP Switching Characteristics NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PREP3 tw(APWM) Pulse Duration, Auxillary PWM (APWM) output 0+2*P (1) ns PREP4 tw(SYNCO) Pulse Duration, Sync output (asynchronous) 0+P (1) ns (1) P = core_clk period Figure 5-106. PRU_ICSSG ECAP Switching Characteristics

5.11.5.15.6 PRU_ICSSG RGMII, MII_RT, and Switch

Table 5-98. PRU_ICSSG MDIO Timing Requirements – MDIO_DATA NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRMDI1 tsu(MDIO-MDC) Setup time, MDIO valid before MDC High 90 ns PRMDI2 th(MDC-MDIO) Hold time, MDIO valid from MDC High 0 ns

ADVANCE□INFORMATION PRMDO1 MDIO_CLK (Output) MDIO_DATA (Output) SPRS91x_TIMING_PRU_MII_RT_03 MDIO_CLK PRMC2 PRMC3 PRMC1 PRMC4 PRMC4 SPRS91x_TIMING_PRU_MII_RT_02 MDIO_CLK (Output) PRMDI1 PRMDI2 MDIO_DATA (Input) SPRS91x_TIMING_PRU_MII_RT_01 213 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated (1) P = Cycle time Figure 5-107. PRU_ICSSG MDIO_DATA Timing – Input Mode Table 5-99. PRU_ICSSG MDIO Switching Characteristics – MDIO_CLK NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRMC1 tc(MDC) Cycle time, MDC 400 ns PRMC2 tw(MDCH) Pulse Duration, MDC High 160 ns PRMC3 tw(MDCL) Pulse Duration, MDC Low 160 ns PRMC4 tt(MDC) Transition time, MDC 5 ns Figure 5-108. PRU_ICSSG MDIO_CLK Timing Table 5-100. PRU_ICSSG MDIO Switching Characteristics – MDIO_DATA NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRMDO td(MDC-MDIO) Delay time, MDC High to MDIO valid 10 ns Figure 5-109. PRU_ICSSG MDIO_DATA Timing – Output Mode

ADVANCE□INFORMATION RGMII_RXC PRRG2 PRRG3 PRRG1 SPRS91x_TIMING_PRU_RGMII_RT_04 PRRG4 214 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-101. PRU-ICSSG RGMII Timing Requirements - RGMII_RCLK NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRRG1 tc(RXC) Cycle time, RXC 10 Mbps TBD TBD ns

100 Mbps TBD TBD ns

1000 Mbps 7.2 8.8 ns PRRG2 tw(RXCH) Pulse duration, RXC high 10 Mbps TBD TBD ns 1000 Mbps 3.6 4.4 ns PRRG3 tw(RXCL) Pulse duration, RXC low 10 Mbps TBD TBD ns 1000 Mbps 3.6 4.4 ns PRRG4 tt(RXC) Transition time, RXC 10 Mbps TBD ns

100 Mbps TBD ns

1000 Mbps 0.75 ns Figure 5-110. PRU_ICSSG RGMII_RCLK Input Timing Table 5-102. PRU-ICSSG RGMII Timing Requirements - RGMII_RD[3:0] and RGMII_RCTL NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRRG5 tsu(RD-RXC) Setup time, RD[3:0] valid before RXC high/low 10 Mbps TBD ns

1000 Mbps 1 ns

tsu(RX_CTL-RXC) Setup time, RX_CTL valid before RXC high/low 10 Mbps TBD ns PRRG6 th(RXC-RD) Hold time, RD[3:0] valid after RXC high/low 10 Mbps TBD ns th(RXC-RX_CTL) Hold time, RX_CTL valid after RXC high/low 10 Mbps TBD ns PRRG7 tt(RD) Transition time, RD 10 Mbps TBD ns 1000 Mbps 0.75 ns tt(RX_CTL) Transition time, RX_CTL 10 Mbps TBD ns 1000 Mbps 0.75 ns

ADVANCE□INFORMATION SPRS91x_TIMING_PRU_RGMII_RT_06 RGMII_TXC PRRG9 PRRG10 PRRG8 PRRG1 1 PRRG1 1 SPRS91x_TIMING_PRU_RGMII_RT_05 RGMII_RXCLK (Input) PRPG5 PRPG6 RGMII_RXD[3:0], RGMII_RXDV, RGMII_RXER (Inputs) PRPG7 215 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Figure 5-111. PRU_ICSSG RGMII_RD[3:0] and RGMII_RCTL Input Timing Table 5-103. PRU-ICSSG RGMII Switching Characteristics - RGMII_TCLK NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRRG8 tc(TXC) Cycle time, TXC 10 Mbps TBD TBD ns 1000 Mbps 7.2 8.8 ns PRRG9 tw(TXCH) Pulse duration, TXC high 10 Mbps TBD TBD ns 1000 Mbps 3.6 4.4 ns PRRG10 tw(TXCL) Pulse duration, TXC low 10 Mbps TBD TBD ns 1000 Mbps 3.6 4.4 ns PRRG11 tt(TXC) Transition time, TXC 10 Mbps TBD ns 1000 Mbps 0.75 ns Figure 5-112. PRU_ICSSG RGMII_RCLK Output Timing Table 5-104. PRU-ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TCTL NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRRG12 tsk(TD-TXC) TD to TXC output skew 10 Mbps TBD TBD ns

1000 Mbps TBD TBD ns

tsk(TX_CTL-TXC) TX_CTL to TXC output skew 10 Mbps TBD TBD ns

ADVANCE□INFORMATION MII_RXCLK PMIR2 PMIR3 PMIR1 SPRS91x_TIMING_PRU_MII_RT_04 SPRS91x_TIMING_PRU_RGMII_RT_07 PRRG12 RGMII_TXC RGMII_TD[3:0] RGMII_TX_CTL PRRG13 216 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-104. PRU-ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TCTL (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRRG13 tt(TD) Transition time, TD 10 Mbps TBD ns 1000 Mbps 0.75 ns tt(TX_CTL) Transition time, TX_CTL 10 Mbps TBD ns 1000 Mbps 0.75 ns (1) P = Cycle time Figure 5-113. PRU_ICSSG RGMII_RD[3:0] and RGMII_RCTL Output Timing NOTE In order to guarantee the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz, 225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1 register must be set to 0h (default value). Table 5-105. PRU_ICSSG MII_RT Timing Requirements – MII_RXCLK NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIR1 tc(RX_CLK) Cycle time, RX_CLK 10 Mbps 399.96 400.04 ns 100 Mbps 39.996 40.004 ns PMIR2 tw(RX_CLKH) Pulse Duration, RX_CLK High 10 Mbps 140 260 ns

100 Mbps 14 26 ns

PMIR3 tw(RX_CLKL) Pulse Duration, RX_CLK Low 10 Mbps 140 260 ns Figure 5-114. PRU_ICSSG MII_RXCLK Timing Table 5-106. PRU_ICSSG MII_RT Timing Requirements – MII_TXCLK NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIT1 tc(TX_CLK) Cycle time, TX_CLK 10 Mbps 399.96 400.04 ns 100 Mbps 39.996 40.004 ns

ADVANCE□INFORMATION MII_MRCLK (Input) PMIR4 PMIR5 MII_RXD[3:0], MII_RXDV, MII_RXER (Inputs) SPRS91x_TIMING_PRU_MII_RT_06 MII_TXCLK PMIT2 PMIT3 PMIT1 PMIT4 PMIT4 SPRS91x_TIMING_PRU_MII_RT_05 217 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-106. PRU_ICSSG MII_RT Timing Requirements – MII_TXCLK (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIT2 tw(TX_CLKH) Pulse Duration, TX_CLK High 10 Mbps 140 260 ns PMIT3 tw(TX_CLKL) Pulse Duration, TX_CLK Low 10 Mbps 140 260 ns PMIT4 tt(TX_CLK) Transition time, TX_CLK 10 Mbps 5 ns

100 Mbps 5 ns

Figure 5-115. PRU_ICSSG MII_TXCLK Timing Table 5-107. PRU_ICSSG MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIR4 tsu(RXD-RX_CLK) Setup time, RXD[3:0] valid before RX_CLK 10 Mbps 8 ns tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK 8 ns tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK 8 ns tsu(RXD-RX_CLK) Setup time, RXD[3:0] valid before RX_CLK 100 Mbps 8 ns tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK 8 ns tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK 8 ns PMIR5 th(RX_CLK-RXD) Hold time, RXD[3:0] valid after RX_CLK 10 Mbps 8 ns th(RX_CLK-RX_DV) Hold time, RX_DV valid after RX_CLK 8 ns th(RX_CLK-RX_ER) Hold time, RX_ER valid after RX_CLK 8 ns th(RX_CLK-RXD) Hold time, RXD[3:0] valid after RX_CLK 100 Mbps 8 ns th(RX_CLK-RX_DV) Hold time, RX_DV valid after RX_CLK 8 ns th(RX_CLK-RX_ER) Hold time, RX_ER valid after RX_CLK 8 ns Figure 5-116. PRU_ICSSG MII_RXD[3:0], MII_RXDV, and MII_RXER Timing

ADVANCE□INFORMATION T1 T2 TIMIx TIMER_01 T3 T4 TIMOx PMIT5 MII_TXCLK (input) MII_TXD[3:0], MII_TXEN (outputs) SPRS91x_TIMING_PRU_MII_RT_07 218 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated Table 5-108. PRU_ICSSG MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIT5 td(TX_CLK-TXD) Delay time, TX_CLK High to TXD[3:0] valid 10 Mbps 5 25 ns td(TX_CLK-TX_EN) Delay time, TX_CLK to TX_EN valid 5 25 ns td(TX_CLK-TXD) Delay time, TX_CLK High to TXD[3:0] valid 100 Mbps 5 25 ns td(TX_CLK-TX_EN) Delay time, TX_CLK to TX_EN valid 5 25 ns Figure 5-117. PRU_ICSSG MII_TXD[3:0], MII_TXEN Timing For more information, see section Programmable Real-Time Unit Subsystem and Industrial Communication Subsystems - Gigabit (PRU_ICSSG) in chapter Processors and Accelerators of the device TRM.

5.11.5.16 Timers

For more details about features and additional description information on the device Timers, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-109, Table 5-110 and Figure 5-118 present timings and switching characteristics of the Timers. Table 5-109. Timing Requirements for Timers NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT T1 tw(TINPH) Pulse duration, high CAPTURE 5 + 4P(1) ns T2 tw(TINPL) Pulse duration, low CAPTURE 5 + 4P(1) ns (1) P = functional clock period in ns. Table 5-110. Switching Characteristics for Timers NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT T3 tw(TOUTH) Pulse duration, high PWM -3 + 4P(1) ns T4 tw(TOUTL) Pulse duration, low PWM -3 + 4P(1) ns (1) P = functional clock period in ns. Figure 5-118. Timer Timing For more information, see section Timers in chapter Peripherals of the device TRM.

ADVANCE□INFORMATION Start Bit Data Bits UART _TXDi Data Bits Bit Start UART _RXDi 219 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated

5.11.5.17 UART

For more details about features and additional description information on the device Universal Asynchronous Receiver Transmitter, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-111, Table 5-112, and Figure 5-119 present Timing Requirements and Switching Characteristics for UART interface. Table 5-111. Timing Requirements for UART NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT 4 tw(RX) Pulse width, receive data bit, 15/30 pF high or low 0.95U (1) 1.05U (1) ns 5 tw(CTS) Pulse width, receive start bit, 15/30 pF high or low 0.95U (1) 1.05U (1) ns td(RTS-TX) Delay time, transmit start bit to transmit data P (2) ns td(CTS-TX) Delay time, receive start bit to transmit data P (2) ns (1) U = UART baud time = 1/Programmed baud rate (2) P = Clock period of the reference clock (FCLK, usually 48 MHz or 192 MHz) Table 5-112. Switching Characteristics Over Recommended Operating Conditions for UART NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT f(baud) Maximum programmable baud rate 15 pF 12 MHz 30 pF 0.115 2 tw(TX) Pulse width, transmit data bit, 15/30 pF high or low U - 2 (1) U + 2 (1) ns 3 tw(RTS) Pulse width, transmit start bit, 15/30 pF high or low U - 2 (1) U + 2 (1) ns (1) U = UART baud time = 1/Programmed baud rate Figure 5-119. UART Timing For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in chapter Peripherals of the device TRM.

5.11.5.18 USB

The USB 2.0 subsystem is fully-compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the specification for timing details. The USB 3.1 GEN1 Dual-Role Device Subsystem is compliant with the Universal Serial Bus (USB) 3.1 Specification, revision 1.0. Refer to the specification for timing details. For more details about features and additional description information on the device Universal Serial Bus Subsystem (USB), see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description.

ADVANCE□INFORMATION TRC_DATA TRC_CLK ( ) ( ) (Ideal) Worst Case 1 Worst Case 2 DBTR1 DBTR2 DBTR3 DBTR4 DBTR6 DBTR5 DBTR7 DBTR4 DBTR6 DBTR9 DBTR5 DBTR7 DBTR8 DBTR8 DBTR9 SPRSP08_Debug_01 220 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Specifications Copyright © 2018, Texas Instruments Incorporated For more information, see section Universal Serial Bus (USB) Subsystem in chapter Peripherals of the device TRM.

5.11.6 Emulation and Debug

5.11.6.1 Debug Trace

Table 5-113 and Figure 5-120 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-113. Debug Trace Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 10.16 ns DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 4.33 ns DBTR3 tw(TRC_CLKL) Pulse width, TRC_CLK low 4.33 ns DBTR4 tosu(TRC_DATAV- TRC_CLK) Output setup time, TRC_DATA valid to TRC_CLK edge 1.27 ns DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid 1.27 ns DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge 1.27 ns DBTR7 toh(TRC_CLK-TRC_CTLI) Output hold time, TRC_CLK edge to TRC_CTL invalid 1.27 ns DBTR8 trx(TRC_CLK_DATA_CTL) Output rise time, 30% VDD to 70% VDD 0.75 ns DBTR9 tfx(TRC_CLK_DATA_CTL) Output fall time, 70% VDD to 30% VDD 0.75 ns Figure 5-120. Debug Trace Timing 5.11.6.2 IEEE 1149.1 Standard-Test-Access Port (JTAG) For more details about features and additional description information on the device IEEE 1149.1 Standard-Test-Access Port, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description.

5.11.6.2.1 JTAG Electrical Data and Timing

Table 5-114, Table 5-115, and Figure 5-121 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-114. Timing Requirements for IEEE 1149.1 JTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT J1 tc(TCK) Cycle time minimum, TCK 75 ns J2 tw(TCKH) Pulse width minimum, TCK high 30 ns J3 tw(TCKL) Pulse width minimum, TCK low 30 ns

ADVANCE□INFORMATION TDO TCK TDI / TMS J6 J7 J4 J5 221 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M SpecificationsCopyright © 2018, Texas Instruments Incorporated Table 5-114. Timing Requirements for IEEE 1149.1 JTAG (continued) NO. PARAMETER DESCRIPTION MIN MAX UNIT J4 tsu(TDI-TCK) Input setup time minimum, TDI valid to TCK high 8 ns tsu(TMS-TCK) Input setup time minimum, TMS valid to TCK high 8 ns J5 th(TCK-TDI) Input hold time minimum, TDI valid from TCK high 5.2 ns th(TCK-TMS) Input hold time minimum, TMS valid from TCK high 5.2 ns Table 5-115. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT J6 td(TCKL-TDOI) Delay time minimum, TCK low to TDO invalid 0 ns J7 td(TCKL-TDOV) Delay time maximum, TCK low to TDO valid 27.75 ns Figure 5-121. JTAG Test-Port Timing

ADVANCE□INFORMATION 222 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

6 Detailed Description

6.1 Overview

Automobiles are becoming more and more connected - both inside the car, within the various subsystems / domains as well as with the outside world, with connectivity via Bluetooth, LTE, WiFi etc. Much more information and data are being shared or transferred between the various domains; for example, video from rear and surround view cameras for displayed in the head unit; data from the chassis is sent to the on-board diagnostic unit, etc. As the amount of data that has to be integrated and transported between the various domains in a time sensitive manner has increased, car manufacturers are looking to include a network gateway, based on Ethernet protocols, in cars. Such gateways should be able to handle multiple connectivity protocols such as CAN, CAN-FD, TCP/IP to name a few. TI’s DRA80x family of products enable automotive manufacturers to build scalable and cost optimized network gateway features in cars, thanks to its high level of integration and purpose built peripherals, such as Gigabit Ethernet MACs. DRA80x Automotive Gateway processors are built to meet the intense processing needs of automotive gateway. The DRA80x family of devices combines four or two Arm® Cortex-A53 cores with an ASIL-C capable dual Cortex-R5 MCU subsystem and six Gigabit Ethernet MACs in the MAIN domain and one Gigabit Ethernet MAC in the MCU domain to create an SoC capable of implementing an Automotive Gateway system with plenty of automotive connectivity and functional safety processing. The four A53 cores are arranged in two dual-core clusters with shared L2 memory to create two processing channels to address additional safety concepts. Extensive ECC is included for on-chip memory and interconnects for reliability. Cryptographic acceleration and secure boot are available on DRA80x devices, in addition to granular whitelist firewalls managed by a security controller core. Programmability is provided by the quad-core ARM Cortex-A53 RISC CPUs with Neon™ extension, and the dual Cortex-R5 MCU subsystem is available for general purpose use. The Ethernet subsystem can be used to provide up to six ports of Ethernets, including TSN, for standard Ethernet connectivity. Additionally, TI provides a complete set of development tools for the ARM cores including C compilers and a debugging interface for visibility into source code execution. Safety documentation is available for applications needing to meet functional safety standards. NOTE For more information on features, subsystems, and architecture of superset device System on Chip (SoC), see the device TRM.

ADVANCE□INFORMATION Interconnect Media & Data Storage Audio Peripherals General Connectivity Automotive Interfaces intro_001 DRA80x 2x MMC/SD 3x MCASP PCIe® 2x Single/1x Dual Lane Gen 3 (3) GPIO 1x USB 2.0 DRD High-Speed Serial Interfaces 4x UART 5x MCSPI (2) Copyright © 2018, Texas Instruments Incorporated 5x I2C 2x ADC (1) 2x Arm® Cortex –A53® 512KB L2 with ECC Memory Subsystem DDRSS with ECCGPMC Navigator Subsystem MCU Island 2x Arm Cortex -R5F 1x USB 3.1 DRD 2x RTI/WWDT System Services 12x GP Timers PDMA Debug PDMA 2x Arm® Cortex –A53® 512KB L2 with ECC DMSC Security Accelerators AESAES AESPKA AESMD5 AESSHA AESDRBG AES3DES 2x OSPI or 1x OSPI + 1x Hyperbus (1) MSMC 2MB SRAM with ECC ELM 3x MCSPI (1)(2) 1x UART (1) 1x I2C (1) 2x MCAN-FD (1) (With optional Lockstep) 10/100/1000 Ethernet (1) PDMA4x RTI/WWDT UDMA Proxy 2x PVU CPTS RA MCRC INTR 12x Mailbox Spinlock 3x INTA 2x TIMER_MGR Channelized FW Navigator Subsystem UDMA Proxy MCRC RA INTR INTA Channelized FW 2x RTI/WWDT 4x GP TimersPDMA ESM Scratchpad RAM 512B MCU_MSRAM 512KB ESM Ethernet Subsystem 3x PRU_ICSSG (3) (Up to 6x Ethernet ports) (3) 223 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

6.2 Functional Block Diagram

(1) This interface is located on the MCU Island but is available for the full system to access. (2) One port is internally connected only; not connected to any pins. (3) SGMII, USB3.1 and PCIe share a total of two SerDes lanes. Figure 6-1. DRA80x Block Diagram

ADVANCE□INFORMATION 224 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

6.3 Arm Cortex-A53

The SoC implements two Dual-Core Arm Cortex-A53 Subsystems (CC_ARMSS0 and CC_ARMSS1), which are both integrated inside the Compute Cluster (along with the MSMC module). The Cortex-A53 cores are general-purpose processors that can be used for running customer applications. NOTE Notes on references used in this document:

Both Arm Cortex-A53 Subsystems are functionally identical and are referred to as a single subsystem (CC_ARMSS), where appropriate.
CC_ARMSS is also referred to as Arm CorePac.
Cortex-A53 is often shortened to A53. The CC_ARMSS is built around the Cortex-A53 MPCore (Arm A53 Cluster), which is provided by Arm and configured by TI. It is based on the symmetric multiprocessor (SMP) architecture, and thus it delivers high performance and optimal power management, debug and emulation capabilities. The A53 processor is an Armv8A-compatible, multi-issue out-of-order superscalar execution engine with integrated L1 Instruction and Data Caches. It delivers significantly more performance than its predecessors at a higher level of power efficiency. The Armv8-A architecture brings a number of new features. These include 64-bit data processing, extended virtual addressing and 64-bit general purpose registers. The A53 processor is Arm’s first Armv8- A processor aimed at providing power-efficient 64-bit processing. It features an in-order, 8-stage, dual- issue pipeline, and improved integer, NEON™ , Floating-Point Unit (FPU) and memory performance. The A53 CPU supports two execution states: AArch32 and AArch64. The AArch64 state gives the A53 CPU its ability to execute 64-bit applications, while the AArch32 state allows the processor to execute existing Armv7-A applications. Details on the Compute Cluster module and the interaction between CC_ARMSS(s) and MSMC can be found in the Compute Cluster chapter. The CC_ARMSS supports the following key features:

ADVANCE□INFORMATION 225 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

Cortex-A53 MPCore (A53 Cluster) features: – Dual-core configuration (coherent SMP processors within the cluster) – Full compliance to Armv8-A architecture
AArch32 and AArch64 Execution States – AArch32 for full backward compatibility with Armv7 – AArch64 for 64b support and new architectural features
All exception levels EL0-3
A32 Instruction Set
T32 Instruction Set
A64 Instruction Set – NEON Advanced SIMD – VFPv4 Floating point – Hardware virtualization support – Armv8 Cryptography Extensions – Arm GICv3 architecture – In-order pipeline with symmetric dual-issue of most instructions – Harvard L1 with system MMU
32KB Instruction (Program) Cache
32KB Data Cache – 512KB Shared L2 Cache – Snoop Control Unit (SCU) managing the interconnect, arbitration, communication, cache-to-cache and system memory transfers, cache coherence and other capabilities for the processor – Generic Timer(s) – Arm CoreSight™ Debug and Trace Architecture – Functional safety support
Error Correction Code (ECC) protection for: – L1 Data Cache (Data RAM) – L2 Cache (Data RAM, Tag RAM) – L1 SCU Duplicate Tags
Parity protection for: – L1 Instruction Cache (Data RAM and Tag RAM) – L1 Data Cache Tag RAM and Dirty Bits – TLB
No error protection on branch protection and L2 victim RAM
Support for error injection to all supported ECC memory blocks – Provided for testing ECC functionality in safety-critical applications (add-on function from TI) – Supported by ECC Aggregators at the CC_ARMSS level
256-bit wide, synchronous or asynchronous VBUSM.C master interface – AXI2VBUSM_MASTER Bridge – Sync/Async boot time selectable via pin – Cache pre-warming via use of ACP Port
64-bit graycoded system input time
48-bit graycoded debug input time
32-bit VBUSP slave interface for debug (internally converted to APB)
32-bit ATB output port for debug/trace
Interface with Arm GIC-500 Interrupt Controller (SoC level, not part of CC_ARMSS)
Supports the SoC multi-core cache coherency architecture

ADVANCE□INFORMATION 226 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

Dedicated MPU clocking (Arm PLLs) for full flexibility in performance trade-offs
Advanced power management with fine-grained control of individual A53 CPU power domains, coarse- grained cluster-level power management, and low-power standby modes (WFI/WFE modes)
Dedicated RTI windowed watchdog timer per core
Support for Big-Endian (BE) and Little-Endian (LE) at core level For more information, see section Arm Cortex-A53 Subsystem in chapter Processors and Accelerators of the device TRM.

6.4 Arm Cortex-R5F

The MCU_ARMSS is a dual-core implementation of the Arm® Cortex-R5F® processor configured for split/lock operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and various wrappers for protocol conversion and address translation for easy integration into the SoC. NOTE The Cortex-R5F processor is a Cortex-R5 processor that includes the optional Floating Point Unit (FPU) extension. In this TRM, all references to the Cortex-R5 processor by default apply to the Cortex-R5F processor. The MCU_ARMSS supports the following features:

ADVANCE□INFORMATION 227 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

Dual Arm Cortex-R5F CPU configuration – Revision r1p3 – Armv7-R profile – Split/Lock operation
Split mode: Two independently operating cores (Asymetric Multi Processing, no coherence)
Lock (lockstep) mode: One main operating core with the other operating in lockstep for safety
Boot-time configurable to be in split or lock mode – L1 Memory System
16KB Instruction Cache – 4x4KB ways – SECDED ECC protected per 64 bits
16KB Data Cache – 4x4KB ways – SECDED ECC protected per 32 bits
64KB Tightly-Coupled Memory (TCM) per CPU – SECDED ECC protected per 32 bits – Readable/Writable from system – Split into A and B banks (with B further splitting into B0 and B1 interleaved banks) – 32KB TCMA (ATCM) – 16KB TCMB0 (B0TCM) – 16KB TCMB1 (B1TCM) – Low interrupt latency with restartable instructions – Non-Maskable Interrupt (NMI) – Full-Precision Floating Point (VFPv3) – 16-Region Memory Protection Unit (MPU) – 8 Breakpoints – 8 Watchpoints – Dynamic Branch Prediction with Global History Buffer and 4-entry Return Stack – CoreSight Debug Access Port (DAP) – CoreSight ETM-R5 Interface – Performance Monitoring Unit (PMU)
Interfaces – 64-bit VBUSM master pair (1 read, 1 write) for L3 memory accesses (per core) – 64-bit VBUSM slave for TCM access (per core)
Also allows access to cache for debug purposes – 32-bit VBUSP master for peripheral access (per core) – 32-bit VBUSP slave config port (per core) – 32-bit VBUSP slave debug port
Allows access to all MCU_ARMSS internal debug logic
32-bit to 48-bit Region-based Address Translation (RAT) on memory access masters – 16 Regions
Synchronous clock domain crossing on all interfaces

ADVANCE□INFORMATION 228 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

Integrated Vectored Interrupt Manager (VIM) – 512 interrupts per core
Only interrupts connected to R5F Core 0 are available in lock mode
Each interrupt programmable as either IRQ or FIQ
Each interrupt has a programmable enable mask
Each interrupt has a programmable 4-bit priority – Priority interrupt supported – Vectored Interrupt Interface
Compatible with R5F VIC Port
Programmable 32-bit vector address per interrupt – Address is SECDED error protected – Default vector addresses provided on DED
Software Interrupt generation
Standard Arm CoreSight debug and trace architecture at the MCU_ARMSS level – Cross Triggering: Supported by Cross Trigger Interface (CTI) (per CPU) and Cross Trigger Matrix (CTM) components – Processor Trace: Supported by Embedded Trace Macrocell (ETM) (per CPU) and Advanced Trace Bus (ATB) Funnel components
Integrated ECC Aggregators – Support for error injection to all supported ECC memory blocks to test ECC functionality in safety- critical applications (add-ON function from TI) – One ECC Aggregator per core to cover all RAMs associated with that core
Boot – From ROM or external memory – From TCM The MCU_ARMSS does not support the following features in this device:
ACP Port (no coherence)
AXI Peripheral Port (PPX/PPV); corresponds to the VBUSM Peripheral Port at the MCU_ARMSS level
Bus parity/ECC For more information, see section MCU Cortex-R5F Subsystem in chapter Processors and Accelerators of the device TRM.

6.5 PRU-ICSSG

The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG) consists of:

Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1)
Two Real-Time Transfer Units (RTU_PRU0 and RTU_PRU1)
Data RAMs per PRU core
Instruction RAMs per PRU and per RTU_PRU cores
Shared RAM
Peripheral modules
Interrupt controller (INTC) The programmable nature of the PRU cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the device.

ADVANCE□INFORMATION 229 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate independently or in coordination with each other and can also work in coordination with the device-level host CPU. This interaction between processors is determined by the nature of the firmware loaded into the PRU’s instruction memory. The device has integrated three identical PRU_ICSSG subsystems (PRU_ICSSG0, PRU_ICSSG1 and PRU_ICSSG2 ). The PRU_ICSSG subsystem includes the following main features:

20 Enhanced General-Purpose Inputs (EGPI) and 20 Enhanced General-Purpose Outputs (EGPO)
Asynchronous capture [Serial Capture Unit (SCU)] with EnDat 2.2 protocol and Sigma-Delta demodulation support
Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1), each with – 12KB program memory per PRU CPU (signified PRU0_IRAM for PRU0 and PRU1_IRAM for PRU1) with ECC – 4KB Broadside (BS) RAM – MAC (Multiplier with optional Accumulation) – CRC16/32 HW accelerator – Byte Swap, for Little/Big Endian conversion – SUM32 for UDP checksum – Task Manager – Supports 128-bit wide PSI-L TX port for streaming access to NAVSS0 – Broadside (32-bit) connection to MII_G_RTn (where n= 1 or 2), Filter Data Base (FDB), Scratchpad Memory (SPAD), SPINLOCK, XFR2VBUS, and RTU_PRUm (where m= 0 or 1)
Two Real-Time Transfer Units (RTU_PRU0 and RTU_PRU1), each with – 8KB program memory with ECC – 16KB Broadside (BS) RAM – MAC (Multiplier with optional Accumulation) – CRC32/16 HW accelerator – Byte Swap, for Little/Big Endian conversion – Two instances of SUM32 – Task Manager – XFR2TR, for accelerating the internal memory copy of worklist from TR – Supports 128-bit wide PSI-L RX/TX port for streaming access through NAVSS0
Scratchpad Memory (SPAD) with 4 banks of 30 x 32-bit registers
64KB Shared general purpose memory RAM with ECC (signified Data RAM2), shared between PRU0 and PRU1
Two 8KB Data Memories with ECC (signified Data RAM0 and Data RAM1)
Two 256-bit VBUSM Master Ports: – Separate port for each PRUn/RTU_PRUn (where n = 0 or 1) – Optional address translation for PRUn (where n = 0 or 1) transactions to External Host
16 Software Events generated by 2 PRUs
Two Real-Time Ethernet ports (MII_G_RT1 and MII_G_RT2) configurable to connect to each PRUn (where n = 0 or 1) to support multiple industrial communication protocols. – Each of the Ethernet ports can be configured as MII/RGMII/SGMII ports – NOTE: SGMII mode is supported only for PRU_ICSSG2 instance

ADVANCE□INFORMATION 230 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

Two Industrial Ethernet Peripheral's (IEP0/IEP1) to manage/generate Industrial Ethernet functions such as time stamping. – Each of the Industrial Ethernet 64-bit timers support 10 capture and 16 compare events along with slow and fast compensation. – Supports up to 4 sets of 3 phased motor control with 12 primary and 12 complimentary programmable PWM outputs. – Up to 9 safety events with optional external trip IO per PWM set with hardware glitch filter.
One MDIO port to control external Ethernet PHY
16550-compatible UART with a dedicated 192MHz clock to support 12-Mbps PROFIBUS®
Interrupt Controller (INTC) – Up to 64 internal events, generated by modules, internal to the PRU_ICSSG – Up to 96 external events, generated by the system – Supports up to 20 interrupt channels – Generation of 20 Host interrupts:
2 Host interrupts to PRU0 and PRU1
2 Host interrupts to RTU_PRU0 and RTU_PRU1
8 Host interrupts, exported from the PRU_ICSSG for signaling the Arm interrupt controllers (pulse and level provided)
8 Host Interrupts for the Task Managers – Each system event can be enabled and disabled – Each host event can be enabled and disabled – Hardware prioritization of events
One 32-bit VBUSP slave (target) port for memory mapped register and internal memories access
Flexible power management support
Integrated 32-bit Interconnect The following PRU_ICSSG features are not supported:
Only 4 of the IEP0 (and none of the IEP1) Ethernet Digital Data Input/Output's of each ICSS_G are pinned out
UART Modem interface is not supported
The following features are not supported only for PRU_ICSSG0 and PRU_ICSSG1 – 12 Enhanced General-Purpose Inputs (pr<0/1>_pru0_r31_in[31:20]) are not pinned out – 12 Enhanced General-Purpose Outputs (pr<0/1>_pru0_r31_out[31:20]) are not pinned out – SGMII mode is not supported on PRU_ICSSG0 and PRU_ICSSG1
The following features are not supported only for PRU_ICSSG2: – 14 Enhanced General-Purpose Inputs (pr<2>_pru0_r31_in[31:18]) are not pinned out – 14 Enhanced General-Purpose Outputs (pr<2>_pru0_r31_out[31:18]) are not pinned out For more information, see section Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) in chapter Processors and Accelerators of the device TRM.

6.6 DMSC

This section describes the Device Management and Security Controller (DMSC) module in the device. NOTE DMSC controls the boot sequence, power management and security of the device, hence does not fall under specific industry standards. The device supports one DMSC module - WKUP_DMSC0, located in WKUP domain

ADVANCE□INFORMATION 231 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated A dedicated subsystem for device management and security functions. The DMSC is located in the WKUPSS. With the factory-sealed firmware, DMSC performs:

Device management
On-chip power management
Secure boot gate-keeping
Runtime security gate-keeping
Power feature /Wake-up control DMSC module supports the following features:
Arm Cortex-M3 based subsystem – Boot sequence – Device management – Power management – Security control
Arm Cortex-M3 RISC Processor (Single core) – Armv7-M architecture profile. – Support for NVIC (Nested Vectored Interrupt Controller) to achieve low interrupt latency – Ability to execute code from internal memory (via I-code/D-code) or external memories
Read-only Memory (ROM) to allow boot sequence, authentication and provide security service – 160KB Size (4-bytes words). – Accessible to only Cortex-M3.
Separate local memory bank within subsystem for I-code and d-code – 192KB of Instruction code (I-code). – 80KB of data space (D-code), split in 2 banks. – I-code and D-code can be mixed in any memory bank. – External world can access these memories if allowed via Firewall.
Firewall enabled 32-bits VBUSP CBA-SS interconnect – Low latency access from Cortex-M3 to ROM/RAM. – Cross-bar to allow Cortex-M3 and external host to access resources within DMSC. – Firewall policies enforced at each slave port to restrict access. – Channelized firewall for Message manager. – External 32-bits VBUSP master and slave interface – Address translation module to allow Cortex-M3 to reach any memory, with option Security attributes.
Interrupts – Up to 80 input interrupts
Active high level or pulse interrupts – internally treated as asynchronous.
Capable of Waking up the DMSC and SoC from Standby mode.
Configurable Wakeup capability. – Interrupt Aggregator module for MiniNav and Main Nav interrupts
Four timer module – 32-bits up counter. – 64-bits can be achieved by cascading two timer modules.
One WW RTI module (watch dog timer) – RTI mode. – WatchDog – Issue cold/warm reset to SoC.

ADVANCE□INFORMATION 232 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

Debug – DAP based debug interface to Arm core. – Full debug support inside Arm core. All debug functionality is present including data matching for watch point generation. – Standard trace support using ITM. – Limited Support for external Arm cross trigger interface (CTI) by providing interface signal to halt.
Fault Detection and Correction – Supports Double detection and Single error correction for I-code memory – Supports Double detection and Single error correction for D-code memory – Lock-Unlock based on 32bit keys for critical MMR writes. – Dedicated fault detected interrupt output.
Power Management features – DMSC Control Module
Contains various control, configuration and status MMRs for power management functions. – Main Oscillator Control
Controls the main SOC oscillator power down.
Controls the POR-RC oscillator root clock gating to avoid high frequency clock propagation during the SOC DeepSleep and DeeperSleep .
Support for DMTIMER to continue counting and generate interrupt via SWAKEUP even during SOC oscillator power down mode. The 4 DMTIMER modules support SWAKEUP generation. – Memory power management
Power OFF of ROM during sleep modes.
Retention of RAM during sleep modes. – IO Power Management
Controls IO Isolation while going into Standby mode.
Controls IO Wakeup capability. – External signals for power control
Support for 64 Cortex-M3 controlled general purpose outputs.
Support for 64 general purpose inputs which can be used by Cortex-M3.
Support for 64 hardware controlled outputs.
Support for 64 hardware controlled inputs.

ADVANCE□INFORMATION 233 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

Security Control features – Security Manager module
Device security management
Device type control (GP, EMU, HS etc.).
Emulation control
JTAG control
Key Management – Firewall and Priv-ID manager
Dedicated VBUSP port for firewall emulation and security configuration.
Issues interrupt to Cortex-M3 upon exception detection.
Accessible by Cortex-M3 only as default setting. – Debug SS handshake protocol for challenge-response protocol
Communication channel between DebugSS and DMSC to carry-out challenge response protocol to open SoC level JTAG port. – AES engine with 128, 192 and 256-bits support
No data fetch engine, data pushed via host into AES registers.
Separate firewall control for two HIB.
Ability to select KEK as default key for AES operation.
DPA /EMA countermeasure DMSC module Not Supported features:
Cortex-M3 Memory Protection Unit (MPU)
ETM
No big-endian support.
No support for SWAKEUP/CLKSTOP_WAKEUP event generation from WW-RTI. For more information, see section Device Management and Security Controller (DMSC) in chapter Device Configuration of the device TRM.

ADVANCE□INFORMATION 234 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

6.7 Memory Subsystem

6.7.1 MSMC

The Multi-core Shared Memory Controller (MSMC) forms the heart of the compute cluster (COMPUTE_CLUSTER0) providing high-bandwidth resource access both to and from all of the connected processing elements and the rest of the system. MSMC serves as the data-movement backbone of the compute cluster. MSMC supports the following features:

2MB (2 banks x 1MB) SRAM with ECC: – Shared coherent level 2/level 3 memory-mapped SRAM – Shared coherent level 3 cache
256-bit processor port bus and 40-bit physical address bus
Coherent unified bi-directional interfaces to connect to processors or device masters
One infrastructure master interface
Single external memory master interface
Supports distributed virtual system
Supports internal DMA engine – DRU (Data Routing Unit) – DMA in/out L2 SRAM, MSMC, DDR and system – L2, L3 cache pre-warming and post flushing
Bandwidth management with starvation bound
Two-level QoS support for real-time/non-real-time split
Security firewall for SRAM/cache and external memory
ECC error protection
Scrubbing on MSMC data memory (no scrubbing on tag RAMs or memory blocks used by DRU)
Parity protection and detection on all addresses, routing control and SECDED protection on data pipelines
One interconnect messaging interface that supports DMA/prefetch requests to DRU
Trace and debugging support
Supports dynamic power up and power down on PDs low power modes, if required by system

applications

Supports dynamic clock gating on all logic units
Supports low power mode during low-usage processor states MSMC does not support the following:
Cache coherence between multiple MSMC clusters
Atomic operation for compute cluster interface
AMBA-style exclusive bus operations to strongly ordered, device, or non-cacheable memory locations.
DRU memory management unit
PSI-L supported MMU control messaging For more information, see section Multicore Shared Memory Controller (MSMC) in chapter Device Configuration of the device TRM.

ADVANCE□INFORMATION 235 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

6.8 Interprocessor Communication

6.8.1 NAVSS

NAVSS specifies the data structures used by Texas Instruments standard communications modules to facilitate direct memory access (DMA) and to provide a consistent application programming interface (API) to the host software in multi-core devices. The data structures and the API used to manipulate them will be jointly referred to as NAVSS. Frequent tasks are commonly offloaded from the host processor to peripheral hardware to increase system performance. Significant performance gains may result from careful design of the host software and communication module interface. In networking systems, packet transmission and reception are critical tasks. Texas Instruments has developed the NAVSS standard, which is aimed at maximizing the efficiency of interaction between the host software and communications modules. The design goals for NAVSS are as follows:

Minimize host interaction
Maximize memory use efficiency
Maximize bus burst efficiency
Maximize symmetry between transmit/receive operations
Maximize scalability for number of connections/buffer sizes/queue sizes/protocols supported
Minimize protocol specific features
Minimize complexity Navigator subsystem's (main NAVSS) has the following hardware components:
Ring Accelerator (RA)
Proxy
Secure Proxy
Interrupt Aggregator (IA)
Interrupt Router (IR)
Unified DMA – Third Party Channel Controller (UDMA-C)
Unified Transfer Controller (UTC)
Data Routing Unit (DRU)
Unified DMA – Peripheral Root Complex (UDMA-P)
Peripheral DMA (PDMA)
Embedded DMA
UDMA Hardware/Software Interface For more information, see section Navigator Subsystem (NAVSS) in chapter Interprocessor Communication of the device TRM.

ADVANCE□INFORMATION 236 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

6.9 DMA Controllers

6.9.1 PDMA Controller

The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer needs of peripherals, which perform data transfers using memory mapped registers accessed via a standard non-coherent bus fabric. The PDMA module is intended to be located close to one or more peripherals which require an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and supporting only statically configured Transfer Request (TR) operations. The PDMA is only responsible for performing the data movement transactions which interact with the peripherals themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral. The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer complexity at each point in the system to match the requirements of whatever is being transferred to or from. Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO dimensioning requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically for sample size and FIFO depth), hardcoded address maps, and simple triggering capabilities. Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and employs round-robin scheduling between channels in order to share the underlying DMA hardware. There are five PDMA modules in the device.

6.9.1.1 PDMA Features

6.9.1.1.1 MCU_PDMA0 Features

The MCU domain PDMA0 supports the following features:

Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)
Provides 0 memory write access units
Provides 1 memory read access unit (Read Unit 0): – Supports 1 outstanding read per interface (VBUSP) – Supports read burst up to 32 bytes (limited by Rx Per-Channel FIFO depth) – Provides a 32-bit wide VBUSP read only master interface for peripheral accesses
Supports up to 0 simultaneous destination (Tx) channels
Supports up to 4 simultaneous source (Rx) channels
Supports static Transfer Requests (TRs) only
Supports MCAN special transfer mode
Provides per-channel buffering: – Provides 8x128-bit word deep data FIFO for each destination channel – Provides 8x128-bit word deep data FIFO for each source channel – Provides 128-bit wide PSI-L compliant data interface to remote UDMA and remote peripherals – Includes 1 output event transport lane – Provides 128-bit wide PSI-L compliant data interface from remote UDMA and remote peripherals – Includes 1 input event transport lane

6.9.1.1.2 MCU_PDMA1 Features

The MCU domain PDMA1 supports the following features:

ADVANCE□INFORMATION 237 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)
Provides 1 memory write access unit (Write Unit 0): – Supports write bursts up to 32 bytes (limited by Tx Per-Channel FIFO depth) – Provides a 32-bit wide VBUSP write-only master interface for peripheral accesses. – Supports up to 8 outstanding writes
Provides 1 memory read access unit – Supports 1 outstanding read per interface (VBUSP) – Supports read burst up to 32 bytes (limited by Rx Per-Channel FIFO depth) – Provides a 32-bit wide VBUSP read-only master interface for peripheral accesses
Supports up to 3 simultaneous destination (Tx) channels
Supports up to 3 simultaneous source (Rx) channels
Supports static Transfer Requests (TRs) only
Supports MCAN special transfer mode
Provides per-channel buffering: – Provides 8x128-bit word deep data FIFO for each destination channel – Provides 8x128-bit word deep data FIFO for each source channel – Provides 128-bit wide PSI-L compliant data interface to remote UDMA and remote peripherals – Includes 1 output event transport lane – Provides 128-bit wide PSI-L compliant data interface from remote UDMA and remote peripherals – Includes 1 input event transport lane

6.9.1.1.3 PDMA0 Features

The MAIN domain PDMA0 supports the following features:

Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)
Provides 1 memory write access unit (Write Unit 0): – Supports write bursts up to 32 bytes (limited by Tx Per-Channel FIFO depth) – Provides a 32-bit wide VBUSP write-only master interface for peripheral accesses – Supports up to 8 outstanding writes
Provides 1 memory read access unit (Read Unit 0): – Supports 1 outstanding read per interface (VBUSP) – Supports read burst up to 32 bytes (limited by Rx Per-Channel FIFO depth) – Provides a 32-bit wide VBUSP read-only master interface for peripheral accesses
Supports up to 3 simultaneous destination (Tx) channels
Supports up to 3 simultaneous source (Rx) channels
Supports static Transfer Requests (TRs) only
Supports MCAN special transfer mode
Provides per-channel buffering: – Provides 8x128-bit word deep data FIFO for each destination channel – Provides 8x128-bit word deep data FIFO for each source channel – Provides 128-bit wide PSI-L compliant data interface to remote UDMA and remote peripherals – Includes 1 output event transport lane – Provides 128-bit wide PSI-L compliant data interface from remote UDMA and remote peripherals – Includes 1 input event transport lane

6.9.1.1.4 PDMA1 Features

The MAIN domain PDMA1 supports the following features:

Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)

ADVANCE□INFORMATION 238 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

Provides 1 memory write access unit (Write Unit 0): – Supports write bursts up to 32 bytes (limited by Tx Per-Channel FIFO depth) – Provides a 32-bit wide VBUSP write-only master interface for peripheral accesses – Supports up to 8 outstanding writes
Provides 1 memory read access unit (Read Unit 0): – Supports 1 outstanding read per interface (VBUSP) – Supports read burst up to 32 bytes (limited by Rx Per-Channel FIFO depth) – Provides a 32-bit wide VBUSP read-only master interface for peripheral accesses
Supports up to 23 simultaneous destination (Tx) channels
Supports up to 23 simultaneous source (Rx) channels
Supports static Transfer Requests (TRs) only
Supports MCAN special transfer mode
Provides per-channel buffering: – Provides 8x128-bit word deep data FIFO for each destination channel – Provides 8x128-bit word deep data FIFO for each source channel – Provides 128-bit wide PSI-L compliant data interface to remote UDMA and remote peripherals – Includes 1 output event transport lane – Provides 128-bit wide PSI-L compliant data interface from remote UDMA and remote peripherals – Includes 1 input event transport lane
Includes support for converting 16 local events to global events with corresponding mapping registers

6.9.1.1.5 PDMA_DEBUG Features

The Debug PDMA supports the following features:

Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)
Provides 0 memory write access units
Provides 1 memory read access unit (Read Unit 0): – Supports 1 outstanding read per interface (VBUSP) – Supports read burst up to 32 bytes (limited by Rx Per-Channel FIFO depth) – Provides a 64-bit wide VBUSP read-only master interface for peripheral accesses
Supports up to 0 simultaneous destination (Tx) channels
Supports up to 3 simultaneous source (Rx) channels
Supports static Transfer Requests (TRs) only
Supports MCAN special transfer mode
Provides per-channel buffering: – Provides 8x128-bit word deep data FIFO for each destination channel – Provides 8x128-bit word deep data FIFO for each source channel – Provides 128-bit wide PSI-L compliant data interface to remote UDMA and remote peripherals – Includes 1 output event transport lane – Provides 128-bit wide PSI-L compliant data interface from remote UDMA and remote peripherals – Includes 1 input event transport lane

6.9.1.2 PDMA Not Supported Features

The following unsupported features apply to all PDMA modules in the device:

Dynamic Transfer Requests are not supported
Cross Channel Triggering is not supported For more information, see section PDMA Controller in chapter DMA Controllers of the device TRM.

ADVANCE□INFORMATION 239 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

6.10 Peripherals

6.10.1 ADC

The analog-to-digital converter (ADC) module is an 8 channel general purpose analog-to-digital converter, which supports 12-bit conversion samples from an analog front end (AFE). There are total of two ADC modules in the device. Each ADC module has the following features:

8 channels
12-bit data
4 MSPS at 60 MHz sample clock
Programmable Finite State Machine (FSM) sequencer that supports 15 steps: – Software register bit for start of conversion – Optional start-of-conversion (SOC) synchronized to external hardware event – Single conversion (one-shot) – Continuous conversions – Sequence through all input channels based on a mask – Programmable open delay before sampling each channel – Programmable sampling delay for each channel – Programmable averaging of input samples - 16, 8, 4, 2, or 1 – Store data in either of two FIFO – 256-word 16-bit RAM – Option to encode channel number with data – Support for servicing FIFOs via DMA or CPU – Programmable DMA Request event (for each FIFO) – Dynamically enable or disable channel inputs during operation – Stop bit to end conversion – Support for error offset (internal calibration or external calibration via eFuse) inside the AFE
Support for the following interrupts and status, with masking: – Interrupt after a sequence of conversions (all non-masked channels) – Interrupt for FIFO threshold levels – Interrupt if sampled data is out of a programmable range – Interrupt for FIFO overflow and underflow conditions – Status bit to indicate if ADC is busy converting ADC Not Supported Features:
No packing of 16-bit FIFO data onto 32-bit DMA bus
No support for big endian
Support only 32-bit aligned read/write accesses on the MCU_CBASS0/DMA ports For more information, see section Analog-to-Digital Converter (ADC) in chapter Peripherals of the device TRM.

6.10.2 CPSW2G

The two-port Gigabit Ethernet switch subsystem (MCU_CPSW0) provides ethernet packet communication for the device and can be configured as an ethernet switch. MCU_CPSW0 features the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. The MCU_CPSW0 subsystem provides the following features:

ADVANCE□INFORMATION 240 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal (CPPI) port (port
Synchronous 10/100/1000 Mbit operation
Flexible logical FIFO-based packet buffer structure
Eight priority level Quality Of Service (QOS) support (802.1p)
Support for Audio/Video Bridging (P802.1Qav/D6.0)
Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F) – Timestamp module capable of time stamping external timesync events like Pulse-Per-Second and also generating Pulse-Per-Second outputs – CPTS module that supports time stamping for IEEE1588 with support for 4 hardware push events and generation of compare output pulses
DSCP Priority Mapping (IPv4 and IPv6)
Energy Efficient Ethernet (EEE) support (802.3az)
Priority Based Flow Control (802.1QBB) and Flow Control (802.3x) Support
Non Blocking switch fabric
Time Sensitive Network Support – IEEE P902.3br/D2.0 Interspersing Express Traffic – IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
Address Lookup Engine (ALE) – Configurable number of addresses plus VLANs – Wire rate lookup – Host controlled time-based aging and/or auto-aging – Spanning tree support – Multiple spanning tree support – L2 address lock and L2 filtering support – MAC authentication (802.1x) – Receive-based or destination-based Multicast and Broadcast rate limits – MAC address blocking – Source port locking – OUI (Vendor ID) host accept/deny feature – Configurable number of classifier/policers
VLAN support – 802.1Q compliant
Auto add port VLAN for untagged frames on ingress
Auto VLAN removal on egress and auto pad to minimum frame size
Ethernet Statistics: – EtherStats and 802.3Stats Remote network Monitoring (RMON) statistics gathering (per port) – Castagnoli or Ethernet CRC selectable per port – Ethernet Mac transmit to Ethernet Mac receive Loopback mode (digital loopback) supported – CPSGMII Loopback Modes (transmit to receive) – Maximum frame size of 2024 bytes – Management Data Input/Output (MDIO) module for PHY Management with Clause 45 support – Programmable interrupt control with selected interrupt pacing – Host port CPPI Streaming Packet Interface (CPPI_GCLK)
Flow Control Support (802.3x)
Digital loopback and FIFO loopback modes supported
Emulation support

ADVANCE□INFORMATION 241 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

Full duplex mode supported in 10/100/1000 Mbps. Half-duplex mode supported only in 10/100 Mbps modes only.
RAM Error Detection and Correction (SECDED) The following MCU_CPSW0 features are not supported:
Maximum frame size of 9600 bytes
MII/ GMII Mode
SGMII Mode
MACSEC
Synchronous Ethernet
Software reset
Ethernet Port Reset Isolation
Rate-limiting is not supported in half-duplex mode
Dual VLAN switch operations are not supported
Gigabit half-duplex mode is not supported (10/100 Mbps half-duplex mode is supported). For more information, see section Gigabit Ethernet Switch (MCU_CPSW0) in chapter Peripherals of the device TRM.

6.10.3 DCC

The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time execution of an application. Specifically, the DCC is expected to detect 2% drift from the expected frequency within 100ms time. Moreover, the exact accuracy can also be programed based on calculation for each application. In addition, the DCC can also measure the frequency of a selectable clock source using another input clock as a reference. The device has eleven instances of DCC modules. The DCC uses two independent clock sources to detect when one is out of spec. Each DCC module implements the following features:

Two independent counter blocks count clock pulses from each clock source
Each counter block is programmable, however, for proper operation the counters must be programmed with seed values that respect the ratio of the two clock frequencies
Configurable timebase for error signal
Error signal generation when one of the clocks is out of spec
Clock frequency measurement For more information, see section Dual Clock Comparator (DCC) in chapter Peripherals of the device TRM.

6.10.4 DDR Subsystem (DDRSS)

The DDR subsystem in this device comprises Synopsys DDR controller, Synopsys DDR PHY and wrapper logic to integrate these Synopsys blocks in the device. The DDR subsystem is referred to as DDRSS0 and is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. DDRSS0 is accessed via MSMC, and not directly through the system interconnect. The DDRSS0 supports:

Memory Types: – DDR3L – DDR4 – LPDDR4

ADVANCE□INFORMATION 242 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

Memory Bus Features: – 39-bit width with ECC (32 bits for data and 7 bits for ECC) – 1/2 width (22-bit) mode via software configuration – 1/4 width (13-bit) mode via software configuration – Up to 1 rank – SDRAM address range up to 32 GB
System Bus Interface: – 256-bit data width – Clock asynchronous to DDR clock – Little endian only – Address aliasing prevention to block accesses to unpopulated SDRAM region
Configuration Bus Interface: – 32-bit data width – Linear incrementing addressing mode – 32-bit aligned accesses only – Little endian only
Key Features: – Full coherency across all commands – Bank interleaving – Priority based scheduling – Scheduling based on bank openness – Class of Service (CoS)
Three latency classes supported
Programmable counters to tune CoS – Read/write scheduling to avoid turn-around time – Prioritized refresh scheduling – Dynamic change of refresh rate via software for extended temperatures – Statistical counters for performance management
ECC Features: – SECDED for 32-bit interface (39-bit with ECC)
Supported only for DDR4 – SECDED for 16-bit interface (22-bit with ECC)
Supported for DDR4 and LPDDR4 – SECDED for 8-bit interface (13-bit with ECC)
Supported only for DDR4 – Read-modify-write ECC for sub-word writes – ECC address error logging – Statistical counters for counting ECC errors – Injecting ECC errors during normal operation for validation – Automatic ECC scrub operation inside the Synopsys DDR Controller for any read command received which has led to a single-bit error.
At any time, only one outstanding ECC scrub operation is allowed inside the Synopsys DDR Controller

ADVANCE□INFORMATION 243 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

Low Power Features: – All power modes defined by JEDEC (clock stop for LPDDRx, self-refresh, power-down, etc.) – Self-refresh entry and exit via software or clock stop req/ack – System bus clock stop via clock stop request when controller is idle – Automatic idle power saving mode when no or low activity is detected – DDR and system bus clock frequency change using self-refresh via software or clock stop request – Turning off SoC power after DDR is put into self-refresh (DDR reset and CKE IO retention)
Functional Safety Features: – ECC on data – Parity on address and command – ECC on internal RAMs
DDR PHY Features: – Partial data macro use for ECC in 39-bit and 22-bit mode – Automatic and software controllable DDR-PHY and I/Os initialization and calibration (ZQ) – Automatic and software controllable delay line calibrations with voltage and temeprature (VT) compensation – Automatic and software controllable write levelling with VT compensation – Automatic read DQS gating training per rank with VT compensation – Automatic and software controllable DQ/DQS eye training per rank – Automatic and software controllable read and write data bit deskew – Automatic and software controllable Command/Address (CA) levelling with VT compensation for LPDDR4 – Automatic and software controllable CA bit deskew for LPDDR4 – Refreshes to SDRAM during leveling and training – Any bit in the byte lane as prime bit for write leveling and read trainings – No seeding requirement based on board topology for any of the leveling and training algorithms – Max channel length of 3 inches with controlled impedance for command and data channels – Dynamic/automatic I/O receiver disable when read transfer is not on going – Capability of disabling unused data macros and I/Os when not in use – Ability to keep DLL/PLL ON during stress/burn-in testing (BIST loopback with DLL/PLL operational but not used) DDRSS0 does not support the following:
4-bit wide DDR4 devices
UDIMMs
SODIMMs
RDIMMs
LRDIMMs
Address mirroring for DIMMs
Data bus obfuscation or any other kind of encryption
Automatic periodic scrubbing of SDRAM for ECC – Does not support the ECC Scrubber block provided by Synopsys for a fully automated flexible scrubbing solution
32-bit with ECC (39-bit) for LPDDR4
8-bit with ECC (13-bit) for LPDDR4
8-bit without ECC for LPDDR4
Two independent 16-bit channel operation for LPDDR4 For more information, see section DDR Subsystem (DDRSS) in chapter Peripherals of the device TRM.

ADVANCE□INFORMATION 244 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

6.10.5 ELM

The ELM is used with the GPMC. Syndrome polynomials generated on-the-fly when reading a NAND flash page and stored in GPMC registers are passed to the ELM. A host processor can then correct the data block by flipping the bits to which the ELM error-location outputs point. When reading from NAND flash memories, some level of error-correction is required. In the case of NAND modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is delegated to the memory controller. The General-Purpose Memory Controller (GPMC) probes data read from an external NAND flash and uses this to compute checksum-like information, called syndrome polynomials, on a per-block basis. Each syndrome polynomial gives a status of the read operations for a full block, including 512 bytes of data, parity bits, and an optional spare-area data field, with a maximum block size of 1023 bytes. Computation is based on a Bose-Chaudhuri-Hocquenghem (BCH) algorithm. The ELM extracts error addresses from these syndrome polynomials. Based on the syndrome polynomial value, the ELM can detect errors, compute the number of errors, and give the location of each error bit. The actual data is not required to complete the error-correction algorithm. Errors can be reported anywhere in the NAND flash block, including in the parity bits. The maximum acceptable number of errors that can be corrected depends on a programmable configuration parameter. 4-, 8-, and 16-bit error-correction levels are supported. The ELM depends on a static and fixed definition of the generator polynomial for each error-correction level that corresponds to the generator polynomials defined in the GPMC (there are three fixed polynomial for the three correction error levels). A larger number of errors than the programmed error-correction level may be detected, but the ELM cannot correct them all. The offending block is then tagged as uncorrectable in the associated computation exit status register. If the computation is successful, that is, if the number of errors detected does not exceed the maximum value authorized for the chosen correction capability, the exit status register contains the information on the number of detected errors. When the error-location process completes, an interrupt is triggered to inform the software that its status can be checked. The number of detected errors and their locations in the NAND block can be retrieved from the module through register accesses. The ELM has the following features:

4, 8, and 16 bits per 512-byte block error-location, based on BCH algorithms
Eight simultaneous processing contexts
Page-based and continuous modes
Interrupt generation on error-location process completion: – When the full page has been processed in page mode – For each syndrome polynomial in continuous mode. For more information, see section Error Location Module (ELM) in chapter Peripherals of the device TRM.

6.10.6 ESM

The Error Signaling Module (ESM) aggregates safety-related events and/or errors from throughout the device into one location. It can signal both low and high priority interrupts to a processor to deal with a safety event and/or manipulate an I/O error pad to signal an external hardware that an error has occurred. Therefore an external controller is able to reset the device or keep the system in a fail-safe state. The device has three instances of ESM modules. Each ESM module implements the following features:

Up to 1024 error event inputs – Implemented in groups of 32 events – Level or Pulse inputs (Pulse inputs are triple redundant)

ADVANCE□INFORMATION 245 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

Selectable low and high priority interrupt error pad prioritization of each error event
Error pad to signal severe device failure
Configurable timebase for error signal
Error forcing capability
Internal redundant flops on safety critical fields For more information, see section Error Signaling Module (ESM) in chapter Peripherals of the device TRM.

6.10.7 GPIO

The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an output, user can write to an internal register to control the state driven on the output pin. When configured as an input, user can obtain the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different interrupt/event generation modes. The device has three instances of GPIO144 modules. The GPIO pins are grouped into banks (16 pins per bank), which means that each GPIO module provides up to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIO0_[56:143], GPIO0_[96:143], and GPIO1_[90:143] are reserved in this Device, general purpose interface supports up to 242 pins. Each channel in the GPIO modules has the following features:

Supports 9 banks of 16 GPIO signals
Supports up to 9 banks of interrupt capable GPIOs
Interrupts: – Can enable interrupts for each bank of 16 GPIO signals – Interrupts can be triggered by rising and/or falling edge (or neither edge = disabled), specified for each interrupt capable GPIO signal
Set/clear functionality: – Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to another process during GPIO programming).
Separate Input/Output registers: – Output register in addition to set/clear so that if preferred by firmware, some GPIO output signals can be toggled by direct write to the output register(s). – Output register, when read in, reflects output drive status. This, in addition to the input register reflecting pin status and open-drain I/O cell, allows wired logic be implemented. GPIO do not support the following features: GPIO Not Supported Features:
The following apply to WKUP_GPIO0: – WKUP_GPIO0_[56:143] are not pinned out. – Interrupts [56:143] are not pinned out. – Bank Interrupts [8:4] are not pinned out.
The following apply to GPIO0: – GPIO0_[96:143] are not pinned out. – Interrupts [96:143] are not pinned out. – Bank Interrupts [8:6] are not pinned out.

ADVANCE□INFORMATION 246 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

The following apply to GPIO1: – GPIO1_[90:143] are not pinned out. – Interrupts [90:143] are not pinned out. – Bank Interrupts [8:6] are not pinned out. – GPI[10,77] buffer is output only. – Interrupt [10,77] buffer is output only. – GPO[12] buffer is input only. For more information, see section General-Purpose Interface (GPIO) in chapter Peripherals of the device TRM.

6.10.8 GPMC

The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external memory devices like:

Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash devices
NAND flash
Pseudo-SRAM devices The main features of the GPMC are:
8- or 16-bit-wide data path to external memory device
Supports up to 4 chip select regions of programmable size and programmable base addresses in a total address space of 1 GB
Supports on-the-fly error code detection using the Bose-ChaudhurI-Hocquenghem (BCH) (t = 4, 8, or 16) or Hamming code to improve the reliability of NAND with a minimum effect on software (NAND flash with 512-byte page size or greater)
Fully pipelined operation for optimal memory bandwidth usage
The clock to the external memory is provided from GPMC_FICLK divided by 1, 2, 3, or 4
Supports programmable autoclock gating when no access is detected
Independent and programmable control signal timing parameters for setup and hold time on a per-chip basis. Parameters are set according to the memory device timing parameters with a timing granularity of one GPMC_FICLK clock cycle.
Flexible internal access time control (wait state) and flexible handshake mode using external WAIT pin monitoring
Support bus keeping
Support bus turnaround
Prefetch and write posting engine associated with DMA controller at system level to achieve full performance from the NAND device with minimum effect on NOR/SRAM concurrent access
32-bit interconnect slave interface which supports non-wrapping and wrapping burst of up to 16x32 bits. The GPMC supports the following various access types:
Asynchronous read/write access
Asynchronous read page access (4, 8, and 16 Word16)
Synchronous read/write access
Synchronous read/write burst access without wrap capability (4, 8 and 16 Word16)
Synchronous read/write burst access with wrap capability (4, 8 and 16 Word16)
Address-data-multiplexed (AD) access
Address-address-data (AAD) multiplexed access

ADVANCE□INFORMATION 247 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

Little-endian access only The GPMC can communicate with a wide range of external devices:
External asynchronous or synchronous 8-bit wide memory or device (non burst device)
External asynchronous or synchronous 16-bit wide memory or device
External 16-bit non-multiplexed NOR flash device
External 16-bit address and data multiplexed NOR Flash device
External 8-bit and 16-bit NAND flash device
External 16-bit pseudo-SRAM (pSRAM) device The following features are not supported on this family of devices:
DMA mode is not supported.
WAIT[3:2] are not pinned out. All CS regions must use WAIT0 or WAIT1.
Asynchronous page write mode is not supported.
Multiple write access in asynchronous mode is not supported.
Multiple read is not supported in address/data-multiplexed and AAD-multiplexed modes. For more information, see section General-Purpose Memory Controller (GPMC) in chapter Peripherals of the device TRM.

6.10.9 HYPERBUS

The Hyperbus module is a part of the device Flash Subsystem (FSS). The Hyperbus module is low pin count memory interface that provides high read/write performance. The Hyperbus module connects to hyperbus memory (HyperFlash or HyperRAM) and uses simple hyperbus protocol for read and write transactions. There is one Hyperbus module inside the device. The Hyperbus module includes one HyperBus Memory Controller (HBMC). Hyperbus module supports the following features:

Support for Cypress®/Spansion® HyperFlash and HyperRAM
Up to 166 MHz maximum memory bus operation for reads – Support up to 166 MHz dual data rate (333 MBps) flash devices for system requiring rapid boot or instant-on displays – Support up to 333 MBps external pseudo-RAM (HyperRAM) for systems
Low pin count interface with LVCMOS I/O pins that may be muxed with other FSS interfaces (OSPIs)
Two memory chip selects
Linear incrementing mode for reads and writes
Up to 16 outstanding read transactions
Asynchronous bus clock Hyperbus Not Supported Features:
Cache-line wrap and fixed address modes for reads or writes
General Purpose Output register of the HBMC is not used For more information, see section Hyperbus Interface in chapter Peripherals of the device TRM.

6.10.10 I2C

The device contains six multimaster inter-integrated circuit (I2C) controllers each of which provides an interface between a local host (LH), such as an Arm and any I2C-bus-compatible device that connects via the I2C serial bus. External components attached to the I2C bus can serially transmit and receive up to 8 bits of data to and from the LH device through the 2-wire I2C interface.

ADVANCE□INFORMATION 248 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated Each multimaster I2C module can be configured to act like a slave or master I2C-compatible device. WKUP_I2C0 and MCU_I2C0 controllers have dedicated I2C compliant open drain buffers, and support Fast mode (up to 400 Kbps). I2C0, I2C1, I2C2, and I2C3 controllers are multiplexed with standard LVCMOS I/O and connected to emulate open drain. I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic 1. For the specific I/O timing characteristics of the different I2C instances, see the device-specific Data Manual. The multimaster I2C module has the following features:

Compliant with Philips I2C-bus specification version 2.1
Supports a standard mode (up to 100 Kbps) and fast mode (up to 400 Kbps)
7-bit and 10-bit device addressing modes
General call
Start/Restart/Stop
Multimaster transmitter/slave receiver mode
Multimaster receiver/slave transmitter mode
Built-in configurable FIFOs (8, 16, 32, 64 bytes) for buffered read or write
Module enable/disable capability
Programmable multislave channel (responds to four separate addresses)
Programmable clock generation
8-bit-wide data access
Designed for low power consumption
Implement Auto Idle mechanism
Implement Idle Request/Idle Acknowledge handshake mechanism
Support for asynchronous wakeup mechanism
Wide interrupt capability I2C Not Supported Features:
Serial Camera Control Bus (SCCB) Protocol
High-Speed (HS) Mode
DMA Mode
Full I2C electrical compliance only for MAIN domain I2C modules For more information, see section Inter-Integrated Circuit (I2C) Interface in chapter Peripherals of the device TRM.

6.10.11 MCAN

The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a high level of security. CAN has high immunity to electrical interference and the ability to self-diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire network, which provides for data consistency in every node of the system. The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices can coexist on the same network without any conflict. The device supports two MCAN modules - MCU_MCAN0 and MCU_MCAN1. They connect to the physical layer of the CAN network through external (for the device) transceivers. Each MCAN module supports flexible bit rates greater than 1 Mbps and is compliant to ISO 11898-1:2015. Each MCAN module implements the following features:

Conforms with CAN Protocol 2.0 A, B and ISO 11898-1:2015
Full CAN FD support (up to 64 data bytes)

ADVANCE□INFORMATION 249 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

AUTOSAR and SAE J1939 support
Up to 32 dedicated Transmit Buffers
Configurable Transmit FIFO, up to 32 elements
Configurable Transmit Queue, up to 32 elements
Configurable Transmit Event FIFO, up to 32 elements
Up to 64 dedicated Receive Buffers
Two configurable Receive FIFOs, up to 64 elements each
Up to 128 filter elements
Internal Loopback mode for self-test
Maskable interrupts, two interrupt lines
Two clock domains (CAN clock/Host clock)
Parity/ECC support - Message RAM single error correction and double error detection (SECDED) mechanism
Local power-down and wakeup support
Timestamp Counter
Using DCC module (used for MCAN clock domains monitoring, for more information, see ) MCAN subsystems do not support the following features:
Host bus firewall
GPIO mode
Clock calibration
External (IO) Loopback mode
Debug DMA (see )
TX DMA channels [31:3]
Extension interface signals (signals for indication of configuration change enable and interrupt register flags are not supported) For more information, see section Modular Controller Area Network (MCAN) in chapter Peripherals of the device TRM.

6.10.12 MCASP

The MCASP functions as a general-purpose audio serial port optimized to the requirements of various audio applications. The MCASP module can operate in both transmit and receive modes. The MCASP is useful for time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and transmission as well as for an intercomponent digital audio interface transmission (DIT). The MCASP has the flexibility to gluelessly connect to a Sony/Philips digital interface (S/PDIF) transmit physical layer component. Although intercomponent digital audio interface reception (DIR) mode (this is, S/PDIF stream receiving) is not natively supported by the MCASP module, a specific TDM mode implementation for the MCASP receivers allows an easy connection to external DIR components (for example, S/PDIF to I2S format converters). The device have integrated three MCASP modules with:

MCASP0 supporting up to 16 channels with independent TX/RX clock/sync domain
MCASP1 supporting up to 10 channels with independent TX/RX clock/sync domain
MCASP2 supporting up to 4 channels with independent TX/RX clock/sync domain MCASP module includes the following main features:
Independent serializer for each AXRx channel of each MCASP module.
Clock stop request/acknowledge protocol

ADVANCE□INFORMATION 250 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

A single 32-bit buffer per serializer for transmit and receive operations
1 x interconnect interface port for CBASS0
Two independent clock generator modules for transmit and receive. – Clocking flexibility allows the MCASP to receive and transmit at different rates. For example, the MCASP can receive data at 48 kHz but output up-sampled data at 96 kHz or 192 kHz.
MCASP module functional clock can be generated: – internally (master mode) – supplied over MCASP serial interface (slave mode) – has a controllable functional clock divide ratio
Independent transmit and receive modules, each includes: – Programmable clock and frame sync generator. – TDM streams from 2 to 32, and 384 time slots. – Support for time slot sizes of 8, 12, 16, 20, 24, 28, and 32 bits. – Data formatter for bit manipulation.
Glueless connection to audio analog-to-digital converters (ADC), digital-to-analog converters (DAC), codec, digital audio interface receiver (DIR), and S/PDIF transmit physical layer components.
Wide variety of I2S and similar bit-stream format.
Integrated digital audio interface transmitter (DIT): – S/PDIF, IEC60958-1, AES-3 formats. – Enhanced channel status/user data RAM.
384-slot TDM with external digital audio interface receiver (DIR) device. – For DIR reception, an external DIR receiver integrated circuit should be used with I2S output format and connected to the MCASP receive section.
Support for 2x DMA requests (one per direction): – 1 level-sensitive transmit direct memory access (DMA) request common for all of the MCASP serializers – 1 level-sensitive receive direct memory access (DMA) request common for all of the MCASP serializers – All transmit DMA requests are mapped to the device DMA controllers
One transmit interrupt request common for all serializers
One receive interrupt request common for all serializers
Each of the Rx and Tx interrupts is propagated to different host processors via the device Interrupts NOTE Because a serializer receive and transmit channels data is shared on the same MCASP data pin, user can choose to have either Tx or Rx function from a serializer, not both at the same time. The MCASP module does not support the following features:
Muting output (AMUTE)
Muting input (AMUTEIN) For more information, see section Multi-channel Audio Serial Port (McASP) in chapter Peripherals of the device TRM.

ADVANCE□INFORMATION 251 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

6.10.13 MCRC Controller

VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the integrity of a memory system. A signature representing the contents of the memory is obtained when the contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate the signature for a set of data and then compare the calculated signature value against a pre- determined good signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC controller compresses each data being read through CPU read data bus. MCRC has the following features:

Four channels to perform background signature verification on any memory subsystem
Data compression on 8-, 16-, 32-, and 64-bit data size
Maximum-length PSA (Parallel Signature Analysis) register constructed based on 64-bit primitive polynomial
Each channel has a CRC Value Register which contains the pre-determined CRC value
Use timed base event trigger from timer to initiate DMA data transfer
Programmable 20-bit pattern counter per channel to count the number of data patterns for compression
Three modes of operation: – Auto – Semi-CPU – Full-CPU
For each channel, CRC can be performed either by MCRC Controller or by CPU
Automatically performs signature verification without CPU intervention in AUTO mode
Generates interrupt to CPU in Semi-CPU mode to allow CPU to perform signature verification itself
Generates CRC fail interrupt in AUTO mode if signature verification fails
Generates Timeout interrupt if CRC is not performed within the time limit
Generates DMA request per channel to initiate CRC value transfer
An 128-byte block burst address for the PSA register to DMA without constant mode bus attribute For more information, see section MCRC Controller in chapter Interprocessor Communication of the device TRM.

6.10.14 MCSPI

The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus. There are total of eight MCSPI modules in the device. MCSPI3 and MCSPI4 include internal connectivity to MCSPI modules in the MCU domain, as follows:

MCSPI3 is connected as a master to MCU_MCSPI1 by default at power-up. MCU_MCSPI1 and MCSPI3 may be optionally mapped to external device pads.
MCSPI4 is directly connected as a slave to MCU_MCSPI2 by default at power-up. MCSPI4 and MCU_MCSPI2 are not pinned out externally. The MCSPI modules include the following main features:
Serial clock with programmable frequency, polarity, and phase for each channel
Wide selection of MCSPI word lengths, ranging from 4 to 32 bits
Up to four master channels, or single channel in slave mode

ADVANCE□INFORMATION 252 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

Master multichannel mode: – Full duplex/half duplex – Transmit-only/receive-only/transmit-and-receive modes – Flexible input/output (I/O) port controls per channel – Programmable clock granularity – MCSPI configuration per channel. This means, clock definition, polarity enabling and word width
Single interrupt line for multiple interrupt source events
Enable the addition of a programmable start-bit for MCSPI transfer per channel (start-bit mode)
Supports start-bit write command
Supports start-bit pause and break sequence
Programmable shift operations (1-32 bits)
Programmable timing control between chip select and external clock generation
Built-in FIFO available for a single channel. The following features are not supported on this family of devices:
Slave mode wake-up
Retention during power down
MCU_MCSPI2 and MCSPI4 are not pinned out. For more information, see section Multichannel Serial Peripheral Interface (MCSPI) in chapter Peripherals of the device TRM.

6.10.15 MMC/SD

There are two MMCSD modules inside the device - MMCSD0 and MMCSD1. Each MMCSD module includes one MMCSD Host Controller. Each controller has the following data width:

MMCSD0 - 8-bit wide data bus
MMCSD1 - 4-bit wide data bus The MMCSD Host Controller provides an interface to eMMC 5.1 (embedded MultiMedia Card), SD 4.10 (Secure Digital), and SDIO 4.0 (Secure Digital IO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking for syntactical correctness. Each MMCSD Host Controller supports:
eMMC5.1 Host Specification (JESD84-B51)
SD Host Controller Standard Specification 4.10
Integrated DMA controller supporting SD Advanced ADMA2 and ADMA3 (for more information about ADMA support, see , Advanced DMA)
High Voltage eMMC – operating voltage range: 3.0 V - 3.6 V
Dual Voltage eMMC – operating voltage range: 1.70 V - 1.95 V, 3.0 V - 3.6 V
System Bus Interface: – 64-bit data width (master interface) – 64-bit address – Clock asynchronous to MMCSD clock (MMCi_CLK) – Little endian only

ADVANCE□INFORMATION 253 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

Configuration Bus Interface: – 32-bit data width (slave interface) – Linear incrementing addressing mode – 32-bit aligned accesses only – Little endian only MMCSD0 Host Controller: MultiMedia Card Support: – eMMC Electrical Standard 5.1 (JESD84-B51) – Backward compatible with earlier eMMC standards – Legacy MMC card SDR:
3.3 V/1.8 V, 8-bit bus width, 0-26 MHz, 26 MBps
3.3 V/1.8 V, 4-bit bus width, 0-26 MHz, 13 MBps
3.3 V/1.8 V, 1-bit bus width, 0-26 MHz, 3.25 MBps – High Speed SDR:
3.3 V/1.8 V, 8-bit bus width, 0-52 MHz, 52 MBps
3.3 V/1.8 V, 4-bit bus width, 0-52 MHz, 26 MBps
3.3 V/1.8 V, 1-bit bus width, 0-52 MHz, 6.5 MBps – High Speed DDR:
3.3 V/1.8 V, 8-bit bus width, 0-52 MHz, 104 MBps
3.3 V/1.8 V, 4-bit bus width, 0-52 MHz, 52 MBps – HS200 SDR:
1.8 V, 0-200 MHz, 8-bit bus width, 200 MBps
1.8 V, 0-200 MHz, 4-bit bus width, 100 MBps Secure Digital Card Support: – Backward compatible with earlier SD card specifications – SD Physical Layer Specification v3.01 – SDIO support – SDIO Specification v3.00 – High Voltage SD memory card – operating voltage range: 3.0 V - 3.6 V – Default Speed mode: 3.3 V signaling, frequency up to 25 MHz, up to 12.5 MBps – High Speed mode: 3.3 V signaling, frequency up to 50 MHz, up to 25 MBps – SDR12: UHS-I 1.8 V signaling, frequency up to 25 MHz, up to 12.5 MBps – SDR25: UHS-I 1.8 V signaling, frequency up to 50 MHz, up to 25 MBps – SDR50: UHS-I 1.8 V signaling, frequency up to 100 MHz, up to 50 MBps – SDR104: UHS-I 1.8 V signaling, frequency up to 208 MHz, up to 104 MBps – DDR50: UHS-I 1.8 V signaling, frequency up to 50 MHz, up to 50 MBps MMCSD1 Host Controller: MultiMedia Card Support: – eMMC Electrical Standard 5.1 (JESD84-B51) – Backward compatible with earlier eMMC standards – Legacy MMC card SDR:
3.3 V/1.8 V, 4-bit bus width, 0-26 MHz, 13 MBps
3.3 V/1.8 V, 1-bit bus width, 0-26 MHz, 3.25 MBps – High Speed SDR:
3.3 V/1.8 V, 4-bit bus width, 0-52 MHz, 26 MBps
3.3 V/1.8 V, 1-bit bus width, 0-52 MHz, 6.5 MBps – High Speed DDR:

ADVANCE□INFORMATION 254 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

3.3 V/1.8 V, 4-bit bus width, 0-52 MHz, 52 MBps – HS200 SDR:
1.8 V, 0-200 MHz, 4-bit bus width, 100 MBps Secure Digital Card Support: – Backward compatible with earlier SD card specifications – SD Physical Layer Specification v3.01 – SDIO support – SDIO Specification v3.00 – High Voltage SD memory card – operating voltage range: 3.0 V - 3.6 V – Default Speed mode: 3.3 V signaling, frequency up to 25 MHz, up to 12.5 MBps – High Speed mode: 3.3 V signaling, frequency up to 50 MHz, up to 25 MBps – SDR12: UHS-I 1.8 V signaling, frequency up to 25 MHz, up to 12.5 MBps – SDR25: UHS-I 1.8 V signaling, frequency up to 50 MHz, up to 25 MBps – SDR50: UHS-I 1.8 V signaling, frequency up to 100 MHz, up to 50 MBps – SDR104: UHS-I 1.8 V signaling, frequency up to 208 MHz, up to 104 MBps – DDR50: UHS-I 1.8 V signaling, frequency up to 50 MHz, up to 50 MBps MMCSD Not Supported Features: MMCSD0 Host Controller:
MultiMedia Card: – 3.0 V and 1.2 V
Secure Digital Card – SD Specifications Part 1 Physical Layer Simplified Specification v4.01 – UHS-II SD Memory Card – Operating voltage range VDD1: 2.7 V - 3.6 V, VDD2: 1.70 V - 1.95 V – UHS156: UHS-II RCLK Frequency Range 26 MHz - 52 MHz, up to 1.56 Gbps per lane MMCSD1 Host Controller:
MultiMedia Card – 3.0 V and 1.2 V – Legacy MMC card SDR: 1.8 V, 8-bit bus width, 0-26 MHz, 26 MBps – High Speed SDR: 1.8 V, 8-bit bus width, 0-52 MHz, 52 MBps – High Speed DDR: 1.8 V, 8-bit bus width, 0-52 MHz, 104 MBps – HS200 SDR: 1.8 V, 0-200 MHz, 8-bit bus width, 200 MBps
Secure Digital Card – SD Specifications Part 1 Physical Layer Simplified Specification v4.01 – UHS-II SD Memory Card – Operating voltage range VDD1: 2.7 V - 3.6 V, VDD2: 1.70 V - 1.95 V – UHS156: UHS-II RCLK Frequency Range 26 MHz - 52 MHz, up to 1.56 Gbps per lane For more information, see section Multimedia Card/Secure Digital (MMC/SD) Interface in chapter Peripherals of the device TRM.

6.10.16 OSPI

The Octal Serial Peripheral Interface (OSPI™ ) module is a kind of Serial Peripheral Interface (SPI) module which allows single, dual, quad or octal read and write access to external flash devices. This module has a memory mapped register interface, which provides a direct memory interface for accessing data from external flash devices, simplifying software requirements.

ADVANCE□INFORMATION 255 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor wishing to execute code directly from external flash memory), or in an indirect mode where the module is set-up to silently perform some requested operation, signalling its completion via interrupts or status registers. For indirect operations, data is transferred between system memory and external flash memory via an internal SRAM which is loaded for writes and unloaded for reads by a device master at low latency system speeds. Interrupts or status registers are used to identify the specific times at which this SRAM should be accessed using user programmable configuration registers. The OSPI modules have the following features:

Support for single, dual, quad (QSPI mode) or octal (on MCU_FSS0_OSPI0 only) I/O instructions.
Support dual Quad-SPI mode for fast boot applications.
Memory mapped ‘direct’mode of operation for performing flash data transfers and executing code from flash memory.
Software triggered 'indirect' mode of operation for performing low latency and non-processor intensive flash data transfers.
Local SRAM of configurable size to reduce advanced high-performance bus overhead and buffer flash data during indirect transfers.
Set of software advanced peripheral bus accessible flash control registers to perform any flash command, including data transfers up to 8-bytes at a time.
Additional addressable Memory Bank to accommodate more than 8-bytes at a time.
Supports any device clock frequency, including frequencies of: – 166 MHz SDR or 200 MHz DDR (with DQS) for Octal-SPI devices – 133 MHz SDR or 70 MHz DDR for Quad-SPI devices
Support for XIP (Execute in Place), sometimes referred to as continuous mode.
Support for DDR Mode and DTR protocol (including Octal DDR protocol with DQS for Octal-SPI devices)
Programmable device sizes.
Programmable write protected regions to block system writes from taking effect.
Programmable delays between transactions.
Legacy mode allowing software direct access to low level transmit and receive FIFOs, bypassing the higher layer processes.
An independent reference clock to decouple bus clock from SPI clock – allows slow system clocks.
Programmable baud rate generator to generate OSPI clocks.
Features included to improve high speed read data capture mechanism.
Option to use adapted clocks or DQS to further improve read data capturing.
Programmable interrupt generation.
Up to four external device selects - OSPI and QSPI devices can be mixed: – MCU_FSS0_OSPI0 has four chip-selects – MCU_FSS0_OSPI1 has two chip-selects.
Programmable data decoder, enables continuous addressing mode for each of connected devices and auto-detection of boundaries between devices.
Support BOOT mode.
Support for data safety mechanisms: – Bidirectional CRC on Multiple-SPI interface. – Handling ECC errors for flash devices with embedded correction engine.
Full integration with PHY module dedicated to more flexible and power efficient transfers. The following features are not supported on this family of devices:
OSPI1_D[7:4] are not pinned out.

ADVANCE□INFORMATION 256 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

OSPI1_SCn[3:2] are not pinned out.
DMA not supported.
Pulse events not used.
In Octal-SPI mode, Mode 1 and 2 are not supported. In Mode 3 DDR is not supported.
In Quad-SPI mode, Mode 1 and 2 are not supported. In Mode 3 DDR is not supported. For more information, see section Octal Serial Peripheral Interface (OSPI) in chapter Peripherals of the device TRM.

6.10.17 PCIE

The Peripheral Component Interconnect Express (PCIe) subsystem is built around a multi-lane dual-mode PCIe controller that provides low pin-count, high reliability, and high-speed data transfers at rates of up to 8.0 Gbps per lane for serial links on backplanes and printed wiring boards. The device includes two instantiations of PCIe subsystem named PCIE0 and PCIE1. Each PCIe subsystem supports the following main features: The PCIe subsystems do not support the following features:

Compliance to PCIe® Base Specification, Revision 3.1
One or two-lane configuration with up to 8.0 Gbps/lane (Gen3/Gen2) – PCIE0 used as 2-lane controller, configurable in 1x1 or 1x2 mode – PCIE1 used as 1-lane controller configured in 1x1 mode
Gen3 (8 Gbps 128/130-bit encoding), Gen2 (5 Gbps 8/10-bit encoding) and Gen1 (2.5 Gbps 8/10-bitb encoding) with auto-negotiation
Dynamic width conversion when switching between Gen1/2/3 modes
Root Complex (RC) or End Point (EP) operation modes
Maximum outbound payload size of 128 bytes
Maximum inbound payload size of 256 bytes
Maximum remote read request size of 4K bytes
Ultra-low transmit and receive latency
Automatic lane reversal as specified in the PCIe 3.0 specification (transmit and receive)
Polarity inversion on receive
One Physical Functions (PF), One Virtual Function (VF)
Single function in End Point (EP) mode
Four virtual channels (VC)
Four traffic classes (TC)
Automatic credit management
ECRC generation and checking
PCI Device Power Management states D0, D1, D3Hot and D3Cold with the exception of D3 cold with Vaux
PCIe Active State Power Management (ASPM) state L0s and L1 (with exceptions)
PCIe Link Power Management states, except L2 state
PCIe Advanced Error Reporting
PCIe messages for both transmit and receive
Filtering for Posted, Non-posted, and Completion traffic
Configurable BAR filtering, I/O filtering, configuration filtering, and completion lookup/timeout
Access to configuration space registers and external application memory-mapped registers through BAR0 and through configuration access
Legacy interrupts reception (in RC mode) and generation (in EP mode)

ADVANCE□INFORMATION 257 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

MSI-X generation and reception
Precision Time Measurement in combination with time-stamp (CPTS) module
Quality-of-Service (QoS) mechanism by enabling priority or round-robin arbitration on VCs
Two host bus master interfaces for high and low priority traffic mapped to four virtual channels
PCIe compliant PHY (PIPE 4.0) interface for connection to a SERDES based PHY The PCIe subsystems do not support the following features:
PCIe beacon for in-band wake
Vendor Messaging
I/O access in inbound direction in RC or EP mode
Single-root I/O Virtualization (SR-IOV)
Address Translation Services (ATS)
Addressing modes other than incremental for burst transactions. As a result, the PCIe addresses cannot be in cacheable memory space. For more information, see section Peripheral Component Interconnect Express (PCIe) Subsystem in chapter Peripherals of the device TRM.

6.10.18 SerDes

SerDes goal is to convert device (SoC) parallel data into serialized data that can be output over a high- speed electrical interface. In the opposite direction, SerDes converts high-speed serial data into parallel data that can be processed by the device. To this end, the SerDes contains a variety of functional blocks to handle both the external analog interface as well as the internal digital logic. The device contains two SerDeses. Most important building blocks of SerDes are:

Lanes: The lanes handle all inputs and outputs from the serial interface, and contain the Tx/Rx I/Os, serializer/deserializer, and Clock and Data Recovery (CDR) unit.
Clock Multiplier Unit (CMU): The CMU handles peripheral and Tx clocking of the SerDes. It consists of an internal PLL and the reference clock input buffers.
Physical Coding Sub-block (PCS): The PCS is responsible for translating data from/to the parallel interface, as well as data encoding/decoding and symbol alignment.
WIZ: The WIZ acts as a wrapper for the SerDes, and can both send control signals to and report status signals from the SerDes, and muxes SerDes to peripherals. The SERDES PHY module features include:
Single lane PHY containing: – Transmit and Receive I/Os – Serializer – Deserializer – Clock and data recovery (CDR) unit
Clock Multiplying Unit (CMU) – PLLs – Master bias – Termination calibration – Reference clock input buffers

ADVANCE□INFORMATION 258 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

Physical Coding Sub-block (PCS) – 8b/10b encoder/decoder (PCIe 1 and PCIe 2) – 128b/130b encoder/decoder (PCIe 3) – Symbol alignment – Polarity inversion – Bit stream reordering
Physical Media Attachment (PMA) layer – Transmit equalization – Receive equalization The SERDES mux (WIZ) module supports the following features:
Multiplexes device interfaces onto a single SERDES lane (one Tx and one Rx)
Provides registers to implement SERDES control and status functions and alignment delays
Clock generator block for providing MAC transmit clock
Rx comma align block – Performs de-stuffing the Rx data stream in the event that the Rx rate is different from the Tx rate – Supports comma detection that is not sensitive to false commas using all 8B10B character combinations For more information, see section Serializer/Deserializer (SerDes) in chapter Peripherals of the device TRM.

6.10.19 Timers

There are sixteen timer modules in the device. All timers include specific functions to generate accurate tick interrupts to the operating system. Each timer can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz clock. The selection of clock source is made from registers in the MCU_CTRL_MMR0/CTRL_MMR0. In the MCU domain the device provides 2 timer pins to be used as MCU Timer Capture inputs or as MCU Timer PWM outputs. In order to provide maximum flexibility, these 2 pins may be used with any of MCU_TIMER0 through MCU_TIMER3 instances. System level muxes are used to control the capture source pin for each MCU_TIMER[3-0] and the MCU_TIMER[3-0] source for each MCU_TIMER_IO[1-0] PWM output. In the MAIN domain the device provides 8 timer pins to be used as Timer Capture inputs or as Timer PWM outputs. For maximum flexibility, these 8 pins may be used with any of TIMER0 through TIMER11 instances. System level muxes are used to control the capture source pin for each TIMER[11-0] and the TIMER[11-0] source for each TIMER_IO[7-0] PWM output. Each odd numbered timer instance from each of the domains may be optionally cascaded with the previous even numbered timer instance from the same domain to form up to a 64-bit timer. For example, TIMER1 may be cascaded to TIMER0, MCU_TIMER1 may be cascaded to MCU_TIMER0, etc. When cascaded, TIMERi acts as a 32-bit prescaler to TIMERi+1, as well as MCU_TIMERn acts as a 32- bit prescaler to MCU_TIMERn+1. TIMERi / MCU_TIMERn must be configured to generate a PWM output edge at the desired rate to increment the TIMERi+1/ MCU_TIMERn+1 counter. For more information, see section Timers in chapter Peripherals of the device TRM.

6.10.20 UART

The UART is a slave peripheral that utilizes the DMA for data transfer or interrupt polling via host CPU. There are five UART modules in the device. All UART modules support IrDA and CIR modes when 48 MHz function clock is used. Each UART can be used for configuration and data exchange with a number of external peripheral devices or interprocessor communication between devices.

ADVANCE□INFORMATION 259 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated The UART include the following features:

16C750-compatible
RS-485 external transceiver auto flow control support
64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
Programmable interrupt trigger levels for FIFOs
Programmable sleep mode
The 48 MHz functional clock option allows baud rates up to 3.6Mbps
The 192 MHz functional clock option allows baud rates up to 12Mbps
Auto-baud between 1200 bits/s and 115.2 Kbits/s (only when 48 MHz function clock is used)
Optional multi-drop transmission
Configurable time-guard feature
Configurable data format: – Data bit: 5, 6, 7, or 8 bits – Parity bit: Even, odd, none – Stop-bit: 1, 1.5, 2 bit(s)
Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
False start bit detection
Line break generation and detection
Fully prioritized interrupt system controls
Internal test and loopback capabilities
Modem control functions (CTS, RTS)
USART0 module in MAIN domain has extended modem control signals (DCD, RI, DTR, DSR) The IrDA includes the following features:
Support of IrDA 1.4 slow infrared (SIR), medium infrared (MIR), and fast infrared (FIR) communications: – Slow infrared (SIR 115.2 KBAUD), medium infrared (MIR 0.576 MBAUD) and fast infrared (FIR 4.0 MBAUD) operations (very fast infrared (VFIR) is not supported) – Frame formatting: Addition of variable beginning-of-frame (xBOF) characters and end-of-frame (EOF) characters – Uplink/downlink cyclic redundancy check (CRC) generation/detection – Asynchronous transparency (automatic insertion of break character) – Eight-entry status FIFO (with selectable trigger levels) to monitor frame length and frame errors – Framing error, CRC error, illegal symbol (FIR), and abort pattern (SIR, MIR) detection
IrDA mode when 48 MHz function clock is used The CIR mode uses a variable pulse-width modulation (PWM) technique (based on multiples of a programmable t period) to encompass the various formats of infrared encoding for remote-control applications. The CIR logic transmits data packets based on a user-definable frame structure and packet content. The CIR includes the following features to provide CIR support for remote-control applications:
Transmit and receive mode
Free data format (supports any remote-control private standards)
Selectable bit rate
Configurable carrier frequency
1/2, 5/12, 1/3, or 1/4 carrier duty cycle
CIR mode when 48 MHz function clock is used UART Not Supported Features:

ADVANCE□INFORMATION 260 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Detailed Description Copyright © 2018, Texas Instruments Incorporated

Synchronous mode
ISO7816 mode For more information, see section Universal Synchronous/Asynchronous Receiver/Transmitter (UART) in chapter Peripherals of the device TRM.

6.10.21 USB

Similar to earlier versions of USB bus, USB 3.0 is a general-purpose cable bus, supporting data exchange between a host device and a wide range of simultaneously accessible peripherals. The device supports two USB subsystems, both instantiated in the MAIN system domain:

USB3SS0 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0) PHY and HS/FS (USB2.0) PHY
USB3SS1 is HighSpeed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS (USB2.0) PHY The USB subsystem, supports the following USB features:
General features: – Supports Peripheral (aka Device) mode at Superspeed (5 Gbps), Highspeed (480 Mbps), and Fullspeed (12 Mbps) – Supports Host mode at Superspeed (5 Gbps), Highspeed (480 Mbps), Fullspeed (12 Mbps), and Lowspeed (1.5 Mbps) – Static peripheral operation – Static host operation – Limited OTG 2.0 functionality in conjunction with an VBUS/ID analog comparator detection circuit and software handshake – Host Negotiation Protocol (HNP) support in conjunction with an ID comparator detection circuit and software handshake – Accessory Charger Adapter (ACA) support via ID-pin comparator – External Buffer Control (EBC) mode for IN (Tx) Endpoints 14 and 15
Each controller instance contains single xHCI with the following features: – Compatible to the xHCI specification (revision 1.1) in Host mode – Supports 15 Transmit (TX), 15 Receive (RX) endpoints (EPs), and one EP0 endpoint which is bidirectional – Internal DMA controller – Interrupt moderation and blocking – Supports for all USB transfer modes - Control, Bulk, Interrupt, and Isochronous – Supports high bandwidth ISO mode – Descriptor caching and data pre-fetching used to improve system performance – Dynamic FIFO memory allocation for all endpoints – USB power saving states (U0, U1, U2, and U3) – Asynchronous wakeup signal for remote wakeup
Operation flexibility: – Uniform programming model for SS, HS, FS, and LS operation – Multiple interrupt lines:
16 interrupts associated with 16 programmable Event Rings for multi-core support
Interrupt lines for all miscellaneous events
Functional safety: – Internal RAM with ECC – Loopback on USB3 PHY (SerDes)

ADVANCE□INFORMATION 261 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Detailed DescriptionCopyright © 2018, Texas Instruments Incorporated

External requirements: – An external charge pump or power switch for VBUS 5 V generation – An external circuitry or PMIC to start the battery charging upon Battery Charger (BC) detected event – An external reference clock input for USB PHY operation – An external high-precision resistor for PHY termination calibration The following are USB features which are not supported in current device:
OTG 3.0 functionality
HSIC (High Speed inter-chip) and SSIC interface
ULPI Interface for external PHY
SRP and ADP protocols
External Buffer Control (EBC) for OUT (Rx) Endpoint
Hibernation For more information, see section Universal Serial Bus (USB) Subsystem in chapter Peripherals of the device TRM.

ADVANCE□INFORMATION A B MCU_OSPI[x]_CLK OSPI/QSPI/SPI device clock input OSPI/QSPI/SPI device IOy, CS# MCU_OSPI[x]_D[y], MCU_OSPI[x]_CSn[z] 0 * Ω OSPI_Board_01 262 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Applications, Implementation, and Layout Copyright © 2018, Texas Instruments Incorporated

7 Applications, Implementation, and Layout

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test design implementation to confirm system functionality.

7.1 DDR Board Design and Layout Guidelines

The goal of the DDR3L, DDR4, and LPDDR4 Board Design and Layout Guidelines Application Report (SPRACI2) is to make the DDR3L, DDR4, and LPDDR4 system implementation straightforward for all designers. Requirements have been distilled down to a set of layout and routing rules that allow designers to successfully implement a robust design for the topologies that TI supports. TI only supports board designs using DDR3L, DDR4, and LPDDR4 memories that follow the guidelines in this document.

7.2 OSPI Board Design and Layout Guidelines

The following section details the routing guidelines that must be observed when routing the OSPI interfaces.

7.2.1 No Loopback & Internal Pad Loopback

The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450pS (~7cm as stripline or ~8cm as microstrip)
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 7-1
Propagation delays and matching: – A to B < 450ps – Matching skew: < 60pS Figure 7-1. OSPI Interface High Level Schematic NOTE *0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.

ADVANCE□INFORMATION 263 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Applications, Implementation, and LayoutCopyright © 2018, Texas Instruments Incorporated

7.2.2 External Board Loopback

The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) should be approximately equal to half of the signal propagation delay from the MCU_OPSI[x]_LBCLKO pin to the MCU_OSPI[x]_DQS pin ((C to D)/2). See CAUTION note below.
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) must be approximately equal to the signal propagation delay of the control and data signals between the flash device and the SoC device (E to F, or F to E)
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 7-2
Propagation delays and matching: – A to B = E to F = (C to D) / 2 – Matching skew: < 60pS CAUTION The OSPI Board Loopback Hold time requirement (described in Section 5.11.5.12, OSPI) is larger than the Hold time provided by a typical flash device. Therefore, the length of MCU_OPSI[x]_LBCLKO pin to the MCU_OSPI[x]_DQS pin (C to D) may need to be shortened to compensate.

ADVANCE□INFORMATION A B E F MCU_OSPI[x]_CLK OSPI/QSPI/SPI device clock input OSPI/QSPI/SPI device IOy, CS# MCU_OSPI[x]_D[y], MCU_OSPI[x]_CSn[z] 0 * Ω OSPI_Board_02 C D MCU_OSPI[x]_LBCLKO MCU_OSPI[x]_DQS 0 * Ω 264 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Applications, Implementation, and Layout Copyright © 2018, Texas Instruments Incorporated Figure 7-2. OSPI Interface High Level Schematic NOTE *0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK and MCU_OSPI[x]_LBCLKO pins, is placeholder for fine tuning, if needed

7.2.3 DQS (only available by Octal Flash devices)

The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
The DQS pin of the flash devices must be connected to MCU_OSPI[x]_DQS signal
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) should be approximately equal to the signal propagation delay from the MCU_OSPI[x]_DQS pin to the DQS output pin (C to D)
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 7-3
Propagation delays and matching: – A to B = C to D – Matching skew: < 60pS

ADVANCE□INFORMATION A B MCU_OSPI[x]_CLK OSPI/QSPI/SPI device clock input 0 * Ω OSPI_Board_03 C D MCU_OSPI[x]_DQS OSPI device DQS 265 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Applications, Implementation, and LayoutCopyright © 2018, Texas Instruments Incorporated Figure 7-3. OSPI Interface High Level Schematic NOTE *0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.

7.3 High Speed Differential Signal Routing Guidance

The High-Speed Interface Layout Guidelines Application Report (SPRAAR7) available from http://www.ti.com/lit/pdf/spraar7 provides guidance for successful routing of the high speed differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and spacing limits. TI supports only designs that follow the board design guidelines contained in the application report.

7.4 USB Design Guidelines

The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as 20 V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to be 30 V. The DRA80x device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in the Figure 7-4), which limits the voltage applied to the actual device pin (USB0_VBUS, USB1_VBUS). The tolerance of these external resistors should be equal to or less than 1%, and the leakage current of zener diode at 5 V should be less than 100 nA.

ADVANCE□INFORMATION Device USBn_VBUS SPRSP08_USB_VBUS_01 VSS VSS 76.8 k Ω 23.2 k Ω 16 k Ω VBUS signal 266 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Applications, Implementation, and Layout Copyright © 2018, Texas Instruments Incorporated Figure 7-4. USB VBUS Detect Voltage Divider / Clamp Circuit(1) (1) USBn_VBUS, where n = 0 or 1. The USB0_VBUS and USB1_VBUS pins may be considered to be fail-safe because the external circuit in Figure 7-4 limits the input current to the actual device pin in a case where VBUS is applied while the device is powered off.

7.5 Power Distribution Network Implementation Guidance

The Sitara Processor Power Distribution Networks: Implementation and Analysis (SPRAC76) available from http://www.ti.com/lit/pdf/sprac76 provides guidance for successful implementation of the power distribution network. This includes PCB stackup guidance as well as guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only designs that follow the board design guidelines contained in the application report.

7.6 External Capacitors

Figure 7-5 shows an example of the external decoupling capacitor connections.

ADVANCE□INFORMATION Device VDD_MPU1 VDD_MPU0 VDD_CORE VDDA_ADC_MCU VDDA_3P3_IOLDO_WKUP VDDSHV0_WKUP VDDSHV1_WKUP VDDSHV2_WKUP VDDA_LDO_WKUP VDDA_1P8_OLDI0 VDDA_1P8_CSI0 VDDS_OSC1 VDDA_1P8_SERDES0 VDDA_3P3_USB VDDA_PLL0_DDR VDDA_PLL1_DDR VDDA_PLL_CORE VDDA_PLL_PER0 VDDA_PLL_DSS VDDA_SRAM_CORE0 VDDA_SRAM_CORE1 VDDA_PLL_MPU0 VDDA_SRAM_MPU0 VDDA_PLL_MPU1 VDDA_SRAM_MPU1 VDDS_DDR VDDA_3P3_IOLDO0 VDDA_3P3_IOLDO1 VDDSHV0 VDDSHV1 VDDSHV2 VDDSHV3 VDDSHV4 VDDSHV5 VDDSHV6 VDDSHV8 VPP_CORE VDDA_MCU SRAM LDO I/O Bias LDO I/O Bias LDO SRAM LDO SRAM LDO SRAM LDO SRAM LDO SRAM LDO SRAM LDO SRAM LDO SRAM LDO PCIE0 USB1 (1.8V) USB0 (3.3V) USB1 (3.3V) PCIE1 USB0 (1.8V) VDD_WKUP0 VDD_WKUP1 WKUP LDO LF OSC HF OSC SRAM LDO VDDS1_WKUP VDDA_POR_WKUP MCU PLL SRAM LDO CPSW PLL SDIO LDOVDDA_3P3_SDIO I/O Bias LDO VDDA_1P8_SDIO VDDS2_WKUP VDDS1 VDDS2 VDDS8 VDDS0 VDDS3 VDDS4 VDDS5 VDDS6 VDD_MCU CAP_VDDAR_MCU CAP_VDDA_1P8_IOLDO_WKUP CAP_VDDAR_WKUP CAP_VDD_WKUP CAP_VDDAR_CORE0 CAP_VDDAR_CORE1 CAP_VDDAR_CORE2 CAP_VDDAR_CORE3 CAP_VDDAR_MPU0_0 CAP_VDDAR_MPU0_1 CAP_VDDAR_CORE4 CAP_VDDAR_MPU1_0 CAP_VDDAR_MPU1_1 CAP_VDDA_1P8_IOLDO0 CAP_VDDA_1P8_IOLDO1 CAP_VDDA_1P8_SDIO VDDA_WKUP VDDA_DLL_MMC0 VDDA_DLL_MMC1 Compute Cluster CORE A53 MSMC MCU Domain Wakeup Domain Main Domain MMC/SD VPP_MCU SPRSP08 DECOUPLING CAPS_01_ _ (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) VDDS0_WKUP(1) (1) (1) (1) (2) (2) VDDSHVn (3) VDDSn (3) 267 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Applications, Implementation, and LayoutCopyright © 2018, Texas Instruments Incorporated Figure 7-5. External decoupling capacitor connections (1) Refer to Section 7.6.1, LVCMOS External Capacitor Connections for details about external capacitor connections for VDDSHV[0- 2]_WKUP, VDDSHV[0-8], VDDS[0-2]_WKUP, and VDDS[0-8].

ADVANCE□INFORMATION Device VDDA_3P3_IOLDO_WKUP VDDSHV0_WKUP VDDSHV1_WKUP VDDSHV2_WKUP VDDA_3P3_IOLDO0 VDDA_3P3_IOLDO1 VDDSHV7 I/O Bias LDO I/O Bias LDO VDDA_POR_WKUP VDDSHV0 VDDSHV1 VDDSHV2 VDDSHV3 VDDSHV4 VDDSHV5 VDDSHV6 I/O Bias LDO VDDS1 VDDS2 VDDS4 VDDS0 VDDS5 VDDS7 VDDS8 VDDS3 CAP_VDDA_1P8_IOLDO_WKUP CAP_VDDA_1P8_IOLDO0 CAP_VDDA_1P8_IOLDO1 Wakeup Domain Main Domain SPRSP08 DECOUPLING CAPS_01_ _ VDDS2_WKUP VDDS0_WKUP VDDS1_WKUP VDDS6VDDSHV8 268 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Applications, Implementation, and Layout Copyright © 2018, Texas Instruments Incorporated (2) In this Figure, the VDD_WKUP0 and VDD_WKUP1 supplies are sourced through the WKUP LDO, not an external supply. (3) Refer to Section 7.6.1, LVCMOS External Capacitor Connections for details about external capacitor connections when using the SDIO LDO.

7.6.1 LVCMOS External Capacitor Connections

Each VDDSHV[0-8] and VDDSHV[0:2]_WKUP can be configured as 1.8 V or 3.3 V. Figure 7-6 through Figure 7-8 illustrate different system configurations for the dual-voltage I/O supplies. VDDSHV[0-8] and VDDSHV[0:2]_WKUP are the dual-voltage LVCMOS I/O supplies, while VDDS[0-8] are the dual-voltage LVCMOS I/O bias supplies. If any of the VDDSHV[0-8] or VDDSHV[0:2]_WKUP are configured for 3.3 V operation, the corresponding VDDS[0-8] should be sourced from the internal I/O Bias LDO. When any of the VDDSHV[0-8] or VDDSHV[0:2]_WKUP are configured for 1.8 V operation, both VDDS[0-8] and VDDSHV[0-8] or VDDSHV[0:2]_WKUP should be supplied from the same source. Two I/O Bias LDOs are integrated on this device to share load current. The recommended load sharing is as follows:

IOLDO0 : VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV5, VDDSHV7, VDDSHV8
IOLDO1 : VDDSHV3, VDDSHV4, VDDSHV6 Figure 7-6 shows all VDDSHV[0-8] supplies configured for 3.3V operation. Figure 7-6. All VDDSHV[0-8] supplies configured for 3.3 V operation Figure 7-7 shows all VDDSHV[0-8] supplies configured for 1.8 V operation.

ADVANCE□INFORMATION Device VDDA_3P3_IOLDO_WKUP VDDSHV0_WKUP VDDSHV1_WKUP VDDSHV2_WKUP VDDA_3P3_IOLDO0 VDDA_3P3_IOLDO1 VDDSHV7 I/O Bias LDO I/O Bias LDO VDDA_POR_WKUP VDDSHV0 VDDSHV1 VDDSHV2 VDDSHV3 VDDSHV4 VDDSHV5 VDDSHV6 I/O Bias LDO CAP_VDDA_1P8_IOLDO_WKUP CAP_VDDA_1P8_IOLDO0 CAP_VDDA_1P8_IOLDO1 Wakeup Domain Main Domain SPRSP08 DECOUPLING CAPS_03_ _ VDDS2_WKUP VDDS0_WKUP VDDS1_WKUP VDDS1 VDDS2 VDDS7 VDDS0 VDDS3 VDDS4 VDDS5 VDDS6 VDDS8 VDDSHV8 269 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Applications, Implementation, and LayoutCopyright © 2018, Texas Instruments Incorporated Figure 7-7. All VDDSHV[0-8] supplies configured for 1.8V operation

ADVANCE□INFORMATION Device SDIO LDOVDDA_3P3_SDIO VDDA_1P8_SDIO VDDSHVn VDDSn CAP_VDDA_1P8_SDIO CAP_VDDSHV_SDIO MMC/SD SPRSP08 DECOUPLING CAPS_05_ _ (1) (1) 271 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Applications, Implementation, and LayoutCopyright © 2018, Texas Instruments Incorporated Figure 7-9. VDDSHV6 or VDDSHV7 is used as the MMC/SD supply (1) VDDSHVn and VDDSn, where n = 6 or 7.

7.7 Thermal Solution Guidance

The Thermal Design Guide for DSP and Arm Application Processors Application Report (SPRABI3) available from http://www.ti.com/lit/pdf/sprabi3 provides guidance for successful implementation of a thermal solution for system designs containing this device. This document provides background information on common terms and methods related to thermal solutions. TI only supports designs that follow system design guidelines contained in the application report.

ADVANCE□INFORMATION 272 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Device and Documentation Support Copyright © 2018, Texas Instruments Incorporated

8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

8.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example, DRA80x). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS). Device development evolutionary flow: X Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. null Production version of the silicon die that is fully qualified. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully-qualified development-support product. X and P devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. For orderable part numbers of DRA80x devices in the ACD package type, see the Package Option Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative. For additional description of the device nomenclature markings on the die, see the Silicon Errata.

ADVANCE□INFORMATION SPRSP31_PACK_01 JACINTO aBBBBBBBrzIYy Q1PPP PIN ONE INDICATOR O G1YYY ZZZ XXXXXXX 273 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Device and Documentation SupportCopyright © 2018, Texas Instruments Incorporated

8.1.1 Standard Package Symbolization

Figure 8-1. Printed Device Reference

8.1.2 Device Naming Convention

Table 8-1. Nomenclature Description FIELD PARAMETER FIELD DESCRIPTION VALUE DESCRIPTION a Device evolution stage X Prototype P Preproduction (production test flow, no reliability data) BLANK Production BBBBBBB Base production part number DRA804M Quad Core High Tier (See Table 3-1, Device Comparison) DRA802M Dual Core High Tier (See Table 3-1, Device Comparison) r Device revision BLANK SR 1.0 z Device Speed X High speed grade (see Table 5-1, Speed Grade Maximum Frequency) OTHER Alternate speed grade I ICSS designator 6 6 × ICSS MAC ports Yy Device type G General purpose (Prototype and Production) C ASIL Certified devices S ASIL Certified devices, Secure Boot Supported H High security devices Q1 Automotive Designator BLANK not meeting automotive qualification Q1 meeting Q100 equal requirements, with exceptions as specified in DM. XXXXXXX Lot Trace Code (LTC) YYY Production Code; For TI use only ZZZ Production Code; For TI use only O Pin one designator G1 ECAT— Green package designator

ADVANCE□INFORMATION 274 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Device and Documentation Support Copyright © 2018, Texas Instruments Incorporated (1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent evolutionary stages of product development from engineering prototypes through fully qualified production devices. Prototype devices are shipped against the following disclaimer: “This product is still in development and is intended for internal evaluation purposes.” Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability of fitness for a specific purpose, of this device. (2) Applies to device max junction temperature. NOTE BLANK in the symbol or part number is collapsed so there are no gaps between characters.

8.2 Tools and Software

The following products support development for DRA80x platforms: Development Tools DRA80x Clock Tree Tool is an interactive clock tree configuration software that allows the user to visualize the device clock tree, interact with clock tree elements and view the effect on configuration registers, interact with the configuration registers and view the effect on the device clock tree, and view a trace of all the device registers affected by the user interaction with the clock tree. DRA80x Pin Mux Utility is an interactive application that helps a system designer select the appropriate pin-multiplexing configuration for their device-based product design. The Pin Mux Utility provides a way to select valid IO Sets of specific peripheral interfaces to ensure the pinmultiplexing configuration selected for a design only uses valid IO Sets supported by the device.

8.3 Documentation Support

The following documents describe the DRA80x devices. TRM DRA80x SoC for Automotive Infotainment Silicon Revision 1.0 Technical Reference Manual Details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the DRA80x family of devices. Errata DRA80x SoC for Automotive Infotainment Silicon Revision 1.0 Silicon Errata Describes known exceptions to the functional specifications (advisories) with workarounds and situations where the device's behavior may not match presumed or documented behavior (usage notes).

8.3.1 FCC Warning

This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.

8.3.2 Information About Cautions and Warnings

This book may contain cautions and warnings. CAUTION This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.

ADVANCE□INFORMATION 275 DRA80M www.ti.com SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: DRA80M Device and Documentation SupportCopyright © 2018, Texas Instruments Incorporated WARNING This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. The information in a caution or a warning is provided for your protection. Read each caution and warning carefully.

8.4 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 8-2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY DRA804M Click here Click here Click here Click here Click here DRA802M Click here Click here Click here Click here Click here

8.5 Receiving Notification of Documentation Updates

To receive notification of documentation updates — including silicon errata — go to the product folder for your device on ti.com. In the upper right-hand corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document.

8.6 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI Embedded Processors WikiTexas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.

8.7 Trademarks

NEON, CoreSight are trademarks of Arm Limited. Arm, Cortex, TrustZone are registered trademarks of Arm Limited. OSPI is a trademark of Cadence Design Systems, Inc. Hyperbus is a trademark of Mobiveil Inc. PCI-Express, PCIe are registered trademarks of PCI-SIG. PROFIBUS is a registered trademark of PROFIBUS Nutzerorganisation e.V.

8.8 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.9 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

ADVANCE□INFORMATION 276 DRA80M SPRSP31B –APRIL 2018–REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: DRA80M Mechanical Packaging and Orderable Information Copyright © 2018, Texas Instruments Incorporated

9 Mechanical Packaging and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

9.1 Mechanical Data

www.ti.com 12-Oct-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples XDRA804MX6GACDQ1 ACTIVE FCBGA ACD 784 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2018, Texas Instruments Incorporated

Product Information

DRA80M specifications and overview.

Summary

Infotainment Applications Processor Silicon Revision 1.0

Description

Infotainment Applications Processor Silicon Revision 1.0

Source title DRA80M Datasheet(PDF) - Texas Instruments

Related Parts

More parts from the same family.

Browse manufacturer