CH1005C overview

CH1005C is a component documented by List of Unclassifed Man. The PDF description identifies it as "Digital PC to TV Encoder with Macrovision." This guide condenses the most useful engineering information from the available PDF so that designers and sourcing teams can identify the checks that still need confirmation in the original document.

Datasheet snapshot

  • Manufacturer: List of Unclassifed Man...
  • Part number: CH1005C
  • Category: IC
  • Datasheet length: 49 Pages

Key features noted in the PDF

  • Supports Macrovision T M 7.X anti-copy protection
  • Function compatible with CH7004
  • Universal digital interface accepts YCrCb (CCIR601 or 656) or RGB (15,16 or 24-bit) video data in both non-interlaced and interlaced formats
  • TrueScale TM rendering engine supports undescam operations for various graphic resolutions † ¥
  • Enhanced text sharpness and adaptive flicker removal with up to 5-lines of filtering †
  • Enhanced dot crawl control and area reduction
  • Fully programmable through I 2 C port

Specifications and operating details

The following points were extracted from the PDF text. Check the associated conditions, notes and limits in the complete document before using a value in a design.

  • This pins supplies the 5V power to the analog section of the CH7005.
  • This pins supplies the 5V power to CH7005 ’s internal DAC ’s.
  • These pins supply the 3.3V power to the digital section of CH7005.
  • The CH7005 can operate in either master (the CH7004 generates a pixel frequency which is either returned as a phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock).
  • The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired output format (NTSC or PAL), and the amount of scaling desired.
  • The pixel clock may be requested to be 1X, 2X, or 3X the pixel data rate (subject to a 100MHz frequency limitation).
  • YCrCb Non-multiplexed Mode with Embedded Syncs dependent upon the current mode, (not 27MHz, as specified in CCIR656). Table 4.

Topics covered by the datasheet

The document includes sections related to:

  • Features
  • Contents
  • ORDERING INFORMATION

Engineering review checklist

  • Confirm supply rails, clock limits, memory size, peripheral mapping and I/O voltage compatibility.
  • Check package pinout, boot configuration, programming interface and silicon-revision errata.
  • Budget decoupling, thermal margin, startup timing and firmware recovery behavior before release.

Always confirm values against the latest manufacturer-controlled datasheet, especially when qualifying a substitute or releasing a production BOM.

View the complete PDF and model record

Open the CH1005C datasheet and model details to review the complete PDF, document pages and available product information.

Source attribution

Adapted from the PDF associated with this DigiCamel model page.

Source model URL: https://www.digicamel.com/product.php?slug=ch1005c-list-of-unclassifed-man

CH1005C List of Unclassifed Man... IC CH1005C datasheet CH1005C specifications CH1005C applications