CH1005C

CH1005C ETC

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 49

Technical content

Features

• Supports Macrovision T M 7.X anti-copy protection
• Function compatible with CH7004
• Universal digital interface accepts YCrCb (CCIR601 or 656) or RGB (15,16 or 24-bit) video data in both non-interlaced and interlaced formats
• TrueScale TM rendering engine supports undescam operations for various graphic resolutions † ¥
• Enhanced text sharpness and adaptive flicker removal with up to 5-lines of filtering †
• Enhanced dot crawl control and area reduction
• Fully programmable through I 2 C port
• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D, G, H, I, M and N) TV formats
• Provides Composite, S-Video and SCART outputs
• Auto-detection of TV presence
• Supports VBI pass-through
• Programmable power management
• 9-bit video DAC outputs
• Complete Windows and DOS driver software
• Offered in 44-pin PLCC, 44-pin TQFP General Description Chrontel ’s CH7005 digital PC to TV encoder is a stand- alone integrated circuit which provides a PC 99 compliant solution for TV output. Suggested application use with the Intel I740.* It provides a universal digital input port to accept a pixel data stream from a compatible VGA controller (or equivalent) and converts this directly into NTSC or PAL TV format. This circuit integrates a digital NTSC/PAL encoder with 9-bit DAC interface, and new adaptive flicker filter, and high accuracy low-jitter phase locked loop to create outstanding quality video. Through its TrueScale TM scaling and deflickering engine, the CH7005 supports full vertical and horizontal underscan capability and operates in 5 different resolutions including 640x480 and 800x600. A new universal digital interface along with full programmability make the CH7005 ideal for system-level PC solutions. All features are software programmable through a standard I 2 C port, to enable a complete PC solution using a TV as the primary display. † Patent number 5,781,241 ¥ Patent number 5,914,753 Figure 1: Functional Block Diagram TRIPLE DAC PLL RGB-YUV CONVERTER SYSTEM CLOCK Y/R CVBS/B C/G YUV-RGB CONVERTER DIGITAL INPUT INTERFACE I2 C REGISTER & CONTROL BLOCK LINE MEMORY TRUE SCALE SCALING & DEFLICKERING ENGINE TIMING & SYNC GENERATOR NTSC/PAL ENCODER & FILTERS D[15:0] PIXEL DATA XCLK H V XI XO/FIN P-OUTSC SD RESET* DS/BCO RSET CSYNC

2 201-0000-025 Rev 2.1, 8/2/99 Figure 2: 44-Pin PLCC XO/FIN XI DVDD RESET* D[3] D[4] D[5] D[8] D[6] DVDD D[7] DGND SC SD DGND] D[9] D[10] D[11] AVDD VDD RSET GND D [ 2 ] D [ 1 ] V H X C L K D V D D P - O U T D [ 0 ] D G N D D S /B C O A G N D D [ 1 2 ] D [ 1 3 ] D [ 1 4 ] D G N D D [ 1 5 ] D V D D C S Y N C G N D C V B S C Y 4 4 4 3 4 2 4 1 4 0 1 8 1 9 2 0 2 1 2 4 2 3 2 2 2 5 2 6 2 7 2 8 CHRONTEL CH7005

201-0000-025 Rev 2.1, 8/2/99 3 CHRONTEL CH7005C Figure 3: 44-Pin TQFP XO/FIN XI DVDD ADDR D[3] D[4] D[5] D[8] D[6] DVDD D[7] DGND SC SDDGND] D[9] D[10] D[11] AVDD VDD RSET GND D [ 2 ] D [ 1 ] V X C L K D V D D P - O U T D [ 0 ] D G N D D S /B C O A G N D D [ 1 2 ] D [ 1 3 ] D [ 1 4 ] D G N D D [ 1 5 ] D V D D C S Y N C G N D C V B S C Y 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 1 2 1 3 1 4 1 5 1 8 1 7 1 6 1 9 2 0 2 1 2 2 CHRONTEL CH7005 D[3] D[4] D[5] D[8] D[6] DVDD D[7] DGND] D[9] D[10] D[11] XO/FIN XI DVDD RESET* DGND SC SD AVDD VDD RSET GND H

Table 1. Pin Descriptions this pin should kept to a minimum. pin should be kept to a minimum. first active pixel of data for each active line. When configured as an output this pin provides a buffered clock output. is attached to XO/FIN, XI should be connected to ground.

mode, this pin outputs the composite sync signal. supply and is not 5V tolerant. reset is controlled through the I 2 C register. This pins supplies the 5V power to the analog section of the CH7005. This pins supplies the 5V power to CH7005 ’s internal DAC ’s.

These pins provide the ground reference for CH7005 ’s internal DACs. Application Information section. These pins supply the 3.3V power to the digital section of CH7005. in the RGB Pass-Through mode. Table 2. Input Data Formats

201-0000-025 Rev 2.1, 8/2/99 7 CHRONTEL CH7005C The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode. The CH7005 can operate in either master (the CH7004 generates a pixel frequency which is either returned as a phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock). The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X, or 3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7005 will automatically use both clock edges, if a multiplexed data format is selected. Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be selected to be generated by the CH7005. In the case of CCIR656 style input (IDF = 1 or 9), embedded sync may also be used. (In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, time the first value of the ( Total Pixels/line x Total Lines/Frame) column of Table16 on page 31 (Display Mode Register 00H description). The leading edge of the horizontal sync is used to determine the start of each line. The Vertical sync signal must be able to be set to the second value in the ( Total Pixels/Line x Total Lines/Frame) column of Table16 on page 31.) Master Clock Mode: The CH7005 generates a clock signal (output at the P-OUT pin) which will be used by the VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity). Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock signal will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the pixel data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC transmits back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet the specified setup and hold times with respect to the pixel clock. Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after the leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count), plus horizontal sync width, will determine when the chip will begin to sample pixels. Non-multiplexed Mode In the 15/16-bit mode shown in Figure4 , the pixel data bus represents a 15/16-bit non-multiplexed data stream, which contains either RGB or YCrCb formatted data. When operating in RGB mode, each 15/16-bit Pn value will contain a complete pixel encoded in either 5-6-5 or 5-5-5 format. When operating in YCrCb mode, each 16-bit Pn word will contain an 8-bit Y (luminance) value on the upper 8 bits, and an 8-bit C (color difference) value on the lower 8 bits. The color difference will be transmitted at half the data rate of the luminance data, with the sequence- being set as Cb followed by Cr. The Cb and Cr data will be cosited with the Y value transmitted with the Cb value, with the data sequence described in Table3 . The first active pixel is SAV pixels after the leading edge of horizon- tal sync, where SAV is a bus-controlled register.

occur – if the video stream was continuous. This is delineated in Table4 below. Bits S[7] and S[3-0] are ignored. Table 3. YCrCb Non-multiplexed Mode with Embedded Syncs

dependent upon the current mode, (not 27MHz, as specified in CCIR656). Table 4. RGB 8-bit Multiplexed Mode

Note: The AX[7:0] data is ignored. Table 5. RGB 12-bit Multiplexed Mode Table 6. RGB 16-bit Muliplexed Mode Table 7. YCrCb Multiplexed Mode

Bits S[7] and S[3-0] are ignored. Table 8. YCrCb Multiplexed Mode with Embedded Syncs Table 9. RGB 8-bit Multiplexed Mode (24-bit Color)

12 * Patent number 5,874,846 201-0000-025 Rev 2.1, 8/2/99 Functional Description The CH7005 is a TV-output companion chip to graphics controllers providing digital output in either YUV or RGB format. This solution involves both hardware and software elements which work together to produce an optimum TV screen image based on the original computer generated pixel data. All essential circuitry for this conversion are integrated onchip. Onchip circuitry includes memory, memory control, scaling, PLL, DAC, filters, and NTSC/PAL encoder. All internal signal processing, including NTSC/PAL encoding, is performed using digital techniques to ensure that the high-quality video signals are not affected by drift issues associated with analog components. No additional adjustment is required during manufacturing. CH7005 is ideal for PC motherboards, web browsers, or VGA add-in boards where a minimum of discrete support components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation. Architectural Overview The CH7005 is a complete TV output subsystem which uses both hardware and software elements to produce an image on TV which is virtually identical to the image that would be displayed on a monitor. Simply creating a compatible TV output from a VGA input involves a relatively straightforward process. This process includes a standard conversion from RGB to YUV color space, converting from a non-interlaced to an interlaced frame sequence, and encoding the pixel stream into NTSC or PAL compliant format. However, creating an optimum computer-generated image on a TV screen involves a highly sophisticated process of scaling, deflickering, and filtering. This results in a compatible TV output that displays a sharp and subtle image, of the right size, with minimal artifacts from the conversion process. As a key part of the overall system solution, the CH7005 software establishes the correct framework for the VGA input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600), the CH7005 software may be invoked to establish the appropriate TV output display. The software then programs the various timing parameters of the VGA controller to create an output signal that will be compatible with the chosen resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates, total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7005 can render a superior TV image without the added cost of a full frame buffer memory – normally used to implement features such as scaling and full synchronization. The CH7005 hardware accepts digital RGB or YCrCb inputs, which are latched in synchronization with the pixel clock. These inputs are then color-space converted into YUV in 4-2-2 format, and stored in a line buffer memory. The stored pixels are fed into a block where scan-rate conversion, underscan scaling and 2-line, 3-line, 4-line and 5- line vertical flicker filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to either NTSC or PAL scan rates; the vertical flicker filter eliminates flicker at the output while the underscan scaling reduces the size of the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through digital filters to minimize aliasing problems. The digital encoder receives the filtered signals and transforms them to composite and S-Video outputs, which are converted by the three 9-bit DACs into analog outputs. Color Burst Generation* The CH7005 allows the subcarrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator, leaving the subcarrier frequency independent of the sampling rate. As a result, the CH7005 may be used with any VGA chip (with an appropriate digital interface) since the CH7005 subcarrier frequency can be generated without being dependent on the precise pixel rates of VGA controllers. This feature is a significant benefit, since even a ± 0.01% subcarrier frequency variation may be enough to cause some television monitors to lose color lock. In addition, the CH7005 has the capability to genlock the color burst signal to the VGA horizontal sync frequency, which enables a fully synchronous system between the graphics controller and the television. When genlocked, the CH7005 can also stop “dot crawl ” motion (for composite mode operation in NTSC modes) to eliminate the annoyance of moving borders. Both of these features are under programmable control through the register set. Display Modes The CH7005 display mode is controlled by three independent factors: input resolution, TV format, and scale factor, which are programmed via the display mode register. It is designed to accept input resolutions of 640x480, 800x600, 640x400 (including 320x200 scan-doubled output), 720x400, and 512x384.

are listed in detail in Table10 . scan of 10%. ( Negative values) indicate modes which are operating in underscan. viewing text screens, operating games, running productivity applications and working within Windows). Table 10. CH7005 Display Modes

TV is sensed only on composite, the S-Video Off mode could be set by software). chrominance video bandwidth output is shown in Table12 . Non-Disclosure Agreement has been executed between Macrovision T M , Inc. and the customer. Table 11. Power Management reference when in master clock mode. S-Video Off: Power is shut off to the unused DACs associated with S-Video outputs. CH7005 in its lowest power consumption mode.

Intercast or close captioned applications (see register descriptions). The composite luminance and chrominance frequency response is depicted in Figures 7 through 9 . Table 12. Video Bandwidth

201-0000-025 Rev 2.1, 8/2/99 17 CHRONTEL CH7005C Luminance and Chrominance Filter Options (continued) Figure 9: Chrominance Frequency Response 0 1 2 3 4 5 6 7 8 9 10 11 12 < >UVfirdB i n f ,n i 10 6 -12 -18 -24 -30 -36 -42 0 1 2 3 4 5 6 7 8 9 10 11 12 (UVfirdB <i> ) n f n,i 10 6

• The frequencies of Fsc, Fh, and Fv can only be guaranteed in master or pseudo-master modes, not in slave mode when the graphics device generates these frequencies.
• It is assumed that gamma correction, if required, is performed in the graphics device which establishes the color reference signals.
• All modes provide the exact number of lines called out for NTSC and PAL modes respectively, except mode 21, which outputs 800x600 resolution, scaled by 3:4, to PAL format with a total of 627 lines (vs. 625).
• Chroma signal frequency response will fall within 10% of the exact recommended value.
• Pulse widths and rise/fall times for sync pulses, front/back porches, and equalizing pulses are designed to approximate CCIR624-3 requirements, but will fall into a range of values due to the variety of clock frequencies used to support multiple operating modes For this table and all subsequent figures, key values are: Note: 1. RSET = 360 ohms; V(RSET) = 1.235V; 75 ohms doubly terminated load. 2. Durations vary slightly in different modes due to the different clock frequencies used. 3. Active video and black (F, G, H) times vary greatly due to different scaling ratios used in different modes. 4. Black times (F and H) vary with position controls.

Table 13. NTSC/PAL Composite Output Timing Parameters (in µS)

20 201-0000-025 Rev 2.1, 8/2/99 Figure 12: Interlaced PAL Video Timing 621 622 623 624 625 1 2 3 4 5 6 7620 621 622 623 624 625 1 2 3 4 5 6 7620 309 310 311 312 313 314 315 316 317 318 319 320 323308 322 309 310 311 312 313 314 315 316 317 318 319 320308 START OF VSYNC ANALOG FIELD 1 ANALOG FIELD 2 ANALOG FIELD 3 ANALOG FIELD 4 BURST BLANKING PAL SWITCH = 0, +V COMPONENT BURST PHASE = REFERENCE PHASE = 135 RELATIVE TO U ° PAL SWITCH = 1, - V COMPONENT BURST PHASE = REFERENCE PHASE + 90 = 225 RELATIVE TO U °° 8 9 10 321 8 9 10 323322321 621 622 623 624 625 1 2 3 4 5 6 7620 621 622 623 624 625 1 2 3 4 5 6 7620 309 310 311 312 313 314 315 316 317 318 319 320 323308 322 309 310 311 312 313 314 315 316 317 318 319 320308 START OF VSYNC ANALOG FIELD 1 ANALOG FIELD 2 ANALOG FIELD 3 ANALOG FIELD 4 BURST BLANKING PAL SWITCH = 0, +V COMPONENT BURST PHASE = REFERENCE PHASE = 135 RELATIVE TO U ° PAL SWITCH = 1, - V COMPONENT BURST PHASE = REFERENCE PHASE + 90 = 225 RELATIVE TO U °° 8 9 10 321 8 9 10 323322321 IN T E R V A L S

22 201-0000-025 Rev 2.1, 8/2/99 Figure 15: NTSC C (Chrominance) Video Output Waveform (DACG = 0) Figure 16: PAL C (Chrominance) Video Output Waveform (DACG = 1) Color bars: White Yellow Cyan Magenta Green Red Blue BlackColor/Level mA V Cyan/Red 25.80 0.968 Green/Magenta 25.01 0.938 Yellow/Blue 22.44 0.842 Peak Burst 18.08 0.678 Blank 14.29 0.536 Yellow/Blue 6.15 0.230 Green/Magenta 3.57 0.134 Cyan/Red 2.79 0.105 Peak Burst 10.51 0.394

3.579545 MHz Color Burst

(9 cycles) Color bars: White Yellow Cyan Magenta Green Red Blue BlackColor/Level mA V Cyan/Red 27.51 1.032 Green/Magenta 26.68 1.000 Yellow/Blue 23.93 0.897 Peak Burst 19.21 0.720 Blank 15.24 0.572 Yellow/Blue 6.56 0.246 Green/Magenta 3.81 0.143 Cyan/Red 2.97 0.111 Peak Burst 11.28 0.423

4.433619 MHz Color Burst

(10 cycles)

201-0000-025 Rev 2.1, 8/2/99 23 CHRONTEL CH7005C Figure 17: Composite NTSC Video Output Waveform (DACG = 0) Figure 18: Composite PAL Video Output Waveform (DACG = 1) Color/Level mA V Peak Chrome 32.88 1.233 White 26.66 1.000 Sync 0.00 0.000 Peak Burst 11.44 0.429 Black 9.08 0.340 Blank 7.65 0.281 Peak Burst 4.45 0.145 Color bars: White Yellow Cyan Magenta Green Red Blue Black (9 cycles) Color/Level mA V Peak Chrome 33.31 1.249 White 26.75 1.003 Sync 0.00 0.000 Peak Burst 11.97 0.449 Blank/Black 8.00 0.300 Peak Burst 4.04 0.151 Color bars: White Yellow Cyan Magenta Green Red Blue Black (10 cycles)

24 201-0000-025 Rev 2.1, 8/2/99 I2 C Port Operation The CH7005 contains a standard I 2 C control port, through which the control registers can be written and read. This port is comprised of a two-wire serial interface, pins SD (bidirectional) and SC, which can be connected directly to the SDB and SCB buses as shown in Figure19 . The Serial Clock line (SC) is input only and is driven by the output buffer of the master device (also shown in Figure19 ). The CH7005 acts as a slave, and generation of clock signals on the bus is always the responsibility of the master device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the bus can be transferred up to 400 kbit/s. Figure 19: Connection of Devices to the Bus Electrical Characteristics for Bus Devices The electrical specifications of the bus devices ’ inputs and outputs and the characteristics of the bus lines connected to them are shown in Figure19 . A pull-up resistor (R P ) must be connected to a 3.3V ± 10% supply. The CH7005 is a device with input levels related to DVDD. Maximum and minimum values of pull-up resistor (R P ) The value of R P depends on the following parameters:

• Supply voltage
• Bus capacitance
• Number of devices connected (input current + leakage current = I input ) The supply voltage limits the minimum value of resistor R P due to the specified minimum sink current of 2mA at VOL max = 0.4 V for the output stages: R P >= (V DD – 0.4) / 2 (R P in k Ω) The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of R P due to the specified rise time. The equation for RP is shown below: R P <= 10 3 /C (where: R P is in k Ω and C, the total capacitance, is in pF) The maximum HIGH level input current of each input/output connection has a specified maximum value of 10 µA. Due to the desired noise margin of 0.2V DD for the HIGH level, this input current limits the maximum value of R P . The R P limit depends on V DD and is shown below: R P <= (100 x V DD )/ I input (where: R P is in k Ω and I input is in µA) SCLK IN2 DATA IN2 DATAN2 OUT SCB (Serial Clock Bus) SDB (Serial Data Bus) +DVDD R P SLAVE SCLK IN1 DATA IN1 DATAN2 OUT SLAVE SCLK OUT FROM MASTER DATA IN MASTER DATAN2 OUT MASTER BUS MASTER SC SD

201-0000-025 Rev 2.1, 8/2/99 25 CHRONTEL CH7005C Transfer Protocol Both read and write cycles can be executed in “Alternating ” and “Auto-increment ” modes. Alternating mode expects a register address prior to each read or write from that location (i.e., transfers alternate between address and data). Auto-increment mode allows you to establish the initial register location, then automatically increments the transfer protocol is shown in Figure20 and described below. Figure 20: Serial Port Transfer Protocol 1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the “START ” condition. Transitions of address and data bits can only occur while SC is low. 2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the “STOP ” condition. 3. Upon receiving the first START condition, the CH7005 expects a Device Address Byte (DAB) from the master device. The value of the device address is shown in the DAB data format below. 4. After the DAB is received, the CH7005 expects a Register Address Byte (RAB) from the master. The format of the RAB is shown in the RAB data format below (note that B7 is not used). Device Address Byte (DAB) R/W Read/Write Indicator “0 ”: master device will write to the CH7005 at the register location specified by the address AR[5:0] “1 ”: master device will read from the CH7005 at the register location specified by the address AR[5:0]. Register Address Byte (RAB) B7 B6 B5 B4 B3 B2 B1 B0 1 1 1 0 1 0 1 R/W B7 B6 B5 B4 B3 B2 B1 B0

1 AutoInc AR[5] AR[4] AR[3] AR[2] AR[1] AR[0]

R/W* ACK I 2 C acknowledgeacknowledgeacknowledge

26 201-0000-025 Rev 2.1, 8/2/99 Transfer Protocols (continued) AutoInc Register Address Auto-Increment - to facilitate sequential R/W of registers. “1 ”: Auto-Increment enabled (auto-increment mode). Write: After writing data into a register, the Address Register will automatically be incremented by one. Read: Before loading data from a register to the on-chip temporary register (getting ready to be serially read), the Address Register will automatically be incremented by one. However, for the first read after an RAB, the Address Register will not be changed. “0 ”: Auto-Increment disabled (alternating mode). Write: After writing data into a register, the Address Register will remain unchanged until a new RAB is written. Read: Before loading data from a register to the on-chip temporary register (getting ready to be serially read), the Address Register will remain unchanged. AR[5:0] Specifies the Address of the Register to be Accessed. This register address is loaded into the Address Register of the CH7005. The R/W access, which follows, is directed to the register specified by the content stored in the Address Register. The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and AutoInc = 0,1. CH7005 Write Cycle Protocols (R/W = 0) Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the master- transmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slave- receiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the HIGH period of the clock pulse. The CH7005 always acknowledges for writes (see Figure21 ). Note that the resultant state on SD is the wired-AND of data outputs from the transmitter and receiver. Figure 21: Acknowledge on the Bus Figure22 shows two consecutive alternating write cycles for AutoInc = 0 and R/W = 0. The byte of information, following the Register Address Byte (RAB), is the data to be written into the register specified by AR[5:0]. If AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on. SC from Master SD Data Output By the CH7005 Start Condition SD Data Output By Master-Transmitter 1 8 9 not acknowledge acknowledge clock pulse for acknowledgment

tains more than 8 bits, and the remaining bits are located in another register. Table 14. Register Map

30 Reserved for test (details not included herein)

Table 15. I 2 C Alternate Register Map (Note: Macrovision T M controls available only by special arrangement)

table below (default is 640x480 input, NTSC output, 7/8 ’s scaling). Table 16. Display Modes

channel filtering includes a setting to enable the chroma dot crawl reduction circuit. Table 17. Flicker Filter Settings

00 Minimal Flicker Filtering

01 Slight Flicker Filtering

10 Maximum Flicker Filtering

11 Invalid

00 Maximum Text Enhancement

01 Slight Text Enhancement

10 Minimum Text Enhancement

11 Enable Chroma DotCrawl Reduction

in the composite luma channel. The Table18 and 19 below show the various settings. the color signal (such as dot crawl or false colors), which is useful for viewing text with high accuracy. causes a five line flicker filter to be used. The default setting of 0 uses a four line flicker filter. Table 18. Luma Filter Bandwidth

0 Low bandwidth

1 High bandwidth

00 Low bandwidth

01 Medium bandwidth

10 High bandwidth

11 Reserved (decode this and handle the same as 10)

0 Disables the peaking filter in luma S-Video channel

1 Enables the peaking filter in luma S-Video channel

Table 19. Chroma Filter Bandwidth

This register sets the variables required to define the incoming pixel data stream. signal to be directly output at the DACs (subject to a pipeline delay). If RGBBP=0, the bypass mode is disabled. which provides the correct levels for PAL and NTSC-J. Table 20. Input Data Format

at the input of the device. Refer to the “Input Data Format Register ” for these combinations. and 28 must use a 1X XCLK input data format.

• MCP (bit 4) determines which edge of the pixel clock output will be used to latch input data. Zero selects the negative edge, one selects the positive edge.
• M/S* (bit 6) determines whether the device operates in master or slave clock mode. In master mode (1), the 14.31818MHz clock is used as a frequency reference to the PLL. In slave mode (0) the XCLK input is used as a reference to the PLL, and is divided by the value specified by XCM[1:0]. The divide by N and M are forced to one.
• CFRB (bit 7) sets whether the chroma subcarrier free-runs, or is locked to the video signal. One causes the subcarrier to lock to the TV vertical rate, and should be used when the ACIV bit is set to zero. Zero causes the subcarrier to free-run, and should be used when the ACIV bit is set to one. Start Active Video Register Symbol: SAV Address: 07H Bits: 8 This register sets the delay in pixel increments from leading edge of horizontal sync, or the rising edge of data start, to the start of active video. The entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value contained in the position overflow register, bit SAV8. This is decoded as a whole number of pixels, which can be set anywhere between 0 and 511 pixels. Therefore, in any 2X clock mode, the number of 2X clocks from the leading edge of sync to the first active data must be a multiple of two clocks. In any 3X clock mode, the number of 3X clocks from the leading edge of sync to the first active data must be a multiple of three clocks. When using the DS/BCO pin as a data start input, this register should be set to decimal value 11.

Table 21. Input Data Format Register

36 201-0000-025 Rev 2.1, 8/2/99 Register Descriptions (continued) Position Overflow Register Symbol: PO Address: 08H Bits: 3 This position overflow register contains the MSB values for the SAV, HP, and VP values, as follows:

• VP8 (bit 0) is the MSB of the vertical position value (see explanation under “Vertical Position Register ”).
• HP8 (bit 1) is the MSB of the horizontal position value (see explanation under “Horizontal Position Register ”).
• SAV8 (bit 2) is the MSB of the start of active video value (see explanation under “Start Active Video Register ”). Black Level Register Symbol: BLR Address: 09H Bits: 8 This register sets the black level. The luminance data is added to this black level, which must be set between 90 and 208, with the default value being 127. Recommended values for NTSC and PAL-M are 127, 105 for PAL and 100 for NTSC-J. Horizontal Position Register Symbol: H P R Address: 0AH Bits: 8 The horizontal position register is used to shift the displayed TV image in a horizontal direction (left or right) to achieve a horizontally centered image on screen. The entire bit field, HP[8:0] is comprised of this register HP[7:0] plus the MSB value contained in the position overflow register, bit HP8. Increasing this value moves the displayed image position RIGHT; decreasing this value moves the displayed image position LEFT. Each increment moves the image position by 4 input pixels. Bit: 7 6 5 4 3 2 1 0 Symbol: SAV8 HP8 VP8 Type: R/W R/W R/W Default: 0 0 0 Bit: 7 6 5 4 3 2 1 0 Symbol: BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0 Type: R/W R/W R/W R/W R/W R/W R/W R/W Default: 0 1 1 1 1 1 1 1 Bit: 7 6 5 4 3 2 1 0 Symbol: HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 Type: R/W R/W R/W R/W R/W R/W R/W R/W Default: 0 0 0 0 0 0 0 0

201-0000-025 Rev 2.1, 8/2/99 37 CHRONTEL CH7005C Register Descriptions (continued) Vertical Position Register Symbol: VPR Address: 0BH Bits: 8 This register is used to shift the displayed TV image in a vertical direction (up or down) to achieve a vertically cen- tered image on screen. This bit field, VP[8:0] represents the TV line number (relative to the VGA vertical sync) used to initiate the generation and insertion of the TV vertical interval (i.e., the first sequence of equalizing pulses). Increasing values delay the output of the TV vertical sync, causing the image position to move UP on the TV screen. Decreasing values, therefore, move the image position DOWN. Each increment moves the image position by one TV lines (approximately 4 input lines). The maximum value that should be programmed into the VP[8:0] value is the number of TV lines minus one, divided by two (262, 312 or 313). When panning the image up, the number should be increased until (TVLPF-1) /2 is reached; the next step should be to reset the register to zero. When pan- ning the image down the screen, the VP[8:0] value should be decremented until the value zero is reached. The next step should set the register to (TVLPF-1) /2, and then decrementing can continue. If this value is programmed to a number greater than (TV lines per frame-1) /2, a TV vertical SYNC will not be generated. Sync Polarity Register Symbol: SPR Address: 0DH Bits: 4 This register provides selection of the synchronization signal input to, or output from, the CH7005.

• HSP (bit 0) is Horizontal Sync Polarity - an HSP value of zero means the horizontal sync is active low and a value of one means the horizontal sync is active high.
• VSP (bit 1) is Vertical Sync Polarity - a VSP value of zero means the vertical sync is active low and a value of one means the vertical sync is active high.
• SYO (bit 2) is Sync Direction - a SYO value of zero means that H and V sync are input to the CH7005. A value of one means that H and V sync are output from the CH7005.
• DES (bit 3) is Detect Embedded Sync - a DES value of zero means that H and V sync will be obtained from the direct pin inputs. A DES value of one means that H and V sync will be detected from the embedded codes on the pixel input stream. Note that this will only be valid for the YCrCb input modes. Note: When sync direction is set to be an output, horizontal sync will use a fixed pulse width of 64 pixels and vertical sync will use a fixed pulse width of 1 line. Bit: 7 6 5 4 3 2 1 0 Symbol: VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 Type: R/W R/W R/W R/W R/W R/W R/W R/W Default: 0 0 0 0 0 0 0 0 Bit: 7 6 5 4 3 2 1 0 Symbol: DES SYO VSP HSP Type: R/W R/W R/W R/W Default: 0 0 0 0

enable. The CH7005 provides programmable control of its operating states, as described in the table below. itself and the I 2 C state machines. After reset, this bit should be set back to 1 for normal operation to continue. the DACs and composite sync from the CSYNC pin.

1. Ensure the power management register Bits 2-0 is set to 011(normal mode).

Table 22. Power Management

000 Composite Off CVBS DAC is powered down

001 Power Down Most pins and circuitry are disabled (except for the buffered clock outputs

DS/BCO pin is selected to be an output).

010 S-Video Off S-Video DACs are powered down

011 Normal (On) All circuits and pins are active. 1XX Full Power Down All circuitry is powered down, except I 2 C circuit.

1. Set the SENSE bit to a 1. This forces a constant current output onto the Y, C, and CVBS outputs. Note that

during SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted.

1. Reset the SENSE bit to 0. This triggers a comparison between the voltage sensed on these analog outputs
2. Read the status bits. The status bits, Y, C, and CVBST (corresponding to S-Video Y and C outputs and

connected to a TV. Again, a “0 ” indicates a valid connection, a “1 ” indicates an unconnected output.

1. From this point on, the video signal is pulled towards the white direction, with the effect increasing with

increasing settings of CE[2:0]. Table 23. Contrast Enhancement Function

000 Contrast enhancement gain 3 Y out = (5/4)*(Y in -102) = Enhances Black

001 Contrast enhancement gain 2 Y out = (9/8)*(Y in -57)

010 Contrast enhancement gain 1 Y out = (17/16)*(Y in -30)

011 Normal mode Y out = (1/1)*(Yin-0) = Normal Contrast

100 Contrast enhancement gain 1 Y out = (17/16)*(Y in -0)

101 Contrast enhancement gain 2 Y out = (9/8)*(Y in -0)

110 Contrast enhancement gain 3 Y out = (5/4)*(Y in -0)

111 Contrast enhancement gain 4 Y out = (3/2)*(Y in -0) = Enhances White

40 201-0000-025 Rev 2.1, 8/2/99 Register Descriptions (continued) Figure 26: Luma Transfer Function at different contrast enhancement settings. PLL Overflow Register Symbol: MNE Address: 13H Bits: 5 The PLL Overflow Register contains the MSB bits for the ‘M ’ and ‘N ’ values, which will be described in the PLL- M and PLL-N registers, respectively. The reserved bits should not be written to. PLL M Value Register Symbol: PLLM Address: 14H Bits: 8 The PLL M value register determines the division factor applied to the frequency reference clock before it is input to the PLL phase detector when the CH7005 is operating in master or pseudo-master clock mode. In slave mode, an external pixel clock is used instead of the frequency reference, and the division factor is determined by the XCM[3:0] value. This register contains the lower 8 bits of the complete 9-bit M value. Bit: 7 6 5 4 3 2 1 0 Symbol: Reserved Reserved N9 N8 M8 Type: R/W R/W R/W R/W R/W Default: 0 0 0 0 0 Bit: 7 6 5 4 3 2 1 0 Symbol: M7 M6 M5 M4 M3 M2 M1 M0 Type: R/W R/W R/W R/W R/W R/W R/W R/W Default: 0 1 0 0 0 0 0 1 0 32 64 96 128 160 192 224 256 128 160 192 224 256

put.The tables below show the possible outputs. Table 24. M and N Values for Each Mode

Table 25. Clock Output Selection

010 VCO divided by K3 (see Table26 )

011 Field ID signal

110 TV horizontal sync (for test use only)

111 TV vertical sync (for test use only)

Table 26. K3 Selection

When the CH7005 is operating in the master clock mode, the tables below should be used to set the FSCI registers. CFRB bit in register 06H should be set to “0 ”. Table 27. FSCI Values (525-Line Modes) Table 28. FSCI Values (625-Line Modes)

44 201-0000-025 Rev 2.1, 8/2/99 Register Descriptions (continued) Symbol: Address: 1BH Bits: 8 Note: P-OUT P (bit 4) is used to invert the P-OUT signal. Symbol: Address: 1CH Bits: 6 Note: DSEN (bit4) controls the BCO / Data Start I/O pin. When this bit is low, the pin continues to operate as the BCO pin described in the BCO register description. When this bit is high, the pin becomes an input for the Data Start signal. PLL Control Register Symbol: PLLC Address: 20H Bits: 6 The following PLL and memory controls are available through the PLL control register: MEM5V MEM5V is set to 1 when the memory supply is 5 volts. The default value of 0 is used when the memory supply is 3.3 volts. PLL5VA PLL5VA is set to 1 when the phase-locked loop analog supply is 5 volts (default). A value of 0 is used when the phase-locked loop analog supply is 3.3 volts. PLL5VD PLL5VD is set to 1 when the phase-locked loop digital supply is 5 volts. A value of 0 is used when the phase-locked loop digital supply is 3.3 volts (default). PLLS PLLS controls the number of stages used in the PLL. When the PLL5VA is 1 (5V analog PLL supply) PLLS should be 1, and seven stages are used. When PLL5VA is 0 (3.3V analog PLL supply) PLLS should be 0, and five stages are used. PLLCAP PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs. Mode is shown below PLLCPI PLLCHI controls the charge pump current of the PLL. The default value should be used. Bit: 7 6 5 4 3 2 1 0 Symbol: P-OUTP FSCI19 FSCI18 FSCI17 FSCI16 Type: R/W R/W R/W R/W R/W Default: 0 0 0 0 0 Bit: 7 6 5 4 3 2 1 0 Symbol: DSEN FSCI15 FSCI14 FSCI13 FSCI12 Type: R/W R/W R/W R/W R/W Default: 1 0 0 0 0 Bit: 7 6 5 4 3 2 1 0 Symbol: PLLCPI PLLCAP PLLS PLL5VD PLL5VA MEM5V Type: R/W R/W R/W R/W R/W R/W Default: 0 0 1 0 1 0

Table 29. PLL Capacitor Setting

46 201-0000-025 Rev 2.1, 8/2/99 Register Descriptions (continued) CIV Control Register Symbol: CIVC Address: 21H Bits: 5 The following controls are available through the CIV control register: ACIV When the automatic calculated increment value is 1, the number calculated and present at the CIV registers will automatically be used as the increment value for subcarrier generation, removing the need for the user to read the CIV value and write in a new FSCI value. Whenever this bit is set to 1, the subcarrier generation must be forced to free-run mode. CIVH[1:0] These bits control the hysteresis circuit which is used to calculate the CIV value. CIV[25:24] See descriptions in the next section. Calculated Increment Value Register Symbol: CIV Address: 22H - 24H Bits: 8 The CIV registers 22H through 24H contain a 26-bit value, which is the calculated increment value that should be used as the upper 26 bits of FSCI. This value is determined by a comparison of the pixel clock and the 14MHz clock. The bit locations and calculation of CIV are specified as the following: Register

Contents

21H CIV[25:24] 22H CIV[23:16] 23H CIV[15:8] 24H CIV[7:0] Version ID Register Symbol: VID Address: 25H Bits: 8 This read-only register contains a 8-bit value indicating the identification number assigned to this version of the CH7005. The default value shown is pre-programmed into this chip and is useful for checking for the correct version of this chip, before proceeding with its programming. Bit: 7 6 5 4 3 2 1 0 Symbol: CIV25 CIV24 CIVH1 CIVH0 ACIV Type: R R R/W R/W R/W Default: 0 0 0 0 1 Bit: 7 6 5 4 3 2 1 0 Symbol: CIV# CIV# CIV# CIV# CIV# CIV# CIV# CIV# Type: R R R R R R R R Default: 0 0 0 0 0 0 0 0 Bit: 7 6 5 4 3 2 1 0 Symbol: VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Type: R R R R R R R R Default: 0 0 1 1 1 0 1 0

The Address Register points to the register currently being accessed.

1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the

above those indicated under the normal operating condition of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods my affect reliability.

1. The device is fabricated using high-performance CMOS technology. It should be handled as an

can induce destructive latch. Table 30. Absolute Maximum Ratings Table 31. Recommended Operating Conditions

Note: RSET = 360 ΩΩ , VREF = 1.235V, and NTSC CCIR601 operation. Note: 1. V IIC -refers to I2C pins SD and SC.

1. V DATA - refers to all digital pixel and clock inputs.
2. V SD - refers to I2C pin SD as an output.
3. V P-OUT - refers to pixel data output Time - Graphics.

Table 32. Electrical Characteristics (Operating Conditions: T A = 0 o C - 70 o C, V DD = 5V ± 5%) Table 33. Timing - TV Encoder Table 34. Digital Inputs / Outputs

2210 O ’Toole Avenue

San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com 1998 Chrontel, Inc. All Rights Reserved. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WIT HOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to p erform when used as directed can reasonably expect to result in personal injury or death. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provi de no warranty for the use of our products and assume no liability for errors contained in this document. Printed in the U.S.A.

ORDERING INFORMATION

Part number Package type Number of pins Voltage supply CH7005C-V PLCC 44 3V/5V CH7005C-T TQFP 44 3V/5V 201-0000-025 Rev 2.1, 8/2/99 49 CHRONTEL CH7005C Table 35. Timing Graphics