CDCDB803 overview
CDCDB803 is a component documented by Texas Instruments. The PDF description identifies it as "CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5 SNAS820 ??AUGUST 2021." This guide condenses the most useful engineering information from the available PDF so that designers and sourcing teams can identify the checks that still need confirmation in the original document.
Datasheet snapshot
- Manufacturer: Texas Instruments
- Part number: CDCDB803
- Category: Logic IC
- Datasheet length: 31 Pages
Key features noted in the PDF
- 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
- 8 hardware output enable (OE#) controls
- Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)
- Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)
- Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)
- Supports Common Clock (CC) and Individual Reference (IR) architectures – Spread spectrum-compatible
- Output-to-output skew: < 50 ps
Applications listed in the PDF
- Microserver & tower server
- Storage area network & host bus adapter card
- Network attached storage
- Hardware accelerator
- Rack server
Specifications and operating details
The following points were extracted from the PDF text. Check the associated conditions, notes and limits in the complete document before using a value in a design.
- Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) CDCDB803 VQFN (48) 6.00 mm × 6.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet.
- For a high-level input configuration, the pin should be pulled up to 3.3-V VDD through an external pullup resistor from 1k to 5k with 5% tolerance.
- For a low-level input configuration input, the pin should be pulled down to ground through an external pulldown resistor from 1k to 5k with 5% tolerance.
- For a low-level input configuration, the pin should be pulled down to ground through an external pulldown resistor from 1k to 5k with 5% tolerance.
- SUPPLY VOLTAGE AND GROUND VDDR 2 P Power supply input for input clock receiver.
- V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±3500 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allow.
- over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD IO, Core supply voltage 3 3.3 3.6 V VDD_R Input supply voltage 3 3.3 3.6 V TA Ambient temperature −40 105 °C THERMAL METRIC(1) Device Package UNITRSL (.
Topics covered by the datasheet
The document includes sections related to:
- CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6 datasheet (Rev. A)
Engineering review checklist
- Confirm the exact ordering code, package, pinout or terminal arrangement and document revision.
- Compare recommended operating conditions with absolute maximum ratings and retain adequate design margin.
- Validate electrical, thermal, mechanical and environmental behavior in the final application.
Always confirm values against the latest manufacturer-controlled datasheet, especially when qualifying a substitute or releasing a production BOM.
View the complete PDF and model record
Open the CDCDB803 datasheet and model details to review the complete PDF, document pages and available product information.
Source attribution
Adapted from the PDF associated with this DigiCamel model page.
Source model URL: https://www.digicamel.com/product.php?slug=cdcdb803-texas-instruments