CDCDB803

CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6 datasheet (Rev. A)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SNAS820,A]
• PDF pages: 34

Technical content

CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features

• 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
• 8 hardware output enable (OE#) controls
• Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)
• Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)
• Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)
• Supports Common Clock (CC) and Individual Reference (IR) architectures – Spread spectrum-compatible
• Output-to-output skew: < 50 ps
• Input-to-output delay: < 3 ns
• Fail-safe input
• Programmable output slew rate control
• 9 selectable SMBus addresses
• 3.3-V core and IO supply voltages
• Hardware-controlled low power mode (PD#)
• Current consumption: 72 mA maximum
• 6-mm × 6-mm, 48-pin VQFN package

2 Applications

• Microserver & tower server
• Storage area network & host bus adapter card
• Network attached storage
• Hardware accelerator
• Rack server

3 Description

The CDCDB803 is a 8-output LP-HCSL, DB800ZL- compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB803 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB803 is packaged in a 6-mm × 6-mm, 48-pin VQFN package. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) CDCDB803 VQFN (48) 6.00 mm × 6.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. PCIe Gen 4-5 Clock Generator CDCDB803 8x LP-HSCL Output Buffer SMBus Control OE# Control LP-HCSL PCIe PHYPCIe PHYPCIe PHYPCIe PHY LP-HCSL PCIe PHYPCIe PHYPCIe Device Control Interface CDCDB803 System Diagram CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

12.2 Receiving Notification of Documentation Updates..25

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (August 2021) to Revision A (May 2022) Page CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com

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5 Pin Configuration and Functions

48 NC13CK0_P

1 CKPWRGD_PD# 36 CK6_N

47 NC14CK0_N

2 VDDR 35 CK6_P

46 SMBWRTLOCK15VDD

3 CLKIN_P 34 VDD

45 NC16CK1_P

4 CLKIN_N 33 CK5_N

44 VDD17CK1_N

5 SADR0 32 CK5_P

43 NC18OE1#

6 SMBDAT 31 OE5#

42 VDD19VDD

7 SMBCLK 30 OE4#

41 OE7#20NC

8 SADR1 29 CK4_N

40 CK7_N21CK2_P

9 NC 28 CK4_P

39 CK7_P22CK2_N

10 NC 27 VDD

38 VDD23OE2#

11 VDD 26 CK3_N

37 OE6#24OE3#

12 OE0# 25 CK3_P

Figure 5-1. CDCDB803 RSL Package 48-Pin VQFN Top View Table 5-1. Pin Functions PIN TYPE(2) DESCRIPTION NAME NO. INPUT CLOCK CLKIN_P 3 I LP-HCSL differential clock input. Typically connected directly to the differential output of clock source.CLKIN_N 4 I OUTPUT CLOCKS CK0_P 13 O LP-HCSL differential clock output of channel 0. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.CK0_N 14 O CK1_P 16 O LP-HCSL differential clock output of channel 1. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.CK1_N 17 O www.ti.com CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: CDCDB803

Table 5-1. Pin Functions (continued) PIN TYPE(2) DESCRIPTION NAME NO. CK2_P 21 O LP-HCSL differential clock output of channel 2. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.CK2_N 22 O CK3_P 25 O LP-HCSL differential clock output of channel 3. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.CK3_N 26 O CK4_P 28 O LP-HCSL differential clock output of channel 4. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.CK4_N 29 O CK5_P 32 O LP-HCSL differential clock output of channel 5. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.CK5_N 33 O CK6_P 35 O LP-HCSL differential clock output of channel 6. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.CK6_N 36 O CK7_P 39 O LP-HCSL differential clock output of channel 7. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.CK7_N 40 O MANAGEMENT AND CONTROL (1) CKPWRGD_PD# 1 I, S, PD Clock Power Good and Power Down multi-function input pin with internal 180-kΩ pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. After PWRGD has been asserted high for the first time, the pin becomes a PD# pin and it controls power-down mode: LOW: Power-down mode, all output channels tri-stated. HIGH: Normal operation mode. OE0# 12 I, S, PD Output Enable for channel 0 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 0. HIGH: disable output channel 0. OE1# 18 I, S, PD Output Enable for channel 1 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 1. HIGH: disable output channel 1. OE2# 23 I, S, PD Output Enable for channel 2 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 2. HIGH: disable output channel 2. OE3# 24 I, S, PD Output Enable for channel 3, with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 3. HIGH: disable output channel 3. OE4# 30 I, S, PD Output Enable for channel 4, with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 4. HIGH: disable output channel 4. OE5# 31 I, S, PD Output Enable for channel 5, with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 5. HIGH: disable output channel 5. OE6# 37 I, S, PD Output Enable for channel 6 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 6. HIGH: disable output channel 6. OE7# 41 I, S, PD Output Enable for channel 7 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 7. HIGH: disable output channel 7. SMBUS AND SMBUS ADDRESS CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com

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Table 5-1. Pin Functions (continued) PIN TYPE(2) DESCRIPTION NAME NO. SADR0 5 I, S, PU / PD SMBus address strap bit[0]. This is a 3-level input that is decoded in conjunction with pin 8 to set SMBus address. It has internal 180-kΩ pullup / pulldown network biasing to GND when no connect. For a high-level input configuration, the pin should be pulled up to 3.3-V VDD through an external pullup resistor from 1k to 5k with 5% tolerance. For a low-level input configuration input, the pin should be pulled down to ground through an external pulldown resistor from 1k to 5k with 5% tolerance. For a mid-level input configuration, the pin should be left floating and not connected to VDD or ground. SMBDAT 6 I / O Data pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup resistor. The recommended pullup resistor value is > 8.5k. SMBCLK 7 I Clock pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup resistor. The recommended pullup resistor value is > 8.5k. SADR1 8 I, S, PU / PD SMBus address strap bit[1]. This is a 3-level input that is decoded in conjunction with pin B4 to set SMBus address. It has internal 180-kΩ pullup / pulldown network biasing to GND when no connect. For a high-level input configuration, the pin should be pulled up to 3.3-V VDD through an external pullup resistor from 1k to 5k with 5% tolerance. For a low-level input configuration, the pin should be pulled down to ground through an external pulldown resistor from 1k to 5k with 5% tolerance. For a mid-level input configuration, the pin should be left floating and not connected to VDD or ground. SMBWRTLOCK 46 I, PD SMBWRTLOCK: Disables write commands on SMBus. All writes will be ignored when SMBWRTLOCK is asserted (reads are not affected). Internal 180-kΩ pulldown, active high. 0 = SMBus write enabled. 1 = SMBus write disabled. SUPPLY VOLTAGE AND GROUND VDDR 2 P Power supply input for input clock receiver. Connect to 3.3-V power supply rail with decoupling capacitor to GND. Place a 0.1-µF capacitor close to each supply pin between power supply and ground. VDD 11, 15, 19, 27, 34, 38, 42, 44 P 3.3-V power supply for output channels and core voltage. GND DAP G Ground. Connect ground pad to system ground. NO CONNECT NC 9, 10, 20, 43, 45 — Do not connect to GND or VDD. NC 47, 48 — No connect. Pins may be connected to GND, VDD, or otherwise tied to any potential within the Supply Voltage range stated in the Absolute Maximum Ratings. (1) The “#” symbol at the end of a pin name indicates that the active state occurs when the signal is at a low voltage level. When “#” is not present, the signal is active high. (2) The definitions below define the I/O type for each pin.

• I = Input
• O = Output
• I / O = Input / Output
• PU / PD = Internal 180-kΩ Pullup / Pulldown network biasing to VDD/2
• PD = Internal 180-kΩ Pulldown
• S = Hardware Configuration Pin
• P = Power Supply
• G = Ground www.ti.com CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: CDCDB803

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD, VDD_R Power supply voltage −0.3 3.6 V VIN IO input voltage −0.3 3.6 V TJ Junction temperature 125 °C Tstg Storage temperature −65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±3500 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD IO, Core supply voltage 3 3.3 3.6 V VDD_R Input supply voltage 3 3.3 3.6 V TA Ambient temperature −40 105 °C

6.4 Thermal Information

THERMAL METRIC(1) Device Package UNITRSL (QFN)

48 PINS

RθJA Junction-to-ambient thermal resistance 32.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 22.3 °C/W RθJB Junction-to-board thermal resistance 14.3 °C/W ΨJT Junction-to-top characterization parameter 0.5 °C/W ΨJB Junction-to-board characterization parameter 14.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com

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6.5 Electrical Characteristics

VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ TA ≤ 105°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT CONSUMPTION IDD_R Core supply current Active mode. CKPWRGD_PD# = 1 9 mA Power-down mode. CKPWRGD_PD# = 0 2.2 IDD IO supply current All outputs disabled 18 mAAll outputs active, 100MHz (Per output) 7.8 Power-down mode. CKPWRGD_PD# = 0 1.5 CLOCK INPUT fIN Input frequency 50 100 250 MHz VIN Input voltage swing Differential voltage between CLKIN_P and CLKIN_N(1) 200 2300 mVDiff- peak dV/dt Input voltage edge rate 20% - 80% of input swing 0.7 V/ns DVCROSS Total variation of VCROSS Total variation across VCROSS 140 mV DCIN Input duty cycle 40 60 % CIN Input capacitance(2) Differential capacitance between CLKIN_P and CLKIN_N pins 2.2 pF CLOCK OUTPUT fOUT Output frequency 50 100 250 MHz COUT Output capacitance(1) Differential capacitance between CKx_P and CKx_N pins 4 pF VOH Output high voltage Single-ended(2) (3) 225 270 mV VOL Output low voltage 10 150 VHIGH Output high voltage Measured into an AC load as defined in DB800ZL 660 850 VLOW Output low voltage Measured into an AC load as defined in DB800ZL –150 150 VMAX Output Max voltage Measured into an AC load as defined in DB800ZL 1150 VCROSS Crossing point voltage (3) (4) 130 200 VCROSSAC Crossing point voltage (AC load) Measured into an AC load as defined in DB800ZL 250 550 DVCROSS Total variation of VCROSS Variation of VCROSS (3) (4) 35 140 Vovs Overshoot voltage (3) VOH+75 Vovs(AC) Overshoot voltage (AC load) Measured into an AC load as defined in DB800ZL VHIGH+30 Vuds Undershoot voltage (3) VOL–75 Vuds(AC) Undershoot voltage Measured into an AC load as defined in DB800ZL VLOW– 300 mV Vrb Ringback Voltage Measured into an AC load as defined in DB800ZL and taken from Single Ended waveform (relative to VHIGH and VLOW) -0.2 0.2 V ZDIFF Differential impedance (Default setting, 85 Ω) Measured at VOL/VOH 81 85 89 Ω Differential impedance (Output impedance selection bit =1, 100 Ω) Measured at VOL/VOH 95 100 105 ZDIFF_CROS S Differential impedance (Default setting, 85 Ω) Measured at VCROSS 68 85 102 Differential impedance (Output impedance selection bit = 1, 100 Ω) Measured at VCROSS 80 100 120 www.ti.com CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: CDCDB803

VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ TA ≤ 105°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEDGE Differential edge rate Measured (+-150 mV) around VCROSS (7) 2 4 V/ns DtEDGE Edge rate matching Measured (+-75 mV) VCROSS (7) 20 % tSTABLE Power good assertion to stable clock output CKPWRGD_PD# pin transitions from 0 to 1, fIN =

100 MHz

0.2V 1.8 ms tDRIVE_PD# Power good assertion to outputs driven high CKPWRGD_PD# pin transitions from 0 to 1, fIN = 0.2V 300 µs tOE Output enable assertion to stable clock output OEx# pin transitions from 1 to 0 10 CLKIN PeriodstOD Output enable de-assertion to no clock output OEx# pin transitions from 0 to 1 10 tPD Power-down assertion to no clock output CKPWRGD_PD# pin transitions from 1 to 0 3 tDCD Duty cycle distortion Differential; fIN = 100MHz, fIN_DC = 50% –1 1 % tDLY Propagation delay (5) 0.5 3 ns tSKEW Skew between outputs (6) 50 ps tDELAY(IN- OUT) Input to output delay variation Input-to-output delay variation at 100 MHz across voltage and temperature –250 250 ps JCKx_DB2000 Q (7) Additive jitter for DB2000Q DB2000Q filter, for input of 200 mV differential swing @ 1.5 V/ns 0.038 ps, RMS JCKx_PCIE (7) Additive jitter for PCIe6.0 PLL BW: 0.5 - 1 MHz; CDR =

10 MHz

slew rate =

2 V/ns

0.02 ps, RMS Additive jitter for PCIe5.0 PCIe5.0 filter 0.025 Additive jitter for PCIe4.0 PLL BW = 2 - 5 MHz; CDR = slew rate ≥

1.8 V/ns

0.06 Additive jitter for PCIe3.0 Input clock slew rate ≥

0.6 V/ns

0.1 JCKx Additive jitter fIN = 100 MHz; slew rate ≥ 3 V/ns; 12 kHz to 20 MHz integration bandwidth. 100 160 fs, RMS NF Noise floor fIN = 100 MHz; fOffset ≥ 10 MHz Input clock slew rate ≥

3 V/ns

–160 -155 dBc/Hz SMBUS INTERFACE, OEx#, CKPWRGD_PD# VIH High level input voltage 2.0 V VIL Low level input voltage 0.8 IIH Input leakage current With internal pull-up/pull-down GND ≤ VIN ≤ VDD –30 30 µA IIL Input leakage current With internal pull-up/pull-down GND ≤ VIN ≤ VDD –30 30 µA IIH Input leakage current Without internal pull-up/pull- down GND ≤ VIN ≤ VDD −5 5 µA IIL Input leakage current Without internal pull-up/pull- down GND ≤ VIN ≤ VDD −5 5 µA CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com

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VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ TA ≤ 105°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CIN Input capacitance 4.5 pF COUT Output capacitance 4.5 pF 3-LEVEL DIGITAL INTERFACE (SADR0, SADR1) VIH High level input voltage 2.3 VVIM Mid level input voltage 1.25 VDD/2 1.725 VIL Low level input voltage 0.85 IIH Input leakage current With internal pull-up/pull-down VIN = VDD –30 30 µA IIL Input leakage current With internal pull-up/pull-down VIN = GND –30 30 µA CIN Input capacitance(1) 4.5 pF (1) Voltage swing includes overshoot. (2) Not tested in production. Ensured by design and characterization. (3) Measured into DC test load. (4) VCROSS is single-ended voltage when CKx_P = CKx_N with respect to system ground. Only valid on rising edge of CKx, when CKx_P is rising. (5) Measured from rising edge of CLK_IN to any CKx output. (6) Measured from rising edge of any CKx output to any other CKx output. (7) Measured into AC test load.

6.6 Timing Requirements

VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ TA ≤ 105°C. Typical values are at VDD = VDD_A = 3.3 V, 25°C (unless otherwise noted) MIN NOM MAX UNIT SMBUS-COMPATIBLE INTERFACE TIMING fSMB SMBus operating frequency 10 400 kHz tBUF Bus free time between STOP and START 4.7 µs tHD_STA START condition hold time SMBCLK low after SMBDAT low 4 tSU_STA START condition setup time SMBCLK high before SMBDAT low 4.7 tSU_STO STOP condition setup time 4 tHD_DAT SMBDAT hold time 300 ns tSU_DAT SMBDAT setup time 250 tTIMEOUT Detect SMBCLK low timeout In terms of device input clock frequency 1e6 cycles tLOW SMBCLK low period 4.7 µs tHIGH SMBCLK high period 4 50 tF SMBCLK/SMBDAT fall time(1) 300 ns tR SMBCLK/SMBDAT rise time(2) 1000 (1) TF = (VIHMIN + 0.15) to (VILMAX - 0.15) (2) TR = (VILMAX - 0.15) to (VIHMIN + 0.15) www.ti.com CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: CDCDB803

6.7 Typical Characteristics

Figure 6-1 shows both the phase noise of the source as well as the output of the DUT (CDCDB803). It can be seen from the phase noise plot that the DUT has a very low phase noise profile with total jitter of 71 fs, rms. If we rms subtract the clock reference noise, the additive jitter of CDCDB803 under typical conditions would be lower than 71 fs, rms. Figure 6-1. CDCDB803 Clock Out (CK0:8) Phase Noise CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com

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7 Parameter Measurement Information

DUT Differential impedance 85 >100 k < 1 pF GND < 1 pF GND High Impedance Probe 10 inches/ 25.4 cm 2 pF 2 pF CK+ CK- Figure 7-1. AC Test Load (Referencing Intel DB2000QL Document) DUT CK+ CK- 0.75 V 0.75 V GND R2 GND SMA SMA 42.5 R1 = 47 Ω and R2 = 147 Ω. Figure 7-2. DC Simulation Load (Referencing Intel DB2000QL Document) www.ti.com CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: CDCDB803

8 Detailed Description

8.1 Overview

The CDCDB803 is a low additive-jitter, low propagation delay clock buffer designed to meet the strict performance requirements for PCIe Gen 1-6, QPI, UPI, SAS, and SATA reference clocks. The CDCDB803 allows buffering and replication of a single clock source to up to eight individual outputs in the LP-HCSL format. The CDCDB803 also includes status and control registers accessible by an SMBus version 2.0 compliant interface. The device integrates a large amount of external passive components to reduce overall system cost.

8.2 Functional Block Diagram

CLKIN_P CLKIN_N CK0_P CK0_N CK1_P CK1_N CK2_P CK2_N CK3_P CK3_N CK7_P CK7_N SMBDAT SMBCLK Glitch Free Output Control Logic Control Logic CKPWRGD_PD# OE[7:0]# SADR0 SADR1 SMBWRTLOCK

8.3 Feature Description

8.3.1 Fail-Safe Input

The CDCDB803 is designed to support fail-safe input operation feature. This feature allows the user to drive the device inputs before V DD is applied without damaging the device. Refer to the Absolute Maximum Ratings table for more information on the maximum input supported by the device.

8.3.2 Output Enable Control

The CDCDB803 uses SMBus and OE# to control the state of the output channels. The OE# pins control the state of the output with the same number. For example, the OE5# pin controls the state of the CK5 output driver. The SMBus registers may enable or disable the output when the corresponding OE# pin is held low.

8.3.3 SMBus

The CDCDB803 has an SMBus interface that is active only when CKPWRGD_PD# = 1. The SMBus allows individual enable/disable of each output. When CKPWRGD_PD# = 0, the SMBus pins are placed in a Hi-Z state, but all register settings are retained. The SMBus register values are only retained while VDD remains inside of the recommended operating voltage.

8.3.3.1 SMBus Address Assignment

The SMBus address is assigned by configuration of two pins (SADR1 and SADR0) that each support three levels. This configuration allows the CDCDB803 to assume nine different SMBus addresses. CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com

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The SMBus address pins are sampled when PWRGD is set to 1. See Table 8-1 for address pin configuration. The address can only be changed by power cycling the device. Table 8-1. SMBus Address Assignment SADR1 SADR0 SMBus ADDRESS : WRITE OPERATION (READ/WRITE=0) SMBus ADDRESS : READ OPERATION (READ/WRITE=1) L L 0xD8 0xD9 L M 0xDA 0xDB L H 0xDE 0xDF M L 0xC2 0xC3 M M 0xC4 0xC5 M H 0xC6 0xC7 H L 0xCA 0xCB H M 0xCC 0xCD H H 0xCE 0xCF

8.4 Device Functional Modes

8.4.1 CKPWRGD_PD# Function

The CKPWRGD_PD# pin is used to set two state variables inside of the device: PWRGD and PD#. The PWRGD and PD# variables control which functions of the device are active at any time, as well as the state of the input and output pins. The PWRGD and PD# states are multiplexed on the CKPWRGD_PD# pin. CKPWRGD_PD# must remain below VOL and not exceed V DDR + 0.3 V until V DD and V DDR are present and within the recommended operating conditions. After CKPWRGD_PD# is set high, a valid CLKIN must be present to use PD#. The first rising edge of the CKPWRGD_PD# pin sets PWRGD = 1. After PWRGD is set to 1, the CKPWRGD_PD# pin is used to assert PD# mode only. PWRGD variable will only be cleared to 0 with the removal of VDD and VDDR. PWRGD PD# CKPWRGD_PD# VDD/VDDR Figure 8-1. PWRGD and PD# State Changes www.ti.com CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: CDCDB803

8.4.2 OE[7:0]# and SMBus Output Enables

Each output channel, 0 to 7, can be individually enabled or disabled by a SMBus control register bit, called SMB enable bits. Additionally, each output channel has a dedicated, corresponding, OE[7:0]# hardware pin. The OE[7:0]# pins are asynchronously asserted-low signals that may enable or disable the output. Refer to Table 8-2 for enabling and disabling outputs through the hardware and software. Note that both the SMB enable bit must be a 1 and the OEx# pin must be an input low voltage 0 for the output channel to be active. Table 8-2. OE[7:0]# Functionality Control Inputs Power State Variables (Internal) CLKIN OE[7:0]# HARDWARE PINS AND SMBus CONTROL REGISTER BITS CK[7:0]_P/ CK[7:0]_NCKPWRGD_P D# PWRGD PD# OE[7:0]# OUT_EN_CLK[ 7:0] DRIVE_OP_ST ATE_CTRL 0 0 0 X X X X LOW/LOW X(1) X 0

0 LOW/LOW

1 TRI-STATE

Running(1) 0 1 X Running 0 0 X(2) X X (1) To enter the power-down state, CLKIN must remain active for at least 3 clock cycles after CKPWRGD_PD# transitions from 1 to 0. (2) To enter the powered-up state with active clock outputs, CLKIN must be active before CKPWRGD_PD# transitions from 0 to 1.

8.4.3 Output Slew Rate Control

The CDCDB803 provides output slew rate control feature which customer can use to compensate for increased output trace length based on their board design. The slew rate of a bank of 4 outputs 0 to 3 and 4 to 7, can be changed within a given range by a SMBus control register called CAPTRIM. Refer to Table 8-16 for more information.

8.4.4 Output Impedance Control

The integrated termination on the CDCDB803 can be programmed either for 85 Ω or 100 Ω. This flexibility ensures that the customer can use the same device across various applications irrespective of the characteristic board impedance which is typically either 85 Ω or 100 Ω. This termination resistor can be changed for all the outputs as whole using bit 5 of a register called OUTSET. Refer to Table 8-14 for more information.

8.5 Programming

The CDCDB803 uses SMBus to program the states of its eight output drivers. See SMBus for more information on the SMBus programming, and Register Maps for information on the registers. Table 8-3. Command Code Definition BIT DESCRIPTION 7 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation (6:0) Register address for Byte operations, or starting register address for Block, operations CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com

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8.6 Register Maps

8.6.1 CDCDB803 Registers

Table 8-4 lists the CDCDB803 registers. All register locations not listed in Table 8-4 should be considered as reserved locations and the register contents should not be modified. Table 8-4. CDCDB803 Registers Address Acronym Register Name Section 0h RCR1 Reserved Control Register 1 Go 1h OECR1 Output Enable Control 1 Go 2h OECR2 Output Enable Control 2 Go 3h OERDBK Output Enable# Pin Read Back Go 4h RCR2 Reserved Control Register 2 Go 5h VDRREVID Vendor/Revision Identification Go 6h DEVID Device Identification Go 7h BTRDCNT Byte Read Count Control Go 8h OUTSET Output Setting Control Go 4Ch CAPTRIM Slew Rate Capacitor Cluster 1 & 2 Go Complex bit access types are encoded to fit into small table cells. Table 8-5 shows the codes that are used for access types in this section. Table 8-5. CDCDB803 Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value

8.6.1.1 RCR1 Register (Address = 0h) [reset = 47h]

RCR1 is shown in Table 8-6. Return to the Summary Table. The RCR1 register contains reserved bits. Table 8-6. RCR1 Register Field Descriptions Bit Field Type Reset Description 7-4 Reserved R 4h Reserved. 3-0 Reserved R/W 7h Writing to these bits will not affect the functionality of the device.

8.6.1.2 OECR1 Register (Address = 1h) [reset = FFh]

OECR1 is shown in OECR1 Register Field Descriptions. Return to the Summary Table. The OECR1 register contains bits that enable or disable individual output clock channels [5:0]. CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com

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Table 8-7. OECR1 Register Field Descriptions Bit Field Type Reset Description

7 OUT_EN_CLK5 R/W 1h This bit controls the output enable signal for output channel CK5_P/

CK5_N. 0h = Output Disabled 1h = Output Enabled

6 OUT_EN_CLK4 R/W 1h This bit controls the output enable signal for output channel CK4_P/

CK4_N. 0h = Output Disabled 1h = Output Enabled

5 OUT_EN_CLK3 R/W 1h This bit controls the output enable signal for output channel CK3_P/

CK3_N. 0h = Output Disabled 1h = Output Enabled

4 OUT_EN_CLK2 R/W 1h This bit controls the output enable signal for output channel CK2_P/

CK2_N. 0h = Output Disabled 1h = Output Enabled 3 Reserved R/W 1h Writing to this bit will not affect the functionality of the device.

2 OUT_EN_CLK1 R/W 1h This bit controls the output enable signal for output channel CK1_P/

CK1_N. 0h = Output Disabled 1h = Output Enabled

1 OUT_EN_CLK0 R/W 1h This bit controls the output enable signal for output channel CK0_P/

CK0_N. 0h = Output Disabled 1h = Output Enabled 0 Reserved R/W 1h Writing to this bit will not affect the functionality of the device.

8.6.1.3 OECR2 Register (Address = 2h) [reset = 0Fh]

OECR2 is shown in OECR2 Register Field Descriptions. Return to the Summary Table. The OECR2 register contains bits that enable or disable individual output clock channels [7:6]. Table 8-8. OECR2 Register Field Descriptions Bit Field Type Reset Description 7-3 Reserved R/W 1h Writing to these bits will not affect the functionality of the device.

2 OUT_EN_CLK7 R/W 1h This bit controls the output enable signal for output channel CK7_P/

CK7_N. 0h = Output Disabled 1h = Output Enabled 1 Reserved R/W 1h Writing to this bit will not affect the functionality of the device.

0 OUT_EN_CLK6 R/W 1h This bit controls the output enable signal for output channel CK6_P/

CK6_N. 0h = Output Disabled 1h = Output Enabled

8.6.1.4 OERDBK Register (Address = 3h) [reset = 0h]

OERDBK is shown in Table 8-9. Return to the Summary Table. www.ti.com CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: CDCDB803

The OERDBK register contains bits that report the current state of the OE[7:0]# input pins. Table 8-9. OERDBK Register Field Descriptions Bit Field Type Reset Description 7 RB_OE7 R 0h This bit reports the logic level present on the OE7# pin. 6 RB_OE6 R 0h This bit reports the logic level present on the OE6# pin. 5 RB_OE5 R 0h This bit reports the logic level present on the OE5# pin. 4 RB_OE4 R 0h This bit reports the logic level present on the OE4# pin. 3 RB_OE3 R 0h This bit reports the logic level present on the OE3# pin. 2 RB_OE2 R 0h This bit reports the logic level present on the OE2# pin. 1 RB_OE1 R 0h This bit reports the logic level present on the OE1# pin. 0 RB_OE0 R 0h This bit reports the logic level present on the OE0# pin.

8.6.1.5 RCR2 Register (Address = 4h) [reset = 0h]

RCR2 is shown in RCR2 Register Field Descriptions. Return to the Summary Table. The RCR2 register contains reserved bits. Table 8-10. RCR2 Register Field Descriptions Bit Field Type Reset Description 7-0 Reserved R 0h Reserved.

8.6.1.6 VDRREVID Register (Address = 5h) [reset = 0Ah]

VDRREVID is shown in Table 8-11. Return to the Summary Table. The VDRREVID register contains a vendor identification code and silicon revision code. Table 8-11. VDRREVID Register Field Descriptions Bit Field Type Reset Description 7-4 REV_ID R 0h Silicon revision code. Silicon revision code bits [3:0] map to register bits [7:4] directly. 3-0 VENDOR_ID R Ah Vendor identification code. Vendor ID bits [3:0] map to register bits [3:0] directly.

8.6.1.7 DEVID Register (Address = 6h) [reset = E7h]

DEVID is shown in Table 8-12. Return to the Summary Table. The DEVID register contains a device identification code. Table 8-12. DEVID Register Field Descriptions Bit Field Type Reset Description 7-0 DEV_ID R E7h Device ID code. Device ID bits[7:0] map to register bits[7:0] directly. CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com

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8.6.1.8 BTRDCNT Register (Address = 7h) [reset = 8h]

BTRDCNT is shown in Table 8-13. Return to the Summary Table. The BTRDCNT register contains bits [4:0] which configure the number of bytes which will be read back. Table 8-13. BTRDCNT Register Field Descriptions Bit Field Type Reset Description 7-5 Reserved R/W 0h Writing to these bits will not affect the functionality of the device.

4 BYTE_COUNTER R/W 0h

Writing to this register configures how many bytes will be read back. 3-0 BYTE_COUNTER R/W 8h

8.6.1.9 OUTSET Register (Address = 8h) [reset = 0h]

OUTSET is shown in Table 8-14. Return to the Summary Table. Bit5 of the OUTSET register sets the termination for all the outputs while bit4 can be used to set the power-down state for all outputs. The remaining bits for this register are reserved. Table 8-14. OUTSET Register Field Descriptions Bit Field Type Reset Description 7-6 Reserved R 0h Reserved.

5 CH_ZOUT_SEL R/W 0h Select between 85 Ω (0) and 100 Ω (1) Output impedance

4 d_DRIVE_OP_STATE_CTRL R/W 0h Power-down state of all output clocks. 0: LOW/LOW 1: TRI_STATE 3-0 Reserved R/W 0h Register bits can be written to 0. Writing a different value than 0 will affect device functionality.

8.6.1.10 CAPTRIM Register (Address = 4Ch) [reset = 66h]

CAPTRIM is shown in Table 8-16. Return to the Summary Table. Bits [7:4] of the CAPTRIM register is used to control the slew rate for output channel cluster 2. Bits [3:0] control the slew rate for output channel cluster 1. Refer below for cluster identification. Table 8-15. Cluster Identification Cluster Outputs

1 CK3, CK2, CK1, CK0

2 CK7, CK6, CK5, CK4

Table 8-16. CAPTRIM Register Field Descriptions Bit Field Type Reset Description 7-4 CLUSTER2_CAP_TRIM R/W 6h Slew Rate Reduction Cap Trim for Cluster 2. Default value of 6h. 0: minimum F: maximum 3-0 CLUSTER1_CAP_TRIM R/W 6h Slew Rate Reduction Cap Trim for Cluster 1. Default value of 6h. 0: minimum F: maximum www.ti.com CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: CDCDB803

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The CDCDB803 is a fanout buffer that supports PCIe generation 4 and PCIe generation 5 REFCLK distribution. The device is used to distribute up to eight copies of a typically 100-MHz clock.

9.2 Typical Application

Figure 9-1 shows a CDCDB803 typical application. In this application, a clock generator provides a 100-MHz reference to the CDCDB803 which then distributes that clock to PCIe endpoints. The clock generator may be a discrete clock generator like the CDCI6214 or it may be integrated in a larger component such as a Platform Controller Hub (PCH) or application processor. PCIe Gen 4-5 Clock Generator CDCDB803 8x LP-HSCL Output Buffer SMBus Control OE# Control LP-HCSL PCIe PHYPCIe PHYPCIe PHYPCIe PHY LP-HCSL PCIe PHYPCIe PHYPCIe Device Control Interface Figure 9-1. Typical Application

9.2.1 Design Requirements

Consider a typical server motherboard application which must distribute a 100-MHz PCIe reference clock from the PCH of a processor chipset to multiple endpoints. An example of clock input and output requirements is:

• Clock Input: – 100-MHz LP-HCSL
• Clock Output: – 2x 100-MHz to processors, LP-HCSL – 3x 100-MHz to riser/retimer, LP-HCSL – 3x 100-MHz to DDR memory controller, LP-HCSL CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com

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9.2.2 Detailed Design Procedure

The following items must be determined before starting design of a CDCDB803 socket:

• Output Enable Control Method
• SMBus address

9.2.2.1 Output Enable Control Method

The device provides an option to either use SMBus programmed registers (software) to control the outputs or by using the hardware OE# pins. In case of using software to control the outputs, the hardware OE# pins can be left floating as each of these pins have a pulldown to ground. Refer to Table 8-2 and the Register Maps section for more information on programming the register. When the user wants to control the outputs with the hardware OE# pins, they can do so for example by connecting these pins to a GPIO controller and follow the Pin Configuration and Functions section to set the outputs to HIGH/LOW. The bits OUT_EN_CLK7 to OUT_EN_CLK0 used to control the outputs are shown in registers OECR1 ( Table 8-7) and OECR2 ( Table 8-8). These register bits are set to 1 by default to ensure that the outputs are "software enabled" and their state is therefore set by hardware OE# pins.

9.2.2.2 SMBus Address

An SMBus address should be selected from the listed potential addresses in Table 8-1. The appropriate pullup or pulldown resistor should be placed on the SADRx pins as indicated in the table. Ensure the SMBus address is not already in use to avoid conflict.

9.2.3 Application Curves

Figure 6-1 in the Typical Characteristics section can be used as both an application curve and a typical characteristics plot in this example. The Figure 9-2 and Figure 9-3 show characterization data for the Output slew rate for various CAPTRIM codes and across temperature. Customers can use these plots as reference for choosing the appropriate output slew rate based on their system requirement. Figure 9-2. Output Slew Rate vs. CAPTRIM Code Temperature (qC) Slew Rate (V/ns) 120 100 80 60 40 20 0 -20 -40 -60 D002 0 - 3.3 V 1 - 3.3 V 2 - 3.3 V 3 - 3.3 V 4 - 3.3 V 5 - 3.3 V 6 - 3.3 V 7 - 3.3 V 8 - 3.3 V 9 - 3.3 V 10 - 3.3 V 11 - 3.3 V 12 - 3.3 V 13 - 3.3 V Figure 9-3. Slew Rate Variation Across Temperature for Different CAPTRIM Code www.ti.com CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: CDCDB803

10 Power Supply Recommendations

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when the jitter and phase noise is critical to applications. Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the very low impedance path for high-frequency noise and guards the power-supply system against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, place the capacitors very close to the power-supply terminals and lay out with short loops to minimize inductance. TI recommends to insert a ferrite bead between the board power supply and the chip power supply that isolates the high-frequency switching noises generated by the clock buffer. These beads prevent the switching noise from leaking into the board supply. It is imperative to choose an appropriate ferrite bead with very low DC resistance to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at the supply terminals that is greater than the minimum voltage required for proper operation. Figure 10-1 shows the recommended power supply filtering and decoupling method. F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F

3.3 V VDD

F 0.1 F

3.3 V VDDR

2.2 Figure 10-1. Power Supply Decoupling CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com

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11 Layout

11.1 Layout Guidelines

The following section provides the layout guidelines to ensure good thermal performance and power supply connections for the CDCDB803. In Layout Examples , the CDCDB803 has 85- Ω differential output impedance LP-HCSL format drivers as per register default settings. All transmission lines connected to CKx pins should be 85- Ω differential impedance, 42.5-Ω single-ended impedance to avoid reflections and increased radiated emissions. If 100- Ω output impedance is enabled, the transmission lines connected to CKx pins should be 100- Ω differential impedance, 50-Ω single-ended impedance. Take care to eliminate or reduce stubs on the transmission lines.

11.2 Layout Examples

Figure 11-1 through Figure 11-3 are printed circuit board (PCB) layout examples that show the application of thermal design practices and a low-inductance ground connection between the device DAP and the PCB. Figure 11-1. PCB Layout Example for CDCDB803, Top layer www.ti.com CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: CDCDB803

Figure 11-2. PCB Layout Example for CDCDB803, GND Layer Figure 11-3. PCB Layout Example for CDCDB803, Bottom Layer CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 www.ti.com

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12 Device and Documentation Support

12.1 Device Support

12.1.1 TICS Pro

TICS Pro is an offline software tool for EVM programming and also for register map generation to program a device configuration for a specific application. For TICS Pro, go to https://www.ti.com/tool/TICSPRO-SW.

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com CDCDB803 SNAS820A – AUGUST 2021 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: CDCDB803

www.ti.com 8-Jan-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CDCDB803ERSLR Active Production VQFN (RSL) | 48 4000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 CDCB803 CDCDB803ERSLR.A Active Production VQFN (RSL) | 48 4000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 CDCB803 CDCDB803ERSLT Active Production VQFN (RSL) | 48 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 CDCB803 CDCDB803ERSLT.A Active Production VQFN (RSL) | 48 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 CDCB803 CDCDB803RSLR Active Production VQFN (RSL) | 48 4000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 CDCB803 CDCDB803RSLR.A Active Production VQFN (RSL) | 48 4000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 CDCB803 CDCDB803RSLT Active Production VQFN (RSL) | 48 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 CDCB803 CDCDB803RSLT.A Active Production VQFN (RSL) | 48 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 CDCB803 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 8-Jan-2026 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCDB803ERSLR VQFN RSL 48 4000 367.0 367.0 35.0 CDCDB803ERSLT VQFN RSL 48 250 210.0 185.0 35.0 CDCDB803RSLR VQFN RSL 48 4000 353.0 353.0 32.0 CDCDB803RSLT VQFN RSL 48 250 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRSL 48 QUAD FLATPACK - NO LEAD6 x 6, 0.4 mm pitch 4225749/A

www.ti.com PACKAGE OUTLINE 6.1 5.9 6.1 5.9 1.0 0.80.05 0.00 2X 4.4 44X 0.4 2X 4.4 48X 0.5 0.3 4.2 0.1 48X 0.25 0.15 (0.2) TYP VQFN - 1 mm max heightRSL0048G PLASTIC QUAD FLATPACK - NO LEAD 4231403/A 12/2024 0.08 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID (45 X 0.3) SYMM EXPOSED THERMAL PAD SYMM 13 24 3748

0.1 C A B

0.05 C SCALE 2.300 AB C

www.ti.com EXAMPLE BOARD LAYOUT 44X (0.4) (R0.05) TYP

0.05 MAX

0.05 MIN

48X (0.55) 48X (0.2) (5.75) (5.75) ( 4.2) ( 0.2) TYP VIA (0.69) TYP (1.16) TYP (0.69) TYP (1.16) TYP VQFN - 1 mm max heightRSL0048G PLASTIC QUAD FLATPACK - NO LEAD 4231403/A 12/2024 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE SOLDER MASK DETAIL 13 24 3748 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 48X (0.55) 48X (0.2) 44X (0.4) (5.75) (5.75) 9X (1.18) (1.18) (R0.05) TYP (1.38) TYP (1.38) TYP VQFN - 1 mm max heightRSL0048G PLASTIC QUAD FLATPACK - NO LEAD 4231403/A 12/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 MM THICK STENCIL SCALE: 15X EXPOSED PAD 49 71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 13 24 3748

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