XM014035B

XU316-1024-FB265 XMOS | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 101

Technical content

It is our intention to provide you with accurate and comprehensive documentation for the hardware and software components used in this product. To subscribe to receive updates, visit http://www.xmos.ai/. XMOS Ltd.is the owner or licensee of the information in this document and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd.makes no representation that the information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. XMOS and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other countries, and may not be used without written permission. Company and product names mentioned in this document are the trademarks or registered trademarks of their respective owners. /one.pnum

/one.pnum xCORE Multicore Microcontrollers The xcore.ai series is a comprehensive range of /three.pnum/two.pnum-bit multicore microcontrollers that brings the low latency and timing determinism of the xCORE architecture to mainstream embedded applications. Unlike conventional microcontrollers, xCORE multicore micro- controllers execute multiple real-time tasks simultaneously and communicate between tasks using a high speed network. Because xCORE multicore microcontrollers are com- pletely deterministic when executing from internal memory, you can write software to implement functions that traditionally require dedicated hardware. X0Dxx I/O pins xTIME scheduler Hardware response ports core PLL app PLL JTAG X1Dxx I/O pins xTIME scheduler Hardware response ports xCONNECT Switch Internal SRAM OTPALU (FP + int) Vector unit Internal SRAMOTP ALU (FP + int) Vector unit Memory Buffer Processor Switch Processor Switch xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core dual lane MIPI DPHY High speed USB PHY Optional external LPDDR memory Figure /one.pnum: FB/two.pnum6/five.pnum block diagram

• Tiles: Devices consist of one or more xCORE tiles. Each tile contains between /uniFB01ve and eight /three.pnum/two.pnum-bit logical cores with highly integrated I/O and on-chip memory.
• Logical cores Each logical core can execute tasks such as computational code, DSP code, Floating point operations, Vector operationns, control software (including logic decisions and executing a state machine) or software that handles I/O. Section 6./one.pnum
• xTIME scheduler The xTIME scheduler performs functions similar to an RTOS, in hard- ware. It services and synchronizes events in a core, so there is no requirement for in- terrupt handler routines. The xTIME scheduler triggers cores on events generated by hardware resources such as the I/O pins, communication channels and timers. Once triggered, a core runs independently and concurrently to other cores, until it pauses to wait for more events. Section 6./two.pnum
• Channels and channel ends Tasks running on logical cores communicate using chan- nels formed between two channel ends. Data can be passed synchronously or asyn- chronously between the channel ends assigned to the communicating tasks. Section 6./five.pnum
• xCONNECT Switch and Links Between tiles, channel communications are implemented over a high performance network of xCONNECT Links and routed through a hardware xCONNECT Switch. Section 6.6 /two.pnum

• Ports The I/O pins are connected to the processing cores by Hardware Response ports. The port logic can drive its pins high and low, or it can sample the value on its pins optionally waiting for a particular condition. Section 6./three.pnum
• Clock blocks xCORE devices include a set of programmable clock blocks that can be used to govern the rate at which ports execute. Section 6./four.pnum
• Memory Each xCORE Tile integrates a bank of SRAM for instructions and data, and a block of one-time programmable (OTP) memory that can be con/uniFB01gured for system wide security features. A memory buffer can be used to interface to an optional exter- nal LPDDR memory, or to implement software de/uniFB01ned memory. Section /one.pnum/zero.pnum
• Dual PLL One PLL is used to create a high-speed processor clock given a low speed external oscillator. A secondary PLL is for user application. Section /seven.pnum
• USB The USB PHY provides High-Speed and Full-Speed, device, host, and on-the-go functionality. Data is communicated through ports on the digital node. A library is provided to implement USB device functionality. Section /one.pnum/one.pnum
• MIPI The MIPI D-PHY receiver provides a hi speed communication link to single or dual lane MIPI devices. Section /one.pnum/two.pnum
• JTAG The JTAG module can be used for loading programs, boundary scan testing, in-circuit source-level debugging and programming the OTP memory. Section /one.pnum/three.pnum /one.pnum./one.pnum Software Devices are programmed using C, C++ or xC (C with multicore extensions). XMOS pro- vides tested and proven software libraries, which allow you to quickly add interface and processor functionality such as USB, Voice, Ethernet, PWM, graphics driver, and audio EQ to your applications. /one.pnum./two.pnum xTIMEcomposer Studio The xTIMEcomposer Studio development environment provides all the tools you need to write and debug your programs, pro/uniFB01le your application, and write images into /uniFB02ash mem- ory or OTP memory on the device. Because xCORE devices operate deterministically, they can be simulated like hardware within xTIMEcomposer: uniquely in the embedded world, xTIMEcomposer Studio therefore includes a static timing analyzer, cycle-accurate simulator, and high-speed in-circuit instrumentation. The tools are supported on Windows, Linux and MacOS X and available at no cost from xmos.ai/downloads. Information on using the tools is provided in the xTIMEcomposer /three.pnum

• Multicore Microcontroller with Advanced Multi-Core RISC Architecture
• /one.pnum6 real-time logical cores on /two.pnum xCORE tiles
• Cores share up to /one.pnum/two.pnum/zero.pnum/zero.pnum MIPS — Up to /two.pnum/four.pnum/zero.pnum/zero.pnum MIPS in dual issue mode — Up to /one.pnum/two.pnum/zero.pnum/zero.pnum MFLOPS
• Each logical core has: — Guaranteed throughput of between /one.pnum//five.pnumand /one.pnum/8 of tile MIPS — /one.pnum6x/three.pnum/two.pnumbit dedicated registers — All have single clock-cycle execution (except for divide)
• Vector unit, capable of: — up to eight word, /one.pnum6 half-word, or /three.pnum/two.pnum byte multiply-adds. — quad complex multiply, or /two.pnum/five.pnum6 bit-wide multiply-adds.
• USB PHY, fully compliant with USB /two.pnum./zero.pnum speci/uniFB01cation
• MIPI receiver, up to two lanes, up to /one.pnum./five.pnum Gbit/s
• Application PLL with fractional control
• Programmable I/O
• /one.pnum/two.pnum8 general-purpose I/O pins, con/uniFB01gurable as input or output — 8 xCONNECT links
• Port sampling rates of up to 6/zero.pnum MHz with respect to an external clock
• 6/four.pnum channel ends (/three.pnum/two.pnum per tile) for communication with other cores, on or off-chip
• Memory
• /one.pnumMB internal single-cycle SRAM (/five.pnum/one.pnum/two.pnumKB per tile) for code and data storage
• 8KB internal OTP (shared between tiles or split providing /four.pnumKB per tile) for application boot code
• Hardware resources
• /one.pnum/two.pnum clock blocks (6 per tile)
• /two.pnum/zero.pnum timers (/one.pnum/zero.pnum per tile)
• 8 locks (/four.pnum per tile)
• JTAG Module for On-Chip Debug
• Security Features
• Programming lock disables debug and prevents read-back of memory contents
• AES bootloader ensures secrecy of IP held on external /uniFB02ash memory
• Ambient Temperature Range
• /zero.pnum°C to /seven.pnum/zero.pnum°C
• Speed Grade
• Power Consumption
• /three.pnum/zero.pnum/zero.pnum mA (typical)
• /two.pnum6/five.pnum-pin FBGA package /zero.pnum.8 mm pitch /four.pnum

/three.pnum Pin Con/uniFB01guration X0D04 X0D65 32A WEN X0D61 32A CKE VSS VSS X0D49 32A X0D51 32A X0D41 A11 X0D39 A13 VSS X0D32 DQ2 X0D30 DQ4 X1D34 DQ6 X1D32 LDQS X1D31 LDM VDDIOT X0D67 32A RASN X0D07 X0D64 32A BA0 VSS VDDIOT X0D50 32A X0D52 32A X1D43 X0D40 A12 VDDIOTX0D06 X0D34 DQ0 X0D33 DQ1 X0D31 DQ3 X1D35 DQ5 X1D33 DQ7 VSS X0D66 32A CASN X0D01 X0D63 32A BA1 X0D58 32A CK X0D57 32A CKN X0D55 32A X0D53 32A X0D42 A10 VSS VSSX0D05 VSS VDDIOT X1D29 DQ14 X1D27 DQ12 X1D25 DQ10 X0D70 32A DQ8 X0D68 32A UDM X0D00 X0L4 VSS X0D62 32A CSN X0D56 32A X0D54 32A X0D43 VSS X0D37 X0L3 X0D38 X0L3 X0D10 X0L4 X0D15 X0L4 X0D14 X0L4 X1D30 DQ15 X1D28 DQ13 X1D26 DQ11 X1D24 DQ9 X0D69 32A UDQS X0D18 X0L4 VDD VSS VDD VSS X0D29 X0L3 X0D35 X0L3 X0D26 X0L3 X0D36 X0L3 X0D11 X0L4 X0D17 X0L4 X0D16 X0L4 VSS VDD VSS VDD VDDIOT X0D20 X0L4 VDD X0D27 X0L3 X0D28 X0L3 X0D24 X0L3 X0D25 X0L3 X0D19 X0L4 X1D39 X0L5 X1D38 X0L5 VDD X1D36 X0L5 VSS VSS VDDIOR X1D66 32A X0L2 X1D67 32A X0L2 X1D69 32A X0L2 X1D70 32A X0L2 X0D21 X0L5 X1D41 X0L5 X1D40 X0L5 VDDIOL VSS VSS VSS X1D42 X0L5 VSS VSS VDD X1D64 32A X0L2 X1D65 32A X0L2 X1D63 32A X0L2 X1D68 32A X0L2 X1D37 X0L5 X1D02 X0L5 X1D03 X0L5 VDD VSS VSS VSS X1D04 X0L6 VSS VSS VDD VSS VDDIOR X1D61 32A X0L2 X1D62 32A X0L2 X1D05 X0L6 VDDIOL VSS VDD VSS VSS VSS X1D09 X0L6 VSS VSS VDD VSS VSS X1D57 32A X0L1 X1D58 32A X0L1 X1D06 X0L6 X1D08 X0L6 X1D07 X0L6 VDD VSS VSS VSS X1D11 X0L6 VSS VSS VSS X1D54 32A X0L1 X1D55 32A X0L1 X1D51 32A X0L1 X1D56 32A X0L1 X1D10 X0L6 X1D01 X0L6 X1D00 X0L6 VSS VSS VSS VSS MIPI_ VDD18 VDDIOR X1D52 32A X0L1 X1D53 32A X0L1 X1D49 32A X0L1 X1D50 32A X0L1 MIPI_ GND09 VSS VSS VDDIOL MIPI_ DN2 VDD VDDIOB18 VDD VSS X1D18 X0L0 X1D19 X0L0 X1D21 X0L0 X1D22 X0L0 MIPI_ DP2 MIPI_ VDD09 VSS VSS VDD VDDIOB18 VDD VDD MIPI_ DN1 OTP_ VCC NC VSS VSS X1D16 X0L0 X1D17 X0L0 X1D15 X0L0 X1D20 X0L0 MIPI_ DP1 VSS NC LV_L_ N LV_T_ N X0D12 X0L7 X0D22 X0L7 VDDIOB18 MIPI_ DN0 LV_R_ N NC NC VSS VSS VSS X1D13 X0L0 X1D14 X0L0 MIPI_ DP0 VSS RST_N TRST_ N DEBUG_ N X0D13 X0L7 X0D23 X0L7 VSS VSS X1D12 X0L7 NC VSS USB_ ID USB_ VDD33 USB_ GND18 VSS VDDIORPOR_ DISABLE VDDIOB18 TDO PLL_ AGND PLL_ AGND2 TMS X0D02 X0L7 X0D08 X0L7 XOUT X1D23 X0L7 VSS VSS USB_ DM USB_ DP USB_ VDD18 VSS VSSXIN VSS TDI PLL_ AVDD PLL_ AVDD2 TCK X0D03 X0L7 X0D09 X0L7 A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Any pin marked NC should not be connected to any net. /five.pnum

/four.pnum Signal Description and GPIO provides a combination of /one.pnumbit, /four.pnumbit, 8bit and /one.pnum6bit ports, as well as wider ports that are fully or partially (gray) bonded out. All pins of a port provide either output or input, but signals in different directions cannot be mapped onto the same port. Pins may have one or more of the following properties:

• PD/PU: The IO pin has a weak pull-down or pull-up resistor.
• ST: The IO pin has a Schmitt Trigger on its input.
• IOL, IOB, IOR, IOT: The IO pin is powered from VDDIOL, VDDIOB/one.pnum8, VDDIOR, and VDDIOT respectively. Note that all GPIO have optional pull-down, pull-up, and Schmitt triggers. The GPIO func- tions are as follows:
• XLin in/out: this pin can be used for xlink iwire n, input or output.
• NXm: this pin can be used by bit mof N-bit port X
• Any other signal name refers to how this pin can be used for the LPDDR interface Power pins (/one.pnum/two.pnum) Signal Pin Function Type Properties MIPI_VDD/zero.pnum/nine.pnum N/three.pnumMIPI Analog power PWR MIPI_VDD/one.pnum8 M/one.pnumMIPI Analog power PWR OTP_VCC P/one.pnum/zero.pnumOTP power supply PWR PLL_AVDD U/five.pnum Analog power for PLL PWR PLL_AVDD/two.pnum U6Analog power for secondary PLL PWR USB_VDD/one.pnum8 U/one.pnum/five.pnumUSB Analog power PWR USB_VDD/three.pnum/three.pnum T/one.pnum/four.pnumUSB Analog power PWR VDD ... Digital tile power PWR VDDIOB/one.pnum8 ... Digital I/O power (bottom) PWR VDDIOL ... Digital I/O power (left) PWR VDDIOR ... Digital I/O power (right) PWR VDDIOT ... Digital I/O power (top) PWR I/O pins (/one.pnum/two.pnum8) Signal Pin Function Type Properties in /one.pnumA/zero.pnum I/O IOL (continued)

Signal Pin Function Type Properties in /one.pnumC/zero.pnum I/O IOL in /one.pnumD/zero.pnum I/O IOL in /one.pnumE/zero.pnum I/O IOB in /one.pnumF/zero.pnum I/O IOB in /one.pnumG/zero.pnum I/O IOB in /one.pnumH/zero.pnum I/O IOB in /one.pnumI/zero.pnum I/O IOR in /one.pnumJ/zero.pnum I/O IOR out /one.pnumL/zero.pnum I/O IOR out /one.pnumM/zero.pnum8D/zero.pnum/one.pnum6B8 I/O IOR (continued) /seven.pnum

Signal Pin Function Type Properties out /one.pnumA/zero.pnum I/O IOL out /one.pnumB/zero.pnum I/O IOL X/one.pnumD/zero.pnum6 K/two.pnumXL6/two.pnum X/one.pnumD/zero.pnum8 K/three.pnumXL6/zero.pnum out /one.pnumC/zero.pnum I/O IOL out /one.pnumD/zero.pnum I/O IOL out /one.pnumE/zero.pnum I/O IOB in /one.pnumF/zero.pnum I/O IOR out /one.pnumG/zero.pnum I/O IOR out /one.pnumH/zero.pnum I/O IOB (continued)

Signal Pin Function Type Properties in /one.pnumM/zero.pnum8D/zero.pnum/one.pnum6B8 I/O IOL out 8D/four.pnum/one.pnum6B/one.pnum/two.pnum I/O IOL out 8D/five.pnum/one.pnum6B/one.pnum/three.pnum I/O IOL out 8D6 /one.pnum6B/one.pnum/four.pnum I/O IOL in /three.pnum/two.pnumA/zero.pnum I/O IOR in /three.pnum/two.pnumA/one.pnum I/O IOR in /three.pnum/two.pnumA/two.pnum I/O IOR in /three.pnum/two.pnumA/three.pnum I/O IOR in /three.pnum/two.pnumA/four.pnum I/O IOR out /three.pnum/two.pnumA/five.pnum I/O IOR out /three.pnum/two.pnumA6 I/O IOR out /three.pnum/two.pnumA/seven.pnum I/O IOR out /three.pnum/two.pnumA8 I/O IOR out /three.pnum/two.pnumA/nine.pnum I/O IOR in /three.pnum/two.pnumA/one.pnum/zero.pnumI/O IOR in /three.pnum/two.pnumA/one.pnum/one.pnumI/O IOR in /three.pnum/two.pnumA/one.pnum/two.pnumI/O IOR in /three.pnum/two.pnumA/one.pnum/three.pnumI/O IOR in /three.pnum/two.pnumA/one.pnum/four.pnumI/O IOR out /three.pnum/two.pnumA/one.pnum/five.pnum I/O IOR out /three.pnum/two.pnumA/one.pnum6 I/O IOR out /three.pnum/two.pnumA/one.pnum/seven.pnumI/O IOR out /three.pnum/two.pnumA/one.pnum8 I/O IOR out /three.pnum/two.pnumA/one.pnum/nine.pnumI/O IOR ground pins (/five.pnum) Signal Pin Function Type Properties MIPI_GND/zero.pnum/nine.pnum M/two.pnumMIPI Analog ground GND PLL_AGND T/five.pnum Analog ground for PLL GND (continued) /nine.pnum

Signal Pin Function Type Properties PLL_AGND/two.pnum T6Analog ground for secondary PLL GND USB_GND/one.pnum8 T/one.pnum/five.pnumUSB Analog ground GND VSS ... Digital ground GND mipi pins (6) Signal Pin Function Type Properties MIPI_DN/zero.pnum R/one.pnumMIPI lane /zero.pnum, negative Input MIPI_DN/one.pnum P/one.pnumMIPI lane /one.pnum, negative Input MIPI_DN/two.pnum N/one.pnumMIPI lane /two.pnum, negative Input MIPI_DP/zero.pnum R/two.pnumMIPI lane /zero.pnum, positive Input MIPI_DP/one.pnum P/two.pnumMIPI lane /one.pnum, positive Input MIPI_DP/two.pnum N/two.pnumMIPI lane /two.pnum, positive Input poc pins (/three.pnum) Signal Pin Function Type Properties LV_L_N P/five.pnum Select low voltage VDDIOL, active low Input IOB, PU LV_R_N R/one.pnum/zero.pnumSelect low voltage VDDIOR, active low Input IOB, PU LV_T_N P6 Select low voltage VDDIOT, active low Input IOB, PU jtag pins (/seven.pnum) Signal Pin Function Type Properties POR_DISABLE T/two.pnumDisable on chip Power-On-Reset Input IOB, PD RST_N R/four.pnum Global reset input, active low Input IOB, PU, ST TCK U/seven.pnum Test clock Input IOB, PD, ST TDI U/four.pnum Test data input Input IOB, PU TDO T/four.pnum Test data output Output IOB TMS T/seven.pnum Test mode select Input IOB, PU TRST_N R/five.pnum Test reset input, active low Input IOB, PU, ST System pins (/one.pnum) Signal Pin Function Type Properties DEBUG_N R6 Multi-chip debug, active low I/O IOB, PU usb pins (/three.pnum) Signal Pin Function Type Properties USB_DM U/one.pnum/three.pnumUSB Data- I/O USB_DP U/one.pnum/four.pnumUSB Data+ I/O (continued) /one.pnum/zero.pnum

Signal Pin Function Type Properties USB_ID T/one.pnum/three.pnumUSB Identi/uniFB01cation Input analog pins (/two.pnum) Signal Pin Function Type Properties XIN U/two.pnum Crystal in or clock input Input IOB XOUT U/one.pnum Crystal out Output IOB The device has four IO power domains, three of which can be run from either /three.pnum./three.pnumV or /one.pnum.8V nominal supplies. Three pins, LV_L_N, LV_T_N, and LV_R_N specify which voltage is used on the left, top, and right power domains. These pins should be tied low to specify a domain uses a /one.pnum.8V nominal supply, and should be tied high or left /uniFB02oating to specify the domain uses a /three.pnum./three.pnumV nominal supply. The table above states which GPIO pin is powered from which IO domain. Note that the bottom IO domain, which includes JTAG and the crystal oscillator, is always at /one.pnum.8V. The GPIO pins have software programmable drive strengths, slew rate control, and schmitt trigger:

• When a port is used for output, the default drive settings for each IO pin are to drive at /four.pnum mA nominally, with no slew rate control (fast edge). When a port is used as input, the default settings when you use a port as an input port is to not have a Schmitt-trigger, and not have a pull resistor. From software, the drive strength can be reduced to /two.pnum mA in order to reduce EMI, or they can be driven at 8 or /one.pnum/two.pnum mA in order to increase speed. The total current that can be supplied by each IO domain is limited and speci/uniFB01ed in Section /one.pnum/five.pnum.
• When used as an input, IO pins can be programmed to have a Schmitt trigger enabled, and two programmable pull resistors can be set to either provide a weak pull-down, a weak pull-up, or a bus keep function where the current level is kept until it is changed by a strong low or a strong high. Pins that are not in use have a weak pull-down enabled to keep them in a de/uniFB01ned state.
• The controls are set on a per-port basis by either using the API functions, or by setting six bits using the SETC instruction. /one.pnum/one.pnum

/five.pnum Example Application Diagram XnDnn VDDIOT VDDIOL VDDIOB18 VDDIOR 1V8 in out VDD PLL_AVDD 0V9 in out XIN XOUT

24 MHz

MIPI_VDD18 MIPI_DP0 MIPI_DN0 MIPI_DP1 MIPI_DN1 MIPI_DP2 MIPI_DN2 MIPI MIPI_VDD09 Optional Lane 1 Lane 2 Clock USB_VDD18 USB_VDD33 USB_DP USB_DM USB Optional USB_ID RST_N NC, or external reset TRST_N 3V3 1V8 3V3 1V8 3V3 1V8 3V3 in out Opt OTP_VCC X0D01 X0D04 X0D05 X0D06 X0D07 X0D10 QSPI Flash VDDIOL LPDDR RAM ... VDDIOTOptional PLL_AVDD2 Figure /two.pnum: Simpli/uniFB01ed Reference Schematic

• see Section /one.pnum/one.pnum for details on the USB PHY
• see Section /one.pnum/two.pnum for details on the MIPI D-PHY receiver
• see Section /one.pnum/four.pnum for details on the power supplies and PCB design
• see Section /seven.pnum for details on oscillator frequencies /one.pnum/two.pnum

6 Product Overview

6./one.pnum Logical cores Each tile has 8 active logical cores, which issue instructions down a shared /uniFB01ve-stage pipeline. Instructions from the active cores are issued round-robin. If up to /uniFB01ve logical cores are active, each core is allocated a /uniFB01fth of the processing cycles. If more than /uniFB01ve logical cores are active, each core is allocated at least /one.pnum/n cycles (for n cores). Figure /three.pnum shows the guaranteed core performance depending on the number of cores used. grade MIPS Frequency Minimum issue rate per logical core (MHz) Figure /three.pnum: Logical core performance When executing code from internal memory, there is no way that the performance of a logical core can be reduced below these predicted levels (unless priority threads are used: in this case the guaranteed minimum performance is computed based on the number of priority threads as de/uniFB01ned in the architecture manual). Because cores may be delayed on I/O, however, their unused processing cycles can be taken by other cores. This means that for more than /uniFB01ve logical cores, the performance of each core is often higher than the predicted minimum but cannot be guaranteed. The logical cores are triggered by events instead of interrupts and run to completion. A logical core can be paused to wait for an event. 6./two.pnum xTIME scheduler The xTIME scheduler handles the events generated by xCORE Tile resources, such as channel ends, timers and I/O pins. It ensures that all events are serviced and synchro- nized, without the need for an RTOS. Events that occur at the I/O pins are handled by the Hardware-Response ports and fed directly to the appropriate xCORE Tile. An xCORE Tile can also choose to wait for a speci/uniFB01ed time to elapse, or for data to become available on a channel. Tasks do not need to be prioritised as each of them runs on their own logical xCORE. It is possible to share a set of low priority tasks on a single core using cooperative multi- tasking. 6./three.pnum Hardware Response Ports Hardware Response ports connect an xCORE tile to one or more physical pins and as All pins of a port provide either output or input. Signals in different directions cannot be mapped onto the same port. The port logic can drive its pins high or low, or it can sample the value on its pins, option- ally waiting for a particular condition. Ports are accessed using dedicated instructions that are executed in a single processor cycle. xcore.ai IO pins can be used as open drain /one.pnum/three.pnum

output (drive) input (sample) conditional value readyOut Figure /four.pnum: Port block diagram outputs, where signals are driven low if a zero is output, but left high impedance if a one is output. This option is set on a per-port basis. Data is transferred between the pins and core using a FIFO that comprises a SERDES and transfer register, providing options for serialization and buffered data. Each port has a /one.pnum6-bit counter that can be used to control the time at which data is trans- ferred between the port value and transfer register. The counter values can be obtained at any time to /uniFB01nd out when data was obtained, or used to delay I/O until some time in the future. The port counter value is automatically saved as a timestamp, that can be used to provide precise control of response times. The ports and xCONNECT links are multiplexed onto the physical pins. If an xConnect Link is enabled, the pins of the underlying ports are disabled. If a port is enabled, it overrules ports with higher widths that share the same pins. The pins on the wider port that are not shared remain available for use when the narrower port is enabled. Ports always operate at their speci/uniFB01ed width, even if they share pins with another port. 6./four.pnum Clock blocks xCORE devices include a set of programmable clocks called clock blocks that can be used to govern the rate at which ports execute. Each xCORE tile has six clock blocks: the /uniFB01rst clock block provides the tile reference clock and runs at a default frequency of /one.pnum/zero.pnum/zero.pnumMHz; the remaining clock blocks can be set to run at different frequencies. A clock block can use a /one.pnum-bit port as its clock source allowing external application clocks to be used to drive the input and output interfaces. xcore.ai clock blocks optionally divide the clock input from a /one.pnum-bit port. In many cases I/O signals are accompanied by strobing signals. The xCORE ports can input and interpret strobe (known as readyIn and readyOut) signals generated by external sources, and ports can generate strobe signals to accompany output data. /one.pnum/four.pnum

Figure /five.pnum: Clock block diagram On reset, each port is connected to clock block /zero.pnum, which runs from the xCORE Tile refer- ence clock. 6./five.pnum Channels and Channel Ends Logical cores communicate using point-to-point connections, formed between two chan- nel ends. A channel-end is a resource on an xCORE tile, that is allocated by the program. Each channel-end has a unique system-wide identi/uniFB01er that comprises a unique number and their tile identi/uniFB01er. Data is transmitted to a channel-end by an output-instruction; and the other side executes an input-instruction. Data can be passed synchronously or asynchronously between the channel ends. 6.6 xCONNECT Switch and Links XMOS devices provide a scalable architecture, where multiple xCORE devices can be con- nected together to form one system. Each xCORE device has an xCONNECT interconnect that provides a communication infrastructure for all tasks that run on the various xCORE tiles on the system. The interconnect relies on a collection of switches and XMOS links. Each xCORE device has an on-chip switch that can set up circuits or route data. The switches are connected by xConnect Links. An XMOS link provides a physical connection between two switches. The switch has a routing algorithm that supports many different topologies, including lines, meshes, trees, and hypercubes. The links operate in either /two.pnum wires per direction or /five.pnum wires per direction mode, depending on the amount of bandwidth required. Circuit switched, streaming and packet switched data can both be supported ef/uniFB01ciently. Streams provide the fastest possible data rates between xCORE Tiles, but each stream requires a single link to be reserved between switches on two tiles. All packet communications can be multiplexed onto a single link. Information on the supported routing topologies that can be used to connect multiple devices together can be found in the xCONNECT Architecture guide. /one.pnum/five.pnum

xCONNECT Link to another device switch CORE CORE CORE CORE CORE CORE CORE xCORE Tile xCORE Tile xCONNECT switch Figure 6: Switch, links and channel ends /seven.pnum Oscillator, Clocks, and PLLs The device executes using a clock that is scaled up by two on-chip PLLs: a core-PLL that provides a clock for the digital logic, and a secondary fractional-N PLL for application use. Both PLLs are driven from an oscillator on the XIN and XOUT pins. If you use a crystal, 8 and /three.pnum/zero.pnum MHz, with an accuracy governed by your application. Note that the USB PHY only supports limited frequencies, see Section /one.pnum/one.pnum. The clock structure of the device is shown in Figure /seven.pnum. The main purpose of the core PLL is to generate the clocks needed for the digital blocks of the device, including the two processing cores and the switch. The main purpose of the secondary PLL is to provide an application clock if required. The blue frequencies are typical frequencies used in the device. The /one.pnum/zero.pnum/zero.pnum MHz reference frequency can be used by software to time software and interfaces. The core and switch clocks can be clocked down as required to save power, independent of the reference clock. In very low power modes, both PLLs can be placed in a low-power mode, and the whole chip executed directly from the oscillator. In this case, the reference can no longer operate at /one.pnum/zero.pnum/zero.pnum MHz. The green labels list the registers in appendices B, C, and D, that are used to control the clocks. /seven.pnum./one.pnum Core PLL The core PLL creates a high-speed clock that is used for the switch, tile, and reference clock. The initial PLL multiplication value is shown in Figure 8: /one.pnum6

xCORE1 dividerREF clk divider Oscillator output divider output divider

700 MHz

PSWITCH_PLL_CLK_DIVIDER SSWITCH_SWITCH_CLK_DIVIDER PSWITCH_PLL_CLK_DIVIDERSSWITCH_REF_CLK_DIVIDER SSWITCH_PLL_CTL SSWITCH_SS_APP_PLL_CTL SSWITCH_SS_APP_PLL _FRAC_N_DIVIDER PS_XCORE_CTRL0 PS_XCORE_CTRL0 App clock divider SSWITCH_SS_APP_CLK_DIVIDER Core 1 port 1D out in Watchdog MIPI cfg divider ÷2 MIPI demux divider ÷2 200 MHz 100 MHz MIPI Rx PHY MIPI demux SSWITCH_MIPI_CLK_DIVIDER SSWITCH_MIPI_CGF_CLK_DIVIDER USB PHY LPDDR divider ÷2 100 MHz LPDDR Controller X0D58 X0D57 SWITCH_DDR_CLK_DIVIDER Core 0 port 32A out[9] out[8] Figure /seven.pnum: Clock structure Oscillator Tile Boot PLL Ratio PLL settings Frequency Frequency OD F R Figure 8: The initial PLL multiplier values Figure 8 lists the oscillator frequency range, and the values of OD, F and R, which are the registers that de/uniFB01ne the ratio of the tile frequency to the oscillator frequency: Fcore = Fosc ×F + 1 2 × 1 R+ 1 × 1 OD+ 1 OD, F and Rmust be chosen so that 0 ≤R ≤63, 1 ≤F ≤8191, 0 ≤OD ≤7, and 360MHz ≤Fosc ×F+1 2 × 1 R+1 ≤1800MHz. The OD, F, and Rvalues can be modi/uniFB01ed by writing to the digital node PLL con/uniFB01guration register, see Appendix D./five.pnum. If a different tile frequency is required (eg, /five.pnum/zero.pnum/zero.pnum MHz), then the PLL must be reprogrammed after boot to provide the required tile frequency. The XMOS tools perform this operation by default. /seven.pnum./two.pnum Secondary PLL The secondary PLL can be used for generating clocks inside the device, or to create an application clock out of the device. When used as an application clock, the output is /one.pnum/seven.pnum

on port /one.pnumD. If the clock is required on other tiles, then the clock should be routed to one-bit ports on those tiles over the PCB. An output divider (Appendix D./one.pnum/three.pnum) can be programmed in even steps. xCore Tile 1 X1D11 PORT_1D Secondary PLL disabled xCore Tile 1 X1D11 PORT_1D Secondary PLL used for app xCore device xCore device Figure /nine.pnum: Secondary PLL connectivity. The secondary PLL is con/uniFB01gured using the register documented in Appendix D./one.pnum/four.pnum. The output frequency of the secondary PLL is Fpll2 = Fpll2in ×F + 1 2 × 1 R+ 1 × 1 OD+ 1 OD, F and Rmust be chosen so that 0 ≤R ≤63, 1 ≤F ≤8191, 0 ≤OD ≤7, and 360MHz ≤Fpll2in ×F+1 2 × 1 R+1 ≤1800MHz. A /uniFB02ag allows the user to choose between two input frequencies, Fpll2in can be set to either the oscillator ( Fosc) or the output of the core PLL ( Fcore). The secondary PLL has an optional fractional divider (Appendix D./one.pnum/seven.pnum). When enabled, the fractional divider will count a period of input clocks, and over part of this period it will cause the secondary PLL to use a divider F + 1 rather than F. The period pand fraction fare set through the control register for the fractional divider, and will result in an output frequency: Fpll2 = Fpll2in × F + 1 + f+1 p+1 2 × 1 R+ 1 × 1 OD+ 1 The use of fractional control adds /uniFB02exibility to create arbitrary frequencies at the expense of extra jitter. The fractional divider only works for f <p. /seven.pnum./three.pnum Oscillator circuit The device has an on-chip oscillator. To use this, you need to connect a crystal, two capacitors, and damping and feedback resistors to the device as shown in Figure /one.pnum/zero.pnum. Instead of using a crystal, you can supply a /one.pnumV8 clock input on the XIN pin. The clock must be running when the chip gets out of reset. Cl2 Cl1 XIN XIN XOUT XOUT xCORE 1v8 Oscillator Rd N.C. xCORE Rf Figure /one.pnum/zero.pnum: Example circuits using a crystal (left), or external oscillator (right). Rf should be /one.pnumMΩ. Calculation of Cl1, Cl2 and Rd are beyond the scope of this datasheet, and we recommend that you use a crystal with characteristics as speci/uniFB01ed in Table /one.pnum/one.pnum. These have an ESR of at most 6/zero.pnum Ohm, have a load capacitance of /one.pnum/two.pnum pF, and all resonate at their fundamental frequency. /one.pnum8

Name Frequency Load max ESR Power Rd Cl1, Cl2 Figure /one.pnum/one.pnum: Example crystals /seven.pnum./four.pnum Low power use For systems that need to run in a low-power mode, the following sequence of operations can be taken:

• set the core clock divider to an appropriately high value. This will reduce performance and power
• set the PLL to a low frequency. This will reduce power consumption.
• provide a clock into the XIN pin instead of using the oscillator circuit.

8 Reset logic

The device has an on-chip Power-on-Reset (POR). This keeps the chip in reset whilst the supplies are coming up, as shown in Figure /one.pnum/two.pnum. The device assumes that the supplies come up monotonically to reach their minimum operating voltages within the times spec- i/uniFB01ed in Section /one.pnum/five.pnum.6. The POR resets the whole device to a de/uniFB01ned state, including the PLL con/uniFB01guration, the JTAG logic, the PHYs, and the cores. When in reset, all GPIO pins have a pull-down enabled. TRST_N Internal pull-up Voltage comp. VDD VDDIOB18 PORST_N RST_N internal device reset_nInternal pull-up Watchdog internal jtag reset_n Delay Th(VDD) Th(VDDIOB18) T(POR) Figure /one.pnum/two.pnum: Simpli/uniFB01ed reset circuit When the device comes out of reset, the boot procedure starts (Section /nine.pnum). The chip can be reset externally using the RST_N pin. If required, the JTAG state machine can be reset to its idle state by clocking TCK /uniFB01ve times whilst TMS is high, or TRST_N can be asserted. If the chip needs to be reset at a later stage, this can be done from software using the PLL control register (Appendix D./five.pnum). This soft resets everything except for the PLL logic. It is therefore possible to reset keeping the current PLL settings. /one.pnum/nine.pnum

When the device comes out of reset, the processor will attempt to boot within a very short period of time. If booting from external /uniFB02ash, ensure that there is enough time between before RST_N coming up for the external /uniFB02ash to settle. An independent watchdog runs from the input clock pin XIN. It can be set to take the chip into reset when the watchdog has not been updated or cleared in time. The /one.pnum/two.pnum- bit watchdog timer with a /one.pnum6-bit divider provides accuracies of between /one.pnum input clock and /nine.pnum Boot Procedure The xCORE Tile Tile boot procedure is illustrated in Figure /one.pnum/three.pnum. If the secure-boot bit of the security register (which resides at pre-de/uniFB01ned locations in OTP , see Section /one.pnum/zero.pnum./four.pnum) is set, the device boots from OTP . Otherwise it boots from external device(s) according to boot shortly after reset with the internal weak pull-downs enabled on those pins. In typical use, a boot mode other than QSPI Flash can be selected by using one or more pull-ups on those pins. Care should be taken if other external devices are connected to this port that the boot mode is selected correctly. Primary Boot Copy OTP contents to RAM Load RAM according to boot source pins secure boot bit set? yes no Start Execute code from base of RAM Figure /one.pnum/three.pnum: Boot procedure The boot image provided by an external device has the following format:

• A /three.pnum/two.pnum-bit program sizesin words.
• Program consisting of s×4 bytes. formed. /two.pnum/zero.pnum

/zero.pnum /zero.pnum /zero.pnumQSPI /uniFB02ash Channel end /zero.pnum None /zero.pnum /zero.pnum /one.pnumSPI /uniFB02ash Channel end /zero.pnum None /zero.pnum /one.pnum /zero.pnumSPI slave Channel end /zero.pnum None /zero.pnum /one.pnum /one.pnumSPI slave SPI slave None XL/one.pnum, XL/two.pnum, XL/five.pnum, and XL6 (/five.pnumw) Figure /one.pnum/four.pnum: Boot source pins The program size and CRC are stored least signi/uniFB01cant byte /uniFB01rst. The program is loaded into the lowest memory address of RAM, and the program is started from that address. The CRC is calculated over the byte stream represented by the program size and the initialized with /zero.pnumxFFFFFFFF and the residue is inverted to produce the CRC. /nine.pnum./one.pnum Boot from QSPI /uniFB02ash If set to boot from QSPI /uniFB02ash, the processor enables the six pins speci/uniFB01ed in Figure /one.pnum/five.pnum, and drives the SPI clock. A Quad I/O READ command (/zero.pnumxEB) is issued with three address bytes (/zero.pnumx/zero.pnum/zero.pnum) and one dummy byte. Boot data is then expected from the /uniFB02ash and input into the device. The clock polarity and phase are /zero.pnum / /zero.pnum. The /uniFB02ash is assumed to be ready in reset using RST_N until the /uniFB02ash is ready. The /uniFB02ash is assumed to be in its power-up state, where QSPI-mode accesses will succeed. In particular, the /uniFB02ash device must be set into quad mode or similar. If the /uniFB02ash is set to an alternate mode, for example QPI, and the xCORE device is reset, then the subsequent boot will fail. Pin Signal Description X/zero.pnumD/zero.pnum/one.pnumSS Slave Select X/zero.pnumD/zero.pnum6SPIO/two.pnumData/two.pnum X/zero.pnumD/one.pnum/zero.pnumSCLK Clock Figure /one.pnum/five.pnum: QSPI pins The xCORE Tile expects each byte to be transferred with the least-signi/uniFB01cant nibble /uniFB01rst. Programmers who write bytes into an QSPI interface using the most signi/uniFB01cant nibble /uniFB01rst may have to reverse the nibbles in each byte of the image stored in the QSPI device. The pins used for QSPI boot are hardcoded in the boot ROM and cannot be changed. If required, a QSPI boot program can be burned into OTP that uses different pins. The boot sequence up to the start of the QSPI boot is outlined in Figure /one.pnum6 /two.pnum/one.pnum

0.0 1.8 Time Internal PORST_N VDD 0.0 0.9 XOUT Internal clock X0D10 (SCLK) X0D01 (SS) Device out of reset when vdd and vddiob18 valid Oscillator starts when device gets out of reset core PLL enabled when oscillator stable Boot process starts when core PLL is locked external pull-up CS_N asserted SPI Clock starts 0.0 V(VDDIOL) 0.0 V(VDDIOL) 0.0 1.8 Figure /one.pnum6: Outline boot sequence /nine.pnum./two.pnum Boot from SPI /uniFB02ash If set to boot from SPI master, the processor enables the four pins speci/uniFB01ed in Figure /one.pnum/seven.pnum, and drives the SPI clock. A READ command (/zero.pnumx/zero.pnum/three.pnum) is issued with three address bytes (/zero.pnumx/zero.pnum/zero.pnum), no dummy, then the data is expected from the /uniFB02ash. The clock polarity and phase are /zero.pnum / /zero.pnum. The xCORE Tile expects each byte to be transferred with the least-signi/uniFB01cant bit /uniFB01rst. Pro- grammers who write bytes into an SPI interface using the most signi/uniFB01cant bit /uniFB01rst may have to reverse the bits in each byte of the image stored in the SPI device. /two.pnum/two.pnum

X/zero.pnumD/zero.pnum/zero.pnumMISO Master In Slave Out (Data) X/zero.pnumD/zero.pnum/one.pnumSS Slave Select X/zero.pnumD/one.pnum/zero.pnumSCLK Clock X/zero.pnumD/one.pnum/one.pnumMOSI Master Out Slave In (Data) Figure /one.pnum/seven.pnum: SPI master pins If a large boot image is to be read in, it is faster to /uniFB01rst load a small boot-loader that reads the large image using a faster SPI clock, for example /five.pnum/zero.pnum MHz or as fast as the /uniFB02ash device supports. The pins used for SPI boot are hardcoded in the boot ROM and cannot be changed. If required, a SPI boot program can be burned into OTP that uses different pins. The boot sequence up to the start of the SPI boot is outlined in Figure /one.pnum6 /nine.pnum./three.pnum Boot as SPI slave If set to boot from SPI slave, the processor enables the three pins speci/uniFB01ed in Figure /one.pnum8 and expects a boot image to be clocked in. There is no command sequence, data is input directly from the /uniFB01rst rising edge of clock. The supported clock polarity and phase are Pin Signal Description X/zero.pnumD/zero.pnum/zero.pnumSS Slave Select X/zero.pnumD/one.pnum/zero.pnumSCLK Clock X/zero.pnumD/one.pnum/one.pnumMOSI Master Out Slave In (Data) Figure /one.pnum8: SPI slave pins The xCORE Tile expects each byte to be transferred with the least-signi/uniFB01cant bit /uniFB01rst. The pins used for SPI boot are hardcoded in the boot ROM and cannot be changed. If required, an SPI boot program can be burned into OTP that uses different pins. /nine.pnum./four.pnum Boot from xConnect Link If set to boot from an xConnect Link, the processor enables its link(s) shortly after the boot process starts. Enabling the Link switches off the pull-down resistors on the link, drives all the TX wires low (the initial state for the Link), and monitors the RX pins for boot-traf/uniFB01c; they must be low at this stage. If the internal pull-down is too weak to drain any residual charge, external pull-downs may be required on those pins. The boot-rom on the core will then: /one.pnum. Allocate channel-end /zero.pnum. /two.pnum. Input a word on channel-end /zero.pnum. It will use this word as a channel to acknowledge the /three.pnum. Input the boot image speci/uniFB01ed above, including the CRC. /two.pnum/three.pnum

/four.pnum. Input an END control token. /five.pnum. Output an END control token to the channel-end received in step /two.pnum. 6. Free channel-end /zero.pnum. /seven.pnum. Jump to the loaded code. /nine.pnum./five.pnum Boot from OTP If an xCORE tile is set to use secure boot (see Figure /one.pnum/three.pnum), the boot image is read from address /zero.pnum of the OTP memory in the tile’s security module. This feature can be used to implement a secure bootloader which loads an encrypted image from external /uniFB02ash, decrypts and CRC checks it with the processor, and discon- tinues the boot process if the decryption or CRC check fails. XMOS provides a default secure bootloader that can be written to the OTP along with secret decryption keys. Each tile can be con/uniFB01gured to have its own individual OTP memory, and hence some tiles can be booted from OTP while others are booted from SPI or the channel interface. This enables systems to be partially programmed, dedicating one or more tiles to perform a particular function, leaving the other tiles user-programmable. /one.pnum/zero.pnum Memory The address space as seen by the each core is shown in Figure /one.pnum/nine.pnum. This address space Outside the normal address space the device contains a one-time-programmable mem- tion set, instead is accessed through a library. /one.pnum/zero.pnum./one.pnum SRAM Each xCORE Tile integrates a single /five.pnum/one.pnum/two.pnumKB SRAM bank for both instructions and data. All supported and are executed within one tile clock cycle. /one.pnum/zero.pnum./two.pnum LPDDR memory interface The xCORE can be connected to an LPDDR memory through the pins in the VDDIOT power domain. The GPIO pins on the VDDIOT domain are overlaid onto a JEDEC com- enabling a memory of /one.pnum6-/one.pnum/two.pnum8 MByte to be interfaced. This pin muxing is shown in Fig- ure /two.pnum/zero.pnum. DDR speeds of up to /one.pnum/zero.pnum/zero.pnum MHz are supported and care should be taken with the PCB design. See the appnote on xcore.ai External Memory for a reference layout. /two.pnum/four.pnum

Figure /one.pnum/nine.pnum: Address space X0D30 X0D31 X0D32 X0D33 X0D34 X0D39 X0D40 X0D41 X0D42 X0D43 X0D49 X0D50 X0D51 X0D52 X0D53 X0D54 X0D55 X0D56 X0D57 X0D58 X0D61 X0D62 X0D63 X0D64 X0D65 X0D66 X0D67 X0D68 X0D69 X0D70 X1D24 X1D25 X1D26 X1D27 X1D28 X1D29 X1D30 X1D31 X1D32 X1D33 X1D34 X1D35 X1D43 xCORE0 X0D30 X0D31 X0D32 X0D33 X0D34 X0D39 X0D40 X0D41 X0D42 X0D43 X0D49 X0D50 X0D51 X0D52 X0D53 X0D54 X0D55 X0D56 X0D57 X0D58 X0D61 X0D62 X0D63 X0D64 X0D65 X0D66 X0D67 X0D68 X0D69 X0D70 LPDDR controller and PHY DQ4 DQ3 DQ2 DQ1 DQ0 A13 A12 A11 A10 CLK_N CLK CKE CS_N BA1 BA0 WE_N CAS_N RAS_N UDM UDQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDM LDQS DQ7 DQ6 DQ5 SRAMExecution pipeline 8-line buffer xCORE1 SRAMExecution pipeline 8-line buffer X1D24 X1D25 X1D26 X1D27 X1D28 X1D29 X1D30 X1D31 X1D32 X1D33 X1D34 X1D35 X1D43 Address Data LPDDR memory device DQ4 DQ3 DQ2 DQ1 DQ0 A13 A12 A11 A10 CLK_N CLK CKE CS_N BA1 BA0 WE_N CAS_N RAS_N UDM UDQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDM LDQS DQ7 DQ6 DQ5 xCORE device Figure /two.pnum/zero.pnum: LPDDR pin muxing. Logically, the memory can be connected to either Tile /zero.pnum or Tile /one.pnum; it is up to the program- mer to decide which one. The memory is connected by the tile enabling the external memory interface through a process-status control register, see Section B./three.pnum. Only one tile should enable the external memory interface. A small buffer decouples the LPDDR memory from the device. The memory is addressed in the enabled device from address /two.pnum/five.pnum

Details on external memory can be found in the application note on “xcore.ai external /one.pnum/zero.pnum./three.pnum Software de/uniFB01ned memory The device can map any memory into the address space under software control. For example, a QSPI /uniFB02ash can be mapped into the address space (to execute code from), or - /zero.pnumx/seven.pnumFFF FFFF. Refer to the XS/three.pnum ISA speci/uniFB01cation for details on how to use software memory. /one.pnum/zero.pnum./four.pnum OTP The device integrates /four.pnumKB of one-time programmable (OTP) memory per tile. This mem- ory contains some global information about the chip behaviour, and optionally code and data that can be used for, for example, secure boot. The memory map of the OTP is shown in Figure /two.pnum/one.pnum. Address Name Meaning The security con/uniFB01guration word for tile /zero.pnum Indi- vidual bits determine which features are dis- abled, see Figure /two.pnum/two.pnum. The security con/uniFB01guration word for tile /one.pnum in uni- /uniFB01ed mode. Individual bits determine which fea- tures are disabled see Figure /two.pnum/two.pnum. /zero.pnumx/zero.pnum/zero.pnum/four.pnumOTP_JTAG_USER_WORD Bits /one.pnum/three.pnum:/zero.pnum are copied into the JTAG_USERCODE[/three.pnum/one.pnum:/one.pnum8] The security con/uniFB01guration word for tile /one.pnum in split mode. Individual bits determine which fea- tures are disabled see Figure /two.pnum/two.pnum. /zero.pnumx/four.pnum/zero.pnum/four.pnum Reserved Figure /two.pnum/one.pnum: OTP address map The OTP memory is programmed using three special I/O ports. Programming is per- formed through libotp and xburn . /one.pnum/one.pnum USB PHY The USB PHY provides High-Speed and Full-Speed, device, host, and on-the-go function- /two.pnum6

Disable JTAG /zero.pnum Set to /one.pnum to disable the JTAG interface to the tile. This makes it impossible for the tile state or memory content to be accessed via the JTAG interface. Disable JTAG to PLL /four.pnumSet to /one.pnum to disable JTAG access to the PLL con/uniFB01guration register. Secure Boot /five.pnum Set to /one.pnum to force the xCORE Tile to boot from address /zero.pnum of the OTP Uni/uniFB01ed mode /seven.pnum Set to /one.pnum to create one uni/uniFB01ed OTP rather than two half OTPs for Write disable 8 Disable programming. Read disable /nine.pnumDisable read access. Disable Global Debug /one.pnum/four.pnumDisables access to the DEBUG_N pin. Figure /two.pnum/two.pnum: Security register

features

and data is communicated through ports on the digital node. A library, XUD, is provided to implement the MAC layer and full USB-device functionality. abling the USB PHY on a tile will connect the ports shown to the USB PHY. These ports will not be available for GPIO on that tile. All other IO pins and ports are unaffected. The USB PHY should not be enabled on both tiles. Two clock blocks can be used to clock the USB ports. One clock block for the TXDATA path, and one clock block for the RXDATA path. Details on how to connect those ports are documented in an application note on USB for xcore.ai. PORT_1J PORT_1I PORT_8B CLKBLK RXD PORT_1H CLKBLK PORT_1K PORT_8A TXD xCORE USB connector ID connection is optional DM may be marked as DN USB_VDD18 USB_VDD33 3V3 1V8 3V3 1V8 Regulators GND PORT_1E FLAG0 PORT_1F FLAG1 USB PHY RXD[0..7] RXRDY CLK TXD[0..7] TXRDY OUT TXRDY IN VBUS 1-10uF USB_DP USB_DMDP DM ID LINESTATE0 RXACTIVE LINESTATE1 RXERROR SWITCHUSB_SHIM_CFG USB_ID Figure /two.pnum/three.pnum: Bus powered USB-device /one.pnum/one.pnum./one.pnum USB VBUS If you use the USB PHY to design a self-powered USB-device, then the device must be able detect the presence of VBus on the USB connector (so the device can disconnect its pull-up resistors from D+/D- to ensure the device does not have any voltage on the D+/D- pins when VBus is not present, “USB Back Voltage Test”). This requires a GPIO pin XnDnn to be connected to the VBUS pin of the USB connector as is shown in Figure /two.pnum/four.pnum. /two.pnum/seven.pnum

PORT_1J PORT_1I PORT_8B CLKBLK RXD PORT_1H CLKBLK PORT_1K PORT_8A TXD xCORE USB connector ID connection is optional DM may be marked as DN USB_VDD18 USB_VDD33 3V3 1V8 3V3 1V8 Regulators GND PORT_1E FLAG0 PORT_1F FLAG1 USB PHY RXD[0..7] RXRDY CLK TXD[0..7] TXRDY OUT TXRDY IN VBUS 1-10uF USB_DP USB_DMDP DM ID LINESTATE0 RXACTIVE LINESTATE1 RXERROR SWITCHUSB_SHIM_CFG USB_ID XnDnn 47K 220K External supply 100K (1V8 IO) 330K (3V3 IO) Figure /two.pnum/four.pnum: Self powered USB-device When connecting a USB cable to the device it is possible an overvoltage transient will be present on VBus due to the inductance of the USB cable combined with the required input capacitor on VBus. The circuit in Figure /two.pnum/four.pnum ensures that the transient does not transient is /uniFB01ltered and does not reach the device. A resistor to ground divides the /five.pnumV VBUS voltage, and makes sure that the signal on the GPIO pin is not more than the IO resistor to ground is a bleeder resistor to discharge the input capacitor when VBus is not value would be /two.pnum./two.pnumuF to ensure the /one.pnumuF minimum requirement is met even under voltage bias conditions. In any case, extra components (such as a ferrite bead and diodes) may be required for EMC compliance and ESD protection. Different wiring is required for USB-host and USB- OTG. /one.pnum/one.pnum./two.pnum Logical Core Requirements The XMOS XUD library runs in a single logical core with endpoint and application cores communicating with it via a combination of channel communication and shared memory variables. Each IN (host requests data from device) or OUT (data transferred from host to device) endpoint requires one logical core. /one.pnum/two.pnum MIPI PHY The device has a two Data Lane MIPI D-PHY receiver on board, capable of receiving MIPI lanes can be con/uniFB01gured (and the lanes/clocks swapped around) using the MIPI lane con/uniFB01guration register, see Appendix D./three.pnum8. The MIPI receiver has a decoder for common CSI-/two.pnum packed formats, and is connected to the ports shown in Figure /two.pnum/five.pnum. The MIPI block is clocked from its own clock source that /two.pnum8

PORT_1O PORT_1I PORT_8B CLKBLK RXDATA Please note: One or two data lanes supported MIPI_VDD18 MIPI_VDD09 0V9 1V8 MIPI_DP0 MIPI_DN0 MIPI_DP2 MIPI_DN2 MIPI_DP1 MIPI_DN1 MIPI Device Clock carried over a separate pair PORT_1E RXACTIVE PLL block L1P L1N L2P L2N CP CN Diff pair lane mux RXD[0..7] RXRDY MIPI D-PHY CSI2 demux RXACT DEMUX CLK CONFIG CLK 1µF 1µF Lane1P Lane1N Lane2P Lane2N ClockP ClockN Figure /two.pnum/five.pnum: Connecting a MIPI-device can either be driven from the system PLL (divide by /four.pnum min), or from the secondary PLL. See Section /seven.pnum on how to set the clocks. /one.pnum/three.pnum JTAG The JTAG module can be used for loading programs, boundary scan testing, and in- circuit source-level debugging. JTAG can be used for programming /uniFB02ash and the OTP by loading code onto the device that will program the /uniFB02ash and/or OTP . All JTAG signals use a /one.pnum.8V supply. TDI TDO TCK TMS BS TAP TDI TDO TRST_N DEBUG_N Figure /two.pnum6: JTAG chain structure compliant TAP that can be used for boundary scan of the I/O pins. It has a /four.pnum-bit IR and /three.pnum/two.pnum-bit DR. It also provides access to a chip TAP that in turn can access the xCORE Tile for loading code and debugging. The TRST_N pin can be left not connected, or used to reset the JTAG module. The DE- BUG_N pin is used to synchronize the debugging of multiple xCORE Tiles. This pin can operate in both output and input mode. In output mode and when con/uniFB01gured to do so, DEBUG_N is driven low by the device when the processor hits a debug break point. Prior to this point the pin will be tri-stated. In input mode and when con/uniFB01gured to do so, driving this pin low will put the xCORE Tile into debug mode. Software can set the behavior of /two.pnum/nine.pnum

or left not connected in single core applications. The JTAG device identi/uniFB01cation register can be read by using the IDCODE instruction. Its contents are speci/uniFB01ed in Figure /two.pnum/seven.pnum. Bit/three.pnum/one.pnum Device Identi/uniFB01cation Register Bit/zero.pnum Version Part Number Manufacturer Identity /one.pnum Figure /two.pnum/seven.pnum: IDCODE return value The JTAG usercode register can be read by using the USERCODE instruction. Its con- devices). The OTP User ID /uniFB01eld is set by the boot ROM when it executes after the device reset has been de-asserted, so its value is not available to read when the device is in reset. Bit/three.pnum/one.pnum Usercode Register Bit/zero.pnum OTP User ID Silicon Revision Figure /two.pnum8: USERCODE return value You can program the PLL and reset the device over JTAG. When IR is set to eight, the DR value is shifted directly into the PLL settings register (Appendix D./five.pnum), which includes bits for resetting the device and for setting the “boot-from-JTAG” bit. Note that if TCK is not free running then at least /one.pnum/zero.pnum/zero.pnum TCK clocks must be provided after shifting the value into DR for the write to take effect. /one.pnum/four.pnum Board Integration The device has power and ground pins for different supplies. Several pins of each type may be provided to minimize the effect of inductance within the package, all of which must be connected.

• VDD pins for the xCORE Tile. The VDD supply should be well decoupled at high frequen- close to the chip between the supplies and GND.
• VDDIO pins for the I/O lines. Separate I/O supplies are provided for the left, bottom, top, and right side of the package; different I/O voltages may be supplied on those. The sig- nal description (Section /four.pnum) speci/uniFB01es which I/O is powered from which power-supply. The VDDIO supplies should be decoupled close to the chip by several /one.pnum/zero.pnum/zero.pnum nF low in- ductance multi-layer ceramic capacitors between the supplies and GND, for example, of the VDDIOL, VDDIOT, or VDDIOR domains, then you must strap the corresponding LV_L_N, LV_T_N, or LV_R_N pins to GROUND
• PLL_AVDD pin for the PLL, with an associated PLL_AGND. The PLL_AVDD supply should be separated from the other noisier supplies on the board. The PLL requires a very clean power supply, and a low pass /uniFB01lter (for example, a /one.pnumµF multi-layer ceramic /three.pnum/zero.pnum

• PLL_AVDD/two.pnum pins for the secondary PLL, with an associated PLL_AGND/two.pnum. This should be /uniFB01ltered the same way as PLL_AVDD.
• OTP_VCC pins for the OTP
• A MIPI_VDD/zero.pnum/nine.pnum pin for the analogue core supply to the MIPI D-PHY , with an asso- MIPI_VDD/zero.pnum/nine.pnum to ground if MIPI is not used in the design.
• A MIPI_VDD/one.pnum8 pin for the analogue /one.pnum.8V supply to the MIPI D-PHY. This supply needs a /one.pnumµF decoupler close to the pin. Connect MIPI_VDD/one.pnum8 to ground if MIPI is not used in the design.
• A USB_VDD/one.pnum8 pin for the analogue /one.pnum.8V supply to the USB-PHY, with an associated USB_GND/one.pnum8. You can leave USB_VDD/one.pnum8 unconnected if USB is not used in the design. unconnected if USB is not used in the design.
• GND for all other supplies, including VDD and VDDIO. All ground pins must be connected directly to the board ground. The ground side of the decoupling capacitors should have as short a path back to the GND pins as possible. A bulk decoupling capacitor of at least /one.pnum/zero.pnum uF should be placed on VDD and VDDIO supplies. The power supplies must be brought up monotonically and input voltages must not ex- ceed speci/uniFB01cation at any time. Power sequencing is summarised in Figure /two.pnum/nine.pnum. VDDIO and VDD can ramp up indepen- dently. In order to reduce stresses on the device, it is preferable to make them ramp up within a short time of each other, no more than /five.pnum/zero.pnum ms apart. You must ensure that the VDDIOL, VDDIOT, and VDDIOR domains are valid before the device is taken out of reset, as the boot pins are on VDDIOL. If you use a single /one.pnum.8V VDDIO power supply, then the on-chip power-on-reset will ensure that reset stays low until all supplies are valid. If you use multiple power supplies, then you must either ensure that RST_N stays asserted until the VDDIOL/R/T domains are valid, or ensure that VDDIOL/R/T are valid by the time that VDDIOB/one.pnum8 and VDD are valid. /one.pnum/four.pnum./one.pnum Differential pair signal routing and placement If you are using the USB PHY and/or the MIPI D-PHY , then you should route the differen- tial pair marked D+ and D- carefully in order to ensure signal integrity. The D+ and D- lines are the positive and negative data polarities of a high speed signal respectively. Their high-speed differential nature implies that they must be coupled and properly isolated. The board design must ensure that the board traces for D+ and D- are tightly matched. In addition the differential impedance of D+ and D- must meet its speci/uniFB01cations. We on how to space and stack the board when routing differential pairs. /three.pnum/one.pnum

0.0 valid VDD VDDIOB18 VDDIO* valid valid0.9 0.0 1.8 0.0 V(VDDIO*) VDDIOB18 and VDD valid VDDIO* must be valid before VDDIO* valid 0.0 V(VDDIO*) RST_N high VDDIO* valid before 0.0 External RST_N 1.8 Time (a) Power sequencing, rely on internal POR Time (b) Power sequencing, use external RST_N Internal PORST_N Th(VDDIOB18) Th(VDD) T(POR) VDDIOB18 and VDD must be valid within T(POR) of crossing threshold Figure /two.pnum/nine.pnum: Sequencing of power supplies and RST_N (if used) D+ D- D+ D- Low speed signal High speed signalSignal Signal GND Power Differential pairDifferential pair W S1 S2S2 S3 H Figure /three.pnum/zero.pnum: Spacings of a low speed signal, two differential pairs and a high speed signal Parameter USB MIPI Value Unit Value Unit Skew between D+/D- /one.pnum mm /zero.pnum./five.pnum mm Skew between clock/data N/A /two.pnum mm Figure /three.pnum/one.pnum: Differential pair parameters /one.pnum/four.pnum./two.pnum General routing and placement guidelines The following guidelines will help to avoid signal quality and EMI problems on high speed designs. They relate to a four-layer (Signal, GND, Power, Signal) PCB. /three.pnum/two.pnum

For best results, most of the routing should be done on the top layer (assuming the de- vices are on the top layer) closest to GND. Reference planes should be below the trans- mission lines in order to maintain control of the trace impedance. We recommend that the high-speed clock and high-speed differential pairs are routed /uniFB01rst before any other routing. When routing high speed signals, the following guidelines should be followed:

• High speed differential pairs should be routed together.
• High-speed signal pair traces should be trace-length matched.
• Ensure that high speed signals (clocks, differential pairs) are routed as far away from off-board connectors as possible.
• High-speed clock and periodic signal traces that run parallel should be at least a dis-
• Low-speed and non-periodic signal traces that run parallel should be at least S2 away
• Route high speed signals on the top of the PCB wherever possible.
• Route high speed traces over continuous power planes, with no breaks. If a trade-off must be made, changing signal layers is preferable to crossing plane splits.
• Follow the 20 ×hrule; keep traces 20 ×h(the height above the power plane) away from the edge of the power plane.
• Use a minimum of vias in high speed traces.
• Avoid corners in the trace. Where necessary, rather than turning through a /nine.pnum/zero.pnum degree angle, use two /four.pnum/five.pnum degree turns or an arc.
• DO NOT route differential pair traces near clock sources, clocked circuits or magnetic devices.
• Avoid stubs on high speed signals. In order to optimise MIPI routing, the D+/D- pairs can be swapped, and the lane/clock differential pairs can be reassigned, see Appendix D./three.pnum8. /one.pnum/four.pnum./three.pnum Land patterns and solder stencils The land patterns and solder stencils will depend on the PCB manufacturing process. We recommend you design them with using the IPC speci/uniFB01cations“Generic Requirements to achieve desired targets of heel, toe and side /uniFB01llets for solder-joints. The mechanical drawings in Section /one.pnum6 specify the dimensions and tolerances. /three.pnum/three.pnum

/one.pnum/four.pnum./four.pnum Ground and Thermal Vias Vias from the ground balls into the ground plane of the PCB are recommended for a low inductance ground connection and good thermal performance. The central ground balls form the main thermal path for heat dissipation and you should aim to use one via per BGA ball into the ground plane. /one.pnum/four.pnum./five.pnum Moisture Sensitivity XMOS devices are, like all semiconductor devices, susceptible to moisture absorption. When removed from the sealed packaging, the devices slowly absorb moisture from the surrounding environment. If the level of moisture present in the device is too high during re/uniFB02ow, damage can occur due to the increased internal vapour pressure of moisture. Example damage can include bond wire damage, die lifting, internal or external package cracks and/or delamination. All XMOS devices are Moisture Sensitivity Level (MSL) /three.pnum - devices have a shelf life of /one.pnum68 hours between removal from the packaging and re/uniFB02ow, provided they are stored below /three.pnum/zero.pnumC and 6/zero.pnum% RH. If devices have exceeded these values or an included moisture indicator card shows excessive levels of moisture, then the parts should be baked as appropriate before use. This is based on information from Joint IPC/JEDEC Standard For Moisture/Re/uniFB02ow Sensitivity Classi/uniFB01cation For Nonhermetic Solid State Surface-Mount Devices J-STD-/zero.pnum/two.pnum/zero.pnum Revision D. /one.pnum/four.pnum.6 Re/uniFB02ow The package is RoHS compliant and uses Pb-free solder balls for connection to the sys- tem PCB. For this reason, a Pb-free solder paste and re/uniFB02ow pro/uniFB01le should be used to generate a reliable interconnect. You should ensure that the board assembly process is optimised for the design; for details of the recommended re/uniFB02ow pro/uniFB01le, please refer to the Joint IPC/JEDEC standard J-STD-/zero.pnum/two.pnum/zero.pnum. /three.pnum/four.pnum

/one.pnum/five.pnum Electrical Characteristics /one.pnum/five.pnum./one.pnum Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Symbol Parameter MIN MAX UNITS Notes Tstg Storage temperature -6/five.pnum /one.pnum/five.pnum/zero.pnum°C I(XxDxx) Current per GPIO pin -/two.pnum/five.pnum/two.pnum/five.pnummA A I(VDDIOL) Sum of current for VDDIOL /two.pnum/five.pnum/two.pnummA B, C, D I(VDDIOR) Sum of current for VDDIOR /three.pnum/seven.pnum8mA B, C, D I(VDDIOT) Sum of current for VDDIOT /five.pnum/zero.pnum/four.pnummA B, C, D I(VDDIOB/one.pnum8) Sum of current for VDDIOB/one.pnum8 /one.pnum/two.pnum6mA B, C, D Figure /three.pnum/two.pnum: Absolute maximum ratings A At /one.pnum.8V B Exceeding these current limits will result in premature aging and reduced lifetime. C This current consumption must be evenly distributed over all VDDIO pins. D All main power (VDD, VDDIO) and ground (VSS) pins must always be connected. /one.pnum/five.pnum./two.pnum Operating Conditions Please note that the numbers below are preliminary. Contact XMOS for information about other temperature ranges. /three.pnum/five.pnum

Symbol Parameter MIN TYP MAX UNITS Notes Ta Ambient operating temperature /zero.pnum /seven.pnum/zero.pnum°C Figure /three.pnum/three.pnum: Operating conditions Symbol Parameter MIN TYP MAX UNITS Notes V(T+) Hysteresis threshold V(T-) Hysteresis threshold V(HYS) Input hysteresis V(OH) Output high voltage /one.pnum./three.pnum/five.pnumV C V(OL) Output low voltage /zero.pnum./two.pnum/four.pnumV C I(PU) Internal pull-up current (Vin=/zero.pnumV) -/three.pnum/five.pnum µA D I(PD) Internal pull-down current (Vin=VDDIO) /three.pnum/two.pnumµA D I(LC) Input leakage current /one.pnum/one.pnum/five.pnumnA Ci Input capacitance 6 pF Figure /three.pnum/four.pnum: DC/two.pnum character- istics A All pins except power supply pins. B When Schmitt-Trigger enabled C Measured with /two.pnum mA drivers sourcing /two.pnum mA. D Used to guarantee logic state for an I/O when high impedance. The internal pull-ups/pull-downs should not be used to pull external circuitry. In order to pull the pin to the opposite state, a /four.pnumK/seven.pnum resistor is recommended to overome the internal pull current. /three.pnum6

0.5 1.0 1.5 I(PD) current, uA IO Pin Voltage, V0.00 -40 -30 -20 -10 0 0.5 1.0 1.5 I(PU) current, uA IO Pin Voltage, V0.0-50 Figure /three.pnum/five.pnum: Typical internal pull-down and pull-up currents at /one.pnumV8 Symbol Parameter MIN TYP MAX UNITS Notes V(IH) Input high voltage /two.pnum VDDIO+/zero.pnum./three.pnumV A V(OH) Output high voltage /two.pnum.68 V C V(OL) Output low voltage /zero.pnum./two.pnum/three.pnumV C I(PU) Internal pull-up current (Vin=/zero.pnumV)-6/five.pnum µA D I(PD) Internal pull-down current (Vin=VDDIO) /five.pnum/four.pnumµA D I(LC) Input leakage current /one.pnum/seven.pnum6nA Ci Input capacitance 6 pF Figure /three.pnum6: DC character- istics A All pins except power supply pins. B When Schmitt-Trigger enabled C Measured with /two.pnum mA drivers sourcing /two.pnum mA. D Used to guarantee logic state for an I/O when high impedance. The internal pull-ups/pull-downs should not be used to pull external circuitry. In order to pull the pin to the opposite state, a /four.pnumK/seven.pnum resistor is recommended to overome the internal pull current. 20 40 60 80 100 1.0 2.0 3.0 I(PD) current, uA IO Pin Voltage, V0.00 -80 -60 -40 -20 0 1.0 2.0 3.0 I(PU) current, uA IO Pin Voltage, V0.0-100 Figure /three.pnum/seven.pnum: Typical internal pull-down and pull-up currents at /three.pnumV/three.pnum /three.pnum/seven.pnum

/one.pnum/five.pnum./five.pnum ESD Stress Voltage Symbol Parameter MIN TYP MAX UNITS Notes Figure /three.pnum8: ESD stress voltage /one.pnum/five.pnum.6 Reset Timing Symbol Parameters MIN TYP MAX UNITS Notes T(RST) Reset pulse width /five.pnum µs Figure /three.pnum/nine.pnum: Reset timing A Shows the time taken to start booting after RST_N has gone high. /one.pnum/five.pnum./seven.pnum Power Consumption Symbol Parameter MIN TYP MAX UNITS Notes Iddq(VDD) Quiescent VDD current /five.pnummA A, B, C I(PLL_AVDD) PLL_AVDD current /zero.pnum./two.pnum/five.pnummA G I(USB_VDD/three.pnum/three.pnum) (fs tx) VDD/three.pnum/three.pnum current on FS transmission /seven.pnum/two.pnum/five.pnummA I(USB_VDD/one.pnum8) (fs tx) VDD/one.pnum8 current on FS transmission 6.8 8./two.pnummA I(VDD) (hs) VDD current in hs mode 6 /nine.pnummA I(VDD) (fs tx) VDD current for USB FS tx /one.pnum.66./five.pnummA I(MIPI_VDD/one.pnum8A)MIPI_VDD/one.pnum8A current /one.pnum/zero.pnummA Figure /four.pnum/zero.pnum: xCORE Tile currents A Use for budgetary purposes only. B Assumes typical tile and I/O voltages with no switching activity. C Excludes PLL current. D Assumes typical tile and I/O voltages with nominal switching activity. E PD(TYP) value is the usage power consumption under typical operating conditions. G PLL_AVDD = /zero.pnum./nine.pnum V The tile power consumption of the device is highly application dependent and should be used for budgetary purposes only. /three.pnum8

/one.pnum/five.pnum.8 Clock Please note that the numbers below are preliminary. Contact XMOS for information about other speed ranges. Symbol Parameter MIN TYP MAX UNITS Notes f Input frequency 8 /two.pnum/four.pnum/three.pnum/zero.pnumMHz SR(CLK) Slew rate, clock /zero.pnum./one.pnumV/ns T J(L T) Long term input jitter (pk-pk) /two.pnum% A, B f(MAX) Core clock frequency 6/zero.pnum/zero.pnumMHz C Figure /four.pnum/one.pnum: Clock A Percentage of CLK period. B When used with an external oscillator on XIN C Assumes typical tile and I/O voltages with nominal activity. /one.pnum/five.pnum./nine.pnum xCORE Tile I/O AC Characteristics Symbol Parameter MIN TYP MAX UNITS Notes Figure /four.pnum/two.pnum: I/O AC charac- teristics /one.pnumV8 A With a /five.pnum pf Load @ /four.pnummA drive strength Symbol Parameter MIN TYP MAX UNITS Notes Figure /four.pnum/three.pnum: I/O AC charac- teristics /three.pnumV/three.pnum A With a /five.pnum pf Load @ /four.pnummA drive strength Symbol Parameter MIN TYP MAX UNITS Notes B(/two.pnumblinkP)/two.pnumb link bandwidth (packetized) 8/seven.pnumMBit/s A, B Figure /four.pnum/four.pnum: Link performance A Assumes /three.pnum/two.pnum-byte packet in /three.pnum-byte header mode. Actual performance depends on size of the header and payload. B /seven.pnum./five.pnum ns symbol time. The asynchronous nature of links means that the relative phasing of CLK clocks is not important in a multi-clock system, providing each meets the required stability criteria. /three.pnum/nine.pnum

Symbol Parameter MIN TYP MAX UNITS Notes f(TCK_D) TCK frequency (debug) /two.pnum/five.pnumMHz f(TCK_B) TCK frequency (boundary scan) /two.pnum/five.pnumMHz Figure /four.pnum/five.pnum: JTAG timing All JTAG operations are synchronous to TCK apart from the global asynchronous reset TRST_N. /four.pnum/zero.pnum

/one.pnum6 Package Information C /four.pnum/one.pnum

/one.pnum6./one.pnum Part Marking FCCRNTMOP MCYYWWXX LLLLLL.LL F CC R N T M OP MC YYWW XX Wafer Lot code - Product Family - Number of logical cores - RAM [in log2(kbytes)] - Flash [in log2(Mbytes)+1] - Optional temperature grade - Optional speed [in 100 MHz] - Optional programming code - Manufacturer - Date - Reserved [variable length] Figure /four.pnum6: Part marking scheme /one.pnum/seven.pnum Ordering Information Please note that the numbers below are preliminary. Contact XMOS for information about other temperature and speed ranges. Product Code Marking Quali/uniFB01cationSpeed Grade Figure /four.pnum/seven.pnum: Orderable part numbers /four.pnum/two.pnum

The device is con/uniFB01gured through banks of registers, as shown in Figure /four.pnum8. X0Dxx I/O pins xTIME scheduler Hardware response ports core PLL app PLL JTAG X1Dxx I/O pins xTIME scheduler Hardware response ports xCONNECT Switch Internal SRAM OTPALU (FP + int) Vector unit Internal SRAMOTP ALU (FP + int) Vector unit Memory Buffer Processor Switch Processor Switch xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core xCORE "logical" core dual lane MIPI DPHY High speed USB PHY Optional external LPDDR memory Node configuration registers Tile configuration registers Tile configuration registers Processor configuration registers Processor configuration registers Figure /four.pnum8: Registers The following communication sequences specify how to access those registers. Any messages transmitted contain the most signi/uniFB01cant /two.pnum/four.pnum bits of the channel-end to which a response is to be sent. This comprises the node-identi/uniFB01er and the channel number within the node. if no response is required on a write operation, supply /two.pnum/four.pnum-bits with the last 8-bits set, which suppresses the reply message. Any multi-byte data is sent most signi/uniFB01cant byte /uniFB01rst. Registers are addressed by a number, for each register a symbolic constant is de/uniFB01ned in the xs1.h include /uniFB01le which has one of the following three names:

• XS1_PS_ NAME for processor status registers.
• XS1_PSWITCH_ NAME_NUM for tile con/uniFB01guration registers.
• XS1_SSWITCH_ NAME_NUM for node con/uniFB01guration registers. Each register typically comprises a set of bit-/uniFB01eldsthat control individual functions. These bit/uniFB01elds are speci/uniFB01ed in the tables in subsequent appendices. Macros are de/uniFB01ned in the xs1.h include /uniFB01le which perform the following support functions:
• XS1_ NAME(x) The value of the bit/uniFB01eld extracted from a wordx .
• x = XS1_ NAME_SET(x, v) Setting the bit/uniFB01eld in a wordx to the value v . Registers and bit-/uniFB01elds have permissions as follows: RO read-only RW read and write /four.pnum/three.pnum

D.. Only works when processor is in Debug mode. A./one.pnum Accessing a processor status register The processor status registers are accessed directly from the processor instruction set. The instructions GETPS and SETPS read and write a word. The register number should be translated into a processor-status resource identi/uniFB01er by shifting the register number left 8 places, and ORing it with /zero.pnumx/zero.pnumB. Alternatively, the functionsgetps(reg) and setps( ↪→reg,value) can be used from XC. A./two.pnum Accessing an xCORE Tile con/uniFB01guration register xCORE Tile con/uniFB01guration registers can be accessed through the interconnect using the functions write_tile_config_reg(tileref, ...) and read_tile_config_reg(tile ref, implement the protocols described below. Instead of using the functions above, a channel-end can be allocated to communicate with the xCORE tile con/uniFB01guration registers. The destination of the channel-end should be set to 0xnnnnC20C where nnnnnn is the tile-identi/uniFB01er. A write message comprises the following: /one.pnum/nine.pnum/two.pnumchannel-end identi/uniFB01erregister number data /one.pnum The response to a write message comprises either control tokens /three.pnum and /one.pnum (for success), or control tokens /four.pnum and /one.pnum (for failure). A read message comprises the following: control-token /two.pnum/four.pnum-bit response/one.pnum6-bit control-token /one.pnum/nine.pnum/three.pnumchannel-end identi/uniFB01erregister number /one.pnum The response to the read message comprises either control token /three.pnum, /three.pnum/two.pnum-bit of data, and control-token /one.pnum (for success), or control tokens /four.pnum and /one.pnum (for failure). A./three.pnum Accessing node con/uniFB01guration Node con/uniFB01guration registers can be accessed through the interconnect using the func- device is the name of the node. These functions implement the protocols described be- low. Instead of using the functions above, a channel-end can be allocated to communicate with the node con/uniFB01guration registers. The destination of the channel-end should be set to 0xnnnnC30C where nnnn is the node-identi/uniFB01er. A write message comprises the following: /four.pnum/four.pnum

/one.pnum/nine.pnum/two.pnumchannel-end identi/uniFB01erregister number data /one.pnum The response to a write message comprises either control tokens /three.pnum and /one.pnum (for success), or control tokens /four.pnum and /one.pnum (for failure). A read message comprises the following: control-token /two.pnum/four.pnum-bit response/one.pnum6-bit control-token /one.pnum/nine.pnum/three.pnumchannel-end identi/uniFB01erregister number /one.pnum The response to a read message comprises either control token /three.pnum, /three.pnum/two.pnum-bit of data, and control-token /one.pnum (for success), or control tokens /four.pnum and /one.pnum (for failure). /four.pnum/five.pnum

B Processor Status Con/uniFB01guration The processor status control registers can be accessed directly by the processor using processor status reads and writes (use getps(reg) and setps(reg,value) for reads and writes). The identi/uniFB01ers for the registers needs a pre/uniFB01x “XS1_PS_ ” and a post/uniFB01x “_NUM ”, and are declared in “xs1.h ” Number Perm Description Register identi/uniFB01er /zero.pnumx/zero.pnum/zero.pnumRW RAM base address RAM_BASE /zero.pnumx/zero.pnum/one.pnumRW Vector base address VECTOR_BASE /zero.pnumx/zero.pnum/two.pnumRW xCORE Tile control XCORE_CTRL0 /zero.pnumx/zero.pnum/three.pnumRO xCORE Tile boot status BOOT_CONFIG /zero.pnumx/zero.pnum/five.pnumRW Security con/uniFB01guration SECURITY_CONFIG /zero.pnumx/zero.pnum6RW Ring Oscillator Control RING_OSC_CTRL /zero.pnumx/zero.pnum/seven.pnumRO Ring Oscillator Value RING_OSC_DATA0 /zero.pnumx/zero.pnum8RO Ring Oscillator Value RING_OSC_DATA1 /zero.pnumx/zero.pnum/nine.pnumRO Ring Oscillator Value RING_OSC_DATA2 /zero.pnumx/zero.pnumARO Ring Oscillator Value RING_OSC_DATA3 /zero.pnumx/zero.pnumCRO RAM size RAM_SIZE /zero.pnumx/one.pnum/zero.pnumDRW Debug SSR DBG_SSR /zero.pnumx/one.pnum/one.pnumDRW Debug SPC DBG_SPC /zero.pnumx/one.pnum/two.pnumDRW Debug SSP DBG_SSP /zero.pnumx/one.pnum/three.pnumDRW DGETREG operand /one.pnum DBG_T_NUM /zero.pnumx/one.pnum/four.pnumDRW DGETREG operand /two.pnum DBG_T_REG /zero.pnumx/one.pnum/five.pnumDRW Debug interrupt type DBG_TYPE /zero.pnumx/one.pnum6DRW Debug interrupt data DBG_DATA /zero.pnumx/one.pnum8DRW Debug core control DBG_RUN_CTRL Figure /four.pnum/nine.pnum: Summary /four.pnum6

Number Perm Description Register identi/uniFB01er Figure /five.pnum/zero.pnum: Summary (continued) B./one.pnum RAM base address RAM_BASE 0x00 Bits Perm Init Description Identi/uniFB01er /one.pnum:/zero.pnumRO - Reserved /zero.pnumx/zero.pnum/zero.pnum: RAM base address B./two.pnum Vector base address VECTOR_BASE 0x01 Base address of event vectors in each resource. On an interrupt or event, the /one.pnum6 most sig- ni/uniFB01cant bits of the destination address are provided by this register; the least signi/uniFB01cant /one.pnum6 bits come from the event vector. Bits Perm Init Description Identi/uniFB01er /one.pnum8:/zero.pnumRO - Reserved /zero.pnumx/zero.pnum/one.pnum: Vector base address B./three.pnum xCORE Tile control XCORE_CTRL0 0x02 Register to control features in the xCORE tile Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum/three.pnumRO - Reserved Specify size of a connected LPDDR device (options are: /one.pnum/zero.pnumRW /zero.pnumDisable RAMs to save power (contents will be lost) XCORE_CTRL0_RAMSHUTDOWN /nine.pnumRW /zero.pnumEnable memory auto-sleep feature XCORE_CTRL0_MEMSLEEP_ENABLE 8 RW /zero.pnumEnable MIPI interface periph ports XCORE_CTRL0_MIPI_ENABLE /seven.pnum:/five.pnumRO - Reserved /four.pnumRW /zero.pnum Enable the clock divider. This divides the output of the PLL to facilitate one of the low power modes. XCORE_CTRL0_CLK_DIVIDER_EN /three.pnum:/one.pnumRO - Reserved /zero.pnumRW /zero.pnumEnable External memory interface XCORE_CTRL0_EXTMEM_ENABLE /zero.pnumx/zero.pnum/two.pnum: xCORE Tile control /four.pnum/seven.pnum

B./four.pnum xCORE Tile boot status BOOT_CONFIG 0x03 This read-only register describes the boot status of the xCORE tile. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnum/four.pnumRO - Reserved /two.pnum/three.pnum:/one.pnum6RO Processor number. BOOT_CONFIG_PROCESSOR /one.pnum/five.pnum:/nine.pnumRO - Reserved 8 RO Overwrite BOOT_MODE. BOOT_CONFIG_SECURE_BOOT /seven.pnum:/five.pnumRO - Reserved /four.pnumRO Cause the ROM to not poll the OTP for correct read levels BOOT_CONFIG_DISABLE_OTP_POLL /three.pnumRO Boot ROM boots from RAM BOOT_CONFIG_BOOT_FROM_RAM /two.pnumRO Boot ROM boots from JTAG BOOT_CONFIG_BOOT_FROM_JTAG /one.pnum:/zero.pnumRO The boot PLL mode pin value. BOOT_CONFIG_PLL_MODE_PINS /zero.pnumx/zero.pnum/three.pnum: xCORE Tile boot status B./five.pnum Security con/uniFB01guration SECURITY_CONFIG 0x05 Copy of the security register as read from OTP . Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnumRW Disables write permission on this register SECUR_CFG_DISABLE_ACCESS /three.pnum/zero.pnum:/one.pnum/five.pnumRO - Reserved /one.pnum/four.pnumRW Disable access to XCore’s global debug SECUR_CFG_DISABLE_GLOBAL_DEBUG /one.pnum/three.pnum:/one.pnum/zero.pnumRO - Reserved /nine.pnumRW Disable read access to OTP . SECUR_CFG_OTP_READ_LOCK 8 RW Prevent access to OTP SBPI interface to prevent programming and other functions. SECUR_CFG_OTP_PROGRAM_DISABLE /seven.pnumRW Combine OTP into a single address-space for reading. SECUR_CFG_OTP_COMBINED

6 RO - Reserved

/five.pnumRW Override boot mode and read boot image from OTP SECUR_CFG_SECURE_BOOT /four.pnumRW Disable JTAG access to the PLL/BOOT con/uniFB01guration registers SECUR_CFG_DISABLE_PLL_JTAG /three.pnum:/one.pnumRO - Reserved /zero.pnumRW Disable access to XCore’s JTAG debug TAP SECUR_CFG_DISABLE_XCORE_JTAG /zero.pnumx/zero.pnum/five.pnum: Security con/uniFB01guration /four.pnum8

B.6 Ring Oscillator Control RING_OSC_CTRL 0x06 There are four free-running oscillators that clock four counters. The oscillators can be started and stopped using this register. The counters should only be read when the ring oscillator has been stopped for at least /one.pnum/zero.pnum core clock cycles (this can be achieved by inserting two nop instructions between the SETPS and GETPS). The counter values can be read using two subsequent registers. The ring oscillators are asynchronous to the xCORE tile clock and can be used as a source of random bits. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnumRO - Reserved /one.pnumRW /zero.pnumCore ring oscillator enable. RING_OSC_CORE_ENABLE /zero.pnumRW /zero.pnumSet to /one.pnum to enable the core peripheral ring oscillator.RING_OSC_PERPH_ENABLE /zero.pnumx/zero.pnum6: Ring Oscillator Control B./seven.pnum Ring Oscillator Value RING_OSC_DATA0 0x07 This register contains the current count of the xCORE Tile Cell ring oscillator. This value is not reset on a system reset. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum6RO - Reserved /zero.pnumx/zero.pnum/seven.pnum: Ring Oscillator Value B.8 Ring Oscillator Value RING_OSC_DATA1 0x08 This register contains the current count of the xCORE Tile Wire ring oscillator. This value is not reset on a system reset. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum6RO - Reserved /zero.pnumx/zero.pnum8: Ring Oscillator Value B./nine.pnum Ring Oscillator Value RING_OSC_DATA2 0x09 This register contains the current count of the Peripheral Cell ring oscillator. This value is not reset on a system reset. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum6RO - Reserved /zero.pnumx/zero.pnum/nine.pnum: Ring Oscillator Value /four.pnum/nine.pnum

B./one.pnum/zero.pnum Ring Oscillator Value RING_OSC_DATA3 0x0A This register contains the current count of the Peripheral Wire ring oscillator. This value is not reset on a system reset. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum6RO - Reserved /zero.pnumx/zero.pnumA: Ring Oscillator Value B./one.pnum/one.pnum RAM size RAM_SIZE 0x0C The size of the RAM in bytes Bits Perm Init Description Identi/uniFB01er /one.pnum:/zero.pnumRO - Reserved /zero.pnumx/zero.pnumC: RAM size B./one.pnum/two.pnum Debug SSR DBG_SSR 0x10 This register contains the value of the SSR register when the debugger was called. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum/one.pnumRO - Reserved /one.pnum/zero.pnumDRW /one.pnum if in high priority mode SR_QUEUE /nine.pnumDRW /one.pnum if, on kernel entry, the thread will switch to dual issue. SR_KEDI 8 RO /one.pnum when in dual issue mode. SR_DI /seven.pnumDRW /one.pnum when the thread is in fast mode and will continually issue.SR_FAST

6 DRW

/one.pnum when the thread is paused waiting for events, a lock or another resource. SR_WAITING /five.pnumRO - Reserved /four.pnumDRW /one.pnum when in kernel mode. SR_INK /three.pnumDRW /one.pnum when in an interrupt handler. SR_ININT /two.pnumDRW /one.pnum when in an event enabling sequence. SR_INENB /one.pnumDRW /one.pnum when interrupts are enabled for the thread. SR_IEBLE /zero.pnumDRW /one.pnum when events are enabled for the thread. SR_EEBLE /zero.pnumx/one.pnum/zero.pnum: Debug SSR B./one.pnum/three.pnum Debug SPC DBG_SPC 0x11 This register contains the value of the SPC register when the debugger was called. /five.pnum/zero.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumDRW Value. ALL_BITS /zero.pnumx/one.pnum/one.pnum: Debug SPC B./one.pnum/four.pnum Debug SSP DBG_SSP 0x12 This register contains the value of the SSP register when the debugger was called. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumDRW Value. ALL_BITS /zero.pnumx/one.pnum/two.pnum: Debug SSP B./one.pnum/five.pnum DGETREG operand /one.pnum DBG_T_NUM 0x13 The resource ID of the logical core whose state is to be read. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:8RO - Reserved /seven.pnum:/zero.pnumDRW Thread number to be read DBG_T_NUM_NUM /zero.pnumx/one.pnum/three.pnum: DGETREG operand /one.pnum B./one.pnum6 DGETREG operand /two.pnum DBG_T_REG 0x14 Register number to be read by DGETREG Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/five.pnumRO - Reserved /four.pnum:/zero.pnumDRW Register number to be read DBG_T_REG_REG /zero.pnumx/one.pnum/four.pnum: DGETREG operand /two.pnum B./one.pnum/seven.pnum Debug interrupt type DBG_TYPE 0x15 Register that speci/uniFB01es what activated the debug interrupt. /five.pnum/one.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum8RO - Reserved /one.pnum/seven.pnum:/one.pnum6DRW Number of the hardware breakpoint/watchpoint which caused the interrupt (always /zero.pnum for =HOST= and =DCALL=). If multiple break- points/watchpoints trigger at once, the lowest number is taken. DBG_TYPE_HW_NUM /one.pnum/five.pnum:8DRW Number of thread which caused the debug interrupt (always /zero.pnum in the case of =HOST=). DBG_TYPE_T_NUM /seven.pnum:/three.pnumRO - Reserved /two.pnum:/zero.pnumDRW /zero.pnum Indicates the cause of the debug interrupt /one.pnum: Host initiated a debug interrupt through JTAG /two.pnum: Program executed a DCALL instruction /three.pnum: Instruction breakpoint /four.pnum: Data watch point /five.pnum: Resource watch point DBG_TYPE_CAUSE /zero.pnumx/one.pnum/five.pnum: Debug interrupt type B./one.pnum8 Debug interrupt data DBG_DATA 0x16 On a data watchpoint, this register contains the effective address of the memory oper- ation that triggered the debugger. On a resource watchpoint, it countains the resource identi/uniFB01er. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumDRW Value. ALL_BITS /zero.pnumx/one.pnum6: Debug interrupt data B./one.pnum/nine.pnum Debug core control DBG_RUN_CTRL 0x18 This register enables the debugger to temporarily disable logical cores. When returning from the debug interrupts, the cores set in this register will not execute. This enables single stepping to be implemented. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:8RO - Reserved /seven.pnum:/zero.pnumDRW /one.pnum-hot vector de/uniFB01ning which threads are stopped when not in debug mode. Every bit which is set prevents the respective thread from running. DBG_RUN_CTRL_STOP /zero.pnumx/one.pnum8: Debug core control A set of registers used by the debug ROM to communicate with an external debugger, for example over JTAG. This is the same set of registers as the Debug Scratch registers in the xCORE tile con/uniFB01guration. /five.pnum/two.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumDRW Value. ALL_BITS Debug scratch This register contains the address of the instruction breakpoint. If the PC matches this address, then a debug interrupt will be taken. There are four instruction breakpoints that are controlled individually. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumDRW Value. ALL_BITS Instruction breakpoint address This register controls which logical cores may take an instruction breakpoint, and under which condition. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnum/four.pnumRO - Reserved /two.pnum/three.pnum:/one.pnum6DRW /zero.pnum A bit for each thread in the machine allowing the breakpoint to be en- abled individually for each thread. BRK_THREADS /one.pnum/five.pnum:/two.pnumRO - Reserved /one.pnumDRW /zero.pnum When /zero.pnum break when PC == IBREAK_ADDR. When /one.pnum = break when PC != IBREAK_ADDR. IBRK_CONDITION /zero.pnumDRW /zero.pnumWhen /one.pnum the breakpoint is enabled. BRK_ENABLE Instruction breakpoint control This set of registers contains the /uniFB01rst address for the four data watchpoints. Condition Aof a watchpoint is met if the effective address of an instruction is greater than or equal to the value in this register. The CTRL register for the watchpoint will dictate whether the watchpoint triggers on stores only or on loads and stores, and whether it requires either condition Aor B, or both Aand B. /five.pnum/three.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumDRW Value. ALL_BITS Data watchpoint address /one.pnum This set of registers contains the second address for the four data watchpoints. Con- dition Bof a watchpoint is met if the effective address of an instruction is less than or equal to the value in this register. The CTRL register for the watchpoint will dictate whether the watchpoint triggers on stores only or on loads and stores, and whether it requires either condition Aor B, or both Aand B. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumDRW Value. ALL_BITS Data watchpoint address /two.pnum This set of registers controls each of the four data watchpoints. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnum/four.pnumRO - Reserved /two.pnum/three.pnum:/one.pnum6DRW /zero.pnum A bit for each thread in the machine allowing the breakpoint to be en- abled individually for each thread. BRK_THREADS /one.pnum/five.pnum:/three.pnumRO - Reserved /two.pnumDRW /zero.pnumWhen /one.pnum the breakpoints will be be triggered on loads. BRK_LOAD /zero.pnumDRW /zero.pnumWhen /one.pnum the breakpoint is enabled. BRK_ENABLE Data breakpoint control register B./two.pnum6 Resources breakpoint mask DBG_RWATCH_ADDR1 0x80 .. 0x83 This set of registers contains the mask for the four resource watchpoints. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumDRW Value. ALL_BITS Resources breakpoint mask /five.pnum/four.pnum

This set of registers contains the value for the four resource watchpoints. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumDRW Value. ALL_BITS Resources breakpoint value B./two.pnum8 Resources breakpoint control register DBG_RWATCH_CTRL 0x9C .. 0x9F This set of registers controls each of the four resource watchpoints. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnum/four.pnumRO - Reserved /two.pnum/three.pnum:/one.pnum6DRW /zero.pnum A bit for each thread in the machine allowing the breakpoint to be en- abled individually for each thread. BRK_THREADS /one.pnum/five.pnum:/two.pnumRO - Reserved /one.pnumDRW /zero.pnum When /zero.pnum break when condition A is met. When /one.pnum = break when condition B is met. RBRK_CONDITION /zero.pnumDRW /zero.pnumWhen /one.pnum the breakpoint is enabled. BRK_ENABLE Resources breakpoint control register /five.pnum/five.pnum

C Tile Con/uniFB01guration The xCORE Tile control registers can be accessed using con/uniFB01guration reads and writes reads and writes). The identi/uniFB01ers for the registers needs a pre/uniFB01x “XS1_PSWITCH_ ” and a post/uniFB01x “_NUM ”, and are declared in “ xs1.h ” Number Perm Description Register identi/uniFB01er /zero.pnumx/zero.pnum/zero.pnumCRO Device identi/uniFB01cation DEVICE_ID0 /zero.pnumx/zero.pnum/one.pnumCRO xCORE Tile description /one.pnum DEVICE_ID1 /zero.pnumx/zero.pnum/two.pnumCRO xCORE Tile description /two.pnum DEVICE_ID2 /zero.pnumx/zero.pnum/four.pnumCRW PSwitch permissions DBG_CTRL /zero.pnumx/zero.pnum/five.pnumCRW Cause debug interrupts DBG_INT /zero.pnumx/zero.pnum6CRW xCORE Tile clock divider PLL_CLK_DIVIDER /zero.pnumx/zero.pnum/seven.pnumCRO Security con/uniFB01guration SECU_CONFIG /zero.pnumx/four.pnum/zero.pnumCRO PC of logical core /zero.pnum T0_PC /zero.pnumx/four.pnum/one.pnumCRO PC of logical core /one.pnum T1_PC /zero.pnumx/four.pnum/two.pnumCRO PC of logical core /two.pnum T2_PC /zero.pnumx/four.pnum/three.pnumCRO PC of logical core /three.pnum T3_PC /zero.pnumx/four.pnum/four.pnumCRO PC of logical core /four.pnum T4_PC /zero.pnumx/four.pnum/five.pnumCRO PC of logical core /five.pnum T5_PC /zero.pnumx/four.pnum6CRO PC of logical core 6 T6_PC /zero.pnumx/four.pnum/seven.pnumCRO PC of logical core /seven.pnum T7_PC /zero.pnumx6/zero.pnumCRO SR of logical core /zero.pnum T0_SR /zero.pnumx6/one.pnumCRO SR of logical core /one.pnum T1_SR /zero.pnumx6/two.pnumCRO SR of logical core /two.pnum T2_SR /zero.pnumx6/three.pnumCRO SR of logical core /three.pnum T3_SR /zero.pnumx6/four.pnumCRO SR of logical core /four.pnum T4_SR /zero.pnumx6/five.pnumCRO SR of logical core /five.pnum T5_SR /zero.pnumx66CRO SR of logical core 6 T6_SR /zero.pnumx6/seven.pnumCRO SR of logical core /seven.pnum T7_SR Figure /five.pnum/one.pnum: Summary C./one.pnum Device identi/uniFB01cation DEVICE_ID0 0x00 This register identi/uniFB01es the xCORE Tile /five.pnum6

Bits Perm Init Description Identi/uniFB01er /two.pnum/three.pnum:/one.pnum6CRO Number of the node in which this XCore is located. DEVICE_ID0_NODE /one.pnum/five.pnum:8CRO XCore revision. DEVICE_ID0_REVISION /seven.pnum:/zero.pnumCRO XCore version. DEVICE_ID0_VERSION /zero.pnumx/zero.pnum/zero.pnum: Device identi/uniFB01cation C./two.pnum xCORE Tile description /one.pnum DEVICE_ID1 0x01 This register describes the number of logical cores, synchronisers, locks and channel ends available on this xCORE tile. Bits Perm Init Description Identi/uniFB01er /two.pnum/three.pnum:/one.pnum6CRO Number of the locks. DEVICE_ID1_NUM_LOCKS /one.pnum/five.pnum:8CRO Number of synchronisers. DEVICE_ID1_NUM_SYNCS /seven.pnum:/zero.pnumRO - Reserved /zero.pnumx/zero.pnum/one.pnum: xCORE Tile description /one.pnum C./three.pnum xCORE Tile description /two.pnum DEVICE_ID2 0x02 This register describes the number of timers and clock blocks available on this xCORE tile. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum6RO - Reserved /one.pnum/five.pnum:8CRO Number of clock blocks. DEVICE_ID2_NUM_CLKBLKS /seven.pnum:/zero.pnumCRO Number of timers. DEVICE_ID2_NUM_TIMERS /zero.pnumx/zero.pnum/two.pnum: xCORE Tile description /two.pnum C./four.pnum PSwitch permissions DBG_CTRL 0x04 This register can be used to control whether the debug registers (marked with permission CRW) are accessible through the tile con/uniFB01guration registers. When this bit is set, write -access to those registers is disabled, preventing debugging of the xCORE tile over the interconnect. /five.pnum/seven.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnumCRW /zero.pnum When /one.pnum the PSwitch is restricted to RO access to all CRW registers from SSwitch, XCore(PS_DBG_Scratch) and JTAG DBG_CTRL_PSWITCH_RO /three.pnum/zero.pnum:/one.pnumRO - Reserved /zero.pnumCRW /zero.pnum When /one.pnum the PSwitch is restricted to RO access to all CRW registers from SSwitch DBG_CTRL_PSWITCH_RO_EXT /zero.pnumx/zero.pnum/four.pnum: PSwitch permissions C./five.pnum Cause debug interrupts DBG_INT 0x05 This register can be used to raise a debug interrupt in this xCORE tile. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnumRO - Reserved /one.pnumCRW /zero.pnum/one.pnum when the processor is in debug mode. DBG_INT_IN_DBG /zero.pnumCRW /zero.pnumRequest a debug interrupt on the processor. DBG_INT_REQ_DBG /zero.pnumx/zero.pnum/five.pnum: Cause debug interrupts C.6 xCORE Tile clock divider PLL_CLK_DIVIDER 0x06 This register contains the value used to divide the PLL clock to create the xCORE tile clock. The divider is enabled under control of the tile control register Bits Perm Init Description Identi/uniFB01er /three.pnum/zero.pnum:/one.pnum6RO - Reserved /zero.pnumx/zero.pnum6: xCORE Tile clock divider C./seven.pnum Security con/uniFB01guration SECU_CONFIG 0x07 Copy of the security register as read from OTP . /five.pnum8

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnumCRO Disables write permission on this register SECUR_CFG_DISABLE_ACCESS /three.pnum/zero.pnum:/one.pnum/five.pnumRO - Reserved /one.pnum/four.pnumCRO Disable access to XCore’s global debug SECUR_CFG_DISABLE_GLOBAL_DEBUG /one.pnum/three.pnum:/one.pnum/zero.pnumRO - Reserved /nine.pnumCRO Disable read access to OTP . SECUR_CFG_OTP_READ_LOCK

8 CRO

Prevent access to OTP SBPI interface to prevent programming and other functions. SECUR_CFG_OTP_PROGRAM_DISABLE /seven.pnumCRO Combine OTP into a single address-space for reading. SECUR_CFG_OTP_COMBINED /five.pnumCRO Override boot mode and read boot image from OTP SECUR_CFG_SECURE_BOOT /four.pnumCRO Disable JTAG access to the PLL/BOOT con/uniFB01guration registers SECUR_CFG_DISABLE_PLL_JTAG /three.pnum:/one.pnumRO - Reserved /zero.pnumCRO Disable access to XCore’s JTAG debug TAP SECUR_CFG_DISABLE_XCORE_JTAG /zero.pnumx/zero.pnum/seven.pnum: Security con/uniFB01guration C.8 Debug scratch DBG_SCRATCH 0x20 .. 0x27 A set of registers used by the debug ROM to communicate with an external debugger, for example over the switch. This is the same set of registers as the Debug Scratch registers in the processor status. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRW Value. ALL_BITS Debug scratch C./nine.pnum PC of logical core /zero.pnum T0_PC 0x40 Value of the PC of logical core /zero.pnum. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx/four.pnum/zero.pnum: PC of logical core /zero.pnum C./one.pnum/zero.pnum PC of logical core /one.pnum T1_PC 0x41 Value of the PC of logical core /one.pnum. /five.pnum/nine.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx/four.pnum/one.pnum: PC of logical core /one.pnum C./one.pnum/one.pnum PC of logical core /two.pnum T2_PC 0x42 Value of the PC of logical core /two.pnum. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx/four.pnum/two.pnum: PC of logical core /two.pnum C./one.pnum/two.pnum PC of logical core /three.pnum T3_PC 0x43 Value of the PC of logical core /three.pnum. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx/four.pnum/three.pnum: PC of logical core /three.pnum C./one.pnum/three.pnum PC of logical core /four.pnum T4_PC 0x44 Value of the PC of logical core /four.pnum. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx/four.pnum/four.pnum: PC of logical core /four.pnum C./one.pnum/four.pnum PC of logical core /five.pnum T5_PC 0x45 Value of the PC of logical core /five.pnum. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx/four.pnum/five.pnum: PC of logical core /five.pnum C./one.pnum/five.pnum PC of logical core 6 T6_PC 0x46 Value of the PC of logical core 6. 6/zero.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx/four.pnum6: PC of logical core 6 C./one.pnum6 PC of logical core /seven.pnum T7_PC 0x47 Value of the PC of logical core /seven.pnum. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx/four.pnum/seven.pnum: PC of logical core /seven.pnum C./one.pnum/seven.pnum SR of logical core /zero.pnum T0_SR 0x60 Value of the SR of logical core /zero.pnum Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx6/zero.pnum: SR of logical core /zero.pnum C./one.pnum8 SR of logical core /one.pnum T1_SR 0x61 Value of the SR of logical core /one.pnum Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx6/one.pnum: SR of logical core /one.pnum C./one.pnum/nine.pnum SR of logical core /two.pnum T2_SR 0x62 Value of the SR of logical core /two.pnum Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx6/two.pnum: SR of logical core /two.pnum C./two.pnum/zero.pnum SR of logical core /three.pnum T3_SR 0x63 Value of the SR of logical core /three.pnum 6/one.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx6/three.pnum: SR of logical core /three.pnum C./two.pnum/one.pnum SR of logical core /four.pnum T4_SR 0x64 Value of the SR of logical core /four.pnum Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx6/four.pnum: SR of logical core /four.pnum C./two.pnum/two.pnum SR of logical core /five.pnum T5_SR 0x65 Value of the SR of logical core /five.pnum Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx6/five.pnum: SR of logical core /five.pnum C./two.pnum/three.pnum SR of logical core 6 T6_SR 0x66 Value of the SR of logical core 6 Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx66: SR of logical core 6 C./two.pnum/four.pnum SR of logical core /seven.pnum T7_SR 0x67 Value of the SR of logical core /seven.pnum Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumCRO Value. ALL_BITS /zero.pnumx6/seven.pnum: SR of logical core /seven.pnum 6/two.pnum

D Node Con/uniFB01guration The digital node control registers can be accessed using con/uniFB01guration reads and writes reads and writes). The identi/uniFB01ers for the registers needs a pre/uniFB01x “XS1_SSWITCH_ ” and a post/uniFB01x “_NUM ”, and are declared in “ xs1.h ” Number Perm Description Register identi/uniFB01er /zero.pnumx/zero.pnum/zero.pnumRO Device identi/uniFB01cation DEVICE_ID0 /zero.pnumx/zero.pnum/one.pnumRO System switch description DEVICE_ID1 /zero.pnumx/zero.pnum/four.pnumRW Switch con/uniFB01guration NODE_CONFIG /zero.pnumx/zero.pnum/five.pnumRW Switch node identi/uniFB01er NODE_ID /zero.pnumx/zero.pnum6RW PLL settings PLL_CTL /zero.pnumx/zero.pnum/seven.pnumRW System switch clock divider CLK_DIVIDER /zero.pnumx/zero.pnum8RW Reference clock REF_CLK_DIVIDER /zero.pnumx/zero.pnum/nine.pnumR System JTAG device ID register JTAG_DEVICE_ID /zero.pnumx/zero.pnumAR System USERCODE register JTAG_USERCODE /zero.pnumx/zero.pnumBRW LPDDR clock DDR_CLK_DIVIDER /zero.pnumx/zero.pnumCRW Directions /zero.pnum-/seven.pnum DIMENSION_DIRECTION0 /zero.pnumx/zero.pnumDRW Directions 8-/one.pnum/five.pnum DIMENSION_DIRECTION1 /zero.pnumx/zero.pnumERW Application clock divider SS_APP_CLK_DIVIDER /zero.pnumx/zero.pnumFRW Secondary PLL settings SS_APP_PLL_CTL /zero.pnumx/one.pnum/zero.pnumRW DEBUG_N con/uniFB01guration, tile /zero.pnum XCORE0_GLOBAL_DEBUG_CONFIG /zero.pnumx/one.pnum/one.pnumRW DEBUG_N con/uniFB01guration, tile /one.pnum XCORE1_GLOBAL_DEBUG_CONFIG /zero.pnumx/one.pnum/two.pnumRW Secondary PLL Fractional N Divider SS_APP_PLL_FRAC_N_DIVIDER /zero.pnumx/one.pnum/three.pnumRW LPDDR Controller con/uniFB01guration SS_LPDDR_CONTROLLER_CONFIG /zero.pnumx/one.pnum/four.pnumRW MIPI shim clock con/uniFB01g MIPI_CLK_DIVIDER /zero.pnumx/one.pnum/five.pnumRW MIPI PHY clock con/uniFB01g MIPI_CFG_CLK_DIVIDER /zero.pnumx/one.pnumFRO Debug source GLOBAL_DEBUG_SOURCE Figure /five.pnum/two.pnum: Summary 6/three.pnum

Number Perm Description Register identi/uniFB01er /zero.pnumxF/zero.pnum/zero.pnum8RW USB UTMI Con/uniFB01g USB_PHY_CFG0 /zero.pnumxF/zero.pnum/zero.pnumARW USB reset USB_PHY_CFG2 /zero.pnumxF/zero.pnum/zero.pnumCRW USB Shim con/uniFB01guration USB_SHIM_CFG /zero.pnumxF/zero.pnum/one.pnum/one.pnumRO USB Phy Status USB_PHY_STATUS /zero.pnumxF/zero.pnum/two.pnum/zero.pnumRW Watchdog Con/uniFB01g WATCHDOG_CFG /zero.pnumxF/zero.pnum/two.pnum/one.pnumRO Watchdog Prescaler WATCHDOG_PRESCALER /zero.pnumxF/zero.pnum/two.pnum/two.pnumRW Watchdog Prescaler wrap WATCHDOG_PRESCALER_WRAP /zero.pnumxF/zero.pnum/two.pnum/three.pnumRW Watchdog Count WATCHDOG_COUNT /zero.pnumxF/zero.pnum/two.pnum/four.pnumRO Watchdog Status WATCHDOG_STATUS /zero.pnumxE/zero.pnum/one.pnum/three.pnumRW Mipi status MIPI_STATUS0 /zero.pnumxE/zero.pnum/one.pnum/four.pnumRW Mipi shim status MIPI_SHIM_STATUS /zero.pnumxE/zero.pnum/one.pnum8RW MIPI D-PHY reset con/uniFB01g MIPI_DPHY_CFG0 /zero.pnumxE/zero.pnum/one.pnumBRW MIPI D-PHY lane con/uniFB01g MIPI_DPHY_CFG3 /zero.pnumxE/zero.pnum/one.pnumCRW Mipi phy congif /four.pnum MIPI_DPHY_CFG4 /zero.pnumxE/zero.pnum/one.pnumFRW MIPI shim con/uniFB01guration MIPI_SHIM_CFG0 /zero.pnumxC/zero.pnum/zero.pnum/zero.pnumRW LPDDR enable IID transactions LPDDR_IID_ENABLE /zero.pnumxC/zero.pnum/zero.pnum/one.pnumRW LPDDR queue assignment for data LPDDR_IID_0_7 /zero.pnumxC/zero.pnum/zero.pnum/two.pnumRW LPDDR queue assignment for instructions LPDDR_IID_8_15 /zero.pnumxC/zero.pnum/zero.pnum/three.pnumRW LPDDR Queue Control LPDDR_QUEUE_CONT /zero.pnumxC/zero.pnum/zero.pnum8RW LPDDR Arbiter RO priority data LPDDR_RO_COMMAND_QUEUE_PRIORITY /zero.pnumxC/zero.pnum/zero.pnum/nine.pnumRW LPDDR Arbiter RW priority data LPDDR_RW_COMMAND_QUEUE_PRIORITY /zero.pnumxC/zero.pnum/zero.pnumARW LPDDR Arbiter timeout data LPDDR_ARBITRATION_TIMEOUT /zero.pnumxC/zero.pnum/one.pnumDRW LPDDR PHY control LPDDR_PHY_CONTROL /zero.pnumxC/zero.pnum/one.pnumERW LPDDR LMR con/uniFB01g LPDDR_LMR_OPCODE /zero.pnumxC/zero.pnum/one.pnumFRW LPDDR EMR con/uniFB01g LPDDR_EMR_OPCODE /zero.pnumxD/zero.pnum/zero.pnum/zero.pnumRW Padcontrol LPDDR CLK and CLK_N PADCTRL_CLK /zero.pnumxD/zero.pnum/zero.pnum/one.pnumRW Padcontrol LPDDR CKE PADCTRL_CKE /zero.pnumxD/zero.pnum/zero.pnum/two.pnumRW Padcontrol LPDDR CS_N PADCTRL_CS_N /zero.pnumxD/zero.pnum/zero.pnum/three.pnumRW Padcontrol LPDDR WE_N PADCTRL_WE_N /zero.pnumxD/zero.pnum/zero.pnum/four.pnumRW Padcontrol LPDDR CAS_N PADCTRL_CAS_N /zero.pnumxD/zero.pnum/zero.pnum/five.pnumRW Padcontrol LPDDR RAS_N PADCTRL_RAS_N Figure /five.pnum/three.pnum: Summary (continued) 6/four.pnum

Number Perm Description Register identi/uniFB01er /zero.pnumxD/zero.pnum/zero.pnum/nine.pnumRW Padcontrol LPDDR UDQS/LDQS PADCTRL_DQS /zero.pnumxD/zero.pnum/zero.pnumARW Padcontrol LPDDR UDM/LDM PADCTRL_DM Figure /five.pnum/four.pnum: Summary (continued) D./one.pnum Device identi/uniFB01cation DEVICE_ID0 0x00 This register contains version and revision identi/uniFB01ers and the mode-pins as sampled at boot-time. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnum/four.pnumRO - Reserved /two.pnum/three.pnum:/one.pnum6RO Sampled values of BootCtl pins on Power On Reset. SS_DEVICE_ID0_BOOT_CTRL /one.pnum/five.pnum:8RO SSwitch revision. SS_DEVICE_ID0_REVISION /seven.pnum:/zero.pnumRO SSwitch version. SS_DEVICE_ID0_VERSION /zero.pnumx/zero.pnum/zero.pnum: Device identi/uniFB01cation D./two.pnum System switch description DEVICE_ID1 0x01 This register speci/uniFB01es the number of processors and links that are connected to this switch. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnum/four.pnumRO - Reserved /two.pnum/three.pnum:/one.pnum6RO Number of SLinks on the SSwitch. SS_DEVICE_ID1_NUM_SLINKS /one.pnum/five.pnum:8RO Number of processors on the SSwitch. SS_DEVICE_ID1_NUM_PROCESSORS /seven.pnum:/zero.pnumRO Number of processors on the device. SS_DEVICE_ID1_NUM_PLINKS_PER_PROC /zero.pnumx/zero.pnum/one.pnum: System switch

description

D./three.pnum Switch con/uniFB01guration NODE_CONFIG 0x04 This register enables the setting of two security modes (that disable updates to the PLL or any other registers) and the header-mode. 6/five.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnumRW /zero.pnum /zero.pnum = SSCTL registers have write access. /one.pnum = SSCTL registers can not be written to. SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE /three.pnum/zero.pnum:/nine.pnumRO - Reserved 8 RW /zero.pnum /zero.pnum = PLL_CTL_REG has write access. /one.pnum = PLL_CTL_REG can not be writ- ten to. SS_NODE_CONFIG_DISABLE_PLL_CTL_REG /seven.pnum:/one.pnumRO - Reserved /zero.pnumx/zero.pnum/four.pnum: Switch con/uniFB01guration D./four.pnum Switch node identi/uniFB01er NODE_ID 0x05 This register contains the node identi/uniFB01er. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum6RO - Reserved /zero.pnumx/zero.pnum/five.pnum: Switch node identi/uniFB01er D./five.pnum PLL settings PLL_CTL 0x06 An on-chip PLL multiplies the input clock up to a higher frequency clock, used to clock the I/O, processor, and switch, see Oscillator. Note: a write to this register will cause the tile to be reset. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnumRW If set to /one.pnum, the chip will not be reset SS_PLL_CTL_NRESET /three.pnum/zero.pnumRW If set to /one.pnum, the chip will not wait for the PLL to re-lock. Only use this if a gradual change is made to the PLL SS_PLL_CTL_NLOCK /two.pnum/nine.pnumDW If set to /one.pnum, set the boot mode to boot from JTAGSS_TEST_MODE_BOOT_JTAG /two.pnum8DW If set to /one.pnum, set the PLL to be bypassed SS_TEST_MODE_PLL_BYPASS /two.pnum/seven.pnum:/two.pnum6RO - Reserved /two.pnum/two.pnum:/two.pnum/one.pnumRO - Reserved /two.pnum/zero.pnum:8RW F value. SS_PLL_CTL_FEEDBACK_MUL /seven.pnum:6RO - Reserved /five.pnum:/zero.pnumRW SS_PLL_CTL_INPUT_DIVISOR /zero.pnumx/zero.pnum6: PLL settings

D.6 System switch clock divider CLK_DIVIDER 0x07 Sets the ratio of the PLL clock and the switch clock. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum6RO - Reserved /one.pnum/five.pnum:/zero.pnumRW /zero.pnumSSwitch clock divider SS_CLK_DIVIDER_CLK_DIV /zero.pnumx/zero.pnum/seven.pnum: System switch clock divider D./seven.pnum Reference clock REF_CLK_DIVIDER 0x08 Sets the ratio of the PLL clock and the reference clock used by the node. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum6RO - Reserved /one.pnum/five.pnum:/zero.pnumRW /three.pnumSoftware reference clock divider SS_SSWITCH_REF_CLK_DIV /zero.pnumx/zero.pnum8: Reference clock D.8 System JTAG device ID register JTAG_DEVICE_ID 0x09 Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnum8RO SS_JTAG_DEVICE_ID_VERSION /two.pnum/seven.pnum:/one.pnum/two.pnumRO SS_JTAG_DEVICE_ID_PART_NUM /one.pnum/one.pnum:/one.pnumRO SS_JTAG_DEVICE_ID_MANU_ID /zero.pnumRO SS_JTAG_DEVICE_ID_CONST_VAL /zero.pnumx/zero.pnum/nine.pnum: System JTAG device ID register D./nine.pnum System USERCODE register JTAG_USERCODE 0x0A Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum8RO JTAG USERCODE value programmed into OTP SR SS_JTAG_USERCODE_OTP /one.pnum/seven.pnum:/zero.pnumRO metal /uniFB01xable ID code SS_JTAG_USERCODE_MASKID /zero.pnumx/zero.pnumA: System USERCODE register D./one.pnum/zero.pnum LPDDR clock DDR_CLK_DIVIDER 0x0B Sets the ratio of the PLL/APP PLL clock and the LPDDR clock. There is a divide by /two.pnum permanently after the clock divider to create a matched mark space ratio. The LPDDR clock needs to be set to be twice the frequency required. 6/seven.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnumRW /zero.pnum If set to /one.pnum, the secondary PLL is used as a source for the LPDDR clock divider. By default, the output of the core PLL is used. /three.pnum/zero.pnum:/one.pnum/seven.pnumRO - Reserved /one.pnum6RW /one.pnum LPDDR clock divider disable. When set to /zero.pnum, the divider is enabled. SS_DDR_CLK_DIV_DISABLE /one.pnum/five.pnum:/zero.pnumRW /zero.pnum LPDDR clock divider. When set to X the input clock is divided by 2(X + 1). SS_DDR_CLK_DIV /zero.pnumx/zero.pnumB: LPDDR clock This register contains eight directions, for packets with a mismatch in bits /seven.pnum../zero.pnum of the node-identi/uniFB01er. The direction in which a packet will be routed is goverened by the most signi/uniFB01cant mismatching bit. Bits Perm Init Description Identi/uniFB01er /zero.pnumx/zero.pnumC: Directions /zero.pnum-/seven.pnum This register contains eight directions, for packets with a mismatch in bits /one.pnum/five.pnum..8 of the node-identi/uniFB01er. The direction in which a packet will be routed is goverened by the most signi/uniFB01cant mismatching bit.

Bits Perm Init Description Identi/uniFB01er /one.pnum/one.pnum:8RW /zero.pnumThe direction for packets whose dimension is A. DIMA_DIR /three.pnum:/zero.pnumRW /zero.pnumThe direction for packets whose dimension is 8. DIM8_DIR /zero.pnumx/zero.pnumD: Directions 8-/one.pnum/five.pnum D./one.pnum/three.pnum Application clock divider SS_APP_CLK_DIVIDER 0x0E The clock divider and output of the secondary PLL can be set in this register Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnumRW /zero.pnum If set to /one.pnum, the secondary PLL is used as a source for the application clock divider. By default, the output of the core PLL is used. /three.pnum/zero.pnum:/one.pnum/seven.pnumRO - Reserved /one.pnum6RW /one.pnum Application clock divider disable. When set to /zero.pnum, the divider is enabled, and pin X/one.pnumD/one.pnum/one.pnum will be connected to the application clock rather than to port /one.pnumD. SS_APP_CLK_DIV_DISABLE /one.pnum/five.pnum:/zero.pnumRW /zero.pnum Application clock divider. When set to X, the output of the secondary PLL will be divided by 2(X+1) in order to form the output on the output pin SS_APP_CLK_DIV /zero.pnumx/zero.pnumE: Application clock divider D./one.pnum/four.pnum Secondary PLL settings SS_APP_PLL_CTL 0x0F A secondary on-chip PLL multiplies the input clock up to a higher frequency clock. See Section /seven.pnum./two.pnum. 6/nine.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/three.pnum/zero.pnumRO - Reserved /two.pnum/nine.pnumDW If set to /one.pnum, set the APP PLL to be bypassed SS_APP_PLL_BYPASS /two.pnum8DW If set to /one.pnum, use the output of the core PLL as input, otherwise use the crystal oscillator as input. SS_APP_PLL_INPUT_FROM_SYS_PLL /two.pnum/seven.pnumDW /zero.pnumIf set to /one.pnum, enable the secondary PLL SS_APP_PLL_ENABLE /two.pnum6RO - Reserved /two.pnum/two.pnum:/two.pnum/one.pnumRO - Reserved /two.pnum/zero.pnum:8RW F value. SS_PLL_CTL_FEEDBACK_MUL /seven.pnum:6RO - Reserved /five.pnum:/zero.pnumRW SS_PLL_CTL_INPUT_DIVISOR /zero.pnumx/zero.pnumF: Secondary PLL settings D./one.pnum/five.pnum DEBUG_N con/uniFB01guration, tile /zero.pnumXCORE0_GLOBAL_DEBUG_CONFIG 0x10 Con/uniFB01gures the behavior of the DEBUG_N pin. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnumRO - Reserved /one.pnumRW /zero.pnum Set /one.pnum to enable GlobalDebug to generate debug request to XCore. GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ /zero.pnumRW /zero.pnumSet /one.pnum to enable inDebug bit to drive GlobalDebug.GLOBAL_DEBUG_ENABLE_INDEBUG /zero.pnumx/one.pnum/zero.pnum: DEBUG_N con/uniFB01guration, tile /zero.pnum D./one.pnum6 DEBUG_N con/uniFB01guration, tile /one.pnumXCORE1_GLOBAL_DEBUG_CONFIG 0x11 Con/uniFB01gures the behavior of the DEBUG_N pin. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnumRO - Reserved /one.pnumRW /zero.pnum Set /one.pnum to enable GlobalDebug to generate debug request to XCore. GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ /zero.pnumRW /zero.pnumSet /one.pnum to enable inDebug bit to drive GlobalDebug.GLOBAL_DEBUG_ENABLE_INDEBUG /zero.pnumx/one.pnum/one.pnum: DEBUG_N con/uniFB01guration, tile /one.pnum D./one.pnum/seven.pnum Secondary PLL Fractional N DividerSS_APP_PLL_FRAC_N_DIVIDER 0x12 Controls an optional fractional N Divider on the secondary PLL. When enabled, the mul- tiplier F for the secondary PLL will effectively become F + f+1 p+1 , f must be less than p. /seven.pnum/zero.pnum

This is achieved by running the PLL with a divider F for the /uniFB01rst part of the fractional period, and then F + 1 for the remainder of the period. The period is measured in input clocks divided by R+ 1. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnumDW /zero.pnum When set to /one.pnum, the secondary PLL will be a fractionalN divided PLL SS_FRAC_N_ENABLE /three.pnum/zero.pnum:/one.pnum6RO - Reserved /one.pnum/five.pnum:8DW The f value for the fractional divider. The number of clock cycles in the period that a divider F + 1is used is f + 1. SS_FRAC_N_F_HIGH_CYC_CNT /seven.pnum:/zero.pnumDW The p value for the fractional divider. The period over which the frac- tional N divider oscillates between F and F + 1is p + 1 /zero.pnumx/one.pnum/two.pnum: Secondary PLL Fractional N Divider D./one.pnum8 LPDDR Controller con/uniFB01gurationSS_LPDDR_CONTROLLER_CONFIG 0x13 Controls whether LPDDR Controller is enabled, and which core it is accessible to through the mux. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnumRO - Reserved /one.pnumDW De/uniFB01nes which xCORE has access to the LPDDR controller via the mux SS_LPDDR_MUXTO_CORE1 /zero.pnumDW When set to /one.pnum this will allow the LPDDR controller to access the pads SS_LPDDR_ENABLE /zero.pnumx/one.pnum/three.pnum: LPDDR Controller con/uniFB01guration D./one.pnum/nine.pnum MIPI shim clock con/uniFB01gMIPI_CLK_DIVIDER 0x14 Con/uniFB01gures the clock to the MIPI shim, the hardware block interfacing the MIPI PHY to the xCORE. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnumRW /zero.pnum If set to /one.pnum, the secondary PLL is used as a source for the MIPI shim clock divider. By default, the output of the core PLL is used. /three.pnum/zero.pnum:/one.pnum/seven.pnumRO - Reserved /one.pnum6RW /one.pnum MIPI clock divider disable. When set to /zero.pnum, the divider is enabled. SS_SSWITCH_MIPI_CLK_DIV_DISABLE /one.pnum/five.pnum:/zero.pnumRW /three.pnum MIPI shim clock divider. When set to X the input clock is divided by 2(X + 1). SS_SSWITCH_MIPI_CLK_DIV /zero.pnumx/one.pnum/four.pnum: MIPI shim clock con/uniFB01g /seven.pnum/one.pnum

D./two.pnum/zero.pnum MIPI PHY clock con/uniFB01gMIPI_CFG_CLK_DIVIDER 0x15 Con/uniFB01gures the clock to the MIPI PHY. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnumRW /one.pnum If set to /one.pnum, the secondary PLL is used as a source for the MIPI PHY clock divider. By default, the output of the core PLL is used. /three.pnum/zero.pnum:/one.pnum/seven.pnumRO - Reserved /one.pnum6RW /one.pnum MIPI PHY clock divider disable. When set to /zero.pnum, the divider is enabled. SS_MIPI_CFG_CLK_DIV_DISABLE /one.pnum/five.pnum:/zero.pnumRW /zero.pnum MIPI PHY clock divider. When set to X, the input clock will be divided by 2(X + 1). SS_MIPI_CFG_CLK_DIV /zero.pnumx/one.pnum/five.pnum: MIPI PHY clock con/uniFB01g D./two.pnum/one.pnum Debug source GLOBAL_DEBUG_SOURCE 0x1F Contains the source of the most recent debug event. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/five.pnumRO - Reserved /four.pnumRW If set, external pin, is the source of last GlobalDebug event. GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG /three.pnum:/two.pnumRO - Reserved /one.pnumRW If set, XCore/one.pnum is the source of last GlobalDebug event. GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG /zero.pnumRW If set, XCore/zero.pnum is the source of last GlobalDebug event. GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG /zero.pnumx/one.pnumF: Debug source These registers contain status information for low level debugging (read-only), the net- work number that each link belongs to, and the direction that each link is part of. The /seven.pnum/two.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnum6RO - Reserved /two.pnum/five.pnum:/two.pnum/four.pnumRO Identify the SRC_TARGET type /zero.pnum - SLink, /one.pnum - PLink, /two.pnum - SSCTL, /three.pnum - Unde/uniFB01ne. SLINK_SRC_TARGET_TYPE /two.pnum/three.pnum:/one.pnum6RO When the link is in use, this is the destination link number to which all packets are sent. SLINK_SRC_TARGET_ID /one.pnum/five.pnum:/one.pnum/two.pnumRO - Reserved /one.pnum/one.pnum:8RW /zero.pnumThe direction that this link operates in. LINK_DIRECTION /seven.pnum:6RO - Reserved /five.pnum:/four.pnumRW /zero.pnum Determines the network to which this link belongs, reset as /zero.pnum. LINK_NETWORK /three.pnumRO - Reserved /two.pnumRO /one.pnum when the current packet is considered junk and will be thrown away. LINK_JUNK /one.pnumRO /one.pnum when the dest side of the link is in use. LINK_DST_INUSE /zero.pnumRO /one.pnum when the source side of the link is in use. LINK_SRC_INUSE Link status, direction, and network These registers contain status information and the network number that each processor- link belongs to. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnum6RO - Reserved /two.pnum/five.pnum:/two.pnum/four.pnumRO Identify the SRC_TARGET type /zero.pnum - SLink, /one.pnum - PLink, /two.pnum - SSCTL, /three.pnum - Unde/uniFB01ne. PLINK_SRC_TARGET_TYPE /two.pnum/three.pnum:/one.pnum6RO When the link is in use, this is the destination link number to which all packets are sent. PLINK_SRC_TARGET_ID /one.pnum/five.pnum:6RO - Reserved /five.pnum:/four.pnumRW /zero.pnum Determines the network to which this link belongs, reset as /zero.pnum. LINK_NETWORK /three.pnumRO - Reserved /two.pnumRO /one.pnum when the current packet is considered junk and will be thrown away. LINK_JUNK /one.pnumRO /one.pnum when the dest side of the link is in use. LINK_DST_INUSE /zero.pnumRO /one.pnum when the source side of the link is in use. LINK_SRC_INUSE PLink status and network /seven.pnum/three.pnum

These registers contain con/uniFB01guration and debugging information speci/uniFB01c to external links. The link speed and width can be set, the link can be initialized, and the link sta- Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnumRW Write to this bit with ’/one.pnum’ will enable the XLink, writing ’/zero.pnum’ will disable it. This bit controls the muxing of ports with overlapping xlinks. XLINK_ENABLE /two.pnum/nine.pnum:/two.pnum8RO - Reserved /two.pnum/seven.pnumRO Rx buffer over/uniFB02ow or illegal token encoding received.XLINK_RX_ERROR /two.pnum6RO /zero.pnum This end of the xlink has issued credit to allow the remote end to transmit RX_CREDIT /two.pnum/five.pnumRO /zero.pnumThis end of the xlink has credit to allow it to transmit. TX_CREDIT /two.pnum/four.pnumWO Clear this end of the xlink’s credit and issue a HELLO token. XLINK_HELLO /two.pnum/three.pnumWO Reset the receiver. The next symbol that is detected will be the /uniFB01rst symbol in a token. XLINK_RX_RESET /two.pnum/two.pnumRO - Reserved Specify min. number of idle system clocks between two continuous symbols witin a transmit token -/one.pnum. XLINK_INTRA_TOKEN_DELAY /one.pnum/zero.pnum:/zero.pnumRW /zero.pnum Specify min. number of idle system clocks between two continuous transmit tokens -/one.pnum. XLINK_INTER_TOKEN_DELAY Link con/uniFB01guration and initialization These registers are used for static (ie, non-routed) links. When a link is made static, all traf/uniFB01c is forwarded to the designated channel end and no routing is attempted. The registers control links C, D, A, B, G, H, E, and F in that order. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnumRW /zero.pnumEnable static forwarding. XSTATIC_ENABLE /three.pnum/zero.pnum:/nine.pnumRO - Reserved 8 RW /zero.pnum The destination processor on this node that packets received in static mode are forwarded to. XSTATIC_DEST_PROC /seven.pnum:/five.pnumRO - Reserved /four.pnum:/zero.pnumRW /zero.pnum The destination channel end on this node that packets received in static mode are forwarded to. XSTATIC_DEST_CHAN_END Static link con/uniFB01guration /seven.pnum/four.pnum

D./two.pnum6 USB UTMI Con/uniFB01g USB_PHY_CFG0 0xF008 This register con/uniFB01gures the UTMI signals to the USB PHY. See the UTMI speci/uniFB01cation for more details. The oscillator speed should be set to match the crystal on XIN/XOUT. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum/five.pnumRO - Reserved USB_PHY_CFG0_XTLSEL /one.pnum/one.pnumRW /zero.pnumSet to /one.pnum to enable the ID PAD USB_PHY_CFG0_IDPAD_EN /one.pnum/zero.pnumRW /zero.pnumSet to /one.pnum to enable USB LPM USB_PHY_CFG0_LPM_ALIVE /nine.pnumRW /zero.pnumSet to /one.pnum to enable the USB PLL USB_PHY_CFG0_PLL_EN 8 RW /zero.pnumSet to /one.pnum to enable USB Tx BitStuf/uniFB01ngUSB_PHY_CFG0_TXBITSTUFF_EN /seven.pnumRW /zero.pnumSet to /one.pnum to enable the DM Pulldown USB_PHY_CFG0_DMPULLDOWN 6 RW /zero.pnumSet to /one.pnum to enable the DP Pulldown USB_PHY_CFG0_DPPULLDOWN /five.pnumRW /one.pnum Value of the UTMI SuspendM signal to the USB Phy USB_PHY_CFG0_UTMI_SUSPENDM /four.pnum:/three.pnumRW /one.pnumValue of the UTMI OpMode signals to the USB Phy USB_PHY_CFG0_UTMI_OPMODE /two.pnumRW /one.pnum Value of the UTMI Terminal Select signal to the USB Phy USB_PHY_CFG0_UTMI_TERMSELECT /one.pnum:/zero.pnumRW /one.pnum Value of the UTMI XCVRSelect signals to the USB Phy USB_PHY_CFG0_UTMI_XCVRSELECT /zero.pnumxF/zero.pnum/zero.pnum8: USB UTMI Con/uniFB01g D./two.pnum/seven.pnum USB reset USB_PHY_CFG2 0xF00A Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnumRO - Reserved /one.pnumRW /one.pnumUTMI reset, set to /zero.pnum to take UTMI out of reset USB_PHY_CFG2_UTMI_RESET /zero.pnumRW /zero.pnumUSB PHY reset, set to /one.pnum to take the PHY out of resetUSB_PHY_CFG2_PONRST /zero.pnumxF/zero.pnum/zero.pnumA: USB reset D./two.pnum8 USB Shim con/uniFB01guration USB_SHIM_CFG 0xF00C This register contains the hardware interfacing the USB PHY and the xCORE. It governs how the rxActive, rxValid, and line-state signals are mapped onto two one-bit ports. /seven.pnum/five.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnumRO - Reserved /one.pnumRW /zero.pnum USB /uniFB02ag mode selection: /one.pnum selects linestate; /zero.pnum selects RxActive and RxValid USB_SHIM_CFG_FLAG_MODE /zero.pnumRW /zero.pnum When enabled RxValid output to xCore is AND’d with RxActive /zero.pnumxF/zero.pnum/zero.pnumC: USB Shim con/uniFB01guration D./two.pnum/nine.pnum USB Phy Status USB_PHY_STATUS 0xF011 Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/five.pnumRO - Reserved /four.pnumRO /zero.pnum/one.pnum if BIST succeeded USB_PHY_STATUS_BIST_OK /three.pnumRO /zero.pnum /one.pnum if resistance of IDPAD to ground is > /one.pnum/zero.pnum/zero.pnum kOhm (mini B plug) USB_PHY_STATUS_IDPAD /two.pnumRO /zero.pnumSet to /one.pnum if no peripheral is connected USB_PHY_STATUS_HOSTDISCONNECT /zero.pnumxF/zero.pnum/one.pnum/one.pnum: USB Phy Status D./three.pnum/zero.pnum Watchdog Con/uniFB01g WATCHDOG_CFG 0xF020 Register to control the watchdog. By default the watchdog is neither counting, nor trig- gering. When used as a watchdog it should be set to both count and trigger a reset on reaching /zero.pnum. It can be set to just count for debugging purposes Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnumRO - Reserved /one.pnumRW /zero.pnum Set this bit to /one.pnum to enable the watchdog to actually reset the chip. WATCHDOG_TRIGGER_ENABLE /zero.pnumRW /zero.pnumSet this bit to /one.pnum to enable the watchdog counter.WATCHDOG_COUNT_ENABLE /zero.pnumxF/zero.pnum/two.pnum/zero.pnum: Watchdog Con/uniFB01g D./three.pnum/one.pnum Watchdog Prescaler WATCHDOG_PRESCALER 0xF021 Register to read out the current divider counter. Can be used to implement a timer that is independent of the PLL. /seven.pnum6

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum6RO - Reserved /one.pnum/five.pnum:/zero.pnumRO /zero.pnum This is the current count of the prescaler. One is added one every in- put clock edge on the oscillator (XIN). When it reaches the prescaler wrap value (see below), it resets to zero and one is subtracted from the watchdog count (see below). WATCHDOG_PRESCALER_VALUE /zero.pnumxF/zero.pnum/two.pnum/one.pnum: Watchdog Prescaler D./three.pnum/two.pnum Watchdog Prescaler wrapWATCHDOG_PRESCALER_WRAP 0xF022 Register to set the watchdog pre-scale divider value. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum6RO - Reserved /one.pnum/five.pnum:/zero.pnumRW /zero.pnumxFFFF This is the prescaler divider. The input clock on XIN is divided by this value plus one, before being used to adjust the watchdog count (see below). WATCHDOG_PRESCALER_WRAP_VALUE /zero.pnumxF/zero.pnum/two.pnum/two.pnum: Watchdog Prescaler wrap D./three.pnum/three.pnum Watchdog Count WATCHDOG_COUNT 0xF023 Register to set the value at which the watchdog timer should time out. This register must be overwritten regularly to stop the watchdog from resetting the chip. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum/two.pnumRO - Reserved /one.pnum/one.pnum:/zero.pnumRW /zero.pnumxFFF This is the watchdog counter. It counts down every PRESCALER_WRAP_VALUE input clock edges. When it reaches zero the chip is reset. The maximum time for the watchdog is 212 × 216 = 228 = 268, 435, 456 input clocks. WATCHDOG_COUNT_VALUE /zero.pnumxF/zero.pnum/two.pnum/three.pnum: Watchdog Count D./three.pnum/four.pnum Watchdog Status WATCHDOG_STATUS 0xF024 Register that can be used to inspect whether the watchdog has triggered. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnumRO - Reserved /zero.pnumRO /zero.pnum When /one.pnum, the watchdog has been triggered. This bit is only reset to /zero.pnum on a power-on-reset. WATCHDOG_HAS_TRIGGERED /zero.pnumxF/zero.pnum/two.pnum/four.pnum: Watchdog Status /seven.pnum/seven.pnum

D./three.pnum/five.pnum Mipi status MIPI_STATUS0 0xE013 Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum/five.pnumRO - Reserved /one.pnum/four.pnumRO Lane /one.pnum is in the stop state MIPI_STATUS0_STOPSTATE_LAN1 /one.pnum/three.pnumRO Lane /zero.pnum is in the stop state MIPI_STATUS0_STOPSTATE_LAN0 /one.pnum/two.pnumRO Clock lane is in the stop state MIPI_STATUS0_STOPSTATE_CLK /five.pnumRO Test mode data correct lan/two.pnum MIPI_STATUS0_DATA_CORRECT_LAN2 /four.pnumRO Test mode data correct lan/one.pnum MIPI_STATUS0_DATA_CORRECT_LAN1 /three.pnumRO Test mode data correct lan/zero.pnum MIPI_STATUS0_DATA_CORRECT_LAN0 /one.pnumRO Test mode osc clock ready MIPI_STATUS0_OSC_CLK_READY /zero.pnumRO Test mode osc clock act MIPI_STATUS0_OSC_CLK_ACT /zero.pnumxE/zero.pnum/one.pnum/three.pnum: Mipi status D./three.pnum6 Mipi shim status MIPI_SHIM_STATUS 0xE014 This register provides status for the MIPI demuxing logic Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnumRO - Reserved /zero.pnumRW /zero.pnum Set to /one.pnum if an over/uniFB02ow has been detected in the DEMUXER. This is not recoverable, and indicates that the MIPI_CLK is too slow for the rate at which data is received. MIPI_SHIM_STATUS_REG /zero.pnumxE/zero.pnum/one.pnum/four.pnum: Mipi shim status D./three.pnum/seven.pnum MIPI D-PHY reset con/uniFB01gMIPI_DPHY_CFG0 0xE018 Controls the reset signals to the MIPI D-PHY Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnumRO - Reserved /one.pnumRW /zero.pnumSet to /one.pnum MIPI_DPHY_CFG0_RSTB09_ALWAYS_ON /zero.pnumRW /zero.pnumReset, set to /one.pnum to take the MIPI PHY out of resetMIPI_DPHY_CFG0_HW_RSTN /zero.pnumxE/zero.pnum/one.pnum8: MIPI D-PHY reset con/uniFB01g D./three.pnum8 MIPI D-PHY lane con/uniFB01g MIPI_DPHY_CFG3 0xE01B Con/uniFB01gures the settings for the three lanes, in particular, where the wires appear on the physical interfaces and which ones are enabled. /seven.pnum8

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum/five.pnumRO - Reserved /one.pnum/two.pnumRW /one.pnumSet to /zero.pnum to disable the clock lane receiver MIPI_DPHY_CFG3_ENABLE_CLK /nine.pnumRW /zero.pnum Set to /one.pnum to swap the DN/DP pair on the clock lane MIPI_DPHY_CFG3_DPDN_SWAP_CLK 8:6 RW /two.pnum The DP/DN pair over which to input lane /one.pnum (if two lanes are needed) MIPI_DPHY_CFG3_LANE_SWAP_LAN1 /five.pnum:/three.pnumRW /zero.pnumThe DP/DN pair over which to input lane /zero.pnumMIPI_DPHY_CFG3_LANE_SWAP_LAN0 /two.pnum:/zero.pnumRW /one.pnumThe DP/DN pair over which to input the clock MIPI_DPHY_CFG3_LANE_SWAP_CLK /zero.pnumxE/zero.pnum/one.pnumB: MIPI D-PHY lane con/uniFB01g D./three.pnum/nine.pnum Mipi phy congif /four.pnum MIPI_DPHY_CFG4 0xE01C Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnum/four.pnumRO - Reserved /one.pnum/five.pnum:8RW /zero.pnumxAMIPI dphy Tclk-settle in lane /zero.pnum MIPI_DPHY_CFG4_PRECOUNTER_IN_LAN0 /seven.pnum:/zero.pnumRW /zero.pnumxBMIPI dphy Tclk-settle for clock MIPI_DPHY_CFG4_PRECOUNTER_IN_CLK /zero.pnumxE/zero.pnum/one.pnumC: Mipi phy congif /four.pnum D./four.pnum/zero.pnum MIPI shim con/uniFB01gurationMIPI_SHIM_CFG0 0xE01F This register is used to con/uniFB01gure the MIPI shim, the hardware block interfacing the MIPI D-PHY to the xCORE. By default the MIPI shim just passes the data from the MIPI D-PHY must specify the CSI-/two.pnum packet type that demultiplexing should apply to. Optionally, you can choose to align add an extra fourth byte for RGB formats, or you can choose to bias the data so that all the data values are signed. /seven.pnum/nine.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnum/seven.pnumRO - Reserved /two.pnum6RW /zero.pnumMIPI shim con/uniFB01g/zero.pnum sel debug MIPI_SHIM_CFG0_SEL_DEBUG /two.pnum/five.pnumRW /zero.pnumMIPI shim con/uniFB01g/zero.pnum sel debug outMIPI_SHIM_CFG0_SEL_DEBUG_OUT /two.pnum/four.pnumRO - Reserved /two.pnum/three.pnumRW /zero.pnum Set to /one.pnum to offset the output pixels with -/zero.pnumx8/zero.pnum (for 8-bit outputs) or - signed around zero. MIPI_SHIM_BIAS /two.pnum/two.pnumRW /zero.pnum Set to /one.pnum to add an extra data byte after every RGB/five.pnum6/five.pnum or RGB888 pixel. This will align pixels to a /three.pnum/two.pnum-bit word.MIPI_SHIM_DEMUX_STUFF /two.pnum/one.pnum:/one.pnum6RW /zero.pnum Speci/uniFB01es how the demultiplexer operates. The modes supported are MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE /one.pnum/five.pnum:8RW /zero.pnum This /uniFB01eld needs to be set to the CSI-/two.pnum packet type that needs to be demuxed. Only packets with a matching type are demultiplexed. MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE /seven.pnum:/one.pnumRO - Reserved /zero.pnumRW /zero.pnum Set to /one.pnum to enable the MIPI shim to demultiplex data according to the demux mode and stuff /uniFB01elds. Demuxing is only applied to packets that have the correct datatype. MIPI_SHIM_CFG0_PIXEL_DEMUX_EN /zero.pnumxE/zero.pnum/one.pnumF: MIPI shim con/uniFB01guration D./four.pnum/one.pnum LPDDR enable IID transactionsLPDDR_IID_ENABLE 0xC000 This register is used to enable one or more threads to route its requests through speci/uniFB01ed queues. There are three queues (one read-only queue, RO, and two read-write queues, RW/zero.pnum/RW/one.pnum) and for each thread instruction accesses and data accesses can be routed through speci/uniFB01ed queues. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum6RO - Reserved /one.pnum/five.pnum:/zero.pnumRW /zero.pnum Two 8-bit masks, one bit per thread. Top eight bits enable instructions to be routed through a speci/uniFB01ed queue, bottom eight bits enable data to be routed through a speci/uniFB01ed queue. LPDDR_IID_ENABLE /zero.pnumxC/zero.pnum/zero.pnum/zero.pnum: LPDDR enable IID transactions D./four.pnum/two.pnum LPDDR queue assignment for dataLPDDR_IID_0_7 0xC001 For each thread, this register speci/uniFB01es which queue a data access should be routed through. 8/zero.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumRW /zero.pnum Four bits per thread. Top bit sets the queue type that this thread should be using (/zero.pnum: RO, /one.pnum: RW), further three bits the number of the queue. Valid a RW queue. LPDDR_IID_0_7 /zero.pnumxC/zero.pnum/zero.pnum/one.pnum: LPDDR queue assignment for data D./four.pnum/three.pnum LPDDR queue assignment for instructionsLPDDR_IID_8_15 0xC002 For each thread, this register speci/uniFB01es which queue an instruction access should be routed through. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/zero.pnumRW /zero.pnum Four bits per thread. Top bit sets the queue type that this thread should be using (/zero.pnum: RO, /one.pnum: RW), further three bits the number of the queue. Valid a RW queue. LPDDR_IID_8_15 /zero.pnumxC/zero.pnum/zero.pnum/two.pnum: LPDDR queue assignment for instructions D./four.pnum/four.pnum LPDDR Queue Control LPDDR_QUEUE_CONT 0xC003 Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnumRO - Reserved /zero.pnumRW /zero.pnum Slow sys clock. Set this bit if the tile clock is less than the LPDDR clock. LPDDR_QUEUE_CONT /zero.pnumxC/zero.pnum/zero.pnum/three.pnum: LPDDR Queue Control D./four.pnum/five.pnum LPDDR Arbiter RO priority dataLPDDR_RO_COMMAND_QUEUE_PRIORITY 0xC008 Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/three.pnumRO - Reserved /zero.pnumxC/zero.pnum/zero.pnum8: LPDDR Arbiter RO priority data 8/one.pnum

D./four.pnum6 LPDDR Arbiter RW priority dataLPDDR_RW_COMMAND_QUEUE_PRIORITY 0xC009 Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:6RO - Reserved /zero.pnumxC/zero.pnum/zero.pnum/nine.pnum: LPDDR Arbiter RW priority data D./four.pnum/seven.pnum LPDDR Arbiter timeout dataLPDDR_ARBITRATION_TIMEOUT 0xC00A Setting this to a non-zero value guarantees that each queue is served at least every N transactions and prevents starvation. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/four.pnumRO - Reserved /three.pnum:/zero.pnumRW /four.pnum Maximum number of transactions until a queue is served. Set to /zero.pnum to disable a timeout LPDDR_TOUT /zero.pnumxC/zero.pnum/zero.pnumA: LPDDR Arbiter timeout data D./four.pnum8 LPDDR PHY control LPDDR_PHY_CONTROL 0xC01D Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum/four.pnumRO - Reserved /zero.pnumxC/zero.pnum/one.pnumD: LPDDR PHY control D./four.pnum/nine.pnum LPDDR LMR con/uniFB01gLPDDR_LMR_OPCODE 0xC01E Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum/four.pnumRO - Reserved /zero.pnumxC/zero.pnum/one.pnumE: LPDDR LMR con/uniFB01g D./five.pnum/zero.pnum LPDDR EMR con/uniFB01gLPDDR_EMR_OPCODE 0xC01F Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum/four.pnumRO - Reserved /zero.pnumxC/zero.pnum/one.pnumF: LPDDR EMR con/uniFB01g 8/two.pnum

D./five.pnum/one.pnum LPDDR timings /one.pnumLPDDR_PROTOCOL_ENGINE_CONF_0 0xC020 Register used to set the tREFI, tRAS, tXSR, and tWR timings, all measured in terms of LPDDR clocks Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/two.pnum/four.pnumRO - Reserved /one.pnum/four.pnum:/one.pnum/one.pnumRW 8 LPDDR tRAS clock count LPDDR_PE_TRAS_CNT /zero.pnumxC/zero.pnum/two.pnum/zero.pnum: LPDDR timings /one.pnum D./five.pnum/two.pnum LPDDR timings /two.pnumLPDDR_PROTOCOL_ENGINE_CONF_1 0xC021 Register used to set the tRRC, tRCD, tRP , tRFC, and tRRD timings, all measured in terms of LPDDR clocks. This register is also used to con/uniFB01gure the use of /two.pnum/five.pnum6 bit memories. Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/one.pnum8RO - Reserved /one.pnum6:/one.pnum/five.pnumRW /one.pnumLPDDR tRRD clock count LPDDR_PE_TRRD_CNT /nine.pnum:/seven.pnumRW /four.pnumLPDDR tRP clock count LPDDR_PE_TRP_CNT 6:/four.pnumRW /four.pnumLPDDR tRCD clock count LPDDR_PE_TRCD_CNT /three.pnum:/zero.pnumRW /one.pnum/one.pnumLPDDR tRC clock count LPDDR_PE_TRC_CNT /zero.pnumxC/zero.pnum/two.pnum/one.pnum: LPDDR timings /two.pnum D./five.pnum/three.pnum Padcontrol LPDDR CLK and CLK_NPADCTRL_CLK 0xD000 When LPDDR is enabled, this register controls the PAD properties for the CLK and CLK_N pins 8/three.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/seven.pnumRO - Reserved 6 RW /zero.pnumSet to /one.pnum to enable the schmitt trigger PADCTRL_SCHMITT_TRIGGER_ENABLE /five.pnumRW /zero.pnumSet to /one.pnum to enable slew-rate control PADCTRL_SLEW_RATE_CONTROL /four.pnum:/three.pnumRW /one.pnum/zero.pnum mA. PADCTRL_DRIVE_STRENGTH /two.pnum:/one.pnumRW /zero.pnum/zero.pnum /one.pnum/one.pnum for weak bus-keep. PADCTRL_PULL /zero.pnumRW /zero.pnumSet to /one.pnum to enable the input receiver PADCTRL_RECEIVER_ENABLE /zero.pnumxD/zero.pnum/zero.pnum/zero.pnum: Padcontrol LPDDR CLK and CLK_N D./five.pnum/four.pnum Padcontrol LPDDR CKE PADCTRL_CKE 0xD001 When LPDDR is enabled, this register controls the PAD properties for the CKE pin Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/seven.pnumRO - Reserved 6 RW /zero.pnumSet to /one.pnum to enable the schmitt trigger PADCTRL_SCHMITT_TRIGGER_ENABLE /five.pnumRW /zero.pnumSet to /one.pnum to enable slew-rate control PADCTRL_SLEW_RATE_CONTROL /four.pnum:/three.pnumRW /one.pnum/zero.pnum mA. PADCTRL_DRIVE_STRENGTH /two.pnum:/one.pnumRW /zero.pnum/zero.pnum /one.pnum/one.pnum for weak bus-keep. PADCTRL_PULL /zero.pnumRW /zero.pnumSet to /one.pnum to enable the input receiver PADCTRL_RECEIVER_ENABLE /zero.pnumxD/zero.pnum/zero.pnum/one.pnum: Padcontrol LPDDR CKE D./five.pnum/five.pnum Padcontrol LPDDR CS_N PADCTRL_CS_N 0xD002 When LPDDR is enabled, this register controls the PAD properties for the CS_N pin Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/seven.pnumRO - Reserved 6 RW /zero.pnumSet to /one.pnum to enable the schmitt trigger PADCTRL_SCHMITT_TRIGGER_ENABLE /five.pnumRW /zero.pnumSet to /one.pnum to enable slew-rate control PADCTRL_SLEW_RATE_CONTROL /four.pnum:/three.pnumRW /one.pnum/zero.pnum mA. PADCTRL_DRIVE_STRENGTH /two.pnum:/one.pnumRW /zero.pnum/zero.pnum /one.pnum/one.pnum for weak bus-keep. PADCTRL_PULL /zero.pnumRW /zero.pnumSet to /one.pnum to enable the input receiver PADCTRL_RECEIVER_ENABLE /zero.pnumxD/zero.pnum/zero.pnum/two.pnum: Padcontrol LPDDR CS_N 8/four.pnum

D./five.pnum6 Padcontrol LPDDR WE_N PADCTRL_WE_N 0xD003 When LPDDR is enabled, this register controls the PAD properties for the WE_N pin Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/seven.pnumRO - Reserved 6 RW /zero.pnumSet to /one.pnum to enable the schmitt trigger PADCTRL_SCHMITT_TRIGGER_ENABLE /five.pnumRW /zero.pnumSet to /one.pnum to enable slew-rate control PADCTRL_SLEW_RATE_CONTROL /four.pnum:/three.pnumRW /one.pnum/zero.pnum mA. PADCTRL_DRIVE_STRENGTH /two.pnum:/one.pnumRW /zero.pnum/zero.pnum /one.pnum/one.pnum for weak bus-keep. PADCTRL_PULL /zero.pnumRW /zero.pnumSet to /one.pnum to enable the input receiver PADCTRL_RECEIVER_ENABLE /zero.pnumxD/zero.pnum/zero.pnum/three.pnum: Padcontrol LPDDR WE_N D./five.pnum/seven.pnum Padcontrol LPDDR CAS_N PADCTRL_CAS_N 0xD004 When LPDDR is enabled, this register controls the PAD properties for the CAS_N pin Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/seven.pnumRO - Reserved 6 RW /zero.pnumSet to /one.pnum to enable the schmitt trigger PADCTRL_SCHMITT_TRIGGER_ENABLE /five.pnumRW /zero.pnumSet to /one.pnum to enable slew-rate control PADCTRL_SLEW_RATE_CONTROL /four.pnum:/three.pnumRW /one.pnum/zero.pnum mA. PADCTRL_DRIVE_STRENGTH /two.pnum:/one.pnumRW /zero.pnum/zero.pnum /one.pnum/one.pnum for weak bus-keep. PADCTRL_PULL /zero.pnumRW /zero.pnumSet to /one.pnum to enable the input receiver PADCTRL_RECEIVER_ENABLE /zero.pnumxD/zero.pnum/zero.pnum/four.pnum: Padcontrol LPDDR CAS_N D./five.pnum8 Padcontrol LPDDR RAS_N PADCTRL_RAS_N 0xD005 When LPDDR is enabled, this register controls the PAD properties for the RAS_N pin 8/five.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/seven.pnumRO - Reserved 6 RW /zero.pnumSet to /one.pnum to enable the schmitt trigger PADCTRL_SCHMITT_TRIGGER_ENABLE /five.pnumRW /zero.pnumSet to /one.pnum to enable slew-rate control PADCTRL_SLEW_RATE_CONTROL /four.pnum:/three.pnumRW /one.pnum/zero.pnum mA. PADCTRL_DRIVE_STRENGTH /two.pnum:/one.pnumRW /zero.pnum/zero.pnum /one.pnum/one.pnum for weak bus-keep. PADCTRL_PULL /zero.pnumRW /zero.pnumSet to /one.pnum to enable the input receiver PADCTRL_RECEIVER_ENABLE /zero.pnumxD/zero.pnum/zero.pnum/five.pnum: Padcontrol LPDDR RAS_N When LPDDR is enabled, this register controls the PAD properties for the A/zero.pnum-A/one.pnum/three.pnum pins Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/seven.pnumRO - Reserved 6 RW /zero.pnumSet to /one.pnum to enable the schmitt trigger PADCTRL_SCHMITT_TRIGGER_ENABLE /five.pnumRW /zero.pnumSet to /one.pnum to enable slew-rate control PADCTRL_SLEW_RATE_CONTROL /four.pnum:/three.pnumRW /one.pnum/zero.pnum mA. PADCTRL_DRIVE_STRENGTH /two.pnum:/one.pnumRW /zero.pnum/zero.pnum /one.pnum/one.pnum for weak bus-keep. PADCTRL_PULL /zero.pnumRW /zero.pnumSet to /one.pnum to enable the input receiver PADCTRL_RECEIVER_ENABLE /zero.pnumxD/zero.pnum/zero.pnum6: Padcontrol LPDDR A/zero.pnum-A/one.pnum/three.pnum D.6/zero.pnum Padcontrol LPDDR BA/zero.pnum/BA/one.pnumPADCTRL_BA 0xD007 When LPDDR is enabled, this register controls the PAD properties for the BA/zero.pnum and BA/one.pnum pins Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/seven.pnumRO - Reserved 6 RW /zero.pnumSet to /one.pnum to enable the schmitt trigger PADCTRL_SCHMITT_TRIGGER_ENABLE /five.pnumRW /zero.pnumSet to /one.pnum to enable slew-rate control PADCTRL_SLEW_RATE_CONTROL /four.pnum:/three.pnumRW /one.pnum/zero.pnum mA. PADCTRL_DRIVE_STRENGTH /two.pnum:/one.pnumRW /zero.pnum/zero.pnum /one.pnum/one.pnum for weak bus-keep. PADCTRL_PULL /zero.pnumRW /zero.pnumSet to /one.pnum to enable the input receiver PADCTRL_RECEIVER_ENABLE /zero.pnumxD/zero.pnum/zero.pnum/seven.pnum: Padcontrol LPDDR BA/zero.pnum/BA/one.pnum

When LPDDR is enabled, this register controls the PAD properties for the DQ/zero.pnum-DQ/one.pnum/five.pnum pins Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/seven.pnumRO - Reserved 6 RW /zero.pnumSet to /one.pnum to enable the schmitt trigger PADCTRL_SCHMITT_TRIGGER_ENABLE /five.pnumRW /zero.pnumSet to /one.pnum to enable slew-rate control PADCTRL_SLEW_RATE_CONTROL /four.pnum:/three.pnumRW /one.pnum/zero.pnum mA. PADCTRL_DRIVE_STRENGTH /two.pnum:/one.pnumRW /zero.pnum/zero.pnum /one.pnum/one.pnum for weak bus-keep. PADCTRL_PULL /zero.pnumRW /one.pnumSet to /one.pnum to enable the input receiver PADCTRL_RECEIVER_ENABLE /zero.pnumxD/zero.pnum/zero.pnum8: Padcontrol LPDDR DQ/zero.pnum-DQ/one.pnum/five.pnum D.6/two.pnum Padcontrol LPDDR UDQS/LDQS PADCTRL_DQS 0xD009 When LPDDR is enabled, this register controls the PAD properties for the UDQS and LDQS pins Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/seven.pnumRO - Reserved 6 RW /zero.pnumSet to /one.pnum to enable the schmitt trigger PADCTRL_SCHMITT_TRIGGER_ENABLE /five.pnumRW /zero.pnumSet to /one.pnum to enable slew-rate control PADCTRL_SLEW_RATE_CONTROL /four.pnum:/three.pnumRW /one.pnum/zero.pnum mA. PADCTRL_DRIVE_STRENGTH /two.pnum:/one.pnumRW /zero.pnum/zero.pnum /one.pnum/one.pnum for weak bus-keep. PADCTRL_PULL /zero.pnumRW /one.pnumSet to /one.pnum to enable the input receiver PADCTRL_RECEIVER_ENABLE /zero.pnumxD/zero.pnum/zero.pnum/nine.pnum: Padcontrol LPDDR UDQS/LDQS D.6/three.pnum Padcontrol LPDDR UDM/LDM PADCTRL_DM 0xD00A When LPDDR is enabled, this register controls the PAD properties for the UDM and LDM pins 8/seven.pnum

Bits Perm Init Description Identi/uniFB01er /three.pnum/one.pnum:/seven.pnumRO - Reserved 6 RW /zero.pnumSet to /one.pnum to enable the schmitt trigger PADCTRL_SCHMITT_TRIGGER_ENABLE /five.pnumRW /zero.pnumSet to /one.pnum to enable slew-rate control PADCTRL_SLEW_RATE_CONTROL /four.pnum:/three.pnumRW /one.pnum/zero.pnum mA. PADCTRL_DRIVE_STRENGTH /two.pnum:/one.pnumRW /zero.pnum/zero.pnum /one.pnum/one.pnum for weak bus-keep. PADCTRL_PULL /zero.pnumRW /zero.pnumSet to /one.pnum to enable the input receiver PADCTRL_RECEIVER_ENABLE /zero.pnumxD/zero.pnum/zero.pnumA: Padcontrol LPDDR UDM/LDM

E Resources and their con/uniFB01guration This section documents how many of each resources are present, and how the SETC instruction is used to con/uniFB01gure the resource. For all other information on resources, please refer to the XS/three.pnum ISA speci/uniFB01cation. The SETC operand is a number with the following bit /uniFB01elds that have been organised so that frequently used modes can be encoded in an immediate 6-bit operand. Reserved Long mode setting Value The meaning of the bits is resource dependent. E./one.pnum Ports There are:

• /three.pnum/two.pnum /one.pnum-bit ports
• /one.pnum/two.pnum /four.pnum-bit ports
• 8 8-bit ports
• /four.pnum /one.pnum6-bit ports
• /two.pnum /three.pnum/two.pnum-bit ports The following controls can be set using SETC : 8/nine.pnum

INUSE_OFF , INUSE_ON off (value /zero.pnum). Before using a port it must be switched on. COND_NONE , COND_EQ , COND_NEQ test for equal, and value /two.pnum sets up a test for not equal. An input of a port with a condition will only succeed when the condition matches. SETD is used to set the test operand. IE_MODE_EVENT , IE_MODE_INTERRUPT /zero.pnum) or interrupts (value /one.pnum). By default it generates events. DRIVE_DRIVE , DRIVE_PULL_DOWN , DRIVE_PULL_UP sets the drive transistor to just drive the high side and enable a weak pull-down, Value /two.pnum sets the drive transistors to just drive the low side and enable a weak pull-up control. Bit /two.pnum/three.pnum enables the Schmitt-Trigger. MS_MASTER , MS_SLAVE slave mode (value /one.pnum). BUF_NOBUFFERS , BUF_BUFFERS unbuffered (value /zero.pnum). Unbuffered is the default. RDY_NOREADY , RDY_STROBED , RDY_HANDSHAKE or full handshaking (value /two.pnum). Default is no ready wires. SDELAY_NOSDELAY , SDELAY_SDELAY the falling edge (value /one.pnum) PORT_DATAPORT , PORT_CLOCKPORT , PORT_READYPORT signal (value /two.pnum). By default the port is a data port. This can only be applied to /one.pnum-bit ports. INV_NOINVERT , INV_INVERT (value /one.pnum). input signals by a set number of core clock ticks. Defaults to /zero.pnum. E./two.pnum Timers There are /one.pnum/zero.pnum timers. The following controls can be set usingSETC : /nine.pnum/zero.pnum

COND_NONE , COND_AFTER ter the given time (value /one.pnum). Set the time for comparison using SETD . IE_MODE_EVENT , IE_MODE_INTERRUPT /zero.pnum) or interrupts (value /one.pnum). By default it generates events. E./three.pnum Channel ends There are /three.pnum/two.pnum channel-ends. The following controls can be set usingSETC : IE_MODE_EVENT , IE_MODE_INTERRUPT /zero.pnum) or interrupts (value /one.pnum). By default it generates events. E./four.pnum Synchronizers There are /seven.pnum synchronizers. They cannot be con/uniFB01gured using SETC. E./five.pnum Threads There are 8 threads. They cannot be con/uniFB01gured using SETC. E.6 Locks There are /four.pnum locks. They cannot be con/uniFB01gured using SETC. E./seven.pnum Clock blocks There are 6 clock-blocks. INUSE_OFF , INUSE_ON off (value /zero.pnum). Before using a port it must be switched on. RUN_STOPR , RUN_STARTR running, the clock block cannot be recon/uniFB01gured. clock block by this many core clock cycles. The clock block cannot delay beyond the rising input clock edge. clock block by this many core clock cycles. The clock block cannot delay beyond the falling input clock edge. E.8 Software De/uniFB01ned Memory There are two software de/uniFB01ned memory resources in each tile: the read miss resource and the write miss resource. /nine.pnum/one.pnum

INUSE_OFF , INUSE_ON or off (value /zero.pnum). When on, the software memory address space will be routed to the mini-cache, and misses will cause an even- t/interrupt on this resource. IE_MODE_EVENT , IE_MODE_INTERRUPT /zero.pnum) or interrupts (value /one.pnum). By default it generates events. ware that the software memory miss has been serviced by soft- ware. /nine.pnum/two.pnum

F JTAG, xSCOPE and Debugging If you intend to design a board that can be used with the XMOS toolchain and xTAG debugger, you will need an xSYS/two.pnum connection on your board. There are three physical xSYS/two.pnum connections that XMOS uses:

• In its smallest form you can put 6 testpoints and three through-holes on the PCB and use a TAG-connect cable to connect to an XTAG.
• You can use a half-sized header (approximately /seven.pnum mm wide) that supports just JTAG, which is cabled to an XTAG.
• You can use a full sized header (approximately /one.pnum/three.pnum mm wide) supports both JTAG and XSCOPE, again cabled to an XTAG. Note that the xSYS/two.pnum header has a different form-factor than the xSYS header used on use /one.pnum.8V XTAG adapters to program this device. Figure /five.pnum/five.pnum shows a decision diagram which explains what type of xSYS/two.pnum connectivity you need. The three subsections below explain the options in detail. Is debugging required? Does the QSPI flash need to be programmed? Is xSCOPE required? Is fast printf required? YES NO NOYESNOYES NOYES Use full xSYS2 header See section .4 Use JTAG xSYS2 header See section .3 No xSYS2 header required See section .1 Use TAG connect header See section .2 Figure /five.pnum/five.pnum: Decision diagram for the xSYS/two.pnum header F./one.pnum No xSYS/two.pnum connection The use of an xSYS/two.pnum connection is optional, and may not be required for volume pro- duction designs. However, the XMOS toolchain expects the xSYS/two.pnum connection; if you do not have an xSYS/two.pnum connection then you must provide your own method for writing to /uniFB02ash/OTP and for debugging. /nine.pnum/three.pnum

F./two.pnum JTAG-only TAG-connect header This header requires six test-points on the PCB with three through holes for registration, plugged into an XTAG/four.pnum. For details on the foot-print and on the cable see https://www.tag- connect.com/. Use the following pin-out: GND TMS TDI TDO TCK VREF Figure /five.pnum6: Foot print for tag-connect header

• pin /one.pnum: TCK
• pin /two.pnum: GND
• pin /three.pnum: TMS
• pin /four.pnum: TDI
• pin /five.pnum: VREF
• pin 6: TDO F./three.pnum JTAG-only xSYS/two.pnum header Connect the following pins of the /zero.pnum./zero.pnum/five.pnum" header:
• pins /three.pnum, /five.pnum, /seven.pnum, and /nine.pnum to GROUND
• pin /one.pnum to VDDIOB/one.pnum8 (with a decoupler)
• pin /two.pnum to TMS
• pin /four.pnum to TCK
• pin 6 to TDO
• pin 8 to TDI
• pin /one.pnum/zero.pnum to RST_N The pin-out of this header is shown in the blue section of Figure /five.pnum/seven.pnum. F./four.pnum Full xSYS/two.pnum header For a full xSYS/two.pnum header you will need to connect the pins as discussed in Section F./three.pnum, and then connect a /two.pnum-wire xCONNECT Link to the xSYS/two.pnum header. The pin-out of this header is shown in Figure /five.pnum/seven.pnum. The links can be found in the Signal description table (Section /four.pnum): they are labelled XL/zero.pnum, XL/one.pnum, etc in the function column. The /two.pnum-wire link comprises two inputs and outputs, la- /nine.pnum/four.pnum

VREF_JTAG GND GND GND GND VREF_LINK GND GND GND GND TMS TCK TDO TDI RST_N XL_DN1 XL_DN0 XL_UP0 XL_UP1 DEBUG_N 1.27mm JTAG only XSYS2 header Full XSYS2 header Figure /five.pnum/seven.pnum: xSYS/two.pnum header pin-out, as seen from above belled 1 out, 0 out, 0 in, and 1 in. For example, if you choose to use XL/zero.pnum for xSCOPE I/O, you need to connect up XL/zero.pnum/one.pnum out, XL/zero.pnum/zero.pnum out, XL/zero.pnum/zero.pnum in, XL/zero.pnum/one.pnum in as follows:

• XL/zero.pnum/one.pnum device.
• XL/zero.pnum/zero.pnum device.
• XL/zero.pnum/zero.pnum
• XL/zero.pnum/one.pnum
• Connect pin /one.pnum/one.pnum to the VDDIO that is used to power the link, with a decoupler. In this and for link /seven.pnum use VDDIOB/one.pnum8. /nine.pnum/five.pnum

G Schematics Design Check List This section is a checklist for use by schematics designers using the XU/three.pnum/one.pnum6- each design. G./one.pnum Power supplies Figure /three.pnum/three.pnum). PLL_AVDD is /uniFB01ltered with a low pass /uniFB01lter, for example an RC /uniFB01lter, see Sec- tion /one.pnum/four.pnum . PLL_AVDD/two.pnum is /uniFB01ltered with a low pass /uniFB01lter, for example an RC /uniFB01lter, see Section /one.pnum/four.pnum . If any of the VDDIOL, VDDIOT, or VDDIOR domains are at /one.pnumV8, then then the corresponding LV_L_N, LV_T_N, or LV_R_N pin has been strapped to GROUND (Section /one.pnum/four.pnum). G./two.pnum Power supply decoupling The design has multiple decoupling capacitors per supply, as speci/uniFB01ed in Section /one.pnum/four.pnum. A bulk decoupling capacitor of at least /one.pnum/zero.pnumuF is placed on each supply (Sec- tion /one.pnum/four.pnum). G./three.pnum Power on reset At least one of these two conditions is true: /one.pnum. All VDDIO pins are supplied by the same /one.pnum.8V supply (the on-chip power- on-reset will operate correctly); or /two.pnum. RST_N is kept low until all VDDIO are valid, and RST_N is fast enough to meet USB timings. See Section /one.pnum/four.pnum. G./four.pnum Clock If you put a crystal between XIN/XOUT you followed the guidelines in Sec- tion /seven.pnum./three.pnum. If you supply a clock directly onto XIN, then it is /one.pnum.8V, low jitter, and has monotonic edges. /nine.pnum6

You have chosen an input clock frequency that is supported by the device (Section /seven.pnum). G./five.pnum Boot The device is connected to a QSPI /uniFB02ash for booting, connected to X/zero.pnumD/zero.pnum/one.pnum, through OTP or JTAG, or set it to boot from SPI and connect a SPI /uniFB02ash. The Flash that you have chosen is supported by the tools. G.6 JTAG, XScope, and debugging You have decided as to whether you need an xSYS/two.pnum header or not (Sec- tion F) (Section F) If you have not included an xSYS/two.pnum header, you have devised a method to program the SPI-/uniFB02ash or OTP (Section F). G./seven.pnum GPIO You have not mapped both inputs and outputs to the same multi-bit port. after reset, pulled high and low appropriately (Section /nine.pnum) G.8 Multi device designs Skip this section if your design only includes a single XMOS device. One device is connected to a QSPI or SPI /uniFB02ash for booting. Devices that boot from link have, for example, X/zero.pnumD/zero.pnum6 pulled high and have link XL/zero.pnum connected to a device to boot from (Section /nine.pnum). /nine.pnum/seven.pnum

H PCB Layout Design Check List This section is a checklist for use by PCB designers using the XS/three.pnum-U/one.pnum6A- each design. H./one.pnum Ground Plane Each ground ball has a via to minimize impedance and conduct heat away H./two.pnum Power supply decoupling The decoupling capacitors are all placed close to a supply pin (Section /one.pnum/four.pnum). The decoupling capacitors are spaced around the device (Section /one.pnum/four.pnum). The ground side of each decoupling capacitor has a direct path back to the center ground of the device. H./three.pnum PLL_AVDD The PLL_AVDD /uniFB01lter (especially the capacitor) is placed close to the PLL_AVDD pin (Section /one.pnum/four.pnum). The PLL_AVDD/two.pnum /uniFB01lter (especially the capacitor) is placed close to the PLL_AVDD/two.pnum pin (Section /one.pnum/four.pnum). /nine.pnum8

I Associated Design Documentation Document Title Information Document XMOS Programming Guide Timers, ports, clocks, cores and channels Link XTC Tools Guide Compilers, assembler and linker/mapper Link Timing analyzer, xScope, debugger Flash and OTP programming utilities J Related Documentation Document Title Information Document xCONNECT Architecture Link, switch and system information Link /nine.pnum/nine.pnum

Xmos Ltd.is the owner or licensee of this design, code, or Information (collectively, the “Information”) and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. Xmos Ltd.makes no representation that the Information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. XMOS, xCore, xcore.ai, and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other countries and may not be used without written permission. Company and product names mentioned in this document are the trademarks or registered trademarks of their respective owners. /one.pnum/zero.pnum/zero.pnum