XC886

XC886 INFINEON | Alldatasheet

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Data Sheet, V0.1, Feb. 2006 XC886/888CLM 8-Bit Single-Chip Microcontroller P rel im inar y

Published by Infineon Technologies AG,

81726 München, Germany

© Infineon Technologies AG 2006. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, V0.1, Feb. 2006 XC886/888CLM 8-Bit Single-Chip Microcontroller P rel im inar y

Revision History: 2006-02 V0.1 Previous Version: Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

Data Sheet 1 V0.1, 2006-02 Prelimary XC886/8888-Bit Single-Chip Microcontroller

1 Summary of Features

• High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers
• On-chip memory – 12 Kbytes of Boot ROM – 256 bytes of RAM – 1.5 Kbytes of XRAM – 24/32 Kbytes of Flash; or 24/32 Kbytes of ROM, with additional 4 Kbytes of Flash (includes memory protection strategy)
• I/O port supply at 3.3 V or 5.0 V and co re logic supply at 2.5 V (generated by embedded voltage regulator) (more features on next page) Figure 1 XC886/888 Functional Units Port 0 Port 1 Port 2 Port 3 XC800 Core UART ADC 10-bit 8-channel Boot ROM 12K x 8 XRAM 1.5K x 8 RAM 256 x 8 On-Chip Debug Support Timer 0 16-bit Timer 1 16-bit Timer 2 16-bit UART1 SSCFlash or ROM 1) 24K/32K x 8 Capture/Compare Unit 16-bit Compare Unit 16-bit 8-bit Digital I/O 8-bit Digital I/O 8-bit Digital I/O 8-bit Digital/ Analog Input 1) All ROM devices come with an additional 4K x 8 Flash Port 4Port 5MDU CORDIC MultiCAN Timer 21 16-bit Watchdog Timer 8-bit Digital I/O 8-bit Digital I/O

Data Sheet 2 V0.1, 2006-02 Prelimary Features (continued):

• Power-on reset generation
• Brownout detection for core logic supply
• On-chip OSC and PLL for clock generation – PLL loss-of-lock detection
• Power saving modes – slow-down mode – idle mode – power-down mode with wake-up capability via RXD or EXINT0 – clock gating control to each peripheral
• Programmable 16-bit Watchdog Timer (WDT)
• S i x p o r t s – 34/48 pins as digital I/O – 8 pins as digital/analog input
• 8-channel, 10-bit ADC
• Four 16-bit timers – Timer 0 and Timer 1 (T0 and T1) – Timer 2 and Timer 21
• Multiplication/Division Unit for arithmetic operations (MDU)
• CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear functions
• MultiCAN with 2 nodes, 32 message objects (MCAN)
• Capture/compare unit for PWM signal generation (CCU6)
• Two full-duplex serial interfaces (UART and UART1)
• Synchronous serial channel (SSC)
• On-chip debug support – 1 Kbyte of monitor ROM (part of the 12-Kbyte Boot ROM) – 64 bytes of monitor RAM
• Packages: –P G - T Q F P - 4 8 – PG-TQFP-64
• Temperature range T – SAF (-40 to 85 °C) – SAK (-40 to 125 °C)

Data Sheet 3 V0.1, 2006-02 Prelimary XC886/888 Variant Devices The XC886/888 product family features devic es with different configurations, program memory sizes, package options, temperat ure and quality profiles (Automotive or Industrial), to offer cost-effective solutions for different application requirements. The list of XC886/888 device configurations are summarized in Table 1. For each configuration, 2 types of packages are available:

• PG-TQFP-48, which is denoted by XC886 and;
• PG-TQFP-64, which is denoted by XC888. From these 10 different combinations of configuration and package type, each are further made available in 6 sales types, which are grouped according to program memory sizes, temperature and quality profiles (Automotive or Industrial), as shown in Table 2. Note: The asterisk (*) above denotes th e device configuration letters from Table 1. Corresponding ROM derivatives will be available on request. Table 1 Device Configuration Device Name CAN Module LIN BSL Support MDU Module XC886/888 No No No XC886/888C Yes No No XC886/888CM Yes No Yes XC886/888LM No Yes Yes XC886/888CLM Yes Yes Yes Table 2 Device Profile Sales Type Device Type Program Memory Size (Kbytes) Temperature Profile (°C) Quality Profile SAK-XC886*/888*-8FFA Flash 32 -40 to 125 Automotive SAK-XC886*/888*-6FFA Flash 24 -40 to 125 Automotive SAF-XC886*/888*-8FFA Fla sh 32 -40 to 85 Automotive SAF-XC886*/888*-6FFA Fla sh 24 -40 to 85 Automotive SAF-XC886*/888*-8FFI Flash 32 -40 to 85 Industrial SAF-XC886*/888*-6FFI Flash 24 -40 to 85 Industrial

Data Sheet 4 V0.1, 2006-02 Prelimary

Ordering Information

The ordering code for Infineon Technologi es microcontrollers provides an exact reference to the required product. This ordering code indentifies:

• The derivative itself, i.e. its function set
• the specified temperature range
• the package and the type of delivery For the available ordering codes for the XC886/888, please refer to the “Product Catalog Microcontrollers” which summarizes all available microcontroller variants. Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code.

General Device Information Data Sheet 5 V0.1, 2006-02 Prelimary

2 General Device Information

2.1 Block Diagram

Figure 2 XC886/888 Block Diagram ADC Port 0Port 1Port 2Port 3 UART1CORDIC SSCMDU Timer 2 12-Kbyte Boot ROM1) 256-byte RAM 64-byte monitor RAM 1.5-Kbyte XRAM 24/32-Kbyte Flash or ROM2) XC800 Core T0 & T1 UART 1) Includes 1-Kbyte monitor ROM 2) The 24/32-Kbyte ROM has an additional 4-Kbyte Flash P0.0 - P0.7 P1.0 - P1.7 P3.0 - P3.7 P2.0 - P2.7 VAREF VAGNDClock Generator

9.6 MHz

P4.0 - P4.7 P5.0 - P5.7 WDT OCDS

General Device Information Data Sheet 6 V0.1, 2006-02 Prelimary

2.2 Logic Symbol

Figure 3 XC886/888 Logic Symbol XC886 VDDP VSSP VDDC VSSC VAREF VAGND XTAL1 XTAL2 TMS RESET MBC Port 0 7-Bit Port 1 8-Bit Port 3 8-Bit Port 2 8-Bit Port 4 3-Bit XC888 VDDP VSSP VDDC VSSC VAREF VAGND XTAL1 XTAL2 TMS RESET MBC Port 0 8-Bit Port 1 8-Bit Port 3 8-Bit Port 2 8-Bit Port 4 8-Bit Port 5 8-Bit

General Device Information Data Sheet 7 V0.1, 2006-02 Prelimary

2.3 Pin Configuration

Figure 4 XC886 Pin Configuration, PG-TQFP-48 Package (top view) XC886 123 4 56789 1 0 1 1 1 2 36 35 34 33 32 31 30 29 28 27 26 25 RESET P3.5 P3.4 P4.1 P4.0 P0.3 P0. 4 MBC P3.2 P3.3 P0.7 VDDP VSSP P0. 0 P0. 5 P1. 6 P1. 7 VSSC VDDC XTAL2 XTAL1 TMS P2.2 VDDP VSSP P2.0 P2.1 P2.4 P2.3 P2.5 P2.6 VAREF VAGND P0. 2 P0.1 P1.3 P1.4 P1.2 P1.0 P1.1 P1.5 P2.7 P3.0 P3.1 P3.6 P3.7 P4.3 VDDP

General Device Information Data Sheet 8 V0.1, 2006-02 Prelimary Figure 5 XC888 Pin Configuration, PG-TQFP-64 Package (top view) VDDP XC888 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 6 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RESET P3.5 P3.4 P2.2 VDDP P1.3 P1.4 P5.0 P4.2 P4.1 P4.0 P1.2 VSSP P5.1 P2.0 P0.3 P0.4 P0.5 P1.6 P1.7 P2.1 VSSC VDDC XTAL2 XTAL1 TMS MBC P1.0 P1.1 P1.5 P2.4 P2.3 P2.7 P2.5 P2.6 P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 VAREF VAGND P0.6 P0.7 P4.5 P4.4 P4.6 P4.7 P5.5 P5.6 P5.7 P5.4 VDDP P0.0 NC NC P5.3 P4.3 P5.2 VSSP P0.2 P0.1 Note: The pins shaded in blue are not available in the PG-TQFP-48 package.

General Device Information Data Sheet 9 V0.1, 2006-02 Prelimary

2.4 Pin Definitions and Functions

Table 3 Pin Definitions and Functions Symbol Pin Number (TQFP-48/64) Type Reset State Function P0 I/O Port 0 Port 0 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, UART1, Timer 2, Timer 21, MCAN and SSC. P0.0 11/17 Hi-Z TCK_0 JTAG Clock Input T12HR_1 CCU6 Timer 12 Hardware Run Input CC61_1 Input/Output of Capture/ Compare channel 1 CLKOUT_0 Clock Output RXDO_1 UART Transmit Data Output P0.1 13/21 Hi-Z TDI_0 JTAG Serial Data Input T13HR_1 CCU6 Timer 13 Hardware Run Input RXD_1 UART Receive Data Input RXDC1_0 MCAN Node 1 Receiver Input COUT61_1 Output of Capture/Compare channel 1 EXF2_1 Timer 2 External Flag Output P0.2 12/18 PU CTRAP_2 CCU6 Trap Input TDO_0 JTAG Serial Data Output TXD_1 UART Transmit Data Output/ Clock Output TXDC1_0 MCAN Node 1 Transmitter Output P0.3 48/63 Hi-Z SCK_1 SSC Clock Input/Output COUT63_1 Output of Capture/Compare channel 3 RXDO1_0 UART1 Transmit Data Output

General Device Information Data Sheet 10 V0.1, 2006-02 Prelimary P0.4 1/64 Hi-Z MTSR_1 SSC Master Transmit Output/ Slave Receive Input CC62_1 Input/Output of Capture/ Compare channel 2 TXD1_0 UART1 Transmit Data Output/ Clock Output P0.5 2/1 Hi-Z MRST_1 SSC Master Receive Input/ Slave Transmit Output EXINT0_0 External Interrupt Input 0 T2EX1_1 Timer 21 External Trigger Input RXD1_0 UART1 Receive Data Input COUT62_1 Output of Capture/Compare channel 2 P0.6 –/2 PU GPIO P0.7 47/62 PU CLKOUT_1 Clock Output Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) Type Reset State Function

General Device Information Data Sheet 11 V0.1, 2006-02 Prelimary P1 I/O Port 1 Port 1 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, Timer 0, Timer 1, Timer 2, Timer 21, MCAN and SSC. P1.0 26/34 PU RXD_0 UART Receive Data Input T2EX Timer 2 External Trigger Input RXDC0_0 MCAN Node 0 Receiver Input P1.1 27/35 PU EXINT3 External Interrupt Input 3 T0_1 Timer 0 Input TDO_1 JTAG Serial Data Output TXD_0 UART Transmit Data Output/ Clock Output TXDC0_0 MCAN Node 0 Transmitter Output P1.2 28/36 PU SCK_0 SSC Clock Input/Output P1.3 29/37 PU MTSR_0 SSC Master Transmit Output/ Slave Receive Input TXDC1_3 MCAN Node 1 Transmitter Output P1.4 30/38 PU MRST_0 SSC Master Receive Input/ Slave Transmit Output EXINT0_1 External Interrupt Input 6 RXDC1_3 MCAN Node 1 Receiver Input P1.5 31/39 PU CCPOS0_1 CCU6 Hall Input 0 EXINT5 External Interrupt Input 5 T1_1 Timer 1 Input EXF2_0 Timer 2 External Flag Output RXDO_0 UART Transmit Data Output Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) Type Reset State Function

General Device Information Data Sheet 12 V0.1, 2006-02 Prelimary P1.6 8/10 PU CCPOS1_1 CCU6 Hall Input 1 T12HR_0 CCU6 Timer 12 Hardware Run Input EXINT6_0 External Interrupt Input 6 RXDC0_2 MCAN Node 0 Receiver Input T21_1 Timer 21 Input P1.7 9/11 PU CCPOS2_1 CCU6 Hall Input 2 T13HR_0 CCU6 Timer 13 Hardware Run Input T2_1 Timer 2 Input TXDC0_2 MCAN Node 0 Transmitter Output P1.5 and P1.6 can be used as a software chip select output for the SSC. Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) Type Reset State Function

General Device Information Data Sheet 13 V0.1, 2006-02 Prelimary P2 I Port 2 Port 2 is an 8-bit general purpose input-only port. It can be used as alternate functions for the digital inputs of the JTAG and CCU6. It is also used as the analog inputs for the ADC. P2.0 14/22 Hi-Z CCPOS0_0 CCU6 Hall Input 0 EXINT1_0 External Interrupt Input 1 T12HR_2 CCU6 Timer 12 Hardware Run Input TCK_1 JTAG Clock Input CC61_3 Input of Capture/Compare channel 1 AN0 Analog Input 0 P2.1 15/23 Hi-Z CCPOS1_0 CCU6 Hall Input 1 EXINT2_0 External Interrupt Input 2 T13HR_2 CCU6 Timer 13 Hardware Run Input TDI_1 JTAG Serial Data Input CC62_3 Input of Capture/Compare channel 2 AN1 Analog Input 1 P2.2 16/24 Hi-Z CCPOS2_0 CCU6 Hall Input 2 CTRAP_1 CCU6 Trap Input CC60_3 Input of Capture/Compare channel 0 AN2 Analog Input 2 P2.3 19/27 Hi-Z AN3 Analog Input 3 P2.4 20/28 Hi-Z AN4 Analog Input 4 P2.5 21/29 Hi-Z AN5 Analog Input 5 P2.6 22/30 Hi-Z AN6 Analog Input 6 P2.7 25/33 Hi-Z AN7 Analog Input 7 Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) Type Reset State Function

General Device Information Data Sheet 14 V0.1, 2006-02 Prelimary P3 I/O Port 3 Port 3 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, UART1, Timer 21 and MCAN. P3.0 35/43 Hi-Z CCPOS1_2 CCU6 Hall Input 1 CC60_0 Input/Output of Capture/ Compare channel 0 RXDO1_1 UART1 Transmit Data Output P3.1 36/44 Hi-Z CCPOS0_2 CCU6 Hall Input 0 CC61_2 Input/Output of Capture/ Compare channel 1 COUT60_0 Output of Capture/Compare channel 0 TXD1_1 UART1 Transmit Data Output/ Clock Output P3.2 37/49 Hi-Z CCPOS2_2 CCU6 Hall Input 2 RXDC1_1 MCAN Node 0 Receiver Input RXD1_1 UART1 Receive Data Input CC61_0 Input/Output of Capture/ Compare channel 1 P3.3 38/50 Hi-Z COUT61_0 Output of Capture/Compare channel 1 TXDC1_1 MCAN Node 1 Transmitter Output P3.4 39/51 Hi-Z CC62_0 Input/Output of Capture/ Compare channel 2 RXDC0_1 MCAN Node 0 Receiver Input T2EX1_0 Timer 21 External Trigger Input P3.5 40/52 Hi-Z COUT62_0 Output of Capture/Compare channel 2 EXF21_0 Timer 21 External Flag Output TXDC0_1 MCAN Node 0 Transmitter Output P3.6 33/41 PD CTRAP_0 CCU6 Trap Input Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) Type Reset State Function

General Device Information Data Sheet 15 V0.1, 2006-02 Prelimary P3.7 34/42 Hi-Z EXINT4 External Interrupt Input 4 COUT63_0 Output of Capture/Compare channel 3 P4 I/O Port 4 Port 4 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, Timer 0, Timer 1, Timer 21 and MCAN. P4.0 45/59 Hi-Z RXDC0_3 MCAN Node 0 Receiver Input CC60_1 Output of Capture/Compare channel 0 P4.1 46/60 Hi-Z TXDC0_3 MCAN Node 0 Transmitter Output COUT60_1 Output of Capture/Compare channel 0 P4.2 –/61 PU EXINT6_1 External Interrupt Input 6 T21_0 Timer 21 Input P4.3 32/40 Hi-Z EXF21_1 Timer 21 External Flag Output COUT63_2 Output of Capture/Compare channel 3 P4.4 –/45 Hi-Z CCPOS0_3 CCU6 Hall Input 0 T0_0 Timer 0 Input CC61_4 Output of Capture/Compare channel 1 P4.5 –/46 Hi-Z CCPOS1_3 CCU6 Hall Input 1 T1_0 Timer 1 Input COUT61_2 Output of Capture/Compare channel 1 P4.6 –/47 Hi-Z CCPOS2_3 CCU6 Hall Input 2 T2_0 Timer 2 Input CC62_2 Output of Capture/Compare channel 2 P4.7 –/48 Hi-Z CTRAP_3 CCU6 Trap Input COUT62_2 Output of Capture/Compare channel 2 Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) Type Reset State Function

General Device Information Data Sheet 16 V0.1, 2006-02 Prelimary P5 I/O Port 5 Port 5 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for UART, UART1 and JTAG. P5.0 –/8 PU EXINT1_1 External Interrupt Input 1 P5.1 –/9 PU EXINT2_1 External Interrupt Input 2 P5.2 –/12 PU RXD_2 UART Receive Data Input P5.3 –/13 PU TXD_2 UART Transmit Data Output/ Clock Output P5.4 –/14 PU RXDO_2 UART Transmit Data Output P5.5 –/15 PU TDO_2 JTAG Serial Data Output TXD1_2 UART1 Transmit Data Output/ Clock Output P5.6 –/19 PU TCK_2 JTAG Clock Input RXDO1_2 UART1 Transmit Data Output P5.7 –/20 PU TDI_2 JTAG Serial Data Input RXD1_2 UART1 Receive Data Input VDDP 7, 17, 43/ 7, 25, 55 –– I/O Port Supply (3.3 or 5.0 V) VSSP 18, 42/26, 54 – – I/O Port Ground VDDC 6/6 – – Core Supply Monitor (2.5 V) VSSC 5/5 – – Core Supply Ground VAREF 24/32 – – ADC Reference Voltage VAGND 23/31 – – ADC Reference Ground XTAL1 4/4 I Hi-Z External Oscillator Input (backup for on-chip OSC, normally NC) XTAL2 3/3 O Hi-Z External Oscillator Output (backup for on-chip OSC, normally NC) TMS 10/16 I PD Test Mode Select RESET 41/53 I PU Reset Input MBC 44/58 I PU Monitor & BootStrap Loader Control NC –/21, 59, 60 – – No Connection Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (TQFP-48/64) Type Reset State Function

Data Sheet 17 V0.1, 2006-02 Prelimary

3 Functional Description

3.1 Processor Architecture

The XC886/888 is based on a high-performanc e 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC886/888 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. Access to the Flash memory, however, requires an additional wait state (one machine cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. The XC886/888 CPU provides a range of debugging features, including basic stop/start, single-step execution, break point support and read/write access to the data memory, program memory and SFRs. Figure 6 shows the CPU functional blocks.

Data Sheet 18 V0.1, 2006-02 Prelimary Figure 6 CPU Block Diagram

3.2 Memory Organization

The XC886/888 CPU operates in the following five address spaces:

• 12 Kbytes of Boot ROM program memory
• 256 bytes of internal RAM data memory
• 1.5 Kbytes of XRAM memory (XRAM can be read/written as program memory or external data memory)
• a 128-byte Special Function Register area
• 24/32 Kbytes of Flash program memory (Flash devices); or 24/32 Kbytes of ROM program memory, with additional 4 Kbytes of Flash (ROM devices) Figure 7 illustrates the memory address spaces of the 32-Kbyte Flash devices. For the 24-Kbyte Flash devices, the shaded banks are not available. Register Interface ALU UART Core SFRs 16-bit Registers & Memory Interface Opcode Decoder State Machine & Power Saving Interrupt Controller Multiplier / Divider Opcode & Immediate Registers Timer 0 / Timer 1 Internal Data Memory External SFRs External Data Memory Program Memory fCCLK Memory Wait Reset Legacy External Interrupts (IEN0, IEN1) External Interrupts Non-Maskable Interrupt

Data Sheet 19 V0.1, 2006-02 Prelimary Figure 7 Memory Map of XC886/888 Flash Device 0000H 2000H 4000H 6000H F000H C000H F600H FFFFH 7000H 8000H P-Flash Banks 2 and 3 2 x 4 Kbytes Boot ROM

12 Kbytes

1.5 Kbytes

Program Space External Data Space Internal Data Space Internal RAM XRAM

4 Kbytes

2 x 4 Kbytes 1) In 24-Kbyte Flash devices, the upper 2- Kbyte of Banks 4 and 5 are not available.

Data Sheet 20 V0.1, 2006-02 Prelimary

3.2.1 Memory Protection Strategy

The XC886/888 memory protection strategy includes:

• Read-out protection: The user is able to protect the contents in the Flash (for Flash devices) and ROM (for ROM devices) memory from being read
• Flash program and erase prot ection (for Flash devices only) Flash memory protection modes are available only for Flash devices:
• Mode 0: Only the P-Flash is prot ected; the D-Flash is unprotected
• Mode 1: Both the P-Flash and D-Flash are protected The selection of each protection mode and the restrictions imposed are summarized in Table 4. BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed password must be provided by the user. A password match triggers an automatic erase of the protected P-Flash and D-Flash contents, including the programmed password. The Flash protection is then disabled upon the next reset. Although no protection scheme can be considered infallible, the XC886/888 memory protection strategy provides a very hi gh level of protection for a general purpose microcontroller. Note: If ROM read-out protection is enabled, only read instructions in the ROM memory can target the ROM contents. Table 4 Flash Protection Modes Mode 01 Activation Program a valid password via BSL mode 6 Selection MSB of password = 0 MSB of password = 1 P-Flash contents can be read by Read instructions in the P-Flash Read instructions in the P-Flash or D-Flash P-Flash program and erase Not possible Not possible D-Flash contents can be read by Read instructions in any program memory Read instructions in the P-Flash or D-Flash D-Flash program Possible Not possible D-Flash erase Possible, on the condition that bit DFLASHEN in register MISC_CON is set to 1 prior to each erase operation Not possible

Data Sheet 21 V0.1, 2006-02 Prelimary

3.2.2 Special Function Register

The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80H to FFH. All registers, except the program counter, reside in the SFR area. The SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than the total number of registers required, address extension mechanisms ar e required to increase the number of addressable SFRs. The address extension mechanisms include:

• Mapping
• Paging

3.2.2.1 Address Extension by Mapping

Address extension is perfo rmed at the system level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80 H to FFH, bringing the number of addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, bu t is derived from bit RMAP in the system control register SYSCON0 at address 8F H. To access SFRs in the mapped area, bit RMAP in SFR SYSCON0 must be set. Alternat ively, the SFRs in the st andard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 8. SYSCON0 System Control Register 0 Reset Value: 00H 7654 32 10

0 IMODE 0 RMAP

The functions of the shaded bits are not described here Field Bits Type Description RMAP 0r w Special Function Register Map Control

0 The access to the standard SFR area is

enabled.

1 The access to the mapped SFR area is

enabled. 0 [7:5], [3:1] r Reserved Returns 0 if read; should be written with 0.

Data Sheet 22 V0.1, 2006-02 Prelimary Note: The RMAP bit must be cleared/set by AN L or ORL instructions. The rest bits of SYSCON0 should not be modified. As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Th us, before standard/ma pped registers are accessed, bit RMAP must be cleared/set, respectively, by software. Figure 8 Address Extension by Mapping Module 1 SFRs …... SYSCON0.RMAP SFR Data (to/from CPU) rw Standard Area (RMAP = 0) …... 80H FFH 80H FFH Direct Internal Data Memory Address Mapped Area (RMAP = 1) Module 2 SFRs Module n SFRs Module (n+1) SFRs Module (n+2) SFRs Module m SFRs

Data Sheet 23 V0.1, 2006-02 Prelimary

3.2.2.2 Address Extension by Paging

Address extension is further performed at the module level by paging. With the address extension by mapping, the XC886/888 has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bi t field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SF Rs per page, depending on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 9. Figure 9 Address Extension by Paging SFR0 SFR1 SFRx …... PAGE 0 SFR0 SFR1 SFRy …... PAGE 1 …... SFR0 SFR1 SFRz …... PAGE q MOD_PAGE.PAGE SFR Address (from CPU) SFR Data (to/from CPU) rw Module

Data Sheet 24 V0.1, 2006-02 Prelimary In order to access a register located in a page different from the actual one, the current page must be left. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed. If an interrupt routine is initiated betw een the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and finally, the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can:

• Save the contents of PAGE in STx befo re overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or
• Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt ro utine to restore the previous page setting before the interrupt occurred) Figure 10 Storage Elements for Paging With this mechanism, a certain number of in terrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write oper ations makes the system simp ler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The XC886/888 supports local address extension for:
• Parallel Ports
• Analog-to-Digital Converter (ADC)
• Capture/Compare Unit 6 (CCU6)
• System Control Registers PAGE ST0 ST1 ST2 ST3 value update from CPU STNR

Data Sheet 25 V0.1, 2006-02 Prelimary The page register has the following definition: MOD_PAGE Page Register for module MOD Reset Value: 00H 7654 32 10 OP STNR 0 PAGE ww r r w Field Bits Type Description PAGE [2:0] rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. STNR [5:4] w Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10 the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11 the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 ST0 is selected. 01 ST1 is selected. 10 ST2 is selected. 11 ST3 is selected.

Data Sheet 26 V0.1, 2006-02 Prelimary OP [7:6] w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written.

10 New page programming with automatic page

saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. 0 3r Reserved Returns 0 if read; should be written with 0. Field Bits Type Description

Data Sheet 27 V0.1, 2006-02 Prelimary

3.2.3 Bit Protection Scheme

The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit field PASS closes access to writing of all protected bits. Note that access is opened for maximum 32 CCLKs if the “close access” password is not written. If “open access” password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protected bits include the N- and K-Divider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the power-down and slow-down enable bits, PD and SD. PASSWD Password Register Reset Value: 07 H 76543210 PASS PROTECT _S MODE wh rh rw Field Bits Type Description MODE [1:0] rw Bit Protection Scheme Control bits

00 Scheme Disabled

11 Scheme Enabled (default)

Others: Scheme Enabled These two bits cannot be written directly. To change the value between 11 B and 00B, the bit field PASS must be written with 11000B; only then, will the MODE[1:0] be registered. PROTECT_S 2r h Bit Protection Signal Status bit This bit shows the status of the protection. 0 Software is able to writ e to all protected bits.

1 Software is unable to write to any protected

bits. PASS [7:3] wh Password bits The Bit Protection Scheme only recognizes three patterns. 11000 B Enables writing of the bit field MODE. 10011B Opens access to writing of all protected bits. 10101B Closes access to writing of all protected bits.

Data Sheet 28 V0.1, 2006-02 Prelimary

3.2.4 XC886/888 Register Overview

The SFRs of the XC886/888 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Table 5 to Table 18, with the addresses of the bitaddressable SFRs appearing in bold typeface. The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = 0 or 1). Table 5 CPU Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 or 1 81H SP Reset: 07 H Stack Pointer Register Bit Field SP Type rw 82H DPL Reset: 00 H Data Pointer Register Low Bit Field DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0 Type rw rw rw rw rw rw rw rw 83H DPH Reset: 00 H Data Pointer Register High Bit Field DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0 Type rw rw rw rw rw rw rw rw 87H PCON Reset: 00 H Power Control Register Bit Field SMOD 0 GF1 GF0 0 IDLE Type rw r rw rw r rw 88H TCON Reset: 00 H Timer Control Register Bit Field TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Type rwh rw rwh rw rwh rw rwh rw 89H TMOD Reset: 00 H Timer Mode Register Bit Field GATE1 0 T1M GATE0 0 T0M Type rw r rw rw r rw 8AH TL0 Reset: 00 H Timer 0 Register Low Bit Field VAL Type rwh 8BH TL1 Reset: 00 H Timer 1 Register Low Bit Field VAL Type rwh 8CH TH0 Reset: 00 H Timer 0 Register High Bit Field VAL Type rwh 8DH TH1 Reset: 00 H Timer 1 Register High Bit Field VAL Type rwh 98H SCON Reset: 00 H Serial Channel Control Register Bit Field SM0 SM1 SM2 REN TB8 RB8 TI RI Type rw rw rw rw rw rwh rwh rwh 99H SBUF Reset: 00 H Serial Data Buffer Register Bit Field VAL Type rwh A2H EO Reset: 00 H Extended Operation Register Bit Field 0 TRAP_ EN

0 DPSEL

A8H IEN0 Reset: 00 H Interrupt Enable Register 0 Bit Field EA 0 ET2 ES ET1 EX1 ET0 EX0 T y p e r w r r wr wr wr wr wr w B8H IP Reset: 00 H Interrupt Priority Register Bit Field 0 PT2 PS PT1 PX1 PT0 PX0 T y p e r r wr wr wr wr wr w B9H IPH Reset: 00 H Interrupt Priority Register High Bit Field 0 PT2H PSH PT1H PX1H PT0H PX0H T y p e r r wr wr wr wr wr w D0H PSW Reset: 00 H Program Status Word Register Bit Field CY AC F0 RS1 RS0 OV F1 P Type rwh rwh rw rw rw rwh rw rh E0H ACC Reset: 00 H Accumulator Register Bit Field ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0 Type rw rw rw rw rw rw rw rw E8H IEN1 Reset: 00 H Interrupt Enable Register 1 Bit Field ECCIP ECCIP ECCIP ECCIP EXM EX2 ESSC EADC Type rw rw rw rw rw rw rw rw

Data Sheet 29 V0.1, 2006-02 Prelimary The MDU SFRs can be accessed in the mapped memory area (RMAP = 1). F0H B Reset: 00 H B Register Bit Field B7 B6 B5 B4 B3 B2 B1 B0 Type rw rw rw rw rw rw rw rw F8H IP1 Reset: 00 H Interrupt Priority Register 1 Bit Field PCCIP PCCIP PCCIP PCCIP PXM PX2 PSSC PADC Type rw rw rw rw rw rw rw rw F9H IPH1 Reset: 00 H Interrupt Priority Register 1 High Bit Field PCCIP PCCIP PCCIP PCCIP PXMH PX2H PSSCH PADC H Type rw rw rw rw rw rw rw rw Table 6 MDU Register Overview A d d r R e g i s t e r N a m e B i t 7 6543210 RMAP = 1 B0H MDUSTAT Reset: 00 H MDU Status Register Bit Field 0 BSY IERR IRDY Type r rh rwh rwh B1H MDUCON Reset: 00 H MDU Control Register Bit Field IE IR RSEL START OPCODE Type rw rw rw rwh rw B2H MD0 Reset: 00 H MDU Data Register 0 Bit Field DATA Type rw MR0 Reset: 00 H MDU Data Register 0 Bit Field DATA Type rh B3H MD1 Reset: 00 H MDU Data Register 1 Bit Field DATA Type rw MR1 Reset: 00 H MDU Data Register 1 Bit Field DATA Type rh B4H MD2 Reset: 00 H MDU Data Register 2 Bit Field DATA Type rw MR2 Reset: 00 H MDU Data Register 2 Bit Field DATA Type rh B5H MD3 Reset: 00 H MDU Data Register 3 Bit Field DATA Type rw MR3 Reset: 00 H MDU Data Register 3 Bit Field DATA Type rh B6H MD4 Reset: 00 H MDU Data Register 4 Bit Field DATA Multiplication/Division Type rw Shift/Normalization 0 SLR SCTR rw rw rw MR4 Reset: 00 H MDU Data Register 4 Bit Field DATA Multiplication/Division Type rh Shift/Normalization 0 SCTR rh rh B7H MD5 Reset: 00 H MDU Data Register 5 Bit Field DATA Type rw MR5 Reset: 00 H MDU Data Register 5 Bit Field DATA Type rh Table 5 CPU Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 30 V0.1, 2006-02 Prelimary The CORDIC SFRs can be accessed in the mapped memory area (RMAP = 1). The system control SFRs can be accessed in the standard memory area (RMAP = 0). Table 7 CORDIC Regi ster Overview A d d r R e g i s t e r N a m e B i t 7 6543210 RMAP = 1 9AH CD_CORDXL Reset: 00 H CORDIC X Data Low Byte Bit Field DATAL Type rw 9BH CD_CORDXH Reset: 00 H CORDIC X Data High Byte Bit Field DATAH Type rw 9CH CD_CORDYL Reset: 00 H CORDIC Y Data Low Byte Bit Field DATAL Type rw 9DH CD_CORDYH Reset: 00 H CORDIC Y Data High Byte Bit Field DATAH Type rw 9EH CD_CORDZL Reset: 00 H CORDIC Z Data Low Byte Bit Field DATAL Type rw 9FH CD_CORDZH Reset: 00 H CORDIC Z Data High Byte Bit Field DATAH Type rw A0H CD_STATC Reset: 00 H CORDIC Status and Data Control Register Bit Field KEEPZ KEEPY KEEPX DMAP INT_E N EOC ERRO R BSY Type rw rw rw rw rw rwh rh rh A1H CD_CON Reset: 00 H CORDIC Control Register Bit Field MPS X_USI GN ST_MO DE ROTVE C MODE ST Type rw w rw rw rw rwh Table 8 System Control Register Overview A d d r R e g i s t e r N a m e B i t 7 6543210 RMAP = 0 or 1 8FH SYSCON0 Reset: 00 H System Control Register 0 Bit Field 0 IMODE 0 RMAP Type r rw r rw RMAP = 0 BF H SCU_PAGE Reset: 00 H Page Register Bit Field OP STNR 0 PAGE Type w w r rw RMAP = 0, PAGE 0 B3H MODPISEL Reset: 00 H Peripheral Input Select Register Bit Field 0 URRIS H JTAGT DIS JTAGT CKS EXINT 2IS EXINT 1IS EXINT 0IS URRIS Type r rw rw rw rw rw rw rw B4H IRCON0 Reset: 00 H Interrupt Request Register 0 Bit Field 0 EXINT EXINT EXINT EXINT EXINT EXINT EXINT Type r rwh rwh rwh rwh rwh rwh rwh B5H IRCON1 Reset: 00 H Interrupt Request Register 1 Bit Field 0 CANS RC2 CANS RC1 ADCS RC1 ADCS RC0 RIR TIR EIR Type r rwh rwh rwh rwh rwh rwh rwh B6H IRCON2 Reset: 00 H Interrupt Request Register 2 Bit Field 0 CANS RC3

0 CANS

B7H EXICON0 Reset: F0 H External Interrupt Control Register 0 Bit Field EXINT3 EXINT2 EXINT1 EXINT0 Type rw rw rw rw BAH EXICON1 Reset: 3F H External Interrupt Control Register 1 Bit Field 0 EXINT6 EXINT5 EXINT4 Type r rw rw rw

Data Sheet 31 V0.1, 2006-02 Prelimary BBH NMICON Reset: 00 H NMI Control Register Bit Field 0 NMI ECC NMI VDDP NMI VDD NMI OCDS NMI FLASH NMI PLL NMI WDT Type r rw rw rw rw rw rw rw BCH NMISR Reset: 00 H NMI Status Register Bit Field 0 FNMI ECC FNMI VDDP FNMI VDD FNMI OCDS FNMI FLASH FNMI PLL FNMI WDT Type r rwh rwh rwh rwh rwh rwh rwh BDH BCON Reset: 00 H Baud Rate Control Register Bit Field BGSEL 0 BRDIS BRPRE R Type rw r rw rw rw BEH BG Reset: 00 H Baud Rate Timer/Reload Register Bit Field BR_VALUE Type rwh E9H FDCON Reset: 00 H Fractional Divider Control Register Bit Field BGS SYNEN ERRSY N EOFSY N BRK NDOV FDM FDEN Type rw rw rwh rwh rwh rwh rw rw EAH FDSTEP Reset: 00 H Fractional Divider Reload Register Bit Field STEP Type rw EBH FDRES Reset: 00 H Fractional Divider Result Register Bit Field RESULT Type rh RMAP = 0, PAGE 1 H ID Reset: 09 H Identity Register Bit Field PRODID VERID Type r r B4H PMCON0 Reset: 00 H Power Mode Control Register 0 Bit Field 0 WDT RST WKRS WK SEL SD PD WS Type r rwh rwh rw rw rwh rw B5H PMCON1 Reset: 00 H Power Mode Control Register 1 Bit Field 0 CDC_D IS CAN_D IS MDU_ DIS T2_DIS CCU _DIS SSC _DIS ADC _DIS Type r rw rw rw rw rw rw rw B6H OSC_CON Reset: 08 H OSC Control Register Bit Field 0 OSC PD XPD OSC SS ORDR ES OSCR Type r rw rw rw rwh rh B7H PLL_CON Reset: 90 H PLL Control Register Bit Field NDIV VCOB YP OSC DISC RESLD LOCK Type rw rw rw rwh rh BAH CMCON Reset: 10 H Clock Control Register Bit Field VCO SEL KDIV 0 FCCFG CLKREL Type rw rw r rw rw BBH PASSWD Reset: 07 H Password Register Bit Field PASS PROTE CT_S MODE Type wh rh rw BCH FEAL Reset: 00 H Flash Error Address Register Low Bit Field ECCERRADDR Type rh BDH FEAH Reset: 00 H Flash Error Address Register High Bit Field ECCERRADDR Type rh BEH COCON Reset: 00 H Clock Output Control Register Bit Field 0 TLEN COUT S COREL Type r rw rw rw E9H MISC_CON Reset: 00 H Miscellaneous Control Register Bit Field 0 DFLAS HEN Type r rwh RMAP = 0, PAGE 3 H XADDRH Reset: F0 H On-chip XRAM Address Higher Order Bit Field ADDRH Type rw Table 8 System Control Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 7 6543210

Data Sheet 32 V0.1, 2006-02 Prelimary The WDT SFRs can be accessed in the mapped memory area (RMAP = 1). The Port SFRs can be accessed in the standard memory area (RMAP = 0). B4H IRCON3 Reset: 00 H Interrupt Request Register 3 Bit Field 0 CANS RC5 CCU6S B5H IRCON4 Reset: 00 H Interrupt Request Register 4 Bit Field 0 CANS RC7 CCU6S B7H MODPISEL1 Reset: 00 H Peripheral Input Select Register 1 Bit Field EXINT 6IS

0 UR1RIS T21EXI

S JTAGT DIS1 JTAGT CKS1 Type rw r rw rw rw rw BAH MODPISEL2 Reset: 00 H Peripheral Input Select Register 2 Bit Field 0 T21IS T2IS T1IS T0IS Type r rw rw rw rw BBH PMCON2 Reset: 00 H Power Mode Control Register 2 Bit Field 0 UART1 _DIS T21 _DIS Type r rw rw BDH MODSUSP Reset: 00 H Module Suspend Control Register Bit Field 0 T21SU SP T2SUS P T13SU SP T12SU SP WDTS USP Type r rw rw rw rw rw Table 9 WDT Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 1 BBH WDTCON Reset: 00 H Watchdog Timer Control Register Bit Field 0 WINB EN WDT PR

0 WDT

BCH WDTREL Reset: 00 H Watchdog Timer Reload Register Bit Field WDTREL Type rw BDH WDTWINB Reset: 00 H Watchdog Window-Boundary Count Register Bit Field WDTWINB Type rw BEH WDTL Reset: 00 H Watchdog Timer Register Low Bit Field WDT[7:0] Type rh BFH WDTH Reset: 00 H Watchdog Timer Register High Bit Field WDT[15:8] Type rh Table 10 Port Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 B2H PORT_PAGE Reset: 00 H Page Register for PORT Bit Field OP STNR 0 PAGE Type w w r rw RMAP = 0, Page 0 H P0_DATA Reset: 00 H P0 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 86H P0_DIR Reset: 00 H P0 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_DATA Reset: 00 H P1 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw Table 8 System Control Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 7 6543210

Data Sheet 33 V0.1, 2006-02 Prelimary 91H P1_DIR Reset: 00 H P1 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_DATA Reset: 00 H P5 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 93H P5_DIR Reset: 00 H P5 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw A0H P2_DATA Reset: 00 H P2 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw A1H P2_DIR Reset: 00 H P2 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_DATA Reset: 00 H P3 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B1H P3_DIR Reset: 00 H P3 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C8H P4_DATA Reset: 00 H P4 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C9H P4_DIR Reset: 00 H P4 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw RMAP = 0, Page 1 H P0_PUDSEL Reset: FF H P0 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 86H P0_PUDEN Reset: C4 H P0 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_PUDSEL Reset: FF H P1 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 91H P1_PUDEN Reset: FF H P1 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_PUDSEL Reset: FF H P5 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 93H P5_PUDEN Reset: FF H P5 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw A0H P2_PUDSEL Reset: FF H P2 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw A1H P2_PUDEN Reset: 00 H P2 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_PUDSEL Reset: BF H P3 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B1H P3_PUDEN Reset: 40 H P3 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C8H P4_PUDSEL Reset: FF H P4 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C9H P4_PUDEN Reset: 04 H P4 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw RMAP = 0, Page 2 H P0_ALTSEL0 Reset: 00 H P0 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 86H P0_ALTSEL1 Reset: 00 H P0 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_ALTSEL0 Reset: 00 H P1 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw Table 10 Port Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 34 V0.1, 2006-02 Prelimary The ADC SFRs can be accessed in the standard memory area (RMAP = 0). 91H P1_ALTSEL1 Reset: 00 H P1 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_ALTSEL0 Reset: 00 H P5 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 93H P5_ALTSEL1 Reset: 00 H P5 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_ALTSEL0 Reset: 00 H P3 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B1H P3_ALTSEL1 Reset: 00 H P3 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C8H P4_ALTSEL0 Reset: 00 H P4 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C9H P4_ALTSEL1 Reset: 00 H P4 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw RMAP = 0, Page 3 H P0_OD Reset: 00 H P0 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_OD Reset: 00 H P1 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_OD Reset: 00 H P5 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_OD Reset: 00 H P3 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C8H P4_OD Reset: 00 H P4 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw Table 11 ADC Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 D1H ADC_PAGE Reset: 00 H Page Register for ADC Bit Field OP STNR 0 PAGE Type w w r rw RMAP = 0, Page 0 CAH ADC_GLOBCTR Reset: 30 H Global Control Register Bit Field ANON DW CTC 0 Type rw rw rw r CBH ADC_GLOBSTR Reset: 00 H Global Status Register Bit Field 0 CHNR 0 SAM PLE BUSY Type r rh r rh rh CCH ADC_PRAR Reset: 00 H Priority and Arbitration Register Bit Field ASEN1 ASEN0 0 ARBM CSM1 PRIO1 CSM0 PRIO0 Type rw rw r rw rw rw rw rw CDH ADC_LCBR Reset: B7 H Limit Check Boundary Register Bit Field BOUND1 BOUND0 Type rw rw CEH ADC_INPCR0 Reset: 00 H Input Class Register 0 Bit Field STC Type rw CFH ADC_ETRCR Reset: 00 H External Trigger Control Register Bit Field SYNEN SYNEN ETRSEL1 ETRSEL0 Type rw rw rw rw RMAP = 0, Page 1 Table 10 Port Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 35 V0.1, 2006-02 Prelimary CAH ADC_CHCTR0 Reset: 00 H Channel Control Register 0 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CBH ADC_CHCTR1 Reset: 00 H Channel Control Register 1 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CCH ADC_CHCTR2 Reset: 00 H Channel Control Register 2 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CDH ADC_CHCTR3 Reset: 00 H Channel Control Register 3 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CEH ADC_CHCTR4 Reset: 00 H Channel Control Register 4 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CFH ADC_CHCTR5 Reset: 00 H Channel Control Register 5 Bit Field 0 LCC 0 RESRSEL Type r rw r rw D2H ADC_CHCTR6 Reset: 00 H Channel Control Register 6 Bit Field 0 LCC 0 RESRSEL Type r rw r rw D3H ADC_CHCTR7 Reset: 00 H Channel Control Register 7 Bit Field 0 LCC 0 RESRSEL Type r rw r rw RMAP = 0, Page 2 CAH ADC_RESR0L Reset: 00 H Result Register 0 Low Bit Field RESULT[1:0] 0 VF DRC CHNR Type rh r rh rh rh CBH ADC_RESR0H Reset: 00 H Result Register 0 High Bit Field RESULT[9:2] Type rh CCH ADC_RESR1L Reset: 00 H Result Register 1 Low Bit Field RESULT[1:0] 0 VF DRC CHNR Type rh r rh rh rh CDH ADC_RESR1H Reset: 00 H Result Register 1 High Bit Field RESULT[9:2] Type rh CEH ADC_RESR2L Reset: 00 H Result Register 2 Low Bit Field RESULT[1:0] 0 VF DRC CHNR Type rh r rh rh rh CFH ADC_RESR2H Reset: 00 H Result Register 2 High Bit Field RESULT[9:2] Type rh D2H ADC_RESR3L Reset: 00 H Result Register 3 Low Bit Field RESULT[1:0] 0 VF DRC CHNR Type rh r rh rh rh D3H ADC_RESR3H Reset: 00 H Result Register 3 High Bit Field RESULT[9:2] Type rh RMAP = 0, Page 3 CAH ADC_RESRA0L Reset: 00 H Result Register 0, View A Low Bit Field RESULT[2:0] VF DRC CHNR Type rh rh rh rh CBH ADC_RESRA0H Reset: 00 H Result Register 0, View A High Bit Field RESULT[10:3] Type rh CCH ADC_RESRA1L Reset: 00 H Result Register 1, View A Low Bit Field RESULT[2:0] VF DRC CHNR Type rh rh rh rh CDH ADC_RESRA1H Reset: 00 H Result Register 1, View A High Bit Field RESULT[10:3] Type rh CEH ADC_RESRA2L Reset: 00 H Result Register 2, View A Low Bit Field RESULT[2:0] VF DRC CHNR Type rh rh rh rh CFH ADC_RESRA2H Reset: 00 H Result Register 2, View A High Bit Field RESULT[10:3] Type rh D2H ADC_RESRA3L Reset: 00 H Result Register 3, View A Low Bit Field RESULT[2:0] VF DRC CHNR Type rh rh rh rh D3H ADC_RESRA3H Reset: 00 H Result Register 3, View A High Bit Field RESULT[10:3] Type rh Table 11 ADC Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 36 V0.1, 2006-02 Prelimary RMAP = 0, Page 4 CAH ADC_RCR0 Reset: 00 H Result Control Register 0 Bit Field VFCTR WFR FEN IEN 0 DRCT R Type rw rw rw rw r rw CBH ADC_RCR1 Reset: 00 H Result Control Register 1 Bit Field VFCTR WFR FEN IEN 0 DRCT R Type rw rw rw rw r rw CCH ADC_RCR2 Reset: 00 H Result Control Register 2 Bit Field VFCTR WFR FEN IEN 0 DRCT R Type rw rw rw rw r rw CDH ADC_RCR3 Reset: 00 H Result Control Register 3 Bit Field VFCTR WFR FEN IEN 0 DRCT R Type rw rw rw rw r rw CEH ADC_VFCR Reset: 00 H Valid Flag Clear Register Bit Field 0 VFC3 VFC2 VFC1 VFC0 Type r w w w w RMAP = 0, Page 5 CAH ADC_CHINFR Reset: 00 H Channel Interrupt Flag Register Bit Field CHINF CHINF CHINF CHINF CHINF CHINF CHINF CHINF Type rh rh rh rh rh rh rh rh CBH ADC_CHINCR Reset: 00 H Channel Interrupt Clear Register Bit Field CHINC CHINC CHINC CHINC CHINC CHINC CHINC CHINC T y p e wwww w w w w CCH ADC_CHINSR Reset: 00 H Channel Interrupt Set Register Bit Field CHINS CHINS CHINS CHINS CHINS CHINS CHINS CHINS T y p e wwww w w w w CDH ADC_CHINPR Reset: 00 H Channel Interrupt Node Pointer Register Bit Field CHINP CHINP CHINP CHINP CHINP CHINP CHINP CHINP Type rw rw rw rw rw rw rw rw CEH ADC_EVINFR Reset: 00 H Event Interrupt Flag Register Bit Field EVINF EVINF EVINF EVINF

0 EVINF

CFH ADC_EVINCR Reset: 00 H Event Interrupt Clear Flag Register Bit Field EVINC EVINC EVINC EVINC

0 EVINC

D2H ADC_EVINSR Reset: 00 H Event Interrupt Set Flag Register Bit Field EVINS EVINS EVINS EVINS

0 EVINS

D3H ADC_EVINPR Reset: 00 H Event Interrupt Node Pointer Register Bit Field EVINP EVINP EVINP EVINP

0 EVINP

RMAP = 0, Page 6 CAH ADC_CRCR1 Reset: 00 H Conversion Request Control Register 1 Bit Field CH7 CH6 CH5 CH4 0 T y p e r w hr w hr w hr w h r CBH ADC_CRPR1 Reset: 00 H Conversion Request Pending Register 1 Bit Field CHP7 CHP6 CHP5 CHP4 0 T y p e r w hr w hr w hr w h r CCH ADC_CRMR1 Reset: 00 H Conversion Request Mode Register 1 Bit Field Rsv LDEV CLR PND SCAN ENSI ENTR ENGT Type r w w rw rw rw rw CDH ADC_QMR0 Reset: 00 H Queue Mode Register 0 Bit Field CEV TREV FLUSH CLRV 0 ENTR ENGT T y p e wwww r rw rw Table 11 ADC Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 37 V0.1, 2006-02 Prelimary The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0). The Timer 21 SFRs can be accessed in the standard memory area (RMAP = 1). CEH ADC_QSR0 Reset: 20 H Queue Status Register 0 Bit Field Rsv 0 EMPTY EV 0 FILL Type r r rh rh r rh CFH ADC_Q0R0 Reset: 00 H Queue 0 Register 0 Bit Field EXTR ENSI RF V 0 REQCHNR Type rh rh rh rh r rh D2H ADC_QBUR0 Reset: 00 H Queue Backup Register 0 Bit Field EXTR ENSI RF V 0 REQCHNR Type rh rh rh rh r rh D2H ADC_QINR0 Reset: 00 H Queue Input Register 0 Bit Field EXTR ENSI RF 0 REQCHNR T y p e www r w Table 12 Timer 2 Register Overview A d d r R e g i s t e r N a m e B i t 76543210 C0H T2_T2CON Reset: 00 H Timer 2 Control Register Bit Field TF2 EXF2 0 EXEN2 TR2 0 CP/ RL2 Type rwh rwh r rw rwh r rw C1H T2_T2MOD Reset: 00 H Timer 2 Mode Register Bit Field T2 REGS RHEN EDGE SEL PREN T2PRE DCEN Type rw rw rw rw rw rw C2H T2_RC2L Reset: 00 H Timer 2 Reload/Capture Register Low Bit Field RC2 Type rwh C3H T2_RC2H Reset: 00 H Timer 2 Reload/Capture Register High Bit Field RC2 Type rwh C4H T2_T2L Reset: 00 H Timer 2 Register Low Bit Field THL2 Type rwh C5H T2_T2H Reset: 00 H Timer 2 Register High Bit Field THL2 Type rwh Table 13 T21 Register Overview A d d r R e g i s t e r N a m e B i t 7 6543210 RMAP = 1 C0H T2CON Reset: 00 H Timer 2 Control Register Bit Field TF2 EXF2 0 0 EXEN2 TR2 C/T2 CP/ RL2 Type rwh rwh r r rw rwh rw rw C1H T2MOD Reset: 00 H Timer 2 Mode Register Bit Field T2 REGS RHEN EDGE SEL PREN T2PRE DCEN Type rw rw rw rw rw rw C2H RC2L Reset: 00 H Timer 2 Reload/Capture Register Low Bit Field RC2 Type rwh C3H RC2H Reset: 00 H Timer 2 Reload/Capture Register High Bit Field RC2 Type rwh C4H T2L Reset: 00 H Timer 2 Register Low Bit Field THL2 Type rwh C5H T2H Reset: 00 H Timer 2 Register High Bit Field THL2 Type rwh Table 11 ADC Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 38 V0.1, 2006-02 Prelimary The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). Table 14 CCU6 Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 A3H CCU6_PAGE Reset: 00 H Page Register for CCU6 Bit Field OP STNR 0 PAGE Type w w r rw RMAP = 0, Page 0 9AH CCU6_CC63SRL Reset: 00 H Capture/Compare Shadow Register for Channel CC63 Low Bit Field CC63SL Type rw 9BH CCU6_CC63SRH Reset: 00 H Capture/Compare Shadow Register for Channel CC63 High Bit Field CC63SH Type rw 9CH CCU6_TCTR4L Reset: 00 H Timer Control Register 4 Low Bit Field T12 STD T12 STR

0 DTRES T12

9DH CCU6_TCTR4H Reset: 00 H Timer Control Register 4 High Bit Field T13 STD T13 STR

0 T13

9EH CCU6_MCMOUTSL Reset: 00 H Multi-Channel Mode Output Shadow Register Low Bit Field STRM CM

0 MCMPS

9FH CCU6_MCMOUTSH Reset: 00 H Multi-Channel Mode Output Shadow Register High Bit Field STRHP 0 CURHS EXPHS Type w r rw rw A4H CCU6_ISRL Reset: 00 H Capture/Compare Interrupt Status Reset Register Low Bit Field RT12P M RT12O M RCC62 F RCC62 R RCC61 F RCC61 R RCC60 F RCC60 R T y p e wwww w w w w A5H CCU6_ISRH Reset: 00 H Capture/Compare Interrupt Status Reset Register High Bit Field RSTR RIDLE RWHE RCHE 0 RTRPF RT13 PM RT13 CM T y p e wwww r w w w A6H CCU6_CMPMODIFL Reset: 00 H Compare State Modification Register Low Bit Field 0 MCC63 S

0 MCC62

S MCC61 S MCC60 S Type r w r w w w A7H CCU6_CMPMODIFH Reset: 00 H Compare State Modification Register High Bit Field 0 MCC63 R R MCC61 R MCC60 R Type r w r w w w FAH CCU6_CC60SRL Reset: 00 H Capture/Compare Shadow Register for Channel CC60 Low Bit Field CC60SL Type rwh FBH CCU6_CC60SRH Reset: 00 H Capture/Compare Shadow Register for Channel CC60 High Bit Field CC60SH Type rwh FCH CCU6_CC61SRL Reset: 00 H Capture/Compare Shadow Register for Channel CC61 Low Bit Field CC61SL Type rwh FDH CCU6_CC61SRH Reset: 00 H Capture/Compare Shadow Register for Channel CC61 High Bit Field CC61SH Type rwh FEH CCU6_CC62SRL Reset: 00 H Capture/Compare Shadow Register for Channel CC62 Low Bit Field CC62SL Type rwh FFH CCU6_CC62SRH Reset: 00 H Capture/Compare Shadow Register for Channel CC62 High Bit Field CC62SH Type rwh

Data Sheet 39 V0.1, 2006-02 Prelimary RMAP = 0, Page 1 9AH CCU6_CC63RL Reset: 00 H Capture/Compare Register for Channel CC63 Low Bit Field CC63VL Type rh 9BH CCU6_CC63RH Reset: 00 H Capture/Compare Register for Channel CC63 High Bit Field CC63VH Type rh 9CH CCU6_T12PRL Reset: 00 H Timer T12 Period Register Low Bit Field T12PVL Type rwh 9DH CCU6_T12PRH Reset: 00 H Timer T12 Period Register High Bit Field T12PVH Type rwh 9EH CCU6_T13PRL Reset: 00 H Timer T13 Period Register Low Bit Field T13PVL Type rwh 9FH CCU6_T13PRH Reset: 00 H Timer T13 Period Register High Bit Field T13PVH Type rwh A4H CCU6_T12DTCL Reset: 00 H Dead-Time Control Register for Timer T12 Low Bit Field DTM Type rw A5H CCU6_T12DTCH Reset: 00 H Dead-Time Control Register for Timer T12 High Bit Field 0 DTR2 DTR1 DTR0 0 DTE2 DTE1 DTE0 T y p e r r hr hr h r rw rw rw A6H CCU6_TCTR0L Reset: 00 H Timer Control Register 0 Low Bit Field CTM CDIR STE12 T12R T12 PRE T12CLK Type rw rh rh rh rw rw A7H CCU6_TCTR0H Reset: 00 H Timer Control Register 0 High Bit Field 0 STE13 T13R T13 PRE T13CLK Type r rh rh rw rw FAH CCU6_CC60RL Reset: 00 H Capture/Compare Register for Channel CC60 Low Bit Field CC60VL Type rh FBH CCU6_CC60RH Reset: 00 H Capture/Compare Register for Channel CC60 High Bit Field CC60VH Type rh FCH CCU6_CC61RL Reset: 00 H Capture/Compare Register for Channel CC61 Low Bit Field CC61VL Type rh FDH CCU6_CC61RH Reset: 00 H Capture/Compare Register for Channel CC61 High Bit Field CC61VH Type rh FEH CCU6_CC62RL Reset: 00 H Capture/Compare Register for Channel CC62 Low Bit Field CC62VL Type rh FFH CCU6_CC62RH Reset: 00 H Capture/Compare Register for Channel CC62 High Bit Field CC62VH Type rh RMAP = 0, Page 2 9AH CCU6_T12MSELL Reset: 00 H T12 Capture/Compare Mode Select Register Low Bit Field MSEL61 MSEL60 Type rw rw 9BH CCU6_T12MSELH Reset: 00 H T12 Capture/Compare Mode Select Register High Bit Field DBYP HSYNC MSEL62 Type rw rw rw Table 14 CCU6 Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 40 V0.1, 2006-02 Prelimary 9CH CCU6_IENL Reset: 00 H Capture/Compare Interrupt Enable Register Low Bit Field ENT12 PM ENT12 OM ENCC 62F ENCC 62R ENCC 61F ENCC 61R ENCC 60F ENCC 60R Type rw rw rw rw rw rw rw rw 9DH CCU6_IENH Reset: 00 H Capture/Compare Interrupt Enable Register High Bit Field ENSTR EN IDLE EN WHE EN CHE 0 EN TRPF ENT13 PM ENT13 CM Type rw rw rw rw r rw rw rw 9EH CCU6_INPL Reset: 40 H Capture/Compare Interrupt Node Pointer Register Low Bit Field INPCHE INPCC62 INPCC61 INPCC60 Type rw rw rw rw 9FH CCU6_INPH Reset: 39 H Capture/Compare Interrupt Node Pointer Register High Bit Field 0 INPT13 INPT12 INPERR Type r rw rw rw A4H CCU6_ISSL Reset: 00 H Capture/Compare Interrupt Status Set Register Low Bit Field ST12P M ST12O M SCC62 F SCC62 R SCC61 F SCC61 R SCC60 F SCC60 R T y p e wwww w w w w A5H CCU6_ISSH Reset: 00 H Capture/Compare Interrupt Status Set Register High Bit Field SSTR SIDLE SWHE SCHE SWHC STRPF ST13 PM ST13 CM T y p e wwww w w w w A6H CCU6_PSLR Reset: 00 H Passive State Level Register Bit Field PSL63 0 PSL Type rwh r rwh A7H CCU6_MCMCTR Reset: 00 H Multi-Channel Mode Control Register Bit Field 0 SWSYN 0 SWSEL Type r rw r rw FAH CCU6_TCTR2L Reset: 00 H Timer Control Register 2 Low Bit Field 0 T13TED T13TEC T13 SSC T12 SSC Type r rw rw rw rw FBH CCU6_TCTR2H Reset: 00 H Timer Control Register 2 High Bit Field 0 T13RSEL T12RSEL Type r rw rw FCH CCU6_MODCTRL Reset: 00 H Modulation Control Register Low Bit Field MC MEN

0 T12MODEN

FDH CCU6_MODCTRH Reset: 00 H Modulation Control Register High Bit Field ECT13 O

0 T13MODEN

FEH CCU6_TRPCTRL Reset: 00 H Trap Control Register Low Bit Field 0 TRPM2 TRPM1 TRPM0 Type r rw rw rw FFH CCU6_TRPCTRH Reset: 00 H Trap Control Register High Bit Field TRPPE N TRPEN TRPEN Type rw rw rw RMAP = 0, Page 3 9AH CCU6_MCMOUTL Reset: 00 H Multi-Channel Mode Output Register Low Bit Field 0 R MCMP Type r rh rh 9BH CCU6_MCMOUTH Reset: 00 H Multi-Channel Mode Output Register High Bit Field 0 CURH EXPH Type r rh rh 9CH CCU6_ISL Reset: 00 H Capture/Compare Interrupt Status Register Low Bit Field T12PM T12OM ICC62F ICC62 R ICC61F ICC61 R ICC60F ICC60 R Type rh rh rh rh rh rh rh rh 9DH CCU6_ISH Reset: 00 H Capture/Compare Interrupt Status Register High Bit Field STR IDLE WHE CHE TRPS TRPF T13PM T13CM Type rh rh rh rh rh rh rh rh 9EH CCU6_PISEL0L Reset: 00 H Port Input Select Register 0 Low Bit Field ISTRP ISCC62 ISCC61 ISCC60 Type rw rw rw rw Table 14 CCU6 Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 41 V0.1, 2006-02 Prelimary The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1). The SSC SFRs can be accessed in the standard memory area (RMAP = 0). 9FH CCU6_PISEL0H Reset: 00 H Port Input Select Register 0 High Bit Field IST12HR ISPOS2 ISPOS1 ISPOS0 Type rw rw rw rw A4H CCU6_PISEL2 Reset: 00 H Port Input Select Register 2 Bit Field 0 IST13HR Type r rw FAH CCU6_T12L Reset: 00 H Timer T12 Counter Register Low Bit Field T12CVL Type rwh FBH CCU6_T12H Reset: 00 H Timer T12 Counter Register High Bit Field T12CVH Type rwh FCH CCU6_T13L Reset: 00 H Timer T13 Counter Register Low Bit Field T13CVL Type rwh FDH CCU6_T13H Reset: 00 H Timer T13 Counter Register High Bit Field T13CVH Type rwh FEH CCU6_CMPSTATL Reset: 00 H Compare State Register Low Bit Field 0 CC63 ST CCPO CCPO CCPO CC62 ST CC61 ST CC60 ST T y p e r r hr hr h rh rh rh rh FFH CCU6_CMPSTATH Reset: 00 H Compare State Register High Bit Field T13IM COUT 63PS COUT 62PS CC62 PS COUT 61PS CC61 PS COUT 60PS CC60 PS T y p e r w hr w hr w hr w h rwh rwh rwh rwh Table 15 UART1 Register Overview A d d r R e g i s t e r N a m e B i t 7 6543210 RMAP = 1 H SCON Reset: 00 H Serial Channel Control Register Bit Field SM0 SM1 SM2 REN TB8 RB8 TI RI Type rw rw rw rw rw rwh rwh rwh C9H SBUF Reset: 00 H Serial Data Buffer Register Bit Field VAL Type rwh CAH BCON Reset: 00 H Baud Rate Control Register Bit Field 0 BRPRE R Type r rw rw CBH BG Reset: 00 H Baud Rate Timer/Reload Register Bit Field BR_VALUE Type rwh CCH FDCON Reset: 00 H Fractional Divider Control Register Bit Field 0 NDOV FDM FDEN Type r rwh rw rw CDH FDSTEP Reset: 00 H Fractional Divider Reload Register Bit Field STEP Type rw CEH FDRES Reset: 00 H Fractional Divider Result Register Bit Field RESULT Type rh Table 16 SSC Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 A9H SSC_PISEL Reset: 00 H Port Input Select Register Bit Field 0 CIS SIS MIS Type r rw rw rw Table 14 CCU6 Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 42 V0.1, 2006-02 Prelimary The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0). The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1). AAH SSC_CONL Reset: 00 H Control Register Low Programming Mode Bit Field LB PO PH HB BM Type rw rw rw rw rw Operating Mode Bit Field 0 BC Type r rh ABH SSC_CONH Reset: 00 H Control Register High Programming Mode Bit Field EN MS 0 AREN BEN PEN REN TEN Type rw rw r rw rw rw rw rw Operating Mode Bit Field EN MS 0 BSY BE PE RE TE Type rw rw r rh rwh rwh rwh rwh ACH SSC_TBL Reset: 00 H Transmitter Buffer Register Low Bit Field TB_VALUE Type rw ADH SSC_RBL Reset: 00 H Receiver Buffer Register Low Bit Field RB_VALUE Type rh AEH SSC_BRL Reset: 00 H Baudrate Timer Reload Register Low Bit Field BR_VALUE Type rw AFH SSC_BRH Reset: 00 H Baudrate Timer Reload Register High Bit Field BR_VALUE Type rw Table 17 MultiCAN Register Overview A d d r R e g i s t e r N a m e B i t 7 6543210 RMAP = 0 D8H ADCON Reset: 00 H CAN Address/Data Control Register Bit Field V3 V2 V1 V0 AUAD BSY RWEN Type rw rw rw rw rw rh rw D9H ADL Reset: 00 H CAN Address Low Register Bit Field CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 T y p e r w hr w hr w hr w hr w hr w hr w hr w h DAH ADH Reset: 00 H CAN Address High Register Bit Field 0 CA13 CA12 CA11 CA10 Type r rwh rwh rwh rwh DBH DATA0 Reset: 00 H CAN Data Register 0 Bit Field CD Type rwh DCH DATA1 Reset: 00 H CAN Data Register 1 Bit Field CD Type rwh DDH DATA2 Reset: 00 H CAN Data Register 2 Bit Field CD Type rwh DEH DATA3 Reset: 00 H CAN Data Register 3 Bit Field CD Type rwh Table 18 OCDS Register Overview A d d r R e g i s t e r N a m e B i t 7 6543210 RMAP = 1 E9H MMCR2 Reset: 1U H Monitor Mode Control 2 Register Bit Field STMO DE EXBC DSUSP MBCO N ALTDI MMEP MMOD E JENA Type rw rw rw rwh rw rwh rh rh F1H MMCR Reset: 00 H Monitor Mode Control Register Bit Field MEXIT MEXIT 0 MSTEP MRAM S_P MRAM S TRF RRF Type w hw r rw w rwh rh rh Table 16 SSC Register Overview

Data Sheet 43 V0.1, 2006-02 Prelimary F2H MMSR Reset: 00 H Monitor Mode Status Register Bit Field MBCA M MBCIN EXBF SWBF HWB3 F HWB2 F HWB1 F HWB0 F Type rw rwh rwh rwh rwh rwh rwh rwh F3H MMBPCR Reset: 00 H BreakPoints Control Register Bit Field SWBC HWB3C HWB2C HWB1 C HWB0C Type rw rw rw rw rw F4H MMICR Reset: 00 H Monitor Mode Interrupt Control Register Bit Field DVECT DRETR COM RST MST SEL MMUIE MMUIE RRIE_ P RRIE Type rwh rwh rwh rh w rw w rw F5H MMDR Reset: 00 H Monitor Mode Data Transfer Register Receive Bit Field MMRR Type rh Transmit Bit Field MMTR Type w F6H HWBPSR Reset: 00 H Hardware Breakpoints Select Register Bit Field 0 BPSEL BPSEL Type r w rw F7H HWBPDR Reset: 00 H Hardware Breakpoints Data Register Bit Field HWBPxx Type rw EBH MMWR1 Reset: 00 H Monitor Work Register 1 Bit Field MMWR1 Type rw ECH MMWR2 Reset: 00 H Monitor Work Register 2 Bit Field MMWR2 Type rw Table 18 OCDS Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 7 6543210

Data Sheet 44 V0.1, 2006-02 Prelimary

3.3 Flash Memory

The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not require additional programming or erasing voltage. The sector ization of the Flash memory allows each sector to be erased independently. Features:

• In-System Programming (ISP) via UART
• In-Application Programming (IAP)
• Error Correction Code (ECC) for dynamic correction of single-bit errors
• Background program and erase operations for CPU load minimization
• Support for aborting erase operation
• Minimum program width 1) of 32-byte for D-Flash and 64-byte for P-Flash
• 1-sector minimum erase width
• 1-byte read access
• 135.1 ns minimum read access time (3 × t CCLK @ fCCLK =2 4M H z±7 . 5%2))
• Operating supply voltage: 2.5 V ± 7.5 %
• Program time: 2.3 ms 3)
• Erase time: 120 ms 3) Table 19 shows the Flash data retention and endurance targets4). 1) P-Flash: 64-byte wordline can only be programmed once, i.e., one gate disturb allowed. D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed. 2) fsys =9 6M H z±7 . 5 % ( fCCLK = 24 MHz ± 7.5 %) is the maximum frequency range for Flash read access. 3) fsys = 96 MHz ± 7.5% is the only frequency range for Flash programming and erasing. f sysmin is used for obtaining the worst case timing. Table 19 Flash Data Retention and Endurance Targets Retention up to Endurance up to Programming Temperature Size 20 years 1,000 cycles 0 – 100°C 15 Kbytes 5 years 10,000 cycles -40 – 125°C 896 bytes 2 years 70,000 cycles -40 – 125°C 512 bytes 2 years 100,000 cycles -40 – 125°C 128 bytes 4) Specification according to operating temperature profile with 0.2ppm error rate.

3.3.1 Flash Bank Sectorization

Figure 11. Both types can be used for code and data storage. The label “Data” neither used for data storage. It is used to distin guish the different Flash bank sectorizations. The XC886/888 ROM devices offer a single 4-Kbyte D-Flash bank. greater flexibility and the ability to adapt to a wide range of application requirements.

Data Sheet 46 V0.1, 2006-02 Prelimary

3.3.2 Flash Programming Width

For the P-Flash banks, a programmed wordli ne (WL) must be eras ed before it can be reprogrammed as the Flash cells can only withstand one gate disturb. This means that the entire sector containing the WL must be erased since it is impossible to erase a single WL. For the D-Flash bank, the same WL can be programmed twice before erasing is required as the Flash cells are able to withstand tw o gate disturbs. Hence, it is possible to program the same WL, for example, with 16 bytes of data in two times (see Figure 12). Figure 12 D-Flash Programming Note: When programming a D-Flash WL the second time, the previously programmed Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain its original contents and to prevent “over-programming”. 0000 ….. 0000 H 0000 ….. 0000 H 32 bytes (1 WL) 1111 ….. 1111 H0000 ….. 0000 H 16 bytes 16 bytes 0000 ….. 0000 H 1111 ….. 1111 H Flash memory cells 32-byte write buffers 1111 ….. 0000 H 1111 ….. 1111 H 0000 ….. 0000 H1111 ….. 0000 H Program 1 Program 2 Note: A Flash memory cell can be programmed from 0 to 1, but not from 1 to 0.

Data Sheet 47 V0.1, 2006-02 Prelimary

3.4 Interrupt System

The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interru pt functions supported by the core, e.g., configurable interrupt priority and interr upt masking, the XC886/888 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional st atus registers for detecting and determining the interrupt source.

3.4.1 Interrupt Source

Figure 13 to Figure 17 give a general overview of the interrupt sources and illustrates the request and control flags. Figure 13 Non-Maskable Interrupt Request Sources 0073 H NMIWDT NMICON.0 WDT Overflow >=1 Non Maskable Interrupt NMIPLL NMICON.1 PLL Loss of Lock NMIFLASH Flash Operation Complete NMIVDD NMICON.4 VDD Pre-Warning FNMIWDT NMIISR.0 FNMIPLL NMIISR.1 FNMIFLASH NMIISR.2 FNMIVDD NMIISR.4 NMIVDDP NMICON.5 VDDP Pre-Warning FNMIVDDP NMIISR.5 NMIECC NMICON.6 Flash ECC Error FNMIECC NMIISR.6

Data Sheet 48 V0.1, 2006-02 Prelimary Figure 14 Interrupt Request Sources (Part 1) Highest Lowest Priority Level Bit-addressable Request flag is cleared by hardware 000B HET0 IEN0.1 TF0 TCON.5 Timer 0 Overflow 001B HET1 IEN0.3 TF1 TCON.7 Timer 1 Overflow IP.1/ IPH.1 IP.3/ IPH.3

0023 HES

IEN0.4 IP.4/ IPH.4 >=1 RI SCON.0 TI SCON.1 UART

0003 HEX0

IEN0.0 IE0 TCON.1 IP.0/ IPH.0 0013 H IP.2/ IPH.2 IT0 TCON.0EXINT0 EXICON0.0/1 EXINT0 IRCON0.0 EINT0 EX1 IEN0.2 IE1 TCON.3 IT1 TCON.2EXINT1 EXICON0.2/3 EXINT1 IRCON0.1 EINT1 IEN0.7 EA P o l l i n g S e q u e n c e

Data Sheet 49 V0.1, 2006-02 Prelimary Figure 15 Interrupt Request Sources (Part 2) Highest Lowest Priority Level Bit-addressable Request flag is cleared by hardware 002B H IP.5/ IPH.5 P o l l i n g S e q u e n c e

0033 HEADC

IEN1.0 IP1.0/ IPH1.0 >=1 ADCSRC0 IRCON1.3 ADC_0 ADC_1 ADCSRC1 IRCON1.4 CANSRC1 IRCON1.5 MCAN_1 ET2 IEN0.5 >=1 TF2 T2_T2CON.7 EXF2 T2_T2CON.6 Timer 2 Overflow EXEN2 T2_T2CON.3 CANSRC0 IRCON2.0 MCAN_0 NDOV FDCON.2 Normal Divider Overflow SYNEN FDCON.6 EOFSYN FDCON.4 End of Syn Byte ERRSYN FDCON.5 Syn Byte Error IEN0.7 EA CANSRC2 IRCON1.6 MCAN_2 T2EX EDGES EL T2_T2MOD.5 >=1

Data Sheet 50 V0.1, 2006-02 Prelimary Figure 16 Interrupt Request Sources (Part 3) Highest Lowest Priority Level Bit-addressable Request flag is cleared by hardware P o l l i n g S e q u e n c e 003B HESSC IEN1.1 IP1.1/ IPH1.1 >=1TIR IRCON1.1 RIR IRCON1.2 EIR IRCON1.0 SSC_EIR SSC_TIR SSC_RIR IEN0.7 EA 0043 H IP1.2/ IPH1.2 EXINT2 EXICON0.4/5 EXINT2 IRCON0.2 EINT2 EX2 IEN1.2 IRDY MDUSTAT.0 MDU_0 MDU_1 IERR MDUSTAT.1 EOC CDSTATC.2 Cordic >=1 >=1 RI UART1_SCON.0 TI UART1_SCON.1 UART1 NDOV Normal Divider Overflow UART1_FDCON.2 TF2 T21_T2CON.7 EXF2 T21_T2CON.6 Timer 21 Overflow EXEN2 T21_T2CON.3 T21EX EDGES EL T21_T2MOD.5 >=1

Data Sheet 51 V0.1, 2006-02 Prelimary Figure 17 Interrupt Request Sources (Part 4) IEN0.7 Highest Lowest Priority Level Bit-addressable Request flag is cleared by hardware P o l l i n g S e q u e n c e EA 004B HEXM IEN1.3 IP1.3/ IPH1.3 >=1 EXINT5 EXICON1.2/3 EXINT5 IRCON0.5 EINT5 EXINT3 EXICON1.0/1 EXINT4 IRCON0.4 EINT4 EXINT3 EXICON0.6/7 EXINT3 IRCON0.3 EINT3 EXINT6 EXICON1.4/5 EXINT6 IRCON0.6 EINT6 CANSRC3 IRCON2.4 MCAN_3

Data Sheet 52 V0.1, 2006-02 Prelimary Figure 18 Interrupt Request Sources (Part 5) Highest Lowest Priority Level P o l l i n g S e q u e n c e IEN0.7 Bit-addressable Request flag is cleared by hardware EA 0053 H CCU6 interrupt node 0 IP1.4/ IPH1.4 005B H IP1.5/ IPH1.5 0063 H IP1.6/ IPH1.6 006B H IP1.7/ IPH1.7 ECCIP0 IEN1.4 ECCIP1 IEN1.5 ECCIP2 IEN1.6 ECCIP3 IEN1.7 MCANSRC4 IRCON3.1 MCAN_4 >=1 CCU6 interrupt node 1 MCANSRC5 IRCON3.5 MCAN_5 >=1 CCU6 interrupt node 2 MCANSRC6 IRCON4.1 MCAN_6 >=1 CCU6 interrupt node 3 MCANSRC7 IRCON4.5 MCAN_7 >=1 CCU6SR0 IRCON3.0 CCU6SR1 IRCON3.4 CCU6SR2 IRCON4.0 CCU6SRC3 IRCON4.4

Data Sheet 53 V0.1, 2006-02 Prelimary Figure 19 Interrupt Request Sources (Part 6) CCU6 Interrupt node 0 CCU6 Interrupt node 1 CCU6 Interrupt node 2 CCU6 Interrupt node 3 >=1 CC60 ENCC60R IENL.0 ICC60R ISL.0 ENCC60F IENL.1 ICC60F ISL.1 INPL.1 INPL.0 >=1 CC61 ENCC61R IENL.2 ICC61R ISL.2 ENCC61F IENL.3 ICC61F ISL.3 INPL.3 INPL.2 >=1CC62 ENCC62R IENL.4 ICC62R ISL.4 ENCC62F IENL.5 ICC62F ISL.5 INPL.5 INPL.4 >=1 ENT12OM IENL.6 T12OM ISL.6 ENT12PM IENL.7 T12PM ISL.7 INPH.3 INPH.2 >=1 ENT13CM IENH.0 T13CM ISH.0 ENT13PM IENH.1 T13PM ISH.1 INPH.5 INPH.4 >=1 ENTRPF IENH.2 TRPF ISH.2 ENWHE IENH.5 WHE ISH.5 INPH.1 INPH.0 T12 One match T12 Period match T13 Compare match T13 Period match CTRAP Wrong Hall Event INPL.7 INPL.6 ENCHE IENH.4 CHE ISH.4 Correct Hall Event >=1 ENSTR IENH.7 STR ISH.7 Multi-Channel Shadow Transfer

Data Sheet 54 V0.1, 2006-02 Prelimary

3.4.2 Interrupt Source and Vector

Each interrupt source has an associated interrupt vector addr ess. This vector is accessed to service the corresponding interrupt source request. The interrupt service of each interrupt source can be individually enabled or disabled via an enable bit. The assignment of the XC886/888 interrupt sources to the interrupt vector addresses and the corresponding interrupt source enable bits are summarized in Table 20. Table 20 Interrupt Vector Addresses Interrupt Source Vector Address Assignment for XC886/ 888 Enable Bit SFR NMI 0073 H Watchdog Timer NMI NMIWDT NMICON PLL NMI NMIPLL Flash NMI NMIFLASH VDDC Prewarning NMI NMIVDD VDDP Prewarning NMI NMIVDDP Flash ECC NMI NMIECC XINTR0 0003 H External Interrupt 0 EX0 IEN0 XINTR1 000B H Timer 0 ET0 XINTR2 0013 H External Interrupt 1 EX1 XINTR3 001B H Timer 1 ET1 XINTR4 0023 H UART ES XINTR5 002B H T2 ET2 UART Fractional Divider (Normal Divider Overflow) MultiCAN Node 0 LIN

Data Sheet 55 V0.1, 2006-02 Prelimary XINTR6 0033 H MultiCAN Nodes 1 and 2 EADC IEN1 ADC[1:0] XINTR7 003B H SSC ESSC XINTR8 0043 H External Interrupt 2 EX2 T21 CORDIC UART1 UART1 Fractional Divider (Normal Divider Overflow) MDU[1:0] XINTR9 004B H External Interrupt 3 EXM External Interrupt 4 External Interrupt 5 External Interrupt 6 MultiCAN Node 3 XINTR10 0053 H CCU6 INP0 ECCIP0 MultiCAN Node 4 XINTR11 005B H CCU6 INP1 ECCIP1 MultiCAN Node 5 XINTR12 0063 H CCU6 INP2 ECCIP2 MultiCAN Node 6 XINTR13 006B H CCU6 INP3 ECCIP3 MultiCAN Node 7 Table 20 Interrupt Vector Addresses (cont’d)

Data Sheet 56 V0.1, 2006-02 Prelimary

3.4.3 Interrupt Priority

Each interrupt source, except for NMI, can be individually programmed to one of the four possible priority levels. The NMI has the highest priority and supersedes all other interrupts. Two pairs of interrupt priority registers (IP and IPH, IP1 and IPH1) are available to program the priority level of each non-NMI interrupt vector. A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot be interrupted by any other interrupt source. If two or more requests of different prio rity levels are received simultaneously, the request of the highest priority is serviced first. If requests of the same priority are received simultaneously, then an internal polling sequence determines which request is serviced first. Thus, within each priority le vel, there is a second priority structure determined by the polling sequence shown in Table 21. Table 21 Priority Structure within Interrupt Level Source Level Non-Maskable Interrupt (NMI) (highest) External Interrupt 0 1 Timer 0 Interrupt 2 External Interrupt 1 3 Timer 1 Interrupt 4 UART Interrupt 5 Timer 2,UART Fractional Divider, MCAN, LIN Interrupt ADC, MCAN Interrupt 7 SSC Interrupt 8 External Interrupt 2, Timer 21, UART1, UART1 Fractional Divider, MDU, CORDIC Interrupt External Interrupt [6:3], MCAN Interrupt 10 CCU6 Interrupt Node Pointer 0, MCAN interrupt 11 CCU6 Interrupt Node Pointer 1, MCAN Interrupt 12 CCU6 Interrupt Node Pointer 2, MCAN Interrupt 13 CCU6 Interrupt Node Pointer 3, MCAN Interrupt 14

Data Sheet 57 V0.1, 2006-02 Prelimary

3.5 Parallel Ports

The XC886 has 34 port pins organized into five parallel ports, Port 0 (P0) to Port 4 (P4), while the XC888 has 48 port pins organized into six parallel ports, Port 0 (P0) to Port 6 (P6). Each pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Ports P0, P1, P3, P4 and P5 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected. Port P2 is an input-only port , providing general purpose input functions, alternate input functions for the on-chip per ipherals, and also analog inputs for the Analog-to-Digital Converter (ADC). Bidirectional Port Features:

• Configurable pin direction
• Configurable pull-up/pull-down devices
• Configurable open drain mode
• Transfer of data through digital input s and outputs (general purpose I/O)
• Alternate input/output for on-chip peripherals Input Port Features:
• Configurable input driver
• Configurable pull-up/pull-down devices
• Receive of data through digital input (general purpose input)
• Alternate input for on-chip peripherals
• Analog input for ADC module

Data Sheet 58 V0.1, 2006-02 Prelimary Figure 20 General Structure of Bidirectional Port Px_OD Open Drain Control Register Px_Data Data Register Internal Bus AltDataOut 2 Px_ALTSEL0 Alternate Select Register 0 Px_ALTSEL1 Alternate Select Register 1 AltDataIn Pin Px_PUDEN Pull-up/Pull-down Enable Register Px_PUDSEL Pull-up/Pull-down Select Register AltDataOut1 Pad Out In Output Driver Input Driver Schmitt Trigger enable enable Pull Up Device Pull Down Device VDDP enable enable Px_DIR Direction Register AltDataOut 3 11

Data Sheet 59 V0.1, 2006-02 Prelimary Figure 21 General Structure of Input Port Px_DATA Data Register Internal Bus AltDataIn Px_PUDEN Pull-up/Pull-down Enable Register Px_PUDSEL Pull-up/Pull-down Select Register In Input Driver Schmitt Trigger AnalogIn Px_DIR Direction Register Pad Pull Up Device Pull Down Device VDDP enable enable enable Pin

Data Sheet 60 V0.1, 2006-02 Prelimary

3.6 Power Supply System with Embedded Voltage Regulator

The XC886/888 microcontroller requires two different levels of power supply:

• 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports
• 2.5 V for the core, memory, on-chip oscillator, and peripherals Figure 22 shows the XC886/888 power supply system. A power supply of 3.3 V or 5.0 V must be provided from the external power s upply pin. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the power consumption of the whole chip and the complexity of the application board design. The EVR consists of a main voltage regulat or and a low power voltage regulator. In active mode, both voltage regulators ar e enabled. In power-down mode, the main voltage regulator is switched off, while the low power voltage regulator continues to function and provide power supply to the system with low power consumption. Figure 22 XC886/888 Power Supply System EVR Features:
• Input voltage (V DDP): 3.3 V/5.0 V
• Output voltage (V DDC): 2.5 V ± 7.5%
• Low power voltage regulator provided in power-down mode DDC and VDDP prewarning detection
• V DDC brownout detection On-chip OSC CPU & Memory V DDC (2.5V) VDDP (3.3V/5.0V) VSSP GPIO Ports (P0-P5) EVR Peripheral logic FLASH ADC PLL XTAL1& XTAL2

Data Sheet 61 V0.1, 2006-02 Prelimary

3.7 Reset Control

The XC886/888 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC886/888 is first powered up, the status of certain pins (see Table 23) must be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired boot op tion, which cannot be modified until the next power-on reset or hardware reset. This guarantees stable conditions during the normal operation of the device. In order to power up the system properly, the external reset pin RESET must be asserted until VDDC reaches 0.9*VDDC. The delay of external reset can be realized by an external capacitor at RESET pin. This capacitor value must be selected so that VRESET reaches 0.4 V, but not before VDDC reaches 0.9* VDDC. A typical application example is shown in Figure 23. For a voltage regulator with IDDmax = 100 mA, the V DDP capacitor value is 10 µF. VDDC capacitor value is 220 nF. The capacitor connected to RESET pin is 100 nF. Typically, the time taken for V DDC to reach 0.9*V DDC is less than 50 µs once V DDP reaches 2.3V. Hence, based on the condition that 10% to 90% VDDP (slew rate) is less than 500 µs, the RESET pin should be held low for 500 µs typically. See Figure 24. Figure 23 Reset Circuitry VSSP VDDP VDDC VSSC 3 - 5V / e.g. 100mA RESET EVR VR Vin e.g. 10uF 220nF typ. 100nF XC886/888 30k

Data Sheet 62 V0.1, 2006-02 Prelimary Figure 24 V DDP, VDDC and VRESET during Power-on Reset The second type of reset in XC886/888 is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin RESET is provided for the hardware reset. The Watchdog Timer (WDT) module is also capabl e of resetting the device if it detects a malfunction in the system. Another type of reset that needs to be de tected is a reset while the device is in power-down mode (wake-up reset). While the contents of the static RAM are undefined after a power-on reset, they are well defined after a wake-up reset from power-down mode. VDDP RESET wit h capacitor 2.3V VDDC < 0.4V 0.9*VDDC 2.5V Voltage Voltage Time Time typ. < 50 u s

Data Sheet 63 V0.1, 2006-02 Prelimary

3.7.1 Module Reset Behavior

Table 22 shows how the functions of the XC886/888 are affect ed by the various reset types. A “ ” means that this function is reset to its default state.

3.7.2 Booting Scheme

When the XC886/888 is reset, it must identify the type of configuration with which to start the different modes once the reset sequenc e is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0.0 collectivel y select the different boot options. Table 23 shows the available boot options in the XC886/888. Table 22 Effect of Reset on Device Functions Module/ Function Wake-Up Reset Watchdog Reset Hardware Reset Power-On Reset Brownout Reset CPU Core Peripherals On-Chip Static RAM Not affected, reliable Not affected, reliable Not affected, reliable Affected, un- reliable Affected, un- reliable Oscillator, PLL Not affected Port Pins EVR The voltage regulator is switched on Not affected FLASH NMI Disabled Disabled Table 23 XC886/888 Boot Selection MBC TMS P0.0 Type of Mode PC Start Value 1 0 x User Mode; on-chip OSC/PLL non-bypassed 0000 H 0 0 x BSL Mode; on-chip OSC/PLL non-bypassed 0000 H 0 1 0 OCDS Mode; on-chip OSC/PLL non- bypassed 0000H 1 1 0 User (JTAG) Mode 1); on-chip OSC/PLL non- bypassed (normal) 1) Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose. 0000H

Data Sheet 64 V0.1, 2006-02 Prelimary

3.8 Clock Generation Unit

The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the XC886/888. The power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is di rectly proportional to the frequency. During user program execution, the frequency can be programmed for an optimal ratio between performance and power consumption. Th erefore the power consumption can be adapted to the actual application state. Features:

• Phase-Locked Loop (PLL) for multiplying clock source by different factors
• PLL Base Mode
• Prescaler Mode
• PLL Mode
• Power-down mode support The CGU consists of an oscillator circuit and a PLL. In the XC886/888, the oscillator can be from either of these two sources: the on-chip oscillator (9.6 MHz) or the external oscillator (3 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip oscillator and external oscillator, unless ot herwise stated. After the reset, the on-chip oscillator will be used by default.The external oscillator can be selected via software. In addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows emergency routin es to be executed for system recovery or to perform system shut down.

Data Sheet 65 V0.1, 2006-02 Prelimary Figure 25 CGU Block Diagram Direct Drive (PLL Bypass Operation) During PLL bypass operation, the system clock has the same frequency as the external clock source. For the XC886/888, the PLL bypass cannot be set active. Hence, the direct drive mode is not available for use. PLL Base Mode The system clock is derived from the VCO base frequency clock divided by the K factor. Both VCO bypass and PLL bypass must be inactive for this PLL mode. Prescaler Mode (VCO Bypass Operation) In VCO bypass operation, the system clock is derived from the oscillator clock, divided by the P and K factors. PLL core lock detect N:1 P:1 fvco fn fp osc fail detect OSC fosc K:1 fsys NDIVOSCDISC OSCR LOCK VCOBYP PLLBYP fSYS fOSC= fSYS fVCObase K----×= fSYS fOSC

Data Sheet 66 V0.1, 2006-02 Prelimary PLL Mode The system clock is derived from the oscillat or clock, multiplied by the N factor, and divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for this PLL mode. The PLL mode is used during normal system operation. . System Frequency Selection For the XC886/888, the value of P is fixed to 1. In order to obtain the required fsys, the value of N and K can be selected by bits NDIV and KDIV respectively for different oscillator inputs. The output frequency must always be configured for 96 MHz. Table 24 provides examples on how f sys = 96 MHz can be obtained for the different oscillator sources. Table 25 shows the VCO range for the XC886/888.

3.8.1 Resonator Circuitry

Figure 26 shows the recommended ceramic resonator circuitry. When using an external resonator, its frequency can be within the range of 3 MHz to 12 MHz. A resonator load circuitry must be used, connected to both pins, XTAL1 and XTAL2. It normally consists of two load capacitances C 1 and C2, and in some cases, a feedback (R f) and/or damp (Rd) resistor might be necessary. Table 24 System frequency (f sys =9 6M H z ) Oscillator fosc N P K fsys On-chip 9.6 MHz 20 1 2 96 MHz External 8 MHz 24 1 2 96 MHz

6 MHz 32 1 2 96 MHz

4 MHz 48 1 2 96 MHz

f VCOmin fVCOmax fVCOFREEmin fVCOFREEmax Unit 150 200 20 80 MHz 100 150 10 80 MHz fSYS fOSC N

Data Sheet 67 V0.1, 2006-02 Prelimary Figure 26 External Ceramic Resonator Circuitry Note: The manufacturer of the ceramic res onator should check the resonator circuitry and make recommendations for the C1, C2, Rf and Rd values to be used for stable start-up behavior. XC886/888 XTAL1 XTAL2 Rd Rf Ceramic Resonator

Data Sheet 68 V0.1, 2006-02 Prelimary

3.8.2 Clock Management

The CGU generates all clock signals requir ed within the microcontroller from a single clock, f sys. During normal system operation, the typical frequencies of the different modules are as follow:

• CPU clock: CCLK, SCLK = 24 MHz
• Fast clock (used by MCAN): FCLK = 24 or 48 MHz
• Peripheral clock: PCLK = 24 MHz
• Flash Interface clock: CCLK2 = 96 MHz and CCLK = 24 MHz In addition, different clock frequency can output to pin CLKOUT(P0.0 or P0.7). The clock output frequency can further be divided by 2 using toggle latch (bit TLEN is set to 1), the resulting output frequency has 50% duty cycle. Figure 27 shows the clock distribution of the XC886/888. Figure 27 Clock Generation from f sys PLL N,P,K fsys= 96MHz CLKREL CCLK SCLK PCLK CCLK2 CORE Peripherals FLASH Interface OSC CLKOUT fosc COREL COUTS Toggle Latch TLEN MCAN FCLK FCCFG

Data Sheet 69 V0.1, 2006-02 Prelimary For power saving purposes, the clocks may be disabled or slowed down according to Table 26. Table 26 System frequency (f sys =9 6M H z ) Power Saving Mode Action Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all the peripherals are divided by a common programmable factor defined by bit field CMCON.CLKREL. Power-down Oscillator and PLL are switched off.

Data Sheet 70 V0.1, 2006-02 Prelimary

3.9 Power Saving Modes

The power saving modes of the XC886/888 provide flexible power consumption through a combination of techniques, including:

• Stopping the CPU clock
• Stopping the clocks of in dividual system components
• Reducing clock speed of some peripheral components
• Power-down of the entire system with fast restart capability After a reset, the active mode (normal oper ating mode) is selected by default (see Figure 28) and the system runs in the main system clock frequency. From active mode, different power saving modes can be selected by software. They are:
• Idle mode
• Slow-down mode
• Power-down mode Figure 28 Transition between Power Saving Modes POWER-DOWN IDLE ACTIVE SLOW-DOWN set PD bit set PD bit set IDLE bit set IDLE bit set SD bit clear SD bit any interrupt & SD=0 EXINT0/RXD pin & SD=0 EXINT0/RXD pin & SD=1 any interrupt & SD=1

Data Sheet 71 V0.1, 2006-02 Prelimary

3.10 Watchdog Timer

The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an XC886/888 system rese t. Hence, routine service of the WDT confirms that the system is functioning pr operly. This ensures that an accidental malfunction of the XC886/888 will be aborted in a user-specified time period. In debug mode, the WDT is suspended and stops counting. Therefore, there is no need to refresh the WDT during debugging. Features:

• 16-bit Watchdog Timer
• Programmable reload value for upper 8 bits of timer
• Programmable window boundary
• Selectable input frequency of f PCLK/2 or fPCLK/128
• Time-out detection with NMI generation and reset prewarning activation (after which a system reset will be performed) The WDT is a 16-bit timer incremented by a count rate of f PCLK/2 or f PCLK/128. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog service access in order to modify the watchdog expire time period. The lower 8 bits are reset on each service access. Figure 29 shows the block diagram of the WDT unit. Figure 29 WDT Block Diagram WDTREL MUX WDT Low Byte 1:2 Clear WDT Control 1:128 WDT High Byte WDTTO WDTIN fPCLK Logic ENWDT ENWDT_P WDTRS T Overflow/Time-out Control & Window-boundary control WDTWINB

Data Sheet 72 V0.1, 2006-02 Prelimary If the WDT is not serviced before the timer overflow, a system malfunction is assumed. As a result, the WDT NMI is triggered (a ssert WDTTO) and the reset prewarning is entered. The prewarning period lasts for 30 H count, after which the system is reset (assert WDTRST). The WDT has a “programmable window boundary” which disallows any refresh during the WDT’s count-up. A refresh during this window boundary constitutes an invalid access to the WDT, causing the reset prewarning to be entered but without triggering the WDT NMI. The system will still be reset after the prewarning period is over. The window boundary is from 0000H to the value obtained from the concatenation of WDTWINB and 00H. After being serviced, the WDT continues counting up from the value (<WDTREL> * 28). The time period for an overflow of the WDT is programmable in two ways:

• the input frequency to the WDT can be selected to be either f PCLK/2 or fPCLK/128
• the reload value WDTREL for the high byte of WDT can be programmed in register WDTREL The period, PWDT, between servicing the WDT and the next overflow can be determined by the following formula: If the Window-Boundary Refresh feature of the WDT is enabled, the period P WDT between servicing the WDT and the next over flow is shortened if WDTWINB is greater than WDTREL, see Figure 30. This period can be calculated using the same formula by replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB should not be smaller than WDTREL. Figure 30 WDT Timing Diagram PWDT 2 1W D T I N+ 6×() 216 WDTREL– 28×()× fPCLK WDTREL WDTWINB time Count FFFFH No refresh allowed Refresh allowed

Data Sheet 73 V0.1, 2006-02 Prelimary Table 27 lists the possible watchdog time range that can be achieved for different module clock frequencies . Some numbers are rounded to 3 significant digits. Table 27 Watchdog Time Ranges Reload value in WDTREL Prescaler for fPCLK 2 (WDTIN = 0) 128 (WDTIN = 1)

24 MHz 24 MHz

FFH 21.3 µs1 . 3 7 m s 7FH 2.75 ms 176 ms 00H 5.46 ms 350 ms

Data Sheet 74 V0.1, 2006-02 Prelimary

3.11 UART and UART1

The XC886/888 provides two Universal Asynchronous Receiver/Transmitter (UART and UART1) modules for full-duplex asynchrono us reception/transmission. Both are also receive-buffered, i. e., they can commence receptio n of a second byte before a previously received byte has been read from t he receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost. Features:

• Full-duplex asynchronous modes – 8-bit or 9-bit data frames, LSB first – fixed or variable baud rate
• Receive buffered
• Multiprocessor communication
• Interrupt generation on the completion of a data transmission or reception The UART modules can operate in four asynchronous modes as shown in Table 28. Data is transmitted on TXD and received on RXD. There are several ways to generate the baud rate clock for the serial port, depending on the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at f PCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock and can be configured to either fPCLK/32 or fPCLK/64. For UART1 module, only fPCLK/64 is available. The variable baud rate is set by the underflow rate on the dedicated baud- rate generator. For UART module, the variable baud rate alternatively can be set by the overflow rate on Timer 1. Table 28 UART Modes Operating Mode Baud Rate Mode 0: 8-bit shift register f PCLK/2 Mode 1: 8-bit shift UART Variable Mode 2: 9-bit shift UART f PCLK/32 or fPCLK/641) 1) For UART1 module, the baud rate is fixed at fPCLK/64. Mode 3: 9-bit shift UART Variable

Data Sheet 75 V0.1, 2006-02 Prelimary

3.11.1 Baud-Rate Generator

Both UART modules have their own dedicated baud-rate generator, which is based on a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud rates based on its input clock f PCLK, see Figure 31. Figure 31 Baud-rate Generator Circuitry The baud rate timer is a count-down timer and is clocked by either the output of the fractional divider (f MOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate generation, the fractional divider must be configured to fractional divider mode (FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit reload value in register BG and one clock pulse is generated for the serial channel. Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12. The baud rate (fBR) value is dependent on the following parameters:

• Input clock f PCLK
• Prescaling factor (2 BRPRE) defined by bit field BRPRE in register BCON FDSTEP FDM Adder FDRES FDEN&FDM clk Fractional Divider Prescaler NDOV ‘0’ FDEN (overflow) fBR 8-Bit Baud Rate Timer 8-Bit Reload Value R fDIV fDIVfPCLK fMOD

Data Sheet 76 V0.1, 2006-02 Prelimary

• Fractional divider (STEP/256) defined by register FDSTEP (to be considered only if fractional divider is enabled and operating in fractional divider mode)
• 8-bit reload value (BR_VALUE) for the b aud rate timer defined by register BG The following formulas calculate the final baud rate without and with the fractional divider respectively: The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud. Standard LIN protocal can support a maximum baud rate of 20kHz, the baud rate accuracy is not critical and the fractional divider can be disabled. Only the prescaler is used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of 20kHz to 115.2kHz, the higher baud rates r equire the use of the fractional divider for greater accuracy. Table 29 lists the various commonly used baud rates with their corresponding parameter settings and deviation errors. The fractional divider is disabled and a module clock of 24 MHz is used. The fractional divider allows baud rates of higher accuracy (lower deviation error) to be generated. Table 30 lists the resulting deviation errors from generating a baud rate of 115.2 kHz, using different module clock frequencies. The fractional divider is enabled (fractional divider mode) and the corresponding parameter settings are shown. Table 29 Typical Baud rates for UART with Fractional Divider disabled Baud rate Prescaling Factor BRPRE) Reload Value (BR_VALUE + 1) Deviation Error 19.2 kBaud 1 (BRPRE=000 B) 78 (4E H)0 . 1 7 % 9600 Baud 1 (BRPRE=000 B)1 5 6 ( 9 C H)0 . 1 7 % 4800 Baud 2 (BRPRE=001 B)1 5 6 ( 9 C H)0 . 1 7 % 2400 Baud 4 (BRPRE=010 B)1 5 6 ( 9 C H)0 . 1 7 % baud rate fPCLK 16 2 BRPRE BR_VALUE 1+()×× baud rate fPCLK 16 2 BRPRE BR_VALUE 1+()××

Data Sheet 77 V0.1, 2006-02 Prelimary Table 30 Deviation Error for UART with Fractional Divider enabled fPCLK Prescaling Factor (2BRPRE) Reload Value (BR_VALUE + 1) STEP Deviation Error 24 MHz 1 10 (A H) 197 (C5 H) +0.20 % 12 MHz 1 6 (6 H) 236 (EC H) +0.03 % 6.67 MHz 1 3 (3 H) 236 (EC H) +0.03 %

Data Sheet 78 V0.1, 2006-02 Prelimary

3.11.2 Baud Rate Generation using Timer 1

In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the variable baud rates. In theory, this timer could be used in any of its modes. But in practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the required baud rate. The baud rate is determined by the Timer 1 overflow rate and the value of SMOD as follows: [3.1]

3.12 Normal Divider Mode (8-bit Auto-reload Timer)

Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider mode, while at the same time disables baud rate generation (see Figure 31). Once the fractional divider is enabled (FDEN = 1), it fu nctions as an 8-bit auto-reload timer (with no relation to baud rate generation) and counts up from the reload value with each input clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit field STEP in register FDSTEP defines the reload value. At each timer overflow, an overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP. The output frequency in normal divider mode is derived as follows: [3.2] Mode 1, 3 baud rate 2SMOD fPCLK× fMOD fDIV

Data Sheet 79 V0.1, 2006-02 Prelimary

3.13 LIN Protocol

The UART module can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. This option is not available with UART1 module. The LIN baud rate detection feature provides the capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be synchronized to the LIN baud rate for data transmission and reception. LIN is a holistic communication concept for local interconnected networks in vehicles. The communication is based on the SCI (UART) data format, a single-master/multiple- slave concept, a clock synchronization for nodes without stabilized time base. An attractive feature of LIN is self-synchr onization of the slave nodes without a crystal or ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the baud rate must be calculated and returned with every message frame. The structure of a LIN frame is shown in Figure 32. The frame consists of the:

• header, which comprises a Break (13-bit time low), Synch Byte (55 H), and ID field
• response time
• data bytes (according to UART protocol)
• checksum Figure 32 Structure of LIN Frame

3.13.1 LIN Header Transmission

LIN header transmission is only applicable in master mode. In the LIN communication, a master task decides when and which frame is to be transferred on the bus. It also identifies a slave task to provide the data transported by each fr ame. The information needed for the handshaking between the mast er and slave tasks is provided by the master task through the header portion of the frame. Frame slot Frame Response Inter- frame space Response spaceHeader Synch Protected identifier Data 1 Data 2 Data N Checksum

Data Sheet 80 V0.1, 2006-02 Prelimary The header consists of a break and synch pattern followed by an identifier. Among these three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data. The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes. In the LIN communication, a slave task is required to be synchronized at the beginning of the protected identifier fi eld of frame. For this purpose , every frame starts with a sequence consisting of a break field followed by a synch byte field. This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field. Upon entering LIN communication, a connecti on is established and the transfer speed (baud rate) of the serial communication part ner (host) is automatically synchronized in the following steps: STEP 1: Initialize interface for reception and timer for baud rate measurement STEP 2: Wait for an incoming LIN frame from host STEP 3: Synchronize the baud rate to the host STEP 4: Enter for Master Request Frame or for Slave Response Frame Note: Re-synchronization and setup of baud rate are always done for every Master Request Header or Slave Response Header LIN frame.

Data Sheet 81 V0.1, 2006-02 Prelimary

3.14 High-Speed Synchronous Serial Interface

The High-Speed Synchronous Serial Inte rface (SSC) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices or devices using other synchronous serial interfaces. Features:

• Master and slave mode operation – Full-duplex or half-duplex operation
• Transmit and receive buffered
• Flexible data format – Programmable number of data bits: 2 to 8 bits – Programmable shift directio n: LSB or MSB shift first – Programmable clock polarity: idle low or high state for the shift clock – Programmable clock/data phase: data shift with leading or trailing edge of the shift clock
• Variable baud rate
• Compatible with Serial Peripheral Interface (SPI)
• Interrupt generation – On a transmitter empty condition – On a receiver full condition – On an error condition (receive, phase, baud rate, transmit error)

Data Sheet 83 V0.1, 2006-02 Prelimary

3.15 Timer 0 and Timer 1

Timer 0 and Timer 1 can function as both time rs or counters. When functioning as a timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are incremented in response to a 1-to-0 transition (falling edge) at their respective external input pins, T0 or T1. Timer 0 and 1 are fully compatible and can be configured in four different operating modes for use in a vari ety of applications, see Table 31. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions are specialized. Table 31 Timer 0 and Timer 1 Modes Mode Operation 0 13-bit timer The timer is essentially an 8-bit counter with a divide-by-32 prescaler. This mode is included solely for compatibility with Intel 8048 devices. 1 16-bit timer The timer registers, TLx and THx, are concatenated to form a 16-bit counter. 2 8-bit timer wi th auto-reload The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow.

3 Timer 0 operates as two 8-bit timers

The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and retains its count even if enabled.

Data Sheet 84 V0.1, 2006-02 Prelimary

3.16 Timer 2 and Timer 21

Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode. As a timer, the timers count with an input clock of PCLK/12 (if prescaler is disabled). As a counter, they count 1-to-0 transitions on pin T2. In the counter mode, the maximum resolution for the count is PCLK/24 (if prescaler is disabled). Table 32 Timer 2 Modes Mode Description Auto-reload Up/Down Count Disabled

• Count up only
• Start counting from 16-bit reload value, overflow at FFFF H
• Reload event configurable for trigger by overflow condition only, or by negative/positive edge at input pin T2EX as well
• Programmble reload value in register RC2
• Interrupt is generated with reload event Up/Down Count Enabled
• Count up or down, direction determined by level at input pin T2EX
• No interrupt is generated
• Count up – Start counting from 16-bit reload value, overflow at FFFF H – Reload event triggered by overflow condition – Programmble reload value in register RC2
• Count down – Start counting from FFFF H, underflow at value defined in register RC2 – Reload event triggered by underflow condition – Reload value fixed at FFFF H Channel capture
• Count up only
• Start counting from 0000 H, overflow at FFFFH
• Reload event triggered by overflow condition
• Reload value fixed at 0000 H
• Capture event triggered by falling/rising edge at pin T2EX
• Captured timer value stored in register RC2
• Interrupt is generated wit h reload or capture event

Data Sheet 85 V0.1, 2006-02 Prelimary

3.17 Capture/Compare Unit 6

The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and multi-phase machines. The timer T12 can function in capture and/or compare mode for its three channels. The timer T13 can work in compare mode only. The multi-channel control unit generates ou tput patterns, whic h can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal modulation. Timer T12 Features:

• Three capture/compare channels , each channel can be used either as a capture or as a compare channel
• Supports generation of a three-phase PWM (six outputs, individual signals for highside and lowside switches)
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Dead-time control for each channel to avoid short-circuits in the power stage
• Concurrent update of the re quired T12/13 registers
• Generation of center-aligned and edge-aligned PWM
• Supports single-shot mode
• Supports many interrupt request sources
• Hysteresis-like control mode Timer T13 Features:
• One independent compare channel with one output
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Can be synchronized to T12
• Interrupt generation at period-match and compare-match
• Supports single-shot mode Additional Features:
• Implements block commutation for Brushless DC-drives
• Position detection via Hall-sensor pattern
• Automatic rotational speed measurement for block commutation
• Integrated error handling
• Fast emergency stop without CPU load via external signal (CTRAP
• Control modes for multi-channel AC-drives
• Output levels can be selected and adapted to the power stage

Data Sheet 86 V0.1, 2006-02 Prelimary The block diagram of the CCU6 module is shown in Figure 34. Figure 34 CCU6 Block Diagram channel 0 channel 1 channel 2 T12 dead- time control input / output control CC62 COUT62 CC61 COUT61 CC60 COUT60 COUT63 CTRAP channel 3T13 CCPOS0 2221 start compare capture multi- channel control address decoder clock control interrupt control trap control compare compar e compar e compar e trap input port control CCPOS1 CCPOS2 output select output select Ha ll input module kernel CCU6_block_diagram T13HR T12HR

Data Sheet 87 V0.1, 2006-02 Prelimary

3.18 Analog-to-Digital Converter

The XC886/888 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input channels of the ADC are available at Port 2. Features:

• Successive approximation
• 8-bit or 10-bit resolution (TUE of ± 1 LSB and ± 2 LSB, respectively)
• Eight analog channels
• Four independent result registers
• Result data protection for slow CPU access (wait-for-read mode)
• Single conversion mode
• Autoscan functionality
• Limit checking for conversion results
• Data reduction filter (accumulation of up to 2 conversion results)
• Two independent conversion reques t sources with programmable priority
• Selectable conversion request trigger
• Flexible interrupt generation with configurable service nodes
• Programmable sample time
• Programmable clock divider
• Cancel/restart feature for running conversions
• Integrated sample and hold circuitry
• Compensation of offset errors
• Low power modes

Data Sheet 88 V0.1, 2006-02 Prelimary

3.18.1 ADC Clocking Scheme

A common module clock f ADC generates the various clock signals used by the analog and digital parts of the ADC module:

• f ADCA is input clock for the analog part.
• f ADCI is internal clock for the analog part (defines the time base for conversion length and the sample time). This clock is generated internally in the analog part, based on the input clock fADCA to generate a correct duty cycle for the analog components.
• f ADCD is input clock for the digital part. The internal clock for the analog part fADCI is limited to a maximum frequency of 10 MHz. Therefore, the ADC clock prescaler must be programmed to a value that ensures fADCI does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required. Figure 35 ADC Clocking Scheme analog components fADCI fADC= fPCLK MUX arbiter registers interrupts analog part digital part fADCD fADCA 32÷ clock prescaler CTC ≤Condition: fADCI 10 MHz, where tADCI = fADCI

Data Sheet 89 V0.1, 2006-02 Prelimary For module clock fADC = 24 MHz, the analog clock f ADCI frequency can be selected as shown in Table 33. As fADCI cannot exceed 10 MHz, bit field CTC should not be set to 00 B when f ADC is 24 MHz. During slow-down mode where f ADC may be reduced to 12 MHz, 6 MHz etc., CTC can be set to 00 B as long as the divided analog clock f ADCI does not exceed 10 MHz. However, it is important to note that the conversion error could increase due to loss of charges on the capacitors, if fADC becomes too low during slow-down mode.

3.18.2 ADC Conversion Sequence

The analog-to-digital conversion procedure consists of the following phases:

• Synchronization phase (t SYN)
• Sample phase (t S)
• Conversion phase
• Write result phase (t WR) Figure 36 ADC Conv ersion Timing Table 33 f ADCI Frequency Selection Module Clock fADC CTC Prescaling Ratio Analog Clock f ADCI 24 MHz 00 B ÷ 2 12 MHz (N.A) 01B ÷3 8M H z 10B ÷4 6M H z 11B (default) ÷ 32 750 kHz tS tCONV tWR SAMPLE Bit BUSY Bit Conversion PhaseSample Phase Write Result Phase conversion start trigger Source interrupt Result interrupt tSYN Channel interrupt fADCI

Data Sheet 90 V0.1, 2006-02 Prelimary

3.19 On-Chip Debug Support

The On-Chip Debug Support (OCDS) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles:

• use the built-in debug functionality of the XC800 Core
• add a minimum of hardware overhead
• provide support for most of the operations by a Monitor Program
• use standard interfaces to communicate with the Host (a Debugger) Features:
• Set breakpoints on instruction addre ss and on address range within the Program Memory
• Set breakpoints on internal RAM address range
• Support unlimited software breakpoints in Flash/RAM code region
• Process external breaks via JTAG and upon activating a dedicated pin
• Step through the program code The OCDS functional blocks are shown in Figure 37. The Monitor Mode Control (MMC) block at the center of OCDS system brin gs together control signals and supports the overall functionality. The MMC communicates with the XC800 Core, primarily via the Debug Interface, and also receives reset and clock signals. After processing memory address and control signals from the core, the MMC provides proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for work-data and Monitor-stack). The OCDS system is accessed through the JTAG 1), which is an interface dedicated exclusively for testing and debugging activities and is not normally used in an application. The dedicated MBC pin is used for external configuration and debugging control. Note: All the debug functionality described here can normally be used only after XC886/ 888 has been started in OCDS mode. 1) The pins of the JTAG port can be assigned to either the primary port (Port 0) or either of the secondary ports (Ports 1 and 2/Port 5). User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.

Data Sheet 91 V0.1, 2006-02 Prelimary Figure 37 OCDS Block Diagram

3.19.1 JTAG ID Register

This is a read-only register located inside the JTAG module, and is used to recognize the device(s) connected to the JTAG interf ace. Its content is shifted out when INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is also true immediately after reset. The JTAG ID register contents for the XC886/888 Flash devices are given in Table 34. Note: The asterisk (*) above denotes all possible device configurations. Table 34 JTAG ID Summary Device Type Device Name JTAG ID Flash XC886/888*-8FF 1012 0083 H XC886/888*-6FF 1012 5083 H JTAG Module Monitor & Bootstrap loader Control line JTAG Memory Control Unit User Program Memory XC800 Core PROG & IRAM Addresses Debug Interface Reset Clock TMS TCK TDI TDO TCK TDI TDO Control Memory Control Debug Interface System Control Unit Boot/ Monitor ROM Monitor RAM User Internal RAM Reset Reset Clock PROG Data Monitor Mode Control MBC - parts of OCDS SuspendControl OCDS_XC886C-Block_Diagram-UM-v0.2

Data Sheet 92 V0.1, 2006-02 Prelimary

3.20 Identification Register

The XC886/888 identity register is located at Page 1 of address B3H. ID Identity Register Reset Value: 0000 1001 B 76543210 PRODID VERID rr Field Bits Type Description VERID [2:0] r Version ID 001B PRODID [7:3] r Product ID 00001B

Data Sheet 93 V0.1, 2006-02 Prelimary

4 Electrical Parameters

4.1 General Parameters

4.1.1 Parameter Interpretation

The parameters listed in this section represent partly the characteristics of the XC886/ 888 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the “Symbol” column:

• CC These parameters indicate Controller Characteristics, which are distinctive features of the XC886/888 and must be regarded for a system design.
• SR These parameters indicate System Requirements, which must be provided by the microcontroller system in which the XC886/888 designed in.

Data Sheet 94 V0.1, 2006-02 Prelimary Pr el im inar y

4.1.2 Absolute Maximum Rating

Maximum ratings are the extreme limits to which the XC886/888 can be subjected to without permanent damage. Table 35 Absolute Maximum Rating Parameters Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (V IN >V DDP or V IN <V SS) the voltage on VDDP pin with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Parameter Symbol Limit Values Unit Notes min. max. Ambient temperature TA -40 125 °C under bias Storage temperature TST -65 150 °C Junction temperature TJ -40 150 °C under bias Voltage on power supply pin with respect to VSS VDDP -0.5 6 V Input current on any pin during overload condition IIN -10 10 mA Absolute sum of all input currents during overload condition Σ|IIN|– t b d m A

Data Sheet 95 V0.1, 2006-02 Prelimary Pr el im inar y

4.1.3 Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation of the XC886/888. All parameters mentioned in the following table refer to these operating conditions, unless otherwise noted. Table 36 Operating Condition Parameters Parameter Symbol Limit Values Unit Notes/ Conditionsmin. max. Digital power supply voltage VDDP 4.5 5.5 V 5V range 3.0 3.6 V 3.3V range Digital ground voltage VSS 0V Digital core supply voltage VDDC 2.3 2.7 V System Clock Frequency1) 1) fSYS is the PLL output clock. During normal operating mode, CPU clock is fSYS / 4. Please refer to Figure 27 for detailed description. fSYS 88.8 103.2 MHz Ambient temperature TA -40 85 °C SAF-XC886/ 888... -40 125 °C SAK-XC886/ 888...

Data Sheet 96 V0.1, 2006-02 Prelimary Pr el im inar y

4.2 DC Parameters

4.2.1 Input/Output Characteristics

Table 37 Input/Output Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max. V DDP = 5V Range Output low voltage VOL CC – 1.0 V IOL =1 5m A –0 . 4 V IOL =5m A Output high voltage VOH CC VDDP - 1.0 –V IOH =- 1 5m A VDDP - 0.4 –V IOH =- 5m A Input low voltage on port pins (all except P0.0 & P0.1) VILP SR – 0.3 × VDDP V CMOS Mode Input low voltage on P0.0 & P0.1 VILP0 SR -0.2 0.3 × VDDP V CMOS Mode Input high voltage on port pins (all except P0.0 & P0.1) VIHP SR 0.7 × VDDP –V C M O S M o d e Input high voltage on P0.0 & P0.1 VIHP0 SR 0.7 × VDDP VDDP V CMOS Mode Input Hysteresis1) HYS CC 0.08 × VDDP –V C M O S M o d e Pull-up current IPU SR – -10 µA VIH,min -150 – µA VIL,max Pull-down current IPD SR – 10 µA VIL,max 150 – µA VIH,min Input leakage current2) IOZ1 CC -1 1 µA 0 < VIN < VDDP, TA ≤ 125°C Overload current on any pin IOV SR -5 5 mA Absolute sum of overload currents Σ|IOV| SR –t b d m A 3)

Data Sheet 97 V0.1, 2006-02 Prelimary Pr el im inar y V DDP = 3.3V Range Output low voltage VOL CC – 1.0 V IOL =8m A –0 . 4 V IOL =2 . 5m A Output high voltage VOH CC VDDP - 1.0 –V IOH =- 8m A VDDP - 0.4 –V IOH =- 2 . 5m A Input low voltage on port pins (all except P0.0 & P0.1) VILP SR – 0.3 × VDDP V CMOS Mode Input low voltage on P0.0 & P0.1 VILP0 SR -0.2 0.3 × VDDP V CMOS Mode Input high voltage on port pins (all except P0.0 & P0.1) VIHP SR 0.7 × VDDP –V C M O S M o d e Input high voltage on P0.0 & P0.1 VIHP0 SR 0.7 × VDDP VDDP V CMOS Mode Input Hysteresis1) HYS CC 0.03 × VDDP –V C M O S M o d e Pull-up current IPU SR – -5 µA VIH,min -50 – µA VIL,max Pull-down current IPD SR – 5 µA VIL,max 50 – µA VIH,min Input leakage current2) IOZ1 CC -1 1 µA 0 < VIN < VDDP, TA ≤ 125°C Overload current on any pin IOV SR -5 5 mA Absolute sum of overload currents Σ|IOV| SR –t b d m A 3) 1) Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. 2) An additional error current ( IINJ) will flow if an overload current flows through an adjacent pin. TMS pin and RESET pin have internal pull devices and are not included in the input leakage current characteristic. Table 37 Input/Output Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max.

Data Sheet 98 V0.1, 2006-02 Prelimary Pr el im inar y

4.2.2 Supply Threshold Characteristics

Figure 38 Supply Threshold Parameters 3) Not subjected to production test, verified by design/characterization. Table 38 Supply Threshold Parameters (Operating Conditions apply) Parameters Symbol Limit Values Unit min. typ. max. VDDC prewarning voltage1) 1) Detection is disabled in power-down mode. VDDCPW CC 2.2 2.3 2.4 V VDDC brownout voltage in active mode1) VDDCBO CC 2.0 2.1 2.2 V RAM data retention voltage V DDCRDR CC 0.9 1.0 1.1 V VDDC brownout voltage in power-down mode2) 2) Detection is enabled in both active and power-down mode. VDDCBOPD CC 1.3 1.5 1.7 V VDDP prewarning voltage3) 3) Detection is enabled for external power supply of 5.0V. Detection must be disabled for external power supply of 3.3V. VDDPPW CC 3.4 4.0 4.6 V Power-on reset voltage2)4) 4) The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage. VDDCPOR CC 1.3 1.5 1.7 V VDDP VDDC VDDPPW VDDCPOR VDDCPW VDDCBO VDDCBOPD 5.0V 2.5V VDDCRDR

Data Sheet 99 V0.1, 2006-02 Prelimary Pr el im inar y

4.2.3 ADC Characteristics

The values in the table below are given for an analog power supply between 4.5 V to 5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case, the analog parameters may show a reduced performance. All ground pins (VSS) must be externally connected to one single star point in the system. The vo ltage difference between the ground pins must not exceed 200mV. Table 39 ADC Characteristics (Ope rating Conditions apply; V DDP = 5V Range) Parameter Symbol Limit Values Unit Test Conditions/ Remarksmin. typ . max. Analog reference voltage VAREF SR VAGND + 1 VDDP VDDP + 0.05 V Analog reference ground VAGND SR VSS - 0.05 VSS VAREF - 1 V Analog input voltage range VAIN SR VAGND – VAREF V ADC clocks f ADC – 24 25.8 MHz module clock fADCI – – 10 MHz internal analog clock See Figure 35 Sample time tS CC (2 + INPCR0.STC) × tADCI µs Conversion time tC CC See Section 4.2.3.1 µs Total unadjusted error TUE1)CC – – ±1 LSB 8-bit conversion. 2) –– ±2 LSB 10-bit conversion. Switched capacitance at the reference voltage input C AREFSW CC –1 0 2 0 p F 2)3) Switched capacitance at the analog voltage inputs C AINSW CC –5 7 p F 2)4) Input resistance of the reference input RAREFCC – 1 2 k Ω 2) Input resistance of the selected analog channel RAIN CC – 1 1.5 k Ω 2)

Data Sheet 100 V0.1, 2006-02 Prelimary Pr el im inar y Figure 39 ADC Input Circuits 1) TUE is tested at VAREF =5 . 0V , VAGND =0V , VDDP =5 . 0V . 2) Not subject to production test, verified by design/characterization 3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this, smaller capacitances are successively switched to the reference voltage. 4) The sampling capacity of the conversion C-Network is pre-charged to V AREF/2 before connecting the input to the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2. VAGNDx REXT Analog Input Circuitry VAIN CEXT ANx CAINSW RAIN, On VAGNDx Reference Voltage Input Circuitry CAREFSW RAREF, OnVAREFx VAREF

Data Sheet 101 V0.1, 2006-02 Prelimary Pr el im inar y

4.2.3.1 ADC Conversion Timing

Conversion time, tC =t ADC × ( 1 + r × (3 + n + STC) ) , where r = CTC + 2 for CTC = 00B, 01B or 10B, r = 32 for CTC = 11B, CTC = Conversion Time Control (GLOBCTR.CTC), STC = Sample Time Control (INPCR0.STC), n = 8 or 10 (for 8-bit and 10-bit conversion respectively), tADC =1/f ADC

Data Sheet 102 V0.1, 2006-02 Prelimary Pr el im inar y

4.2.4 Power Supply Current

Table 40 Power Supply Current Parameters (Operating Conditions apply; V DDP = 5V range ) Parameter Symbol Limit Values Unit Test Condition typ.1) 1) The typical IDDP values are based on prelimary measurements and are to be used as reference only. These values are periodically measured at TA =+2 5 °C and VDDP =5 . 0V . max.2) 2) The maximum IDDP values are measured under worst case conditions (TA = + 125 °C and VDDP =5 . 5V ) . V DDP = 5V Range Active Mode IDDP 29 tbd mA 3) 3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz(set by on-chip oscillator of 9.6 MHz and NDIV in PLL_CON to 1001B), RESET = VDDP. Idle Mode IDDP 21.1 tbd mA 4) 4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 24 MHz, RESET = VDDP. Active Mode with slow-down enabled IDDP tbd tbd mA 5) 5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals running at 8 MHz by setting CLKREL in CMCON to 0110B, RESET = VDDP. Idle Mode with slow-down enabled IDDP tbd tbd mA 6) 6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 8 MHz by setting CLKREL in CMCON to 0110 B, RESET = VDDP. Power-Down Mode IPDP 10 tbd µA 7) 7) IPDP (power-down mode) is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs.

Data Sheet 103 V0.1, 2006-02 Prelimary Pr el im inar y Table 41 Power Supply Current Parameters (Operating Conditions apply; V DDP = 3.3V range) Parameter Symbol Limit Values Unit Test Condition typ.1) 1) The typical IDDP values are periodically measured at TA =+2 5 °C and VDDP =3 . 3V . max.2) 2) The maximum IDDP values are measured under worst case conditions (TA = + 125 °C and VDDP =3 . 6V ) . V DDP = 3.3V Range Active Mode IDDP tbd tbd mA 3) 3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz(set by on-chip oscillator of 9.6 MHz and NDIV in PLL_CON to 1001B), RESET = VDDP. Idle Mode IDDP tbd tbd mA 4) 4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 24 MHz, RESET = VDDP. Active Mode with slow-down enabled IDDP tbd tbd mA 5) 5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals running at 8 MHz by setting CLKREL in CMCON to 0110B, RESET = VDDP. Idle Mode with slow-down enabled IDDP tbd tbd mA 6) 6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 8 MHz by setting CLKREL in CMCON to 0110 B,, RESET = VDDP. Power-Down Mode IPDP tbd tbd µA 7) 7) IPDP (power-down mode) is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0= VDDP; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs

Data Sheet 104 V0.1, 2006-02 Prelimary Pr el im inar y

4.3 AC Parameters

4.3.1 Testing Waveforms

The testing waveforms for rise/fall time, output delay and output high impedance are shown in Figure 40, Figure 41 and Figure 42. Figure 40 Rise/Fall Time Parameters Figure 41 Testing Waveform, Output Delay Figure 42 Testing Waveform, Output High Impedance 10% 90% 10% 90% VSS VDDP tR tF VDDE / 2 Test Points VDDE / 2 VSS VDDP VLoad + 0.1 V VOH - 0.1 VTiming Reference PointsVLoad - 0.1 V VOL - 0.1 V

Data Sheet 105 V0.1, 2006-02 Prelimary Pr el im inar y

4.3.2 Output Rise/Fall Times

Figure 43 Rise/Fall Times Parameters Table 42 Output Rise/Fall Times Parameters (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max. V DDP = 5V Range Rise/fall times 1) 2) 1) Rise/Fall time measurements are taken with 10% - 90% of the pad supply. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. tR, tF – 10 ns 20 pF. 3) 3) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.125 ns/pF. V DDP = 3.3V Range Rise/fall times 1) 2) tR, tF – 10 ns 20 pF. 4) 4) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.225 ns/pF. tR 10% 90% 10% 90% tF VSS VDDP

Data Sheet 106 V0.1, 2006-02 Prelimary Pr el im inar y

4.3.3 Power-on Reset and PLL Timing

Table 43 Power-On Reset and PLL Timing (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Pad operating voltage VPAD CC 2.3 – – V On-Chip Oscillator start-up time tOSCST CC ––5 0 0 n s Flash initialization time tFINIT CC – 160 – µs RESET hold time1) 1) RESET signal has to be active (low) until VDDC has reached 90% of its maximum value (typ. 2.5V). tRST SR – 500 – µs VDDP rise time PLL lock-in in time tLOCK CC – – 200 µs PLL accumulated jitter DP ––t b d n s 2) 2) PLL lock at 96 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 48 and P = 1.

Data Sheet 107 V0.1, 2006-02 Prelimary Pr el im inar y Figure 4-1 Power-on Reset Timing VDDP Pads VDDC VPAD OSC tOSCST PLL Reset Initialization Ready to ReadFlash State PLL unlock PLL lock 2) 3) tLOC K tFINIT 1)Pad state undefined 2)ENPS control 3)As Programmed I)until EVR is s table II)until PLL is locked III) until Flash go to Ready-to-Read IV) CPU reset is released; Boot ROM software begin execution RESET tRST

Data Sheet 108 V0.1, 2006-02 Prelimary Pr el im inar y

4.3.4 On-Chip Oscillator Characteristics

Table 44 On-chip Oscillator Characteri stics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Nominal frequency fNOM CC – 9.6 – MHz under nominal conditions1) after IFX-backend trimming 1) Nominal condition: VDDC =2 . 5V , TA =+2 5 °C. Chip-to-chip frequency deviation ∆fCC CC -2.5 – 2.5 % with respect to fNOM Long term frequency deviation ∆fLT CC -5.0 – 5.0 % with respect to fNOM, over lifetime and temperature, for one given device after trimming Short term frequency deviation ∆fST CC -1.0 – 1.0 % with respect to fNOM, within one LIN message

Data Sheet 109 V0.1, 2006-02 Prelimary Pr el im inar y

4.3.5 JTAG Timing

Table 45 TCK Clock Timing (Operating Conditions apply; CL = 50 pF) Figure 44 TCK Clock Timing Parameter Symbol Limits Unit min max TCK clock period tTCK SR 50 − ns TCK high time t1 SR tbd − ns TCK low time t2 SR tbd − ns TCK clock rise time t3 SR − tbd ns TCK clock fall time t4 SR − tbd ns TCK

0.9 VDDP

0.1 VDDP

0.5 VDDP

Data Sheet 110 V0.1, 2006-02 Prelimary Pr el im inar y Table 46 JTAG Timing (Operating Conditions apply; CL =5 0 p F ) Figure 45 JTAG Timing Parameter Symbol Limits Unit min max TMS setup to TCK t1 SR tbd − ns TMS hold to TCK t2 SR tbd − ns TDI setup to TCK t1 SR tbd − ns TDI hold to TCK t2 SR tbd − ns TDO valid output from TCK t3 CC − tbd ns TDO high impedance to valid output from TCK t4 CC − tbd ns TDO valid output to high impedance from TCK t5 CC − tbd ns TMS TDI TCK TDO t4 t3 t5

Data Sheet 111 V0.1, 2006-02 Prelimary Pr el im inar y

4.3.6 SSC Master Mode Timing

Table 47 SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF) Figure 46 SSC Master Mode Timing Parameter Symbol Limit Values Unit min. max. SCLK clock period t0 CC 2*T SSC 1) 1) TSSCmin =T CPU =1 / fCPU. When fCPU = 24MHz, t0 = 83.3ns. TCPU is the CPU clock period. –n s MTSR delay from SCLK t1 CC 0 tbd ns MRST setup to SCLK t2 SR tbd – ns MRST hold from SCLK t3 SR tbd – ns SSC_Tmg1 SCLK1) MTSR1) t1 t1 MRST1) Data valid 1) This timing is based on the following setup: CON.PH = CON.PO = 0.

Package and Quality Declaration Data Sheet 112 V0.1, 2006-02 Prelimary Pr el im inar y

5 Package and Quality Declaration

5.1 Package Outline

Figure 47 PG-TQFP-48-4 Package Outline

Package and Quality Declaration Data Sheet 113 V0.1, 2006-02 Prelimary Pr el im inar y Figure 48 PG-TQFP-64-8 Package Outline

Package and Quality Declaration Data Sheet 114 V0.1, 2006-02 Prelimary Pr el im inar y

5.2 Quality Declaration

Table 48 shows the characteristics of the quality parameters in the XC886/888. Table 48 Quality Parameters Parameter Symbol Limit Values Unit Notes Min. Max. ESD susceptibility according to Human Body Model (HBM) VHBM – 2000 V Conforming to EIA/JESD22- A114-B ESD susceptibility according to Charged Device Model (CDM) pins VCDM – 500 V Conforming to JESD22-C101-C

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