XC864

XC864 INFINEON | Alldatasheet

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V1.1 2009-03 Microcontrollers 8-Bit XC864 8-Bit Single-Chip Microcontroller

81726 Munich, Germany

© 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

V1.1 2009-03 Microcontrollers 8-Bit XC864 8-Bit Single-Chip Microcontroller

Revision History: 2009-03 V1 . 1 Previous Version: V1.0 Page Subjects (major chan ges since last revision) Changes from V1.0 2008-08 to V1.1 2009-03

3 Modified the paragraph to remove the Automotive quality profile

We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

Data Sheet 1 V 1.1, 2009-03 XC8648-Bit Single-Chip Microcontroller XC800 Family

1 Summary of Features

• High-performance XC800 Core – compatible with st andard 8051 processor – two clocks per machine cy cle architecture (for memory access without wait state) – two data pointers
• On-chip memory – 8 Kbytes of Boot ROM – 256 bytes of RAM – 512 bytes of XRAM – 4 Kbytes of Flash for code (and data) (includes memory protection strategy)
• I/O port supply at 3.3 V/5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator) (further features are on next page) Figure 1 XC864 Functional Units Port 0 Port 1 Port 2 Port 3 XC800 Core UART ADC 10-bit 4-channel Boot ROM 8K Bytes XRAM

512 Bytes

256 Bytes

4-bit Digital/Analog Input

Data Sheet 2 V 1.1, 2009-03 Features (continued):

• Reset generation – Power-On reset – Hardware reset – Brownout reset for core logic supply – Watchdog timer reset – Power-Down Wake-up reset
• On-chip OSC and PLL for clock generation – PLL loss-of-lock detection
• Power saving modes – slow-down mode – idle mode – power-down mode wit h wake-up capability via RXD or EXINT0 – clock gating control to each peripheral
• Programmable 16-bit Watchdog Timer (WDT)
• Four ports – 9 pins as digital I/O – 4 pins as digital/analog input
• 4-channel, 8-bit ADC
• Three 16-bit timers – Timer 0 and Time r 1 (T0 and T1) –T i m e r 2
• Capture/compare unit for PW M signal generation (CCU6)
• Full-duplex serial interface (UART)
• Synchronous serial channel (SSC)
• On-chip debug support – 1 Kbyte of monitor ROM (par t of the 8-Kbyte Boot ROM) – 64 bytes of monitor RAM
• PG-TSSOP-20 pin package
• Ambient temp erature range T – SAF (-40 to 85 °C) – SAK (-40 to 125 °C)

Data Sheet 3 V 1.1, 2009-03 XC864 Variant Devices The XC864 product family features devic es with different pow er supply range and temperature, offering cost-effective soluti on for different application requirements. The package type available is TSSOP-20. Table 1-1 summarizes the list of XC864 devices.

Ordering Information

The ordering code for Infineo n Technologies microcontrol lers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the package and th e type of delivery For the available ordering codes for the XC864, please refer to your responsible sales representative or your local distributor. As this document refers to all the derivatives, some de scriptions may no t apply to a specific product. For simplicity all versions are referred to by the term XC864 throughout this document. Table 1-1 Device Profile Sales Type Device Type Program Memory (Kbytes) Power Supply (V) Temp- erature Profile (°C) Quality Profile SAK-XC864L-1FRI 5V Flash 4 5.0 -40 to 125 Industrial SAK-XC864L-1FRI 3V3 Flash 4 3.3 -40 to 125 Industrial SAF-XC864L-1FRI 5V Flash 4 5.0 -40 to 85 Industrial SAF-XC864L-1FRI 3V3 Flash 4 3.3 -40 to 85 Industrial

General Device Information Data Sheet 4 V 1.1, 2009-03

2 General Device Information

2.1 Block Diagram

Figure 2 XC864 Block Diagram ADC Port 0Port 1Port 2Port 3 CCU6 Timer 2 SSC WDT OCDS 8-Kbyte Boot ROM1) 256-byte RAM 64-byte monitor RAM 512-byte XRAM 4-Kbyte Flash XC800 Core T0 & T1 UART 1) Includes 1-Kbyte monitor ROM P0.0 - P0.5 P1.0/ P1.1 P3.0 - P3.1 P2.0 - P2.2, P2.7 VAREF VAGND/VSSPClock Generator

10 MHz

General Device Information Data Sheet 5 V 1.1, 2009-03

2.2 Logic Symbol

Figure 3 XC864 Logic Symbol XC864 VDDP VSSP/VAGND VDDC VSSC VAREF TMS RESET Port 0 6-Bit Port 1 1-Bit Port 3 2-Bit Port 2 4-Bit

General Device Information Data Sheet 6 V 1.1, 2009-03

2.3 Pin Configuration

The pin configuration of t he XC864, which is based on the PG-TSSOP-20 package, is shown in Figure 4. Every package pin is bonded to an input port pin or a bidirectional port pin except Pin 15. It is bonded to 2 bidirect ional port pins namely, P1.0 and P1.1. Configurations of both port pins to output direction concurrently must be avoided to prevent permanent damage to the chip1). In addition, open drain output mode with pull-up device en abled is recommended for P1.1 as TXD function and input mode for P1 .0 as RXD function in single wire UART communication. Figure 4 XC864 Pin Configurat ion, PG-TSSOP-20 Package (top view) 1) Protection against improper usage of P1.0 and P1.1 is not available in XC864. P0.0/TCK_0/T12HR_1/CC61_1/CLKOUT/RXDO_1 10 11 XC864 P2.0/CCPOS0_0/EXINT1/T12HR_2/TCK_1/CC61_3/AN0 P0.2/CTRAP_2/TDO_0/TXD_1 P0.3/SCK_1/COUT63_1 P0.4/MTSR_1/CC62_1P0.5/MRST_1/EXINT0_0/COUT62_1 P1.0/RXD_0/T2EX/ P1.1/EXINT3/TDO_1/TXD_0/T0 P2.1/CCPOS1_0/EXINT2/T13HR_2/TDI_1/CC62_3/AN1 P2.2/CCPOS2_0/CTRAP_1/CC60_3/AN2 P2.7/AN7 P3.0/CC60_0/CCPOS1_2 P3.1/CCPOS0_2/CC61_2/COUT60_0 VDDP VDDC VSSC VAREF VAGND/VSSP TMS P0.1/TDI_0/T13HR_1/RXD_1/EXF2_1/COUT61_1 RESET

General Device Information Data Sheet 7 V 1.1, 2009-03

2.4 Pin Definitions and Functions

Table 1 Pin Definiti ons and Functions Symbol Pin Number Type Reset State Function P0 I/O Port 0 Port 0 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, Timer 2 and SSC. P0.0 5 Hi-Z TCK_0 T12HR_1 CC61_1 CLKOUT_0 RXDO_1 JTAG Clock Input CCU6 Timer 12 Hardware Run Input Input/Output of Capture/ Compare channel 1 Clock Output UART Transmit Data Output P0.1 7 Hi-Z TDI_0 T13HR_1 RXD_1 COUT61_1 EXF2_1 JTAG Serial Data Input CCU6 Timer 13 Hardware Run Input UART Receive Data Input Output of Capture/Compare channel 1 Timer 2 External Flag Output P0.2 6 PU CTRAP_2 TDO_0 TXD_1 CCU6 Trap Input JTAG Serial Data Output UART Transmit Data Output/ Clock Output P0.3 19 Hi-Z SCK_1 COUT63_1 SSC Clock Input/Output Output of Capture/Compare channel 3 P0.4 20 Hi-Z MTSR_1 CC62_1 SSC Master Transmit Output/ Slave Receive Input Input/Output of Capture/ Compare channel 2 P0.5 1 Hi-Z MRST_1 EXINT0_0 COUT62_1 SSC Master Receive Input/Slave Transmit Output External Interrupt Input 0 Output of Capture/Compare channel 2

General Device Information Data Sheet 8 V 1.1, 2009-03 P1 I/O Port 1 Port 1 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, Timer 0, Timer 2 and SSC. P1.0/ P1.1

15 PU RXD_0

TDO_1 TXD_0 UART Receive Data Input Timer 2 External Trigger Input External Interrupt Input 3 Timer 0 Input JTAG Serial Data Output UART Transmit Data Output/ Clock Output Note: Pin 15 is bonded to both P1.0 and P1.1 port pins. See Section 2.3 on the types of port pin configuration to be avoided to prevent permanent damage. Table 1 Pin Definiti ons and Functions (cont’d) Symbol Pin Number Type Reset State Function

General Device Information Data Sheet 9 V 1.1, 2009-03 P2 I Port 2 Port 2 is an 8-bit general purpose input-only port. It can be used as alternate functions for the digital inputs of the JTAG and CCU6. It is also used as the analog inputs for the ADC. P2.0 8 Hi-Z CCPOS0_0 EXINT1_0 T12HR_2 TCK_1 CC61_3 AN0 CCU6 Hall Input 0 External Interrupt Input 1 CCU6 Timer 12 Hardware Run Input JTAG Clock Input Input of Capture/Compare channel 1 Analog Input 0 P2.1 9 Hi-Z CCPOS1_0 EXINT2_0 T13HR_2 TDI_1 CC62_3 AN1 CCU6 Hall Input 1 External Interrupt Input 2 CCU6 Timer 13 Hardware Run Input JTAG Serial Data Input Input of Capture/Compare channel 2 Analog Input 1 P2.2 10 Hi-Z CCPOS2_0 CTRAP_1 CC60_3 AN2 CCU6 Hall Input 2 CCU6 Trap Input Input of Capture/Compare channel 0 Analog Input 2 P2.7 14 Hi-Z AN7 Analog Input 7 Table 1 Pin Definiti ons and Functions (cont’d) Symbol Pin Number Type Reset State Function

General Device Information Data Sheet 10 V 1.1, 2009-03 P3 I/O Port 3 Port 3 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6. P3.0 16 Hi-Z CCPOS1_2 CC60_0 CCU6 Hall Input 1 Input/Output of Capture/ Compare channel 0 P3.1 17 Hi-Z CCPOS0_2 CC61_2 COUT60_0 CCU6 Hall Input 0 Input/Output of Capture/ Compare channel 1 Output of Capture/Compare channel 0 VDDP 11 – – I/O Port Supply (3.3 or 5.0 V) Also used by EVR and analog modules. All pins must be connected. VDDC 3– – Core Supply Monitor (2.5 V) VSSC 2– – Core Supply Ground VAREF 13 – – ADC Reference Voltage VAGND/ VSSP 12 – – ADC Reference Ground/ I/O Ground All pins must be connected. TMS 4I P D Test Mode Select RESET 18 I PU Reset Input Table 1 Pin Definiti ons and Functions (cont’d) Symbol Pin Number Type Reset State Function

Data Sheet 11 V 1.1, 2009-03

3 Functional Description

3.1 Processor Architecture

The XC864 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standar d 8051 processor. While t he standard 8051 processor is designed around a 12-clock machine cycle, the XC864 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM me mories without wait state. Access to the Flash memory, however, requires an additional wait state (one machine cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. The XC864 CPU provides a r ange of debugging features, including basic stop/start, single-step execution, break point support and r ead/write access to the data memory, program memory and SFRs. Figure 5 shows the CPU functional blocks. Figure 5 CPU Block Diagram Register Interface ALU UART Core SFRs 16-bit Registers & Memory Interface Opcode Decoder State Machine & Power Saving Interrupt Controller Multiplier / Divider Opcode & Immediate Registers Timer 0 / Timer 1 Internal Data Memory External SFRs External Data Memory Program Memory fCCLK Memory Wait Reset Legacy External Interrupts (IEN0, IEN1) External Interrupts Non-Maskable Interrupt

Data Sheet 12 V 1.1, 2009-03

3.2 Memory Organization

The XC864 consists of four types of memory:

• 8 Kbytes of Boot ROM program memory
• 256 bytes of inter nal RAM data memory
• 512 bytes of XRAM memory (XRAM can be read/written as program memory or external data memory)
• 128 Special Function Register
• 4 Kbytes of Flash for code (and data) Figure 6 illustrates the memory map of the address spaces of the XC864-1FR device. Figure 6 Memory Map of XC864 0000H 1000H 2000H 3000H F000H C000H E000H F200H FFFFH A000H B000H Boot ROM

8 Kbytes

Program Space External Data Space Internal Data Space Internal RAM XRAM 512 bytes 7FH Internal RAM Flash (overlayed )

4 Kbytes 1)

1) For XC864 device, physically one 4KByte Flash bank is mapped to both address range 0000 H - 0 FFFH and A000 H - AFFFH.

Data Sheet 13 V 1.1, 2009-03

3.2.1 Memory Protection Strategy

The XC864 memory protection strategy includes:

• Read-out protection: The user is able to protect the contents in the Flash memory from being read
• Flash program and erase protection: The Flash memory in all devices can be enabled for program and erase protection
• Block external access and allow only boot in User Mode: Disable BSL and OCDS modes. Flash memory protection modes provided are:
• Mode 0: Protect against accidental erase and block external access.
• Mode 1: Read, program and erase protection are enabled, and block external access. Flash protection is enabled by installing the user passw ord via BSL mode 6. The user setting of password for selection of each protection mode and the restrictions imposed are summarized in Table 2. Flash protection mode 1 is m eaningful only if the Flash is used for code only. Otherwise if the Flash is used partially for code and partially for data, then only Flash protection mode 0 is meaningful. Note: In XC864, the type of Flash protection scheme will affect the entering of BSL Mode once User Mode is entered. Table 2 Flash Protection Modes Mode 01 Selection MSB of password = 0 MSB of password = 1 Flash contents can be read by Read instructions in any program memory Read instructions in Flash Flash program Possible Not possible

Data Sheet 14 V 1.1, 2009-03 BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed pa ssword must be provided by the user. A password match triggers an automatic erase of the r ead-protected Flash contents (sector(s) to erase is defined by password, see Table 3), and the programmed password is erased. The Flash protection is then disabled upon the next reset. Flash erase Possible, on condition that bit DFLASHEN in register MISC_CON is set to 1 prior to each erase operation Not possible Additional Protection Block external access (can only start in User Mode) Block external access (can only start in User Mode) Subsequent entering of BSL mode with LSB of password is 1 Possible 1); For detailed descriptions, see “User Mode Entry 2” on Page 59 Possible; For detailed descriptions, see “User Mode Entry 2” on Page 59 |Subsequent entering of BSL mode with LSB of password is 0 Not possible 1) Not possible 1) With MSB of password = 0, Flash content can be upgraded using a predefined routine in the user code via In- Application Programming(IAP). Progra mming via BSL mode is not needed. See “User Mode Entry 3” on Page 60. Table 2 Flash Protection Modes (cont’d)

Data Sheet 15 V 1.1, 2009-03 Although no protection scheme can be cons idered infallible, the XC864 memory protection strategy provides a very high level of prot ection for a general purpose microcontroller. Table 3 Password Definition Password To Enable Protection: Type of Hardware Protection1) 1) On the whole Flash. This hardware protection is complimented by the ‘block external access’ feature (see Table 2). To Remove Protection: Sectors to Erase2) before Remove Hardware Protection 2) Controlled automatically by BSL mode 6 routine in Boot ROM, based on the password previously installed by the user when enabling Flash protection. 1XXXXXXXB Read/Program/Erase All Sectors 00001XXXB Erase Sector 0 00010XXXB Erase Sector 0 and 1 00011XXXB Erase Sector 0 to 2 00100XXXB Erase Sector 0 to 3 00101XXXB Erase Sector 0 to 4 00110XXXB Erase Sector 0 to 5 00111XXXB Erase Sector 0 to 6 01000XXXB Erase Sector 0 to 7 01001XXXB Erase Sector 0 to 8 01010XXXB Erase All Sector Others Erase None

Data Sheet 16 V 1.1, 2009-03

3.2.2 Special Function Register

The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80H to FFH. All registers, except the program counter, reside in the SFR area. The SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than th e total number of registers required, address extension mechanisms ar e required to increa se the number of addressable SFRs. The address extension mechanisms include:

• Mapping
• Paging

3.2.2.1 Address Extension by Mapping

Address extension is performed at the syst em level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80 H to FFH, bringing the number of addressable SFRs to 256. The extended addre ss range is not directly controlled by the CPU instruction itself, bu t is derived from bit RMAP in the system control register SYSCON0 at address 8F H. To access SFRs in the m apped area, bit RMAP in SFR SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 7. SYSCON0 System Control Register 0 Reset Value: 04H 7654 32 10 01 0 R M A P rr w r r w Field Bits Type Description RMAP 0r w Special Function Register Map Control

0 The access to the st andard SFR area is

enabled.

1 The access to the m apped SFR area is

enabled. 1 2r w Reserved Returns the last value if read; should be written with 1. 0 1,[7:3] r Reserved Returns 0 if read; should be written with 0.

Data Sheet 17 V 1.1, 2009-03 Note: The RMAP bit must be cleared/set by ANL or ORL instructions. As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus , before standard/ma pped registers are accessed, bit RMAP must be cleared/set, respectively, by software. Figure 7 Address Extension by Mapping Module 1 SFRs …... SYSCON0.RMAP SFR Data (to/from CPU) rw Standard Area (RMAP = 0) …... 80H FFH 80H FFH Direct Internal Data Memory Address Mapped Area (RMAP = 1) Module 2 SFRs Module n SFRs Module (n+1) SFRs Module (n+2) SFRs Module m SFRs

Data Sheet 18 V 1.1, 2009-03

3.2.2.2 Address Extension by Paging

Address extension is further performed at the module level by paging. With the address extension by mapping, the XC864 has a 256-SFR address r ange. However, this is still less than the total number of SFRs needed by the on-chi p peripherals. To meet this requirement, some peripherals have a built-i n local address extens ion mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bi t field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SF Rs per page, dependi ng on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 8. Figure 8 Address Exte nsion by Paging SFR0 SFR1 SFRx …... PAGE 0 SFR0 SFR1 SFRy …... PAGE 1 …... SFR0 SFR1 SFRz …... PAGE q MOD_PAGE.PAGE SFR Address (from CPU) SFR Data (to/from CPU) rw Module

Data Sheet 19 V 1.1, 2009-03 In order to access a register located in a page different from the actual one, the current page must be left. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed. If an interrupt routine is initiated be tween the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the ne w one programmed and finally, the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can:

• Save the contents of PAGE in STx bef ore overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or
• Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to rest ore the previous page setting before the interrupt occurred) Figure 9 Storage El ements for Paging With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write oper ations makes the system simp ler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The XC864 supports local address extension for:
• Parallel Ports
• Analog-to-Digital Converter (ADC)
• Capture/Compare Unit 6 (CCU6)
• System Control Registers The page register has the following definition: PAGE ST0 ST1 ST2 ST3 value update from CPU STNR

Data Sheet 20 V 1.1, 2009-03 MOD_PAGE Page Register for module MOD Reset Value: 00H 7654 32 10 OP STNR 0 PAGE ww rr w h Field Bits Type Description PAGE [2:0] rwh Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. STNR [5:4] w Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11 the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 ST0 is selected. 01 ST1 is selected. 10 ST2 is selected. 11 ST3 is selected. OP [7:6] w Operation 0X Manual page mode. Th e value of STNR is ignored and PAGE is directly written.

10 New page programming with automatic page

saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR.

Data Sheet 21 V 1.1, 2009-03 0 3r Reserved Returns 0 if read; should be written with 0. Field Bits Type Description

Data Sheet 22 V 1.1, 2009-03

3.2.3 Bit Protection Scheme

The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit field PASS closes access to writing of all protected bits. Note that access is opened for maximum 32 CCLKs if the “close access” password is not writt en. If “open access” password is written again before the end of 32 CCLK cycles , there will be a recount of 32 CCLK cycles. The protected bits include NDIV, WDTEN, PD, and SD. PASSWD Password Register Reset Value: 07 H 76543210 PASS PROTECT _S MODE wr h r w Field Bits Type Description MODE [1:0] rw Bit Protection Scheme Control bits

00 Scheme Disabled

11 Scheme Enabled (default)

Others: Scheme Enabled These two bits cannot be written directly. To change the value between 11 B and 00B, the bit field PASS must be written with 11000B; only then, will the MODE[1:0] be registered. PROTECT_S 2r h Bit Protection Signal Status bit This bit shows the status of the protection. 0 Software is able to writ e to all protected bits.

1 Software is unable to write to any protected

bits. PASS [7:3] w Password bits The Bit Protection Scheme only recognizes three patterns. 11000 B Enables writing of the bit field MODE. 10011B Opens access to writing of all protected bits. 10101B Closes access to writing of all protected bits.

Data Sheet 23 V 1.1, 2009-03

3.2.4 XC864 Register Overview

The SFRs of the XC864 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Table 4 to Table 12, with the addresses of the bitaddressable SFRs appearing in bold typeface. Note: Bits marked as 0 or 1 must be initialized per se, the functionality of the device with the other setting is not guaranteed. The CPU SFRs can be accessed in both the standard and ma pped memory areas (RMAP = 0 or 1). Table 4 CPU Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 or 1 81H SP Reset: 07 H Stack Pointer Register Bit Field SP Type rw 82H DPL Reset: 00 H Data Pointer Register Low Bit Field DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0 Type rw rw rw rw rw rw rw rw 83H DPH Reset: 00 H Data Pointer Register High Bit Field DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0 Type rw rw rw rw rw rw rw rw 87H PCON Reset: 00 H Power Control Register Bit Field SMOD 0 GF1 GF0 0 IDLE Type rw r rw rw r rw 88H TCON Reset: 00 H Timer Control Register Bit Field TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Type rwh rw rwh rw rwh rw rwh rw 89H TMOD Reset: 00 H Timer Mode Register Bit Field GATE1 0 T1M GATE0 T0S T0M Type rw r rw rw rw rw 8AH TL0 Reset: 00 H Timer 0 Register Low Bit Field VAL Type rwh 8BH TL1 Reset: 00 H Timer 1 Register Low Bit Field VAL Type rwh 8CH TH0 Reset: 00 H Timer 0 Register High Bit Field VAL Type rwh 8DH TH1 Reset: 00 H Timer 1 Register High Bit Field VAL Type rwh 98H SCON Reset: 00 H Serial Channel Control Register Bit Field SM0 SM1 SM2 REN TB8 RB8 TI RI Type rw rw rw rw rw rwh rwh rwh 99H SBUF Reset: 00 H Serial Data Buffer Register Bit Field VAL Type rwh A2H EO Reset: 00 H Extended Operation Register Bit Field 0 TRAP_ EN

0 DPSEL

A8H IEN0 Reset: 00 H Interrupt Enable Register 0 Bit Field EA 0 ET2 ES ET1 EX1 ET0 EX0 T y p e r w r r wr wr wr wr wr w B8H IP Reset: 00 H Interrupt Priority Register Bit Field 0 PT2 PS PT1 PX1 PT0 PX0 T y p e r r wr wr wr wr wr w B9H IPH Reset: 00 H Interrupt Priority Register High Bit Field 0 PT2H PSH PT1H PX1H PT0H PX0H T y p e r r wr wr wr wr wr w D0H PSW Reset: 00 H Program Status Word Register Bit Field CY AC F0 RS1 RS0 OV F1 P Type rwh rwh rw rw rw rwh rw rh

Data Sheet 24 V 1.1, 2009-03 The system control SFRs can be accessed in the standard memory area (RMAP = 0). A special case is SYSCON0 which can be ac cessed in both th e standard and mapped memory areas (RMAP = 0 or 1). E0H ACC Reset: 00 H Accumulator Register Bit Field ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0 Type rw rw rw rw rw rw rw rw E8H IEN1 Reset: 00 H Interrupt Enable Register 1 Bit Field ECCIP ECCIP ECCIP ECCIP EXM EX2 ESSC EADC Type rw rw rw rw rw rw rw rw F0H B Reset: 00 H B Register Bit Field B7 B6 B5 B4 B3 B2 B1 B0 Type rw rw rw rw rw rw rw rw F8H IP1 Reset: 00 H Interrupt Priority Register 1 Bit Field PCCIP PCCIP PCCIP PCCIP PXM PX2 PSSC PADC Type rw rw rw rw rw rw rw rw F9H IPH1 Reset: 00 H Interrupt Priority Register 1 High Bit Field PCCIP PCCIP PCCIP PCCIP PXMH PX2H PSSCH PADC H Type rw rw rw rw rw rw rw rw Table 5 SCU Register Summary A d d r R e g i s t e r N a m e B i t 7 6543210 RMAP = 0 or 1 8FH SYSCON0 Reset: 04 H System Control Register 0 Bit Field 0 1 0 RMAP Type r rw r rw RMAP = 0 BFH SCU_PAGE Reset: 00 H Page Register Bit Field OP STNR 0 PAGE Type w w r rwh RMAP = 0, PAGE 0 B3H MODPISEL Reset: 00 H Peripheral Input Select Register Bit Field 0 JTAGT DIS JTAGT CKS

0 EXINT

B4H IRCON0 Reset: 00 H Interrupt Request Register 0 Bit Field 0 EXINT EXINT EXINT EXINT Type r rwh rwh rwh rwh B5H IRCON1 Reset: 00 H Interrupt Request Register 1 Bit Field 0 ADCS RC1 ADCS RC0 RIR TIR EIR Type r rwh rwh rwh rwh rwh B7H EXICON0 Reset: 00 H External Interrupt Control Register 0 Bit Field EXINT3 EXINT2 EXINT1 EXINT0 Type rw rw rw rw BBH NMICON Reset: 00 H NMI Control Register Bit Field 0 NMI ECC NMI VDDP NMI VDD NMI OCDS NMI FLASH NMI PLL NMI WDT Type r rw rw rw rw rw rw rw BCH NMISR Reset: 00 H NMI Status Register Bit Field 0 FNMI ECC FNMI VDDP FNMI VDD FNMI OCDS FNMI FLASH FNMI PLL FNMI WDT Type r rwh rwh rwh rwh rwh rwh rwh BDH BCON Reset: 00 H Baud Rate Control Register Bit Field BGSEL 0 BRDIS BRPRE R Type rw r rw rw rw BEH BG Reset: 00 H Baud Rate Timer/Reload Register Bit Field BR_VALUE Type rwh Table 4 CPU Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 25 V 1.1, 2009-03 The WDT SFRs can be accessed in the mapped memory area (RMAP = 1). E9H FDCON Reset: 00 H Fractional Divider Control Register Bit Field BGS SYNEN ERRSY N EOFSY N BRK0 NDOV FDM FDEN Type rw rw rwh rwh rwh rwh rw rw EAH FDSTEP Reset: 00 H Fractional Divider Reload Register Bit Field STEP Type rw EBH FDRES Reset: 00 H Fractional Divider Result Register Bit Field RESULT Type rh RMAP = 0, PAGE 1 H ID Reset: 1B H Identity Register Bit Field PRODID VERID Type r rw B4H PMCON0 Reset: 00 H Power Mode Control Register 0 Bit Field 0 WDT RST WKRS WK SEL SD PD WS Type r rwh rwh rw rw rwh rw B5H PMCON1 Reset: 00 H Power Mode Control Register 1 Bit Field 0 T2_DIS CCU _DIS SSC _DIS ADC _DIS Type r rw rw rw rw B7H PLL_CON Reset: 20 H PLL Control Register Bit Field NDIV VCOB YP OSC DISC RESLD LOCK Type rw rw rw rwh rh BAH CMCON Reset: 00 H Clock Control Register Bit Field VCO SEL

0 CLKREL

BBH PASSWD Reset: 07 H Password Register Bit Field PASS PROTE CT_S MODE Type wh rh rw BCH FEAL Reset: 00 H Flash Error Address Register Low Bit Field ECCERRADDR[7:0] Type rh BDH FEAH Reset: 00 H Flash Error Address Register High Bit Field ECCERRADDR[15:8] Type rh BEH COCON Reset: 00 H Clock Output Control Register Bit Field 0 TLEN COUT S COREL Type r rw rw rw E9H MISC_CON Reset: 00 H Miscellaneous Control Register Bit Field 0 DFLAS HEN Type r rwh RMAP = 0, PAGE 3 H XADDRH Reset: F0 H On-chip XRAM Address Higher Order Bit Field ADDRH Type rw B4H IRCON3 Reset: 00 H Interrupt Request Register 3 Bit Field 0 CCU6S

0 CCU6S

B5H IRCON4 Reset: 00 H Interrupt Request Register 4 Bit Field 0 CCU6S BDH MODSUSP Reset: 01 H Module Suspend Control Register Bit Field 0 T2SUS P T13SU SP T12SU SP WDTS USP Type r rw rw rw rw Table 5 SCU Register Summary (cont’d) A d d r R e g i s t e r N a m e B i t 7 6543210

Data Sheet 26 V 1.1, 2009-03 The Port SFRs can be accessed in the standard memory area (RMAP = 0). Table 6 WDT Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 1 BBH WDTCON Reset: 00 H Watchdog Timer Control Register Bit Field 0 WINB EN WDT PR

0 WDT

BCH WDTREL Reset: 00 H Watchdog Timer Reload Register Bit Field WDTREL Type rw BDH WDTWINB Reset: 00 H Watchdog Window-Boundary Count Register Bit Field WDTWINB Type rw BEH WDTL Reset: 00 H Watchdog Timer Register Low Bit Field WDT[7:0] Type rh BFH WDTH Reset: 00 H Watchdog Timer Register High Bit Field WDT[15:8] Type rh Table 7 Port Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 B2H PORT_PAGE Reset: 00 H Page Register for PORT Bit Field OP STNR 0 PAGE Type w w r rwh RMAP = 0, Page 0 80H P0_DATA Reset: 00 H P0 Data Register Bit Field 0 P5 P4 P3 P2 P1 P0 Type r rwh rwh rwh rwh rwh rwh 86H P0_DIR Reset: 00 H P0 Direction Register Bit Field 0 P5 P4 P3 P2 P1 P0 Type r rw rw rw rw rw rw 90H P1_DATA Reset: 00 H P1 Data Register Bit Field 0 P1 P0 Type rwh rwh rwh 91H P1_DIR Reset: 00 H P1 Direction Register Bit Field 0 P1 P0 Type rw rw rw A0H P2_DATA Reset: 00 H P2 Data Register Bit Field P7 0 P2 P1 P0 Type rwh rwh rwh rwh rwh A1H P2_DIR Reset: 00 H P2 Direction Register Bit Field P7 0 P2 P1 P0 Type rw rw rw rw rw B0H P3_DATA Reset: 00 H P3 Data Register Bit Field 0 P1 P0 Type rwh rwh rwh B1H P3_DIR Reset: 00 H P3 Direction Register Bit Field 0 P1 P0 Type rw rw rw RMAP = 0, Page 1 H P0_PUDSEL Reset: FF H P0 Pull-Up/Pull-Down Select Register Bit Field 1 P5 P4 P3 P2 P1 P0 Type r rw rw rw rw rw rw 86H P0_PUDEN Reset: C4 H P0 Pull-Up/Pull-Down Enable Register Bit Field 1 P5 P4 P3 P2 P1 P0 Type r rw rw rw rw rw rw 90H P1_PUDSEL Reset: FF H P1 Pull-Up/Pull-Down Select Register Bit Field 1 P1 P0 Type rw rw rw 91H P1_PUDEN Reset: FF H P1 Pull-Up/Pull-Down Enable Register Bit Field 1 P1 P0 Type rw rw rw

Data Sheet 27 V 1.1, 2009-03 The ADC SFRs can be accessed in the standard memory area (RMAP = 0). A0H P2_PUDSEL Reset: FF H P2 Pull-Up/Pull-Down Select Register Bit Field P7 1 P2 P1 P0 Type rw rw rw rw rw A1H P2_PUDEN Reset: 00 H P2 Pull-Up/Pull-Down Enable Register Bit Field P7 0 P2 P1 P0 Type rw rw rw rw rw B0H P3_PUDSEL Reset: BF H P3 Pull-Up/Pull-Down Select Register Bit Field 1 0 1 P1 P0 Type rw rw rw rw rw B1H P3_PUDEN Reset: 40 H P3 Pull-Up/Pull-Down Enable Register Bit Field 0 1 0 P1 P0 Type rw rw rw rw rw RMAP = 0, Page 2 H P0_ALTSEL0 Reset: 00 H P0 Alternate Select 0 Register Bit Field 0 P5 P4 P3 P2 P1 P0 Type r rw rw rw rw rw rw 86H P0_ALTSEL1 Reset: 00 H P0 Alternate Select 1 Register Bit Field 0 P5 P4 P3 P2 P1 P0 Type r rw rw rw rw rw rw 90H P1_ALTSEL0 Reset: 00 H P1 Alternate Select 0 Register Bit Field 0 P1 P0 Type rw rw rw 91H P1_ALTSEL1 Reset: 00 H P1 Alternate Select 1 Register Bit Field 0 P1 P0 Type rw rw rw B0H P3_ALTSEL0 Reset: 00 H P3 Alternate Select 0 Register Bit Field 0 P1 P0 Type rw rw rw B1H P3_ALTSEL1 Reset: 00 H P3 Alternate Select 1 Register Bit Field 0 P1 P0 Type rw rw rw RMAP = 0, Page 3 H P0_OD Reset: 00 H P0 Open Drain Control Register Bit Field 0 P5 P4 P3 P2 P1 P0 Type r rw rw rw rw rw rw 90H P1_OD Reset: 00 H P1 Open Drain Control Register Bit Field 0 P1 P0 Type rw rw rw B0H P3_OD Reset: 00 H P3 Open Drain Control Register Bit Field 0 P1 P0 Type rw rw rw Table 8 ADC Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 D1H ADC_PAGE Reset: 00 H Page Register for ADC Bit Field OP STNR 0 PAGE Type w w r rwh RMAP = 0, Page 0 CAH ADC_GLOBCTR Reset: 30 H Global Control Register Bit Field ANON DW CTC 0 Type rw rw rw r CBH ADC_GLOBSTR Reset: 00 H Global Status Register Bit Field 0 CHNR 0 SAM PLE BUSY Type r rh r rh rh CCH ADC_PRAR Reset: 00 H Priority and Arbitration Register Bit Field ASEN1 ASEN0 0 ARBM CSM1 PRIO1 CSM0 PRIO0 Type rw rw r rw rw rw rw rw CDH ADC_LCBR Reset: B7 H Limit Check Boundary Register Bit Field BOUND1 BOUND0 Type rw rw CEH ADC_INPCR0 Reset: 00 H Input Class Register 0 Bit Field STC Type rw Table 7 Port Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 28 V 1.1, 2009-03 CFH ADC_ETRCR Reset: 00 H External Trigger Control Register Bit Field SYNEN SYNEN ETRSEL1 ETRSEL0 Type rw rw rw rw RMAP = 0, Page 1 CAH ADC_CHCTR0 Reset: 00 H Channel Control Register 0 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CBH ADC_CHCTR1 Reset: 00 H Channel Control Register 1 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CCH ADC_CHCTR2 Reset: 00 H Channel Control Register 2 Bit Field 0 LCC 0 RESRSEL Type r rw r rw D3H ADC_CHCTR7 Reset: 00 H Channel Control Register 7 Bit Field 0 LCC 0 RESRSEL Type r rw r rw RMAP = 0, Page 2 CAH ADC_RESR0L Reset: 00 H Result Register 0 Low Bit Field RESULT[1:0] 0 VF DRC CHNR Type rh r rh rh rh CBH ADC_RESR0H Reset: 00 H Result Register 0 High Bit Field RESULT[9:2] Type rh CCH ADC_RESR1L Reset: 00 H Result Register 1 Low Bit Field RESULT[1:0] 0 VF DRC CHNR Type rh r rh rh rh CDH ADC_RESR1H Reset: 00 H Result Register 1 High Bit Field RESULT[9:2] Type rh CEH ADC_RESR2L Reset: 00 H Result Register 2 Low Bit Field RESULT[1:0] 0 VF DRC CHNR Type rh r rh rh rh CFH ADC_RESR2H Reset: 00 H Result Register 2 High Bit Field RESULT[9:2] Type rh D2H ADC_RESR3L Reset: 00 H Result Register 3 Low Bit Field RESULT[1:0] 0 VF DRC CHNR Type rh r rh rh rh D3H ADC_RESR3H Reset: 00 H Result Register 3 High Bit Field RESULT[9:2] Type rh RMAP = 0, Page 3 CAH ADC_RESRA0L Reset: 00 H Result Register 0, View A Low Bit Field RESULT[2:0] VF DRC CHNR Type rh rh rh rh CBH ADC_RESRA0H Reset: 00 H Result Register 0, View A High Bit Field RESULT[10:3] Type rh CCH ADC_RESRA1L Reset: 00 H Result Register 1, View A Low Bit Field RESULT[2:0] VF DRC CHNR Type rh rh rh rh CDH ADC_RESRA1H Reset: 00 H Result Register 1, View A High Bit Field RESULT[10:3] Type rh CEH ADC_RESRA2L Reset: 00 H Result Register 2, View A Low Bit Field RESULT[2:0] VF DRC CHNR Type rh rh rh rh CFH ADC_RESRA2H Reset: 00 H Result Register 2, View A High Bit Field RESULT[10:3] Type rh D2H ADC_RESRA3L Reset: 00 H Result Register 3, View A Low Bit Field RESULT[2:0] VF DRC CHNR Type rh rh rh rh D3H ADC_RESRA3H Reset: 00 H Result Register 3, View A High Bit Field RESULT[10:3] Type rh RMAP = 0, Page 4 CAH ADC_RCR0 Reset: 00 H Result Control Register 0 Bit Field VFCTR WFR 0 IEN 0 DRCT R Type rw rw r rw r rw Table 8 ADC Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 29 V 1.1, 2009-03 CBH ADC_RCR1 Reset: 00 H Result Control Register 1 Bit Field VFCTR WFR 0 IEN 0 DRCT R Type rw rw r rw r rw CCH ADC_RCR2 Reset: 00 H Result Control Register 2 Bit Field VFCTR WFR 0 IEN 0 DRCT R Type rw rw r rw r rw CDH ADC_RCR3 Reset: 00 H Result Control Register 3 Bit Field VFCTR WFR 0 IEN 0 DRCT R Type rw rw r rw r rw CEH ADC_VFCR Reset: 00 H Valid Flag Clear Register Bit Field 0 VFC3 VFC2 VFC1 VFC0 Type r w w w w RMAP = 0, Page 5 CAH ADC_CHINFR Reset: 00 H Channel Interrupt Flag Register Bit Field CHINF

0 CHINF

CBH ADC_CHINCR Reset: 00 H Channel Interrupt Clear Register Bit Field CHINC

0 CHINC

CCH ADC_CHINSR Reset: 00 H Channel Interrupt Set Register Bit Field CHINS

0 CHINS

CDH ADC_CHINPR Reset: 00 H Channel Interrupt Node Pointer Register Bit Field CHINP

0 CHINP

CEH ADC_EVINFR Reset: 00 H Event Interrupt Flag Register Bit Field EVINF EVINF EVINF EVINF

0 EVINF

CFH ADC_EVINCR Reset: 00 H Event Interrupt Clear Flag Register Bit Field EVINC EVINC EVINC EVINC

0 EVINC

D2H ADC_EVINSR Reset: 00 H Event Interrupt Set Flag Register Bit Field EVINS EVINS EVINS EVINS

0 EVINS

D3H ADC_EVINPR Reset: 00 H Event Interrupt Node Pointer Register Bit Field EVINP EVINP EVINP EVINP

0 EVINP

RMAP = 0, Page 6 CAH ADC_CRCR1 Reset: 00 H Conversion Request Control Register 1 Bit Field CH7 0 0 Type rwh rwh r CBH ADC_CRPR1 Reset: 00 H Conversion Request Pending Register 1 Bit Field CHP7 0 0 Type rwh rwh r CCH ADC_CRMR1 Reset: 00 H Conversion Request Mode Register 1 Bit Field Rsv LDEV CLR PND SCAN ENSI ENTR 0 ENGT Type r w w rw rw rw r rw CDH ADC_QMR0 Reset: 00 H Queue Mode Register 0 Bit Field CEV TREV FLUSH CLRV TRMD ENTR 0 ENGT T y p e wwww rw rw r rw CEH ADC_QSR0 Reset: 20 H Queue Status Register 0 Bit Field Rsv 0 EMPTY EV 0 Type r r rh rh r CFH ADC_Q0R0 Reset: 00 H Queue 0 Register 0 Bit Field EXTR ENSI RF V 0 REQCHNR Type rh rh rh rh r rh D2H ADC_QBUR0 Reset: 00 H Queue Backup Register 0 Bit Field EXTR ENSI RF V 0 REQCHNR Type rh rh rh rh r rh Table 8 ADC Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 30 V 1.1, 2009-03 The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0). The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). D2H ADC_QINR0 Reset: 00 H Queue Input Register 0 Bit Field EXTR ENSI RF 0 REQCHNR T y p e www r w Table 9 Timer 2 Register Overview A d d r R e g i s t e r N a m e B i t 76543210 C0H T2_T2CON Reset: 00 H Timer 2 Control Register Bit Field TF2 EXF2 0 EXEN2 TR2 0 CP/ RL2 Type rwh rwh r rw rwh r rw C1H T2_T2MOD Reset: 00 H Timer 2 Mode Register Bit Field T2 REGS RHEN EDGE SEL PREN T2PRE DCEN Type rw rw rw rw rw rw C2H T2_RC2L Reset: 00 H Timer 2 Reload/Capture Register Low Bit Field RC2[7:0] Type rwh C3H T2_RC2H Reset: 00 H Timer 2 Reload/Capture Register High Bit Field RC2[15:8] Type rwh C4H T2_T2L Reset: 00 H Timer 2 Register Low Bit Field THL2[7:0] Type rwh C5H T2_T2H Reset: 00 H Timer 2 Register High Bit Field THL2[15:8] Type rwh Table 10 CCU6 Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 A3H CCU6_PAGE Reset: 00 H Page Register for CCU6 Bit Field OP STNR 0 PAGE Type w w r rwh RMAP = 0, Page 0 9AH CCU6_CC63SRL Reset: 00 H Capture/Compare Shadow Register for Channel CC63 Low Bit Field CC63SL Type rw 9BH CCU6_CC63SRH Reset: 00 H Capture/Compare Shadow Register for Channel CC63 High Bit Field CC63SH Type rw 9CH CCU6_TCTR4L Reset: 00 H Timer Control Register 4 Low Bit Field T12 STD T12 STR

0 DTRES T12

9DH CCU6_TCTR4H Reset: 00 H Timer Control Register 4 High Bit Field T13 STD T13 STR

0 T13

9EH CCU6_MCMOUTSL Reset: 00 H Multi-Channel Mode Output Shadow Register Low Bit Field STRM CM

0 MCMPS

9FH CCU6_MCMOUTSH Reset: 00 H Multi-Channel Mode Output Shadow Register High Bit Field STRHP 0 CURHS EXPHS Type w r rw rw Table 8 ADC Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 31 V 1.1, 2009-03 A4H CCU6_ISRL Reset: 00 H Capture/Compare Interrupt Status Reset Register Low Bit Field RT12P M RT12O M RCC62 F RCC62 R RCC61 F RCC61 R RCC60 F RCC60 R T y p e wwww w w w w A5H CCU6_ISRH Reset: 00 H Capture/Compare Interrupt Status Reset Register High Bit Field RSTR RIDLE RWHE RCHE 0 RTRPF RT13 PM RT13 CM T y p e wwww r w w w A6H CCU6_CMPMODIFL Reset: 00 H Compare State Modification Register Low Bit Field 0 MCC63 S

0 MCC62

S MCC61 S MCC60 S Type r w r w w w A7H CCU6_CMPMODIFH Reset: 00 H Compare State Modification Register High Bit Field 0 MCC63 R R MCC61 R MCC60 R Type r w r w w w FAH CCU6_CC60SRL Reset: 00 H Capture/Compare Shadow Register for Channel CC60 Low Bit Field CC60SL Type rwh FBH CCU6_CC60SRH Reset: 00 H Capture/Compare Shadow Register for Channel CC60 High Bit Field CC60SH Type rwh FCH CCU6_CC61SRL Reset: 00 H Capture/Compare Shadow Register for Channel CC61 Low Bit Field CC61SL Type rwh FDH CCU6_CC61SRH Reset: 00 H Capture/Compare Shadow Register for Channel CC61 High Bit Field CC61SH Type rwh FEH CCU6_CC62SRL Reset: 00 H Capture/Compare Shadow Register for Channel CC62 Low Bit Field CC62SL Type rwh FFH CCU6_CC62SRH Reset: 00 H Capture/Compare Shadow Register for Channel CC62 High Bit Field CC62SH Type rwh RMAP = 0, Page 1 9AH CCU6_CC63RL Reset: 00 H Capture/Compare Register for Channel CC63 Low Bit Field CC63VL Type rh 9BH CCU6_CC63RH Reset: 00 H Capture/Compare Register for Channel CC63 High Bit Field CC63VH Type rh 9CH CCU6_T12PRL Reset: 00 H Timer T12 Period Register Low Bit Field T12PVL Type rwh 9DH CCU6_T12PRH Reset: 00 H Timer T12 Period Register High Bit Field T12PVH Type rwh 9EH CCU6_T13PRL Reset: 00 H Timer T13 Period Register Low Bit Field T13PVL Type rwh 9FH CCU6_T13PRH Reset: 00 H Timer T13 Period Register High Bit Field T13PVH Type rwh A4H CCU6_T12DTCL Reset: 00 H Dead-Time Control Register for Timer T12 Low Bit Field DTM Type rw A5H CCU6_T12DTCH Reset: 00 H Dead-Time Control Register for Timer T12 High Bit Field 0 DTR2 DTR1 DTR0 0 DTE2 DTE1 DTE0 Type r rh rh rh r rw rw rw Table 10 CCU6 Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 32 V 1.1, 2009-03 A6H CCU6_TCTR0L Reset: 00 H Timer Control Register 0 Low Bit Field CTM CDIR STE12 T12R T12 PRE T12CLK Type rw rh rh rh rw rw A7H CCU6_TCTR0H Reset: 00 H Timer Control Register 0 High Bit Field 0 STE13 T13R T13 PRE T13CLK Type r rh rh rw rw FAH CCU6_CC60RL Reset: 00 H Capture/Compare Register for Channel CC60 Low Bit Field CC60VL Type rh FBH CCU6_CC60RH Reset: 00 H Capture/Compare Register for Channel CC60 High Bit Field CC60VH Type rh FCH CCU6_CC61RL Reset: 00 H Capture/Compare Register for Channel CC61 Low Bit Field CC61VL Type rh FDH CCU6_CC61RH Reset: 00 H Capture/Compare Register for Channel CC61 High Bit Field CC61VH Type rh FEH CCU6_CC62RL Reset: 00 H Capture/Compare Register for Channel CC62 Low Bit Field CC62VL Type rh FFH CCU6_CC62RH Reset: 00 H Capture/Compare Register for Channel CC62 High Bit Field CC62VH Type rh RMAP = 0, Page 2 9AH CCU6_T12MSELL Reset: 00 H T12 Capture/Compare Mode Select Register Low Bit Field MSEL61 MSEL60 Type rw rw 9BH CCU6_T12MSELH Reset: 00 H T12 Capture/Compare Mode Select Register High Bit Field DBYP HSYNC MSEL62 Type rw rw rw 9CH CCU6_IENL Reset: 00 H Capture/Compare Interrupt Enable Register Low Bit Field ENT12 PM ENT12 OM ENCC 62F ENCC 62R ENCC 61F ENCC 61R ENCC 60F ENCC 60R Type rw rw rw rw rw rw rw rw 9DH CCU6_IENH Reset: 00 H Capture/Compare Interrupt Enable Register High Bit Field ENSTR EN IDLE EN WHE EN CHE 0 EN TRPF ENT13 PM ENT13 CM Type rw rw rw rw r rw rw rw 9EH CCU6_INPL Reset: 40 H Capture/Compare Interrupt Node Pointer Register Low Bit Field INPCHE INPCC62 INPCC61 INPCC60 Type rw rw rw rw 9FH CCU6_INPH Reset: 39 H Capture/Compare Interrupt Node Pointer Register High Bit Field 0 INPT13 INPT12 INPERR Type r rw rw rw A4H CCU6_ISSL Reset: 00 H Capture/Compare Interrupt Status Set Register Low Bit Field ST12P M ST12O M SCC62 F SCC62 R SCC61 F SCC61 R SCC60 F SCC60 R T y p e wwww w w w w A5H CCU6_ISSH Reset: 00 H Capture/Compare Interrupt Status Set Register High Bit Field SSTR SIDLE SWHE SCHE SWHC STRPF ST13 PM ST13 CM T y p e wwww w w w w A6H CCU6_PSLR Reset: 00 H Passive State Level Register Bit Field PSL63 0 PSL Type rwh r rwh A7H CCU6_MCMCTR Reset: 00 H Multi-Channel Mode Control Register Bit Field 0 SWSYN 0 SWSEL Type r rw r rw Table 10 CCU6 Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 33 V 1.1, 2009-03 FAH CCU6_TCTR2L Reset: 00 H Timer Control Register 2 Low Bit Field 0 T13TED T13TEC T13 SSC T12 SSC Type r rw rw rw rw FBH CCU6_TCTR2H Reset: 00 H Timer Control Register 2 High Bit Field 0 T13RSEL T12RSEL Type r rw rw FCH CCU6_MODCTRL Reset: 00 H Modulation Control Register Low Bit Field MC MEN

0 T12MODEN

FDH CCU6_MODCTRH Reset: 00 H Modulation Control Register High Bit Field ECT13 O

0 T13MODEN

FEH CCU6_TRPCTRL Reset: 00 H Trap Control Register Low Bit Field 0 TRPM2 TRPM1 TRPM0 Type r rw rw rw FFH CCU6_TRPCTRH Reset: 00 H Trap Control Register High Bit Field TRPPE N TRPEN TRPEN Type rw rw rw RMAP = 0, Page 3 9AH CCU6_MCMOUTL Reset: 00 H Multi-Channel Mode Output Register Low Bit Field 0 R MCMP Type r rh rh 9BH CCU6_MCMOUTH Reset: 00 H Multi-Channel Mode Output Register High Bit Field 0 CURH EXPH Type r rh rh 9CH CCU6_ISL Reset: 00 H Capture/Compare Interrupt Status Register Low Bit Field T12PM T12OM ICC62F ICC62 R ICC61F ICC61 R ICC60F ICC60 R Type rh rh rh rh rh rh rh rh 9DH CCU6_ISH Reset: 00 H Capture/Compare Interrupt Status Register High Bit Field STR IDLE WHE CHE TRPS TRPF T13PM T13CM Type rh rh rh rh rh rh rh rh 9EH CCU6_PISEL0L Reset: 00 H Port Input Select Register 0 Low Bit Field ISTRP ISCC62 ISCC61 ISCC60 Type rw rw rw rw 9FH CCU6_PISEL0H Reset: 00 H Port Input Select Register 0 High Bit Field IST12HR ISPOS2 ISPOS1 ISPOS0 Type rw rw rw rw A4H CCU6_PISEL2 Reset: 00 H Port Input Select Register 2 Bit Field 0 IST13HR Type r rw FAH CCU6_T12L Reset: 00 H Timer T12 Counter Register Low Bit Field T12CVL Type rwh FBH CCU6_T12H Reset: 00 H Timer T12 Counter Register High Bit Field T12CVH Type rwh FCH CCU6_T13L Reset: 00 H Timer T13 Counter Register Low Bit Field T13CVL Type rwh FDH CCU6_T13H Reset: 00 H Timer T13 Counter Register High Bit Field T13CVH Type rwh FEH CCU6_CMPSTATL Reset: 00 H Compare State Register Low Bit Field 0 CC63 ST CCPO CCPO CCPO CC62 ST CC61 ST CC60 ST Type r rh rh rh rh rh rh rh FFH CCU6_CMPSTATH Reset: 00 H Compare State Register High Bit Field T13IM COUT 63PS COUT 62PS CC62 PS COUT 61PS CC61 PS COUT 60PS CC60 PS Type rwh rwh rwh rwh rwh rwh rwh rwh Table 10 CCU6 Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 34 V 1.1, 2009-03 The SSC SFRs can be accessed in the standard memory area (RMAP = 0). The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1). Certain bits (marked with asterisk) are writable by Monitor program only, in Monitor Mode. In general, user code shall not access these SFRs. Table 11 SSC Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 A9H SSC_PISEL Reset: 00 H Port Input Select Register Bit Field 0 CIS SIS MIS Type r rw rw rw AAH SSC_CONL Reset: 00 H Control Register Low Programming Mode Bit Field LB PO PH HB BM Type rw rw rw rw rw AAH SSC_CONL Reset: 00 H Control Register Low Operating Mode Bit Field 0 BC Type r rh ABH SSC_CONH Reset: 00 H Control Register High Programming Mode Bit Field EN MS 0 AREN BEN PEN REN TEN Type rw rw r rw rw rw rw rw ABH SSC_CONH Reset: 00 H Control Register High Operating Mode Bit Field EN MS 0 BSY BE PE RE TE Type rw rw r rh rwh rwh rwh rwh ACH SSC_TBL Reset: 00 H Transmitter Buffer Register Low Bit Field TB_VALUE Type rw ADH SSC_RBL Reset: 00 H Receiver Buffer Register Low Bit Field RB_VALUE Type rh AEH SSC_BRL Reset: 00 H Baudrate Timer Reload Register Low Bit Field BR_VALUE[7:0] Type rw AFH SSC_BRH Reset: 00 H Baudrate Timer Reload Register High Bit Field BR_VALUE[15:8] Type rw Table 12 OCDS Register Summary A d d r R e g i s t e r N a m e B i t 7 6543210 RMAP = 1 E9H MMCR2 Reset: 1010 000X B Monitor Mode Control 2 Register Bit Field STMO DE EXBC DSUSP MBCO N

0 MMEP MMOD

E JENA Type r rw rw rwh rw rwh rh rh EBH MMWR1 Reset: 00 H Monitor Work Register 1 Bit Field MMWR1 Type rw ECH MMWR2 Reset: 00 H Monitor Work Register 2 Bit Field MMWR2 Type rw F1H MMCR Reset: 00 H Monitor Mode Control Register Bit Field MEXIT MEXIT 0 MSTEP MRAM S_P MRAM S TRF RRF Type w rwh r rw w rwh rh rh F2H MMSR Reset: 00 H Monitor Mode Status Register Bit Field MBCA M MBCIN EXBF SWBF HWB3 F HWB2 F HWB1 F HWB0 F Type rw rwh rwh rwh rwh rwh rwh rwh F3H MMBPCR Reset: 00 H BreakPoints Control Register Bit Field SWBC HWB3C HWB2C HWB1 C HWB0C Type rw rw rw rw rw

Data Sheet 35 V 1.1, 2009-03 F4H MMICR Reset: 00 H Monitor Mode Interrupt Control Register Bit Field DVECT DRETR COMR ST MSTSE L MMUIE MMUIE RRIE_ P RRIE Type rwh rwh rwh rh w rw w rw F5H MMDR Reset: 00 H Monitor Mode Data Transfer Register Receive Bit Field MMRR Type rh F6H HWBPSR Reset: 00 H Hardware Breakpoints Select Register Bit Field 0 BPSEL BPSEL Type r w rw F7H HWBPDR Reset: 00 H Hardware Breakpoints Data Register Bit Field HWBPxx Type rw Table 12 OCDS Register Summary (cont’d) A d d r R e g i s t e r N a m e B i t 7 6543210

Data Sheet 36 V 1.1, 2009-03

3.3 Flash Memory

The Flash memory provides an embedded user-programm able non-volatile memory, allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V supply from the Embedded Voltage Regu lator (EVR) and does not require additional programming or erasing volta ge. The sectorization of t he Flash memory allows each sector to be erased independently. Features:

• In-System Programming (ISP) via UART
• In-Application Programming (IAP)
• Error Correction Code (ECC) for dy namic correction of single-bit errors
• Background program and erase operations for CPU load minimization
• Support for aborti ng erase operation
• 32-byte minimum program width 1)
• 1-sector minimum erase width
• 1-byte read access
• Operating supply vo ltage: 2.5 V ± 7.5 %
• Read access time: 3 × tCCLK = 112.5 ns2)
• Program time: 209440 / fSYS = 2.6 ms3)
• Erase time: 8175360 / fSYS =1 0 2 m s3) Table 13 shows the Flash data retention and endurance targets. 1) 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed. 2) Values shown here are typical values. f sys =8 0M H z±7 . 5 % ( fCCLK = 26.7 MHz ± 7.5 %) is the maximum frequency range for Flash read access. 3) Values shown here are typical values. f sys = 80 MHz ± 7.5% is the only frequency range for Flash programming and erasing. fsysmin is used for obtaining the worst case timing. Table 13 Flash Data Retention and En durance (Operating Conditions apply) Retention Endurance 1) 1) One cycle refers to the programming of all wordlines in a sector and erasing of sector. The Flash endurance data specified in Table 13 is valid only if the following conditions are fulfilled: - the maximum number of erase cycles per Flash sector must not exceed 100,000 cycles. - the maximum number of erase cycles per Flash bank must not exceed 300,000 cycles. - the maximum number of program cycles per Flash bank must not exceed 2,500,000 cycles. Size 20 years 1,000 cycles up to 4 Kbytes 5 years 10,000 cycles 1 Kbyte 2 years 70,000 cycles 512 bytes 2 years 100,000 cycles 128 bytes

Data Sheet 37 V 1.1, 2009-03

3.3.1 Flash Bank Sectorization

The XC864 has 4 Kbytes of embedded Flash memory. The Flash bank sectorization is shown in Figure 10. Figure 10 Flash Bank Sectorization The minimum erase width is always a comp lete sector, and sectors can be erased separately or in parallel. Contrary to st andard EPROMs, erased Flash memory cells contain 0s. Flash memory can be used for code and data storage. The Flash bank is divided into several physical sectors fo r extended erasing and repr ogramming capability; even numbers for each sector size are provided to al low greater flexibilit y and the ability to adapt to a wide range of application requirements. It must be noted that the Flash is dou ble mapped to two addr ess range in the code space: 0000H – 0FFF H and A000H – AFFF H. Accessing 0000H or A000H is physically accessing the same Flash location, and lik ewise for correspond ing addresses within each range. Sector 9: 128-byte Sector 5: 256-byte Sector 3: 512-byte Sector 1: 1-Kbyte Sector 0: 1-Kbyte Sector 7: 128-byte Sector 8: 128-byte Sector 6: 128-byte Sector 4: 256-byte Sector 2: 512-byte 4-Kbyte Flash

Data Sheet 38 V 1.1, 2009-03

3.3.2 Flash Programming Without Erase

The same WL can be programmed twice before erasing is required as the Flash cells are able to withstand two gate disturbs. Th is means if the numbe r of data bytes that needs to be written is sma ller than the 32-byte minimum programming width, the user can opt to program this number of data bytes (x; wher e x can be any integer from 1 to 31) first and program the remaining bytes (32 - x) later. Hence, it is possible to program the same WL, for example, with 16 bytes of data in two times (see Figure 11). Figure 11 Flash Progra mming Without Erase Note: When programming a WL the second time, the previously programmed Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain its original contents and to prevent “over-programming”. 0000 ….. 0000 H 0000 ….. 0000 H 32 bytes (1 WL) 1111 ….. 1111 H0000 ….. 0000 H 16 bytes 16 bytes 0000 ….. 0000 H 1111 ….. 1111 H Flash memory cells 32-byte write buffers 1111 ….. 0000 H 1111 ….. 1111 H 0000 ….. 0000 H1111 ….. 0000 H Program 1 Program 2 Note: A Flash memory cell can be programmed from 0 to 1, but not from 1 to 0.

Data Sheet 39 V 1.1, 2009-03

3.3.3 In-Application Programming

In some applications, the Flash contents may need to be modified during program execution. In-Application Programming (IAP) is supported so that users can program or erase the Flash memory from their Flash user progra m by calling some special subroutines. The Flash subrou tines will first perform some checks and an initialization sequence before starting the program or erase operation. A manual check on the Flash data is necessary to determine if the programming or erasing was successful via using the ‘MOVC’ instruction to read out the Flash contents. Other special subroutines include aborting the Flash erase operation and checking the Flash bank ready-to-read status.

3.3.3.1 Flash Programming

Each call of the Flash prog ram subroutine allows the progr amming of 32 bytes of data into the selected wo rdline (WL) of the Flash bank. Before calling the Flash program subroutine, the user must en sure that required inputs ( Table 14 and Table 15) are provided. Flash Program Subroutine Type 1 If valid inputs have been se t up, calling the subroutine be gins flash programming. The subroutine exits and returns to the user code, while the ta rget Flash bank is still in program mode, and is not accessible by user code. The user code continues ex ecution until the Flash NM I event is generated; bit FNMIFLASH in register NMISR is set, and if enabled via NMIFLASH, an NMI to the CPU is triggered to enter the Flas h NMI service routine. At th is point, the Flash bank is in ready-to-read mode. Table 14 Flash Program Subroutin Type 1 Subroutine DFF6H: FSM_PROG Input DPTR (DPH, DPL1)): Flash WL address R0 of Register Bank 3 (IRAM address 18H): IRAM start address for 32-byte Flash data 32-byte Flash data Flash NMI (NMICON.NMIFLASH) is enabled (1) or disabled (0) Output PSW.CY: 0 = Flash programming is in progress 1 = Flash programming is not started Flag FNMIFLASH will be set when Flash programming has successfully completed. DPTR is incremented by 20 H

Data Sheet 40 V 1.1, 2009-03 Flash Program Subroutine Type 2 This routine will wait until Flash programming is completed before the user code can continue its execution. Therefore, background programming is not supported. This type of routine can be used to program the Flash bank where the user code is in execution. The Flash cannot be in both program mode and read mode at the same time. It can also be used for programm ing the Flash bank w here the interrupt ve ctors are defined as interrupts cannot be handled when the Flash is in program mode. Note: For the Flash programmi ng of XC864 device, Flash Program Subroutine Type 2 is allowed. The users can also use Flash Program Subroutine Type 1 if it is called from XRAM. Stack size required 12 Resource used/ destroyed ACC, B, SCU_PAGE R0 – R7 of Register Bank 3 (IRAM address 18H –1 FH) (8 bytes) IRAM address 36H –3 DH (8 bytes) 1) The last 5 LSB of the DPL is 0 for an aligned WL address, for e.g. 00H, 20H, 40H, 60H, 80H, A0H, C0H and E0H.. 2) DPTR is only incremented by 20H when PSW.CY is 0. Table 15 Flash Program Subroutine Type 2 Subroutine DFDBH: FSM_PROG_NO_BG Input DPTR (DPH, DPL1)): Flash WL address R0 of Register Bank 3 (IRAM address 18H): IRAM start address for 32-byte Flash data 32-byte Flash data All interrupts including NMI must be disabled (0) Set SFR NMISR = 00H Output PSW.CY: 0 = Flash programming is successful 1 = Flash programming is not successful due to: Flash Protection Mode 1 is enabled, or NMI has occurred Flag FNMIFLASH is cleared by this routine before return to user code. DPTR is incremented by 20H Stack size required 15 Table 14 Flash Program Subroutin Type 1 (cont’d)

Data Sheet 41 V 1.1, 2009-03

3.3.3.2 Flash Erasing

Each call of the Flash erase subroutine allo ws the user to sele ct one sector or a combination of several sectors for erase. Before calling the Flash erase subroutine, the user must ensure t hat required inputs ( Table 16 and Table 17) are provided. Also, protected Flash banks should not be targeted for erase. Flash Erase Subroutine Type 1 If valid inputs have been set up, calling t he subroutine begins flash erasing. The subroutine exits and returns to the user code, while the target Flash bank is still in erase mode, and is not accessible by user code. Resource used/ destroyed ACC, B, SCU_PAGE R0 – R7 of Register Bank 3 (IRAM address 18H –1 FH) (8 bytes) IRAM address 36H –3 DH (8 bytes) 1) The last 5 LSB of the DPL is 0 for an aligned WL address, for e.g. 00H, 20H, 40H, 60H, 80H, A0H, C0H and E0H.. 2) DPTR is only incremented by 20H when PSW.CY is 0. Table 16 Flash Erase Subroutine Type 1 Subroutine DFF9H: FLASH_ERASE Input1) R3 of Register Bank 3 (IRAM address 1BH): Select sector(s) to be erased. LSB represents sector 0, MSB represents sector 7. R4 of Register Bank 3 (IRAM address 1CH): Select sector(s) to be erased. LSB represents sector 8, bit 1 represents sector 9. Flash NMI (NMICON.NMIFLASH) is enabled (1) or disabled (0) MISC_CON.DFLASHEN 2) bit = 1 Output PSW.CY: 0 = Flash erasing is in progress 1 = Flash erasing is not started Flag FNMIFLASH will be set when Flash erasing has successfully completed. Stack size required 10 Resource used/ destroyed ACC, B, SCU_PAGE R0 – R7 of Register Bank 3 (IRAM address 18 H –1 FH) (8 bytes) IRAM address 36H –3 DH (8 bytes) Table 15 Flash Program Subroutine Type 2 (cont’d)

Data Sheet 42 V 1.1, 2009-03 Flash Erase Subroutine Type 2 This routine will wait until Flash erasing is completed before the user code can continue its execution. Therefore, background erasing is not supported. This type of routine can be used to erase the Flash bank where the user code is in execution. The Flash cannot be in both erase mode and read mode at the same time. It can also be used for erasing the Flash bank where the interrupt vectors are defined as interrupts cannot be handled when the Flash is in erase mode. This routine will be aborted if the FNMIVD DP, FNMIVDD or FNMI PLL flag is set while they are being polled for error by the routine. Note: For the Flash erasing of XC864 device, Flash Erase Subroutine Type 2 is allowed. The users can also use Flash Erase Subroutine Type 1 if it is called from XRAM. 1) The inputs should be set as 0 if the sector(s) of the bank(s) is/are not to be selected for erasing. 2) When Flash Protection Mode 0 is enabled, in order to erase Flash bank, DFLASHEN bit needs to be set. Table 17 Flash Erase Subroutine Type 2 Subroutine DFDEH: FLASH_ERASE_NO_BG Input1) R3 of Register Bank 3 (IRAM address 1BH): Select sector(s) to be erased for the Flash bank. LSB represents sector 0, MSB represents sector 7. R4 of Register Bank 3 (IRAM address 1CH): Select sector(s) to be erased for the Flash bank. LSB represents sector 8, bit 1 represents sector 9. All interrupts including NMI must be disabled (0) SET SFR NMISR = 00H . MISC_CON.DFLASHEN2) bit = 1 Output PSW.CY: 0 = Flash erasing is successful 1 = Flash erasing is not successful due to: MISC_CON.DFLASHEN bit is not set when Flash Protection Mode 0 is enabled, or Flash Protection Mode 1 is enabled, or NMI has occurred3) Flag FNMIFLASH will be set when Flash erasing has successfully completed. Stack size required 13

Data Sheet 43 V 1.1, 2009-03 Resource used/ destroyed ACC, B, SCU_PAGE R0 – R7 of Register Bank 3 (IRAM address 18H –1 FH) (8 bytes) IRAM address 36H –3 DH (8 bytes) 1) The inputs should be set as 0 if the sector(s) of the bank(s) is/are not to be selected for erasing. 2) When Flash Protection Mode 0 is enabled, in order to erase Flash bank, DFLASHEN bit needs to be set. If DFLASHEN is not set, PSW.CY will be set to 1. 3) NMISR is checked for critical NMI events, namely NMIVDDP, NMIVDD, and NMIPLL. Table 17 Flash Erase Subroutine (cont’d)Type 2

Data Sheet 44 V 1.1, 2009-03

3.4 Interrupt System

The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt nodes. In addition to the standard interrupt f unctions supported by the core, e.g., configurable interrupt priori ty and interrupt masking, t he interrupt system provides extended interrupt support capab ilities such as mapping inte rrupt events to interrupt nodes to increase the numbe r of interrupt sources suppo rted, and additional status registers for detecting and determining the interrupt source.

3.4.1 Interrupt Source

Figure 12 to Figure 16 give a general overview of the interrupt sources and illustrates the request and control flags. Figure 12 Non-Maskable In terrupt Request Sources 0073 H NMIWDT NMICON.0 WDT Overflow >=1 Non Maskable Interrupt NMIPLL NMICON.1 PLL Loss of Lock NMIFLASH Flash Operation Complete NMIVDD NMICON.4 VDD Pre-Warning FNMIWDT NMIISR.0 FNMIPLL NMIISR.1 FNMIFLASH NMIISR.2 FNMIVDD NMIISR.4 NMIVDDP NMICON.5 VDDP Pre-Warning FNMIVDDP NMIISR.5 NMIECC NMICON.6 Flash ECC Error FNMIECC NMIISR.6

Data Sheet 45 V 1.1, 2009-03 Figure 13 Interrupt Request Sources (Part 1) Highest Lowest Priority Level Bit-addressable Request flag is cleared by hardware 000B HET0 IEN0.1 TF0 TCON.5 Timer 0 Overflow 001B HET1 IEN0.3 TF1 TCON.7 Timer 1 Overflow IP.1/ IPH.1 IP.3/ IPH.3

0023 HES

IEN0.4 IP.4/ IPH.4 >=1 RI SCON.0 TI SCON.1 UART Transmit

0003 HEX0

IEN0.0 IE0 TCON.1 IP.0/ IPH.0 0013 H IP.2/ IPH.2 IT0 TCON.0 EX1 IEN0.2 IE1 TCON.3 IT1 TCON.2 IEN0.7 EA P o l l i n g S e q u e n c e UART Receive EXINT0 EXICON0.0/1 EINT0 EXINT1 EXICON0.2/3 EINT1 EXINT0 IRCON0.0 EXINT1 IRCON0.1

Data Sheet 46 V 1.1, 2009-03 Figure 14 Interrupt Request Sources (Part 2) Bit- addressable Request flag is cleared by hardware Highest Lowest Priority Level Bit- addressable Request flag is cleared by hardware 0043HEX2 IEN1.2 IP1.2/ IPH1.2EXINT2 EXICON0.4/5 EXINT2 IRCON0.2 EINT2 002BHET2 IEN0.5 IP.5/ IPH.5 >=1 TF2 EXF2 Timer 2 Overflow EXEN2 T2EX IEN0.7 EA 004BHEXM IEN1.3 IP1.3/ IPH1.3 P o l l i n g S e q u e n c e EXINT3 EXICON0.6/7 EXINT3 IRCON0.3 EINT3 EDGES EL T2MOD.5 NDOV FDCON.2 Normal Divider Overflow FDCON.6 EOFSYN FDCON.4 End of Synch Byte ERRSYNSynch Byte Error SYNEN >=1 FDCON.5 T2_T2CON.7 T2_T2CON.6 T2_T2CON.3 FDCON.6

Data Sheet 47 V 1.1, 2009-03 Figure 15 Interrupt Request Sources (Part 3) IEN0.7 Highest Lowest Priority Level Bit-addressable Request flag is cleared by hardware 003B HESSC IEN1.1 IP1.1/ IPH1.1 >=1TIR IRCON1.1 RIR IRCON1.2 EIR IRCON1.0 SSC Error SSC Transmit SSC Receive

0033 HEADC

IEN1.0 IP1.0/ IPH1.0 >=1 ADCSRC0 IRCON1.3 ADC Service Request 0 ADC Service Request 1 ADCSRC1 IRCON1.4 P o l l i n g S e q u e n c e EA 0053 H CCU6 Node 0 IP1.4/ IPH1.4 005B H CCU6 Node 1 IP1.5/ IPH1.5 0063 H CCU6 Node 2 IP1.6/ IPH1.6 006B H CCU6 Node 3 IP1.7/ IPH1.7 ECCIP0 IEN1.4 ECCIP1 IEN1.5 ECCIP2 IEN1.6 ECCIP3 IEN1.7 CCU6SR0 IRCON3.0 CCU6SR1 IRCON3.4 CCU6SR2 IRCON4.0 CCU6SR3 IRCON4.4

Data Sheet 48 V 1.1, 2009-03 Figure 16 Interrupt Request Sources (Part 4) CCU6 Interrupt node 0 CCU6 Interrupt node 1 CCU6 Interrupt node 2 CCU6 Interrupt node 3 >=1CC60 ENCC60R IENL.0 ICC60R ISL.0 ENCC60F IENL.1 ICC60F ISL.1 INPL.1 INPL.0 >=1CC61 ENCC61R IENL.2 ICC61R ISL.2 ENCC61F IENL.3 ICC61F ISL.3 INPL.3 INPL.2 >=1 CC62 ENCC62R IENL.4 ICC62R ISL.4 ENCC62F IENL.5 ICC62F ISL.5 INPL.5 INPL.4 >=1 ENT12OM IENL.6 T12OM ISL.6 ENT12PM IENL.7 T12PM ISL.7 INPH.3 INPH.2 >=1 ENT13CM IENH.0 T13CM ISH.0 ENT13PM IENH.1 T13PM ISH.1 INPH.5 INPH.4 >=1 ENTRPF IENH.2 TRPF ISH.2 ENWHE IENH.5 WHE ISH.5 INPH.1 INPH.0 T12 One match T12 Period match T13 Compare match T13 Period match CTRAP Wrong Hall Event INPL.7 INPL.6 ENCHE IENH.4 CHE ISH.4 Correct Hall Event >=1 ENSTR IENH.7 STR ISH.7 Multi-Channel Shadow Transfer

Data Sheet 49 V 1.1, 2009-03

3.4.2 Interrupt Source and Vector

Each interrupt source has an associated interrupt vector address. This vector is accessed to service the corresponding interrupt source request. The interrupt service of each interrupt source can be individually enabled or disa bled via an enable bit. The assignment of the XC864 inte rrupt sources to the interr upt vector addresses and the corresponding interrupt source enable bits are summarized in Table 18. Table 18 Interrupt Vector Addresses Interrupt Source Vector Address Assignment for XC864 Enable Bit SFR NMI 0073 H Watchdog Timer NMI NMIWDT NMICON PLL NMI NMIPLL Flash NMI NMIFLASH VDDC Prewarning NMI NMIVDD VDDP Prewarning NMI NMIVDDP Flash ECC NMI NMIECC XINTR0 0003 H External Interrupt 0 EX0 IEN0 XINTR1 000B H Timer 0 ET0 XINTR2 0013 H External Interrupt 1 EX1 XINTR3 001B H Timer 1 ET1 XINTR4 0023 H UART ES XINTR5 002B H T2 ET2 Fractional Divider (Normal Divider Overflow) LIN XINTR6 0033 H ADC EADC IEN1 XINTR7 003B H SSC ESSC XINTR8 0043 H External Interrupt 2 EX2 XINTR9 004B H External Interrupt 3 EXM XINTR10 0053 H CCU6 INP0 ECCIP0 XINTR11 005B H CCU6 INP1 ECCIP1 XINTR12 0063 H CCU6 INP2 ECCIP2 XINTR13 006B H CCU6 INP3 ECCIP3

Data Sheet 50 V 1.1, 2009-03

3.4.3 Interrupt Priority

Each interrupt source, except for NMI, can be individually programmed to one of the four possible priority levels. Th e NMI has the highest priority and supersedes all other interrupts. Two pairs of inte rrupt priority registers (IP and IPH, IP1 and IPH1) are available to program the priority level of each non-NMI interrupt vector. A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot be interrupted by any other interrupt source. If two or more requests of different priority levels ar e received simultaneously, the request of the highest priority is serviced first. If requests of th e same prio rity are received simultaneously, then an internal polling sequence determines which request is serviced first. Thus, within ea ch priority level, there is a second priority structure determined by the polling sequence shown in Table 19. Table 19 Priority Structur e within Interrupt Level Source Level Non-Maskable Interrupt (NMI) (highest) External Interrupt 0 1 Timer 0 Interrupt 2 External Interrupt 1 3 Timer 1 Interrupt 4 UART Interrupt 5 Timer 2,UART Normal Divider Overflow, LIN ADC Interrupt 7 SSC Interrupt 8 External Interrupt 2 9 External Interrupt 3 10 CCU6 Interrupt Node Pointer 0 11 CCU6 Interrupt Node Pointer 1 12 CCU6 Interrupt Node Pointer 2 13 CCU6 Interrupt Node Pointer 3 14

Data Sheet 51 V 1.1, 2009-03

3.5 Parallel Ports

The XC864 has 14 port pins organiz ed into 4 parallel ports, Port 0 (P0) to Port 3 (P3). Each pin has a pair of inte rnal pull-up and pull-down dev ices that can be individually enabled or disabled. Ports P0, P1 and P3 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected. Port P2 is an input-only port, pr oviding general purpose input functions, alternate input functions for the on-chip perip herals, and also a nalog inputs for the Analog-to-Digital Converter (ADC). Note: P1.0 and P1.1 are bonded to the same package pin. See Section 2.3 for the limitation of using these port pins. Bidirectional Port Features:

• Configurable pin direction
• Configurable pull-up/pull-down devices
• Configurable o pen drain mode
• Transfer of data through digital inpu ts and outputs (general purpose I/O)
• Alternate input/output for on-chip peripherals Input Port Features:
• Configurable input driver
• Configurable pull-up/pull-down devices
• Receive of data through digita l input (general purpose input)
• Alternate input for on-chip peripherals
• Analog input for ADC module

Data Sheet 52 V 1.1, 2009-03 Figure 17 General Structure of Bidirectional Port Px_OD Open Drain Control Register Px_Data Data Register Internal Bus AltDataOut 2 Px_ALTSEL0 Alternate Select Register 0 Px_ALTSEL1 Alternate Select Register 1 AltDataIn Pin Px_PUDEN Pull-up/Pull-down Enable Register Px_PUDSEL Pull-up/Pull-down Select Register AltDataOut1 Pad Out In Output Driver Input Driver Schmitt Trigger enable enable Pull Up Device Pull Down Device VDDP enable enable Px_DIR Direction Register AltDataOut 3 11

Data Sheet 53 V 1.1, 2009-03 Figure 18 General Structure of Input Port Px_DATA Data Register Internal Bus AltDataIn Px_PUDEN Pull-up/Pull-down Enable Register Px_PUDSEL Pull-up/Pull-down Select Register In Input Driver Schmitt Trigger AnalogIn Px_DIR Direction Register Pad Pull Up Device Pull Down Device VDDP enable enable enable Pin

Data Sheet 54 V 1.1, 2009-03

3.6 Power Supply System with Embedded Voltage Regulator

The XC864 microcontroller requires two different levels of power supply:

• 5.0 V for the Embedded Volta ge Regulator (EVR) and Ports
• 2.5 V for the core, memory, on- chip oscillator, and peripherals Figure 19 shows the XC864 power supply system. A power supply of 5.0 V must be provided from the external power supply pi n. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the pow er consumption of the whole chip and the complexity of the application board design. The EVR consists of a main voltage regula tor and a low power voltage regulator. In active mode, both voltage regulators are enabled. In power-down mode, the main voltage regulator is switched off, while the low power voltage re gulator continues to function and provide power supply to the system with low power consumption. Figure 19 XC864 Power Supply System EVR Features:
• Input voltage ( VDDP): 5.0 V
• Output voltage ( VDDC): 2.5 V ± 7.5%
• Low power voltage regulator provided in power-down mode
• VDDC and VDDP prewarning detection
• VDDC brownout detection On-chip OSC CPU & Memory VDDC (2.5V) VDDP (3.3V / 5.0V) VSSP GPIO Ports (P0-P5) EVR Peripheral logic FLASH ADC PLL

Data Sheet 55 V 1.1, 2009-03

3.7 Reset Control

The XC864 has five types of reset: power-on reset, hard ware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC864 is first powered up, t he status of certain pins (see Table 21) must be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired b oot option, which cannot be modified until the next power-on reset or hardware reset. Th is guarantees stable conditions during the normal operation of the device. In order to power up the system properly, the external reset pin RESET must be asserted until VDDC reaches 0.9*VDDC. The delay of external reset can be realized by an external capacitor at RESET pin. This capacitor value must be selected so that VRESET reaches 0.4 V, but not before VDDC reaches 0.9* VDDC. A typical application example is shown in Figure 20. VDDP capacitor value is 300 nF. VDDC capacitor value is 220 nF. The capacitor connected to RESET pin is 100 nF. Typically, the time taken for VDDC to reach 0.9* VDDC is less than 50 µs once VDDP reaches 2.3V. Hence, based on the condition that 10% to 90% VDDP (slew rate) is less than 500 µs, the RESET pin should be held low for 500 µs typically. See Figure 21. Figure 20 Reset Circuitry VSSP VDDP VDDC VSSC RESET EVR e.g. 300nF 220nF typ. 100nF XC864 30k

Data Sheet 56 V 1.1, 2009-03 Figure 21 VDDP, VDDC and VRESET during Power-on Reset The second type of reset is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin RESET is provided for the hardware reset. To ensure the recognition of the hardware reset, pin RESET must be held low for at least 100 ns. The Watchdog Timer (WDT) module is also capable of resetting the device if it detects a malfunction in the system. Another type of reset that needs to be detected is a re set while the device is in power-down mode (wake-up reset). While the contents of the static RAM are undefined after a power-on reset, they are well defin ed after a wake-up reset from power-down mode. VDDP RESET wit h capacitor 2.3V VDDC < 0.4V 0.9*VDDC 2.5V Voltage Voltage Time Time typ. < 50 u s

Data Sheet 57 V 1.1, 2009-03

3.7.1 Module Reset Behavior

Table 20 shows how the functions of the XC864 are affected by the various reset types. A “ ” means that this function is reset to its default state. Table 20 Effect of Reset on Device Functions Module/ Function Wake-Up Reset Watchdog Reset Hardware Reset Power-On Reset Brownout Reset CPU Core Peripherals On-Chip Static RAM Not affected, reliable Not affected, reliable Not affected, reliable Affected, un- reliable Affected, un- reliable Oscillator, PLL Not affected Port Pins EVR The voltage regulator is switched on Not affected FLASH NMI Disabled Disabled

Data Sheet 58 V 1.1, 2009-03

3.7.2 Booting Scheme

When the XC864 is reset, it must identify the type of configuration with which to start the different modes once the re set sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins TMS and P0.0 collectively select the different boot options. Table 21 shows the available boot options in the XC864. Note: The boot options are valid only with the default set of UART and JTAG pins.

3.7.2.1 User Mode Entry in BSL Mode

In XC864, User Mode is entered through the BSL Mode. The entry also depends on the type of Flash protection 1) and the NAC (No_Activity_C ount) values. NAC is a user defined parameter as described in each type of user mode entry. There are three types of Us er Mode entry. Each entry wa s designed to be used under different situations. User Mode Entry 1

• TMS = 0 during power-on re set or hardware reset
• Flash is not prot ected (PASSWORD[7:0]2) =0 0H)
• Flash address 0000 H is non-zero value
• NAC is valid Once the chip is in BSL mode with Flash memory not protected and a non-zero at Flash address 0000H, User Mode can be entered with or without delay depending on the NAC values. Delays are calculat ed based on the equation of [(NAC - 1) * 5 ms] where NAC value ranges from 01H -0 CH. Table 22 summarises different type of actions related to the NAC value. In order to ensure the validity of the NAC, the inverted values (NAC) are needed to programmed togerther with the actual values. Table 21 XC864 Boot Selection TMS P0.0 Type of Mode PC Start Value 0 x BSL Mode(User Mode) 1); on-chip OSC/PLL non- bypassed 1) User Mode is enterd via BSL Mode depends on the use r-parameter No_Activity_Count(NAC) and the Flash protection. 0000H 1 0 OCDS Mode; on-chip OSC/PLL non-bypassed 0000 H 1) Flash protection has to be taken and use with proper care as it will directly impact the usage of BSL mode and entry to User Mode. Refer to the 3 types of User Mode entry for detail descriptions. 2) Flash protection can be enabled or disabled by installing the user PASSWORD via BSL mode 6.

Data Sheet 59 V 1.1, 2009-03 Once NAC and NAC is programmed within the valid range, entry to User Mode is always possible. If a LIN frame is received within the delay period(NAC = 02H to 0CH), it will be processed as in the BSL m ode and User mode will not be entered. Alternatively, user can erase the NAC values (and/or program an invalid NAC) to enter BSL mode. This can be done by having a Flash erase(/program) user-routine in the Flash memory. User Mode Entry 2

• TMS = 0 during power-on re set or hardware reset
• Flash is protec ted (PASSWORD[0]1) =1 B)
• NAC is valid (01 H -0 CH) Once the chip is in BSL mode and Flash memory is protected with LSB of PASSWORD set to 1, User Mode can be entered with or without delay depending on the NAC values. The concept of using NAC as delays are similiar to User Mode Entry 1 except for the definition of NAC parameter when flash is protected. Once NAC is valid and programmed with the valid range, entry to User Mode is always possible. If a LIN frame is receiv ed within the delay period (NAC = 02 H to 0C H) as specified in Table 22, it will be processed as in the BSL mode and User mode will not be entered. Alternatively, user can erase the NAC value ( and/or program an invalid NAC) to enter BSL mode. This can be done by having a user-rout ine in Flash to erase the Table 22 Type of Actions related to the NAC value NAC Value Action 01H 0 ms delay. Jump to User Mode immediately 02H 5 ms delay before jumping to User Mode 03H 10 ms delay before jumping to User Mode 04H 15 ms delay before jumping to User Mode 05H 20 ms delay before jumping to User Mode 06H 25 ms delay before jumping to User Mode 07H 30 ms delay before jumping to User Mode 08H 35 ms delay before jumping to User Mode 09H 40 ms delay before jumping to User Mode 0AH 45 ms delay before jumping to User Mode 0BH 50 ms delay before jumping to User Mode 0CH 55 ms delay before jumping to User Mode 0DH -0 F FH, 00H Enter BSL Mode (Invalid NAC) 1) Flash protection can be enabled or disabled by installing the user PASSWORD via BSL mode 6.

Data Sheet 60 V 1.1, 2009-03 existing NAC values and program an invalid NAC located in address(0FF8 H) if flash protection mode 0(MSB of PASSWORD is 0) is selected. When Flash protetcion mode 1(MSB of PASSWORD = 1) is selected, the only way to enter BSL mode is to send a LIN frame within the delay period. Note: Entering of BSL Mode is not possible if MSB of PASSWORD is 1 and NAC is 01H. User Mode Entry 3

• TMS = 0 during power-on re set or hardware reset
• Flash is protec ted (PASSWORD[0]1) =0 B) Once the chip is in BSL mode and Flash memory is protected with LSB of PASSWORD set to 0, User Mode will be en tered immediately. Entering of BSL Mode is not possible in this type of User mode entry. Hence, c hanging of Flash code, XRAM code or flash protection scheme is not allowed. If there is an intention to upgrade Flash content, a pre- defined routine in the user code via In-Appl ication Programming can be used. But it is possible only if flash prot ection mode 0(MSB of PASSWO RD to 0) is selected. This option can be applied to all the user entry mode to change the flash content. 1) Flash protection can be enabled or disabled by installing the user PASSWORD via BSL mode 6.

Data Sheet 61 V 1.1, 2009-03

3.8 Clock Generation Unit

The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the XC864. The power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is directly proportional to the frequency. During user program execution, the fr equency can be programmed fo r an optimal ratio between performance and power cons umption. Therefore the power consumption can be adapted to the actual application state. Features:

• Phase-Locked Loop (PLL) for multiplying clock source by different factors
• PLL Base Mode
• Prescaler Mode
• PLL Mode
• Power-down mode support The CGU consists of an oscillator circuit and a PLL.In the XC864, the oscillator is the on- chip oscillator (10 MHz). In addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows emergency routines to be executed for system recovery or to perform system shut down. Figure 22 CGU Block Diagram The clock system provides three ways to generate the system clock: PLL core lock detect N:1 P:1 fvco fn fp osc fail detect OSC fosc K:1 fsys NDIV OSCR LOCK VCOBYP OSCDISC

Data Sheet 62 V 1.1, 2009-03 PLL Base Mode The system clock is derived from the VCO base (free running) frequency clock divided by the K factor. [1] Prescaler Mode (VCO Bypass Operation) In VCO bypass operation, the system clock is derived from the oscillator clock, divided by the P and K factors. [2] PLL Mode The system clock is derived from the oscill ator clock, multipli ed by the N factor, and divided by the P and K factors. VCO bypass must be inactive for this PLL mode. . [3] Table 3-1 shows the settings of bits OSCDISC and VCOBYP for different clock mode selection. Note: When oscillator clock is disconnected from PLL, the clock mode is PLL Base mode regardless of the setting of VCOBYP bit. In normal running mode, the system works in the PLL mode. Table 3-1 Clock Mode Selection OSCDISC VCOBYP Clock Working Modes 0 0 PLL Mode 0 1 Prescaler Mode 1 0 PLL Base Mode 1 1 PLL Base Mode fSYS fVCObase K----×= fSYS fOSC fSYS fOSC N

Data Sheet 63 V 1.1, 2009-03 For the XC864, the value of P and K are fixed to 1 and 2 respectively. In order to obtain the required fsys at 80 MHz with a fixed oscillator frequency of 10 MHz, the N factor must be set to 16 by programming the NDIV bits to “0010”. In XC864, the output frequency needs to be at 80 MHz. For fsys = 80 MHz and K = 2, fvco = fsys *2 = 160 MHz, VCOSEL bit in CMCON register must be set to 0 to select the VCO range of 150 MHz - 200 MHz.

Data Sheet 64 V 1.1, 2009-03

3.8.1 Clock Management

The CGU generates all clock signals required within the mi crocontroller from a single clock, f sys. During normal system operation, th e typical frequencies of the different modules are as follow:

• CPU clock: CCLK, SCLK = 26.7 MHz
• CCU6 clock: FCLK = 26.7 MHz
• Other peripherals: PCLK = 26.7 MHz
• Flash Interface clock: CCLK3 = 80 MHz, CCLKn = 80 MHz and CCLK = 26.7 MHz In addition, different clock frequency can output to pin CLKOUT(P0.0). The clock output frequency can further be divid ed by 2 using toggle latch (b it TLEN is set to 1), the resulting output frequency has 50% duty cycle. Figure 23 shows the clock distribution of the XC864. Figure 23 Clock Generation from f sys PLL N,P,K fsys CLKREL FCLK CCLK SCLK PCLK CCU6 CORE PeripheralsOSC fosc FLASH Interface CCLK3 CLKOUT COREL COUTS Toggle Latch TLEN CCLKn

Data Sheet 65 V 1.1, 2009-03 For power saving purposes, the clocks may be disabled or slowed down according to Table 23. Note: Flash programming and eras ing can only be performed at f sys =8 0M H z . However, Flash read access can be performed as long as fsys < 80 MHz. Table 23 System frequency (f sys =8 0M H z ) Power Saving Mode Action Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all t he peripherals, including CCU6, are divided by a common programmable factor defined by bit field CMCON.CLKREL. Power-down Oscillator an d PLL are switched off.

Data Sheet 66 V 1.1, 2009-03

3.9 Power Saving Modes

The power saving modes of the XC864 prov ide flexible power consumption through a combination of techniques, including:

• Stopping the CPU clock
• Stopping the clocks of individual system components
• Reducing clock speed of so me peripheral components
• Power-down of the entire system with fast restart capability After a reset, the ac tive mode (normal operating m ode) is selected by default (see Figure 24) and the system runs in the main system clock frequency. From active mode, different power saving modes can be selected by software. They are:
• Idle mode
• Slow-down mode
• Power-down mode Figure 24 Transition betw een Power Saving Modes POWER-DOWN IDLE ACTIVE SLOW-DOWN set PD bit set PD bit set IDLE bit set IDLE bit set SD bit clear SD bit any interrupt & SD=0 EXINT0/RXD pin & SD=0 EXINT0/RXD pin & SD=1 any interrupt & SD=1

Data Sheet 67 V 1.1, 2009-03

3.10 Watchdog Timer

The Watchdog Timer (WDT) provides a high ly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an XC864 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an acci dental malfunction of the XC864 will be aborted in a user-specified time period. In debug mode, the WDT is suspended and stops counting. Therefore, there is no need to refresh the WDT during debugging. Features:

• 16-bit Watchdog Timer
• Programmable reload value for upper 8 bits of timer
• Programmable window boundary
• Selectable input frequency of f PCLK/2 or fPCLK/128
• Time-out detection with NMI gen eration and reset prewarning activation (after which a system reset will be performed) The WDT is a 16-bit timer incr emented by a c ount rate of f PCLK/2 or f PCLK/128. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog service access in order to modify the watchdog expire time period. T he lower 8 bits are reset on each service access. Figure 25 shows the block diagram of the WDT unit. Figure 25 WDT Block Diagram WDTREL MUX WDT Low Byte 1:2 Clear WDT Control 1:128 WDT High Byte WDTTO WDTIN fPCLK Logic ENWDT ENWDT_P WDTRS T Overflow/Time-out Control & Window-boundary control WDTWINB

Data Sheet 68 V 1.1, 2009-03 If the WDT is not serviced before the timer overflow, a system malfunction is assumed. As a result, the WDT NMI is triggered (assert WDTTO) and the reset prewarning is entered. The prewarni ng period lasts for 30 H count, after which the system is reset (assert WDTRST). The WDT has a “programmable window boundary” which disallows any refresh during the WDT’s count-up. A refr esh during this win dow boundary constitutes an invalid access to the WDT, causing the reset prewarning to be entered but without triggering the WDT NMI. The system will still be reset after the prewarning period is over. The window boundary is from 0000H to the value obtained from the concatenation of WDTWINB and 00H. After being serviced, the WDT continues counting up from the value (<WDTREL> * 28). The time period for an overflow of the WDT is programmable in two ways:

• the input frequency to the WDT can be selected to be either fPCLK/2 or fPCLK/128
• the reload value WDTREL for the high by te of WDT can be programmed in register WDTREL The period, PWDT, between servicing the WDT and the next overflow can be determined by the following formula: [4] If the Window-Boundary Refr esh feature of the WDT is enabled, the period P WDT between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL, see Figure 26. This period can be calculated using the same formula by replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB should not be smaller than WDTREL. PWDT 2 1W D T I N+ 6×() 216 WDTREL– 28×()× fPCLK

Data Sheet 69 V 1.1, 2009-03 Figure 26 WDT Timing Diagram Table 24 lists the possible watchdog time ran ge that can be achiev ed for different module clock frequencies . Some numbers are rounded to 3 significant digits. Table 24 Watchdog Time Ranges Reload value in WDTREL Prescaler for fPCLK 2 (WDTIN = 0) 128 (WDTIN = 1) 26.7 MHz 26.7 MHz FFH 19.2 µs 1.23 ms 7FH 2.48 ms 159 ms 00H 4.92 ms 315 ms WDTREL WDTWINB time Count FFFFH No refresh allowed Refresh allowed

Data Sheet 70 V 1.1, 2009-03

3.11 Universal Asynchronous Receiver/Transmitter

The Universal Asynchronous Receiver/Transmitter (UAR T) provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously. It is also receive-buffered, i.e., it can co mmence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost. Beside the standard dual pin configuration for UART, single pin communication is also available in XC864. It is supported by the primary UART pin. Features:

• Full-duplex asynchronous modes – 8-bit or 9-bit data frames, LSB first – fixed or variable baud rate
• Receive buffered
• Multiprocessor communication
• Interrupt generation on the completion of a data transmission or reception The UART can operate in four a synchronous modes as shown in Table 25. Data is transmitted on TXD and received on RXD. There are several ways to generate the baud rate clock for the serial port, depending on the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at fPCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock and can be configur ed to either f PCLK/32 or fPCLK/64. The variable b aud rate is set by either the underflow rate on the dedicated baud-rate generator, or by the overflow rate on Timer 1. Table 25 UART Modes Operating Mode Baud Rate Mode 0: 8-bit shift register f PCLK/2 Mode 1: 8-bit shift UART Variable Mode 2: 9-bit shift UART f PCLK/32 or fPCLK/64 Mode 3: 9-bit shift UART Variable

Data Sheet 71 V 1.1, 2009-03

3.11.1 Baud-Rate Generator

The baud-rate generator is based on a programmable 8- bit reload value, and includes divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud rates based on its input clock fPCLK, see Figure 27. Figure 27 Baud-rate Generator Circuitry The baud rate timer is a count-down timer a nd is clocked by eith er the output of the fractional divider (f MOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate generation, the fractional di vider must be configured to fractional divider mode (FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit reload value in register BG and one clock pulse is generated for the serial channel. Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12. The baud rate (fBR) value is dependent on the following parameters:

• Input clock f PCLK
• Prescaling factor (2 BRPRE) defined by bit field BRPRE in register BCON
• Fractional divider (STEP/256) defined by register FDSTEP (to be considered only if fractional divider is enabled and operating in fractional divider mode) FDSTEP FDM Adder FDRES FDEN&FDM clk Fractional Divider Prescaler NDOV ‘0’ FDEN (overflow) fBR 8-Bit Baud Rate Timer 8-Bit Reload Value R fDIV fDIVfPCLK fMOD

Data Sheet 72 V 1.1, 2009-03

• 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG The following formulas calculate the final baud rate without and with the fractional divider respectively: [5] [6] The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module clock of 26.7 MHz, the maximum achievable baud rate is 0.83 MBaud. Standard LIN protocal can support a ma ximum baud rate of 20kHz, the baud rate accuracy is not critical and the fractional divider can be disabled. Only the prescaler is used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of 20kHz to 115.2kHz, t he higher baud rates re quire the use of the fractional divider for greater accuracy. Table 26 lists the various commonly used baud rates with their corresponding parameter settings and deviation errors. The fractiona l divider is disabled and a module clock of 26.7 MHz is used. The fractional divider allows baud rates of higher accuracy (lower deviation error) to be generated. Table 27 lists the resulting de viation errors from ge nerating a baud rate of Table 26 Typical Baud rates for UART with Fractional Divider disabled Baud rate Prescaling Factor (2BRPRE) Reload Value (BR_VALUE + 1) Deviation Error 19.2 kBaud 1 (BRPRE=000 B) 8 7 ( 5 7 H) -0.22 % 9600 Baud 1 (BRPRE=000 B) 174 (AE H) -0.22 % 4800 Baud 2 (BRPRE=001 B) 174 (AE H) -0.22 % 2400 Baud 4 (BRPRE=010 B) 174 (AE H) -0.22 % baud rate fPCLK 16 2 BRPRE BR_VALUE 1+()×× baud rate fPCLK 16 2 BRPRE BR_VALUE 1+()××

Data Sheet 73 V 1.1, 2009-03 115.2 kHz, using different modu le clock frequencies. The fr actional divider is enabled (fractional divider mode) and the corresponding parameter settings are shown.

3.11.2 Baud Rate Generation using Timer 1

In UART modes 1 and 3, Timer 1 can be used for generating the variable baud rates. In theory, this timer could be used in any of its modes. But in practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the required baud rate. The baud rate is determined by the Time r 1 overflow rate and the value of SMOD as follows: [7]

3.12 Normal Divider Mode (8-bit Auto-reload Timer)

Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider mode, while at the same time disables baud rate generation (see Figure 27). Once the fractional divider is enabled (FDEN = 1), it f unctions as an 8-bit auto-reload timer (with no relation to baud rate generation) and counts up from the reload value with each input clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit field STEP in register FDSTEP defines the reload value. At eac h timer overflow, an overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP. The output frequency in normal divider mode is derived as follows: [8] Table 27 Deviation Error for UART wi th Fractional Divider enabled fPCLK Prescaling Factor (2BRPRE) Reload Value (BR_VALUE + 1) STEP Deviation Error 26.67 MHz 1 10 (A H) 177 (B1 H) +0.03 % 13.33 MHz 1 7 (7 H) 248 (F8 H) +0.11 % 6.67 MHz 1 3 (3 H) 212 (D4 H) -0.16 % Mode 1, 3 baud rate 2SMOD fPCLK× fMOD fDIV

Data Sheet 74 V 1.1, 2009-03

3.13 LIN Protocol

The UART can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature provides the capability to detect the baud rate within LIN protocol us ing Timer 2. This allows the UART to be synchronized to the LIN baud rate for data transmission and reception. LIN is a holistic comm unication concept for local inte rconnected networks in vehicles. The communication is based on the SCI (UAR T) data format, a single-master/multiple- slave concept, a clock synchronization fo r nodes without stabilized time base. An attractive feature of LIN is self-synchronization of the sl ave nodes without a crystal or ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the baud rate must be calculated and returned with every message frame. The structure of a LIN frame is shown in Figure 28. The frame consists of the:

• header, which comprises a Break (1 3-bit time low), Synch Byte (55H), and ID field
• response time
• data bytes (according to UART protocol)
• checksum Figure 28 Structure of LIN Frame

3.13.1 LIN Header Transmission

LIN header transmission is only applicable in master mode. In the LIN communication, a master task decides when and which fram e is to be transferred on the bus. It also identifies a slave task to pr ovide the data trans ported by each frame. The information needed for the handshaking betw een the master and slave ta sks is provided by the master task through the header portion of the frame. The header consists of a break and synch pattern followed by an identifier. Among these three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data. Frame slot Frame Response Inter- frame space Response spaceHeader Synch Protected identifier Data 1 Data 2 Data N Checksum

Data Sheet 75 V 1.1, 2009-03 The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes. In the LIN communication, a slave task is r equired to be synchronized at the beginning of the protected identifier fi eld of frame. For this purpos e, every frame starts with a sequence consisting of a brea k field followed by a synch by te field. This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field. Upon entering LIN communication, a connection is establ ished and the transfer speed (baud rate) of the serial communication part ner (host) is automatically synchronized in the following steps: STEP 1: Initialize interface for reception and timer for baud rate measurement STEP 2: Wait for an incoming LIN frame from host STEP 3: Synchronize the baud rate to the host STEP 4: Enter for Master Request Frame or for Slave Response Frame Note: Re-synchronization and setup of baud rate are always done for every Master Request Header or Slave Response Header LIN frame.

Data Sheet 76 V 1.1, 2009-03

3.14 High-Speed Synchronous Serial Interface

The High-Speed Synchronou s Serial Interface (SSC ) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master m ode), using its own 16-bit bau d-rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices or devices using other synchronous serial interfaces. Features:

• Master and slav e mode operation – Full-duplex or ha lf-duplex operation
• Transmit and re ceive buffered
• Flexible data format – Programmable number of data bits: 2 to 8 bits – Programmable shift directio n: LSB or MSB shift first – Programmable clock polarity: idle lo w or high state for the shift clock – Programmable clock/data phase : data shift with leading or trailing edge of the shift clock
• Variable baud rate
• Compatible with Serial Pe ripheral Interface (SPI)
• Interrupt generation – On a transmitter empty condition – On a receiver full condition – On an error condition (receive, phase, baud rate, transmit error)

Data Sheet 78 V 1.1, 2009-03

3.15 Timer 0 and Timer 1

Timers 0 and 1 are co unt-up timers which ar e incremented every machine cycle, or in terms of the input cl ock, every 2 PCLK cycles. Timer 0 can also be incremented in response to a 1-to-0 transition (falling edge) at the external input pin, T0. Both timers are fully compatible and can be configured in four different operating modes for use in a variety of applications, see Table 28. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions are specialized. Table 28 Timer 0 and Timer 1 Modes Mode Operation 0 13-bit timer The timer is essentially an 8-bit counter with a divide-by-32 prescaler. This mode is included solely for compatibility with Intel 8048 devices. 1 16-bit timer The timer registers, TLx and THx, are concatenated to form a 16-bit counter. 2 8-bit timer with auto-reload The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow.

3 Timer 0 operates as two 8-bit timers

The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and retains its count even if enabled.

Data Sheet 79 V 1.1, 2009-03

3.16 Timer 2

Timer 2 is a 16-bit general pur pose timer (THL2) that has two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode. If the prescalar is disabled, Timer 2 counts with an input clock of PCLK/12. Timer 2 continues counting as long as it is enabled. Table 29 Timer 2 Modes Mode Description Auto-reload Up/Down Count Disabled

• Count up only
• Start counting from 16-bit re load value, overflow at FFFFH
• Reload event configurable for trigger by overflow condition only, or by negative/positive edge at input pin T2EX as well
• Programmble reload value in register RC2
• Interrupt is generated with reload event Up/Down Count Enabled
• Count up or down, direction determi ned by level at input pin T2EX
• No interrupt is generated
• Count up – Start counting from 16-bit re load value, overflow at FFFFH – Reload event triggered by overflow condition – Programmble reload value in register RC2
• Count down – Start counting from FFFF H, underflow at value defined in register RC2 – Reload event triggered by underflow condition – Reload value fixed at FFFF H Channel capture
• Count up only
• Start counting from 0000 H, overflow at FFFFH
• Reload event triggered by overflow condition
• Reload value fixed at 0000 H
• Capture event triggered by fall ing/rising edge at pin T2EX
• Captured timer value stored in register RC2
• Interrupt is generated with reload or capture event

Data Sheet 80 V 1.1, 2009-03

3.17 Capture/Compare Unit 6

The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (P WM) generation, especially for AC-motor control. The CCU6 also supports specia l control modes for block commutation and multi-phase machines. The timer T12 can function in capture and/or compare mode for its three channels. The timer T13 can work in compare mode only. The multi-channel control unit generates output patterns, whic h can be modulated by T12 and/or T13. The modulation sources can be select ed and combined for the signal modulation. Timer T12 Features:

• Three capture/co mpare channels, each channel can be used either as a capture or as a compare channel
• Supports generation of a three-phase PWM (six outputs, individual signals for highside and lowside switches)
• 16-bit resolution, maxi mum count frequency = peripheral clock frequency
• Dead-time control for each channel to av oid short-circuits in the power stage
• Concurrent update of the required T12/13 registers
• Generation of center-ali gned and edge-aligned PWM
• Supports single-shot mode
• Supports many interrupt request sources
• Hysteresis-like control mode Timer T13 Features:
• One independent compare channel with one output
• 16-bit resolution, maxi mum count frequency = peripheral clock frequency
• Can be synchronized to T12
• Interrupt generation at pe riod-match and compare-match
• Supports single-shot mode Additional Features:
• Implements block commutat ion for Brushless DC-drives
• Position detection vi a Hall-sensor pattern
• Automatic rotational speed me asurement for block commutation
• Integrated error handling
• Fast emergency stop without CPU l oad via external signal (CTRAP
• Control modes for mu lti-channel AC-drives
• Output levels can be selected and adapted to the power stage

Data Sheet 81 V 1.1, 2009-03 The block diagram of the CCU6 module is shown in Figure 30. Figure 30 CCU6 Block Diagram channel 0 channel 1 channel 2 T12 dead- time control input / output control CC62 COUT62 CC61 COUT61 CC60 COUT60 COUT63 CTRAP channel 3T13 CCPOS0 2221 start compare captu re multi- channel control address decoder clock control interrupt control trap control compare compar e compar e compar e trap input port control CCPOS1 CCPOS2 outpu t select outpu t select Ha ll input module kernel CCU6_block_diagram T13HR T12HR

Data Sheet 82 V 1.1, 2009-03

3.18 Analog-to-Digital Converter

The XC864 includes a high-performance 8-bi t Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert t he analog voltage levels from up to eight different sources. The analog input channels of the ADC are available at Port 2. Features:

• Successive approximation
• 8-bit resolution or 10-bit resolution
• Eight analog channels
• Four independent result registers
• Result data protection for slow CPU access (wait-for-read mode)
• Single conversion mode
• Autoscan functionality
• Limit checking for conversion results
• Data reduction filter (accumulation of up to 2 conversion results)
• Two independent conversi on request sources with programmable priority
• Selectable conversion request trigger
• Flexible interrupt generation with configurable service nodes
• Programmable sample time
• Programmable clock divider
• Cancel/restart feature for running conversions
• Integrated sample and hold circuitry
• Compensation of offset errors
• Low power modes

Data Sheet 83 V 1.1, 2009-03

3.18.1 ADC Clocking Scheme

A common module clock f ADC generates the various clo ck signals used by the analog and digital parts of the ADC module:

• f ADCA is input clock for the analog part.
• f ADCI is internal clock for the analog part (defines the time base for conversion length and the sample time). This clock is generated internally in the analog part, based on the input clock fADCA to generate a correct duty cycle for the analog components.
• f ADCD is input clock for the digital part. The internal clock for the analog part fADCI is limited to a maximum frequency of 10 MHz. Therefore, the ADC clock prescaler must be programmed to a value that ensures fADCI does not exceed 10 MHz. The prescaler rati o is selected by bit field CTC in register GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required. Figure 31 ADC Clocking Scheme For module clock fADC = 26.7 MHz, the analog clock fADCI frequency can be selected as shown in Table 30. analog components fADCI fADC= fPCLK MUX arbiter registers interrupts analog part digital part fADCD fADCA 32÷ clock prescaler CTC ≤Condition: fADCI 10 MHz, where tADCI = fADCI

Data Sheet 84 V 1.1, 2009-03 As fADCI cannot exceed 10 MHz, bit field CTC should not be set to 00 B when f ADC is 26.7 MHz. During slow-down mode where fADC may be reduced to 13.3 MHz, 6.7 MHz etc., CTC can be set to 00B as long as the di vided analog clock fADCI does not exceed 10 MHz. However, it is important to note that the conversion error could increase due to loss of charges on the capacitors, if fADC becomes too low during slow-down mode.

3.18.2 ADC Conversion Sequence

The analog-to-digital conversion procedure consists of the following phases:

• Synchronization phase (t SYN)
• Sample phase (t S)
• Conversion phase
• Write result phase (t WR) Figure 32 ADC Conversion Timing Table 30 f ADCI Frequency Selection Module Clock fADC CTC Prescaling Rati o Analog Clock f ADCI 26.7 MHz 00 B ÷ 2 13.3 MHz (N.A) 01B ÷3 8 . 9M H z 10B ÷4 6 . 7M H z 11B (default) ÷ 32 833.3 kHz tS tCONV tWR SAMPLE Bit BUSY Bit Conversion PhaseSample Phase Write Result Phase conversion start trigger Source interrupt Result interrupt tSYN Channel interrupt fADCI

Data Sheet 85 V 1.1, 2009-03

3.19 On-Chip Debug Support

The On-Chip Debug Support (OCDS ) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles:

• use the built-in debug func tionality of the XC800 Core
• add a minimum of hardware overhead
• provide support for most of th e operations by a Monitor Program
• use standard interfaces to comm unicate with the Host (a Debugger) Features:
• Set breakpoints on instruction addr ess and within a specified address range
• Set breakpoints on internal RAM address
• Support unlimited softwa re breakpoints in Flash/RAM code region
• Process external breaks
• Step through t he program code The OCDS functional blocks are shown in Figure 33. The Monitor Mode Control (MMC) block at the center of OCDS system brings together control sign als and supports the overall functionality. The MMC communicates with the XC800 Core, primarily via the Debug Interface, and also receives reset and clock signals. After processing memory address and control signals from the core , the MMC provides proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for work-data and Monitor-sta ck). The OCDS system is accessed through the JTAG 1), which is an interface dedicated exclusively for testing and debugging activities and is not normally used in an application. Note: All the debug functionality described here can normally be used only after XC864 has been started in OCDS mode. 1) The pins of the JTAG port can be assigned to either Port 0 (primary) or Ports 1 and 2 (secondary). User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.

Data Sheet 86 V 1.1, 2009-03 Figure 33 OCDS Block Diagram

3.19.1 NMI-mode priority over Debug-mode

While the core is in NMI-mode (after an NMI-request has been accepted and before the RETI instruction is executed, i.e. the time during a NMI-servicing routine), certain debug functions are blocked/restricted: 1. No external break is possible wh ile the core is servicing an NMI. External break requested inside a NMI-servicing routine will be taken only after RETI is executed. 2. A breakpoint into NMI-servicing routine is taken, but single-step is not possible afterwards. If a step is requested, the servicing routine will run as coded and monitor mode will be invoked again only after a RETI is executed. Hardware breakpoints and software breakpoints proceed as normal while CPU is in NMI- mode. JTAG Module JTAG Memory Control Unit User Program Memory XC800 PROG & IRAM Addresses Debug Interface Reset Clock TMS TCK TDI TDO TCK TDI TDO Control Memory Control Primary Debug Interface System Control Boot/ Monitor ROM Monitor RAM User Internal RAM Reset Reset Clock PROG Data Monitor Mode Control NMI Report -p a r t s o f OCDS OCDS_XC864-Block_Diagram-UM-v0.1 Suspend Control

Data Sheet 87 V 1.1, 2009-03

3.19.2 Debug-Suspend of Timers

During debugging (while in Monitor Mo de) and the debug-sus pend functionality is enabled (MMCR2.DSUSP = 1, de fault), timers in certai n modules in XC864 can be suspended based on the setti ngs of their corresponding module suspend bits in the register MODSUSP. When suspended, only the timer stops counting as the counter input clock is gated off. T he module is still clocked so that module registers are accessible. This feature could be quite useful, especially regarding the Watchdog Timer: it allows to prevent XC864 from unintentional WDT-resets while the user software is not executed and respectively - not able to service the Watchdog. MODSUSP Module Suspend Control Register Reset Value: 01 H 76543210

0 T2SUSP T13SUSP T12SUSP WDTSUSP

Field Bits Typ Description WDTSUSP 0r w Watchdog Timer Debug Suspend Bit

0 Watchdog Timer will not be suspended

1 Watchdog Timer will be suspended

T12SUSP 1r w Timer 12 Debug Suspend Bit

0 Timer 12 in Capture/Co mpare Unit will not be

1 Timer 12 in Capture/ Compare Unit will be

T13SUSP 2r w Timer 13 Debug Suspend Bit

0 Timer 13 in Capture/Co mpare Unit will not be

1 Timer 13 in Capture/ Compare Unit will be

T2SUSP 3r w Timer 2 Debug Suspend Bit

0 Timer 2 will not be suspended

1 Timer 2 will be suspended

0 [7:4] r Reserved Returns 0 if read; should be written with 0.

Data Sheet 88 V 1.1, 2009-03 Also suspending the other timer-modules makes sense for debugging: once the application is not running, stopping counters helps for a more complete “freeze” of the device-status during a break. It must be noted, in XC864 all of the debug suspend control bits other than that of WDT, have values 0 after reset, i.e. by default the module will not be suspended upon a break. But normally for debugging, t he device will be started in OCDS mode and then the monitor will be invoked before to star t any user code. Then it is possible using a debugger to configure suspend-controls as desired and only afterwards start the debug- session.

3.19.3 JTAG ID Register

This is a read-only register located inside the JTAG module, and is used to recognize the device(s) connected to the JTAG interface. Its content is shifted out when INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is also true immediately after reset. The JTAG ID for XC864 is 1013 8083H.

Data Sheet 89 V 1.1, 2009-03

3.20 Chip Identification Number

The XC864 identity (ID) register is located at Page 1 of address B3 H. The value of ID register is 1B H. However, for easy id entification of product variants, the Chip Identification Number, which is an unique number assigned to each product variant, is available. The differentiati on is based on the product, variant type and device step information. The Chip Identification Numbers associated with XC864 are 1B810C00H for 5V device and 1B010C00H for 3.3V device. Two methods are provided to read a device’s Chip Identification Number:

• In-application subroutine, GET_CHIP_INFO
• Bootstrap loader (BSL) mode A

Data Sheet 90 V 1.1, 2009-03

4 Electrical Parameters

This chapter provides the characteristi cs of the electrical parameters which are implementation-specific for the XC864.

4.1 General Parameters

The general parameters are described here to aid the us ers in interpreting the parameters mainly in Chapter 4.2 and Chapter 4.3.

4.1.1 Parameter Interpretation

The parameters listed in this section repr esent partly the characteristics of the XC864 and partly its requirements on the system. To aid interpre ting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the “Symbol” column:

• CC These parameters indicate Controller Characteristics, which are distinctive features of the XC864 and must be regarded for a system design.
• SR These parameters indicate System Requirements, which must be provided by the microcontroller system in which the XC864 is designed in.

Data Sheet 91 V 1.1, 2009-03

4.1.2 Absolute Maximum Rating

Maximum ratings are the extreme limits to which the XC864 can be subjected to without permanent damage. Table 31 Absolute Maximu m Rating Parameters Note: Stresses above thos e listed under “Absolute Ma ximum Ratings” may cause permanent damage to the device. This is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for exten ded periods may affect device reliability. During absolute maximum rati ng overload conditions (V IN >V DDP or V IN <V SS) the voltage on VDDP pin with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Parameter Symbol Limit Values Unit Notes min. max. Ambient temperature TA -40 125 °C under bias Storage temperature TST -65 150 °C Junction temperature TJ -40 150 °C under bias Voltage on power supply pin with respect to VSS VDDP -0.5 6 V Voltage on core supply pin with respect to VSS VDDC -0.5 3.25 V Voltage on any pin with respect to VSS VIN -0.5 VDDP + 0.5 or max. 6 V Whatever is lower Input current on any pin during overload condition IIN -10 10 mA Absolute sum of all input currents during overload condition Σ|IIN|– 5 0 m A

Data Sheet 92 V 1.1, 2009-03

4.1.3 Operating Conditions

The following operating conditi ons must not be exceeded in order to ensure correct operation of the XC 864. All parameters mentioned in the following table refer to these operating conditions, unless otherwise noted. Table 32 Operating Condition Parameters Parameter Symbol Limit Values Unit Notes/ Conditionsmin. max. Digital power supply voltage VDDP 4.5 5.5 V Digital power supply voltage VDDP 3.0 3.6 V Digital ground voltage VSS 0V Digital core supply voltage VDDC 2.3 2.7 V System Clock Frequency1) 1) fSYS is the PLL output clock. During no rmal operating mode, CPU clock is fSYS / 3. Refer to Figure 23 for details. fSYS 74 86 MHz Ambient temperature TA -40 85 °C SAF-XC864... -40 125 °C SAK-XC864...

Data Sheet 93 V 1.1, 2009-03

4.2 DC Parameters

4.2.1 Input/Output Characteristics

Table 33 Input/Output Characteristi cs (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max. V DDP = 5V Range Output low voltage VOL CC – 1.0 V IOL =1 5m A –0 . 4 V IOL =5m A Output high voltage VOH CC VDDP - 1.0 –V IOH =- 1 5m A VDDP - 0.4 –V IOH =- 5m A Input low voltage on port pins (all except P0.0 & P0.1) VILP SR – 0.3 × VDDP VC M O S M o d e Input low voltage on P0.0 & P0.1 VILP0 SR -0.2 0.3 × VDDP VC M O S M o d e Input low voltage on RESET pin VILR SR – 0.3 × VDDP VC M O S M o d e Input low voltage on TMS pin VILT SR – 0.3 × VDDP VC M O S M o d e Input high voltage on port pins (all except P0.0 & P0.1) VIHP SR 0.7 × VDDP –V C M O S M o d e Input high voltage on P0.0 & P0.1 VIHP0 SR 0.7 × VDDP VDDP VC M O S M o d e Input high voltage on RESET pin VIHR SR 0.7 × VDDP –V C M O S M o d e Input high voltage on TMS pin VIHT SR 0.7 × VDDP –V C M O S M o d e Input Hysteresis1) HYS CC 0.08 × VDDP –V C M O S M o d e Pull-up current2) IPU SR – -10 µA VIH,min -150 – µA VIL,max

Data Sheet 94 V 1.1, 2009-03 Pull-down current2) IPD SR – 10 µA VIL,max 150 – µA VIH,min Input leakage current3) IOZ1 CC -2.5 1 µA 0 < VIN < VDDP, TA ≤ 125°C Overload current on any pin IOV SR -5 5 mA Absolute sum of overload currents Σ|IOV| SR –2 5 m A 4) Voltage on any pin during VDDP power off VPO SR – 0.3 V 5) Maximum current per pin (excluding VDDP and VSS) IM SR – 15 mA Maximum current for all pins (excluding VDDP and VSS) Σ|IM| SR –6 0 m A Maximum current into VDDP IMVDDP SR –8 0 m A Maximum current out of VSS IMVSS SR –8 0 m A V DDP = 3.3V Range Output low voltage VOL CC – 1.0 V IOL =8m A –0 . 4 V IOL =2 . 5m A Output high voltage VOH CC VDDP - 1.0 –V IOH =- 8m A VDDP - 0.4 –V IOH =- 2 . 5m A Input low voltage on port pins (all except P0.0 & P0.1) VILP SR – 0.3 × VDDP VC M O S M o d e Input low voltage on P0.0 & P0.1 VILP0 SR -0.2 0.3 × VDDP VC M O S M o d e Table 33 Input/Output Characteristi cs (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max.

Data Sheet 95 V 1.1, 2009-03 Input low voltage on RESET pin VILR SR – 0.3 × VDDP VC M O S M o d e Input low voltage on TMS pin VILT SR – 0.3 × VDDP VC M O S M o d e Input high voltage on port pins (all except P0.0 & P0.1) VIHP SR 0.7 × V DDP –V C M O S M o d e Input high voltage on P0.0 & P0.1 VIHP0 SR 0.7 × VDDP VDDP VC M O S M o d e Input high voltage on RESET pin VIHR SR 0.7 × VDDP –V C M O S M o d e Input high voltage on TMS pin VIHT SR 0.75 × VDDP –V C M O S M o d e Input Hysteresis1) HYS CC 0.03 × V DDP –V C M O S M o d e Pull-up current2) IPU SR – -5 µA VIH,min -50 – µA VIL,max Pull-down current2) IPD SR – 5 µA VIL,max 50 – µA VIH,min Input leakage current3) IOZ1 CC -2.5 1 µA 0 < VIN < VDDP, TA ≤ 125°C Overload current on any pin IOV SR -5 5 mA Absolute sum of overload currents Σ|IOV| SR –2 5 m A 4) Voltage on any pin during VDDP power off VPO SR – 0.3 V 5) Maximum current per pin (excluding VDDP and VSS) IM SR – 15 mA Maximum current for all pins (excluding VDDP and VSS) Σ|IM| SR –6 0 m A Table 33 Input/Output Characteristi cs (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max.

Data Sheet 96 V 1.1, 2009-03 Maximum current into VDDP IMVDDP SR –8 0 m A Maximum current out of VSS IMVSS SR –8 0 m A 1) Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. 2) Single pull device is enabled for the measurement of P0.0/P1.0. 3) An additional error current ( IINJ) will flow if an overload current flows through an adjacent pin. TMS pin and RESET pin have internal pull devices and are not included in the input leakage current characteristic. 4) Not subjected to production test, verified by design/characterization. 5) Not subjected to production test, verified by design/characterization. However, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin when VDDP is powered off. Table 33 Input/Output Characteristi cs (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max.

Data Sheet 97 V 1.1, 2009-03

4.2.2 Supply Threshold Characteristics

Figure 34 Supply Th reshold Parameters Table 34 Supply Threshold Parameters (Operating Conditions apply) Parameters Symbol Limit Values Unit min. typ. max. VDDC prewarning voltage1) 1) Detection is disabled in power-down mode. VDDCPW CC 2.2 2.3 2.4 V VDDC brownout voltage in active mode1) VDDCBO CC 2.0 2.1 2.3 V RAM data retention voltage VDDCRDR CC 0.9 1.0 1.1 V VDDC brownout voltage in power-down mode2) 2) Detection is enabled in both active and power-down mode. VDDCBOPD CC 1.3 1.5 1.7 V VDDP prewarning voltage VDDPPW CC 3.4 4.0 4.6 V Power-on reset voltage2)3) 3) The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage. VDDCPOR CC 1.3 1.5 1.7 V VDDP VDDC VDDPPW VDDCPOR VDDCPW VDDCBO VDDCBOPD 5.0V 2.5V VDDCRDR

Data Sheet 98 V 1.1, 2009-03

4.2.3 ADC Characteristics

The values in the table be low are given for an analog power supply between 4.5 V to 5.5 V. The ADC can be used with an analog power supply down to 3 V. Note that in this case, the analog part may show a re duced performance.All ground pins (VSS) must be externally connected to one single star point in the sy stem. The voltage difference between the ground pins must not exceed 200mV. Table 35 ADC Characteristics (Ope rating Conditions apply; V DDP = 5V Range) Parameter Symbol Limit Values Unit Test Conditions/ Remarksmin. typ . max. Analog reference voltage VAREF SR VAGND + 1 VDDP VDDP + 0.05 V Analog reference ground VAGND SR VSS - 0.05 VSS VAREF - 1 V Analog input voltage range VAIN SR VAGND – VAREF V ADC clocks f ADC – 20 40 MHz module clock fADCI – – 10 MHz internal analog clock See Figure 31 Sample time tS CC (2 + INPCR0.STC) × tADCI µs Conversion time tC CC See Section 4.2.3.1 µs Total unadjusted error TUE1)CC – – ±1 LSB 8-bit conversion. 2) –– ±2 LSB 10-bit conversion. Differential Nonlinearity DNL CC – ±1 – LSB 10-bit conversion 4) Integral Nonlinearity INL CC – ±1 – LSB 10-bit conversion 4) Offset OFF CC – ±1 – LSB 10-bit conversion 4) Gain GAIN CC – ±1 – LSB 10-bit conversion 4) Switched capacitance at the reference voltage input C AREFSW CC –1 0 2 0 p F 2)3)

Data Sheet 99 V 1.1, 2009-03 Switched capacitance at the analog voltage inputs C AINSW CC – 57p F 2)4) Input resistance of the reference input RAREFC C – 12k Ω 2) Input resistance of the selected analog channel RAIN CC – 1 1.5 k Ω 2) 1) TUE is tested at VAREF =5 . 0V , VAGND =0V , VDDP =5 . 0V . 2) Not subject to production test, verified by design/characterization. 3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this, smaller capacitances are successively switched to the reference voltage. 4) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2. Table 35 ADC Characteristics (Ope rating Conditions apply; V DDP = 5V Range) Parameter Symbol Limit Values Unit Test Conditions/ Remarksmin. typ . max.

Data Sheet 100 V 1.1, 2009-03 Figure 35 ADC Input Circuits

4.2.3.1 ADC Conversion Timing

Conversion time, tC =t ADC × ( 1 + r × (3 + n + STC) ) , where r=C T C+2 f o r C T C=0 0B, 01B or 10B, r = 32 for CTC = 11B, CTC = Conversion Time Control (GLOBCTR.CTC), STC = Sample Time Control (INPCR0.STC), n = 8 or 10 (for 8-bitand 10-bit conversion respectively), t ADC =1/f ADC VAGNDx REXT Analog Input Circuitry VAIN CEXT ANx CAINSW RAIN, On VAGNDx Reference Voltage Input Circuitry CAREFSW RAREF, OnVAREFx VAREF

Data Sheet 101 V 1.1, 2009-03

4.2.4 Power Supply Current

Table 36 Power Supply Curre nt Parameters (Operating Conditions apply; V DDP = 5V range) Table 37 Power Down Current (O perating Conditions apply; V DDP = 5V range) Parameter Symbol Limit Va lues Unit Test Condition typ.1) 1) The typical IDDP values are periodically measured at TA =+2 5 °C and VDDP =5 . 0V . max.2) 2) The maximum IDDP values are measured under worst case conditions (TA = + 125 °C and VDDP =5 . 5V ) . V DDP = 5V Range Active Mode IDDP 22.6 24.5 mA 3) 3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 26.7 MHz(set by on-chip oscillator of 10 MHz and NDIV in PLL_CON to 0010B), RESET = VDDP, no load on ports. Idle Mode IDDP 12.5 14 mA 4) 4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 26.7 MHz, RESET = VDDP, no load on ports. Active Mode with slow-down enabled IDDP 5.6 7.5 mA 5) 5) IDDP (active mode with slow-down mode) is measured wi th: CPU clock and input clock to all peripherals running at 833 KHz by setting CLKREL in CMCON to 0101B, RESET = VDDP, no load on ports. Idle Mode with slow-down enabled IDDP 5.1 7.2 mA 6) 6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 833 KHz by setting CLKREL in CMCON to 0101 B, RESET = VDDP, no load on ports. Parameter Symbol Limit Va lues Unit Test Condition typ.1) 1) The typical IPDP values are measured at VDDP =5 . 0V . max.2) 2) The maximum IPDP values are measured at VDDP =5 . 5V . V DDP = 5V Range Power-Down Mode3) 3) IPDP (power-down mode) has a maximum value of 200 µA at TA = + 125 °C. IPDP 11 0 µ A TA =+2 5 °C.4) 4) IPDP (power-down mode) is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. 5) Not subject to production test, verified by design/characterization.

Data Sheet 102 V 1.1, 2009-03 Table 38 Power Supply Curre nt Parameters (Operating Conditions apply; V DDP = 3.3V range) Table 39 Power Down Current (O perating Conditions apply; V DDP = 3.3V range ) Parameter Symbol Limit Va lues Unit Test Condition typ.1) 1) The typical IDDP values are periodically measured at TA =+2 5 °C and VDDP =3 . 3V . max.2) 2) The maximum IDDP values are measured under worst case conditions (TA = + 125 °C and VDDP =3 . 6V ) . V DDP = 3.3V Range Active Mode IDDP 21.6 23.3 mA 3) 3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 26.7 MHz (set by on-chip oscillator of 10 MHz and NDIV in PLL_CON to 0010B), RESET = VDDP, no load on ports. Idle Mode IDDP 12 13.5 mA 4) 4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 26.7 MHz, RESET = VDDP, no load on ports. Active Mode with slow-down enabled IDDP 5.7 7.3 mA 5) 5) IDDP (active mode with slow-down mode) is measured wi th: CPU clock and input clock to all peripherals running at 833 KHz by setting CLKREL in CMCON to 0101B, RESET = VDDP, no load on ports. Idle Mode with slow-down enabled IDDP 5.4 6.9 mA 6) 6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enable and running at 833 KHz by setting CLKREL in CMCON to 0101 B,, RESET = VDDP, no load on ports. Parameter Symbol Limit Va lues Unit Test Condition typ.1) 1) The typical IPDP values are measured at VDDP =3 . 3V . max.2) 2) The maximum IPDP values are measured at VDDP =3 . 6V . V DDP = 3.3V Range Power-Down Mode3) 3) IPDP (power-down mode) has a maximum value of 200 µA at TA = + 125 °C. IPDP 11 0 µ A TA =+2 5 °C.4) 4) IPDP (power-down mode) is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0= VDDP; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. 5) Not subject to production test, verified by design/characterization.

Data Sheet 103 V 1.1, 2009-03

4.3 AC Parameters

4.3.1 Testing Waveforms

The testing waveforms for rise /fall time, output delay an d output high impedance are shown in Figure 36, Figure 37 and Figure 38. Figure 36 Rise/Fall Time Parameters Figure 37 Testing Waveform, Output Delay Figure 38 Testing Waveform, Output High Impedance 10% 90% 10% 90% VSS VDDP tR tF VDDE / 2 Test Points VDDE / 2 VSS VDDP VLoad + 0.1 V VOH - 0.1 VTiming Reference PointsVLoad - 0.1 V VOL - 0.1 V

Data Sheet 104 V 1.1, 2009-03

4.3.2 Output Rise/Fall Times

Figure 39 Rise/Fall Times Parameters Table 40 Output Rise/Fall Times Parame ters (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max. V DDP = 5V Range Rise/fall times 1) 2) 1) Rise/Fall time measurements are taken with 10% - 90% of the pad supply. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. tR, tF –1 0 n s 2 0 p F . 3) 3) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.125 ns/pF. V DDP = 3.3V Range Rise/fall times1)2) t R, tF –1 0 n s 2 0 p F . 4) 4) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.225 ns/pF. tR 10% 90% 10% 90% tF VSS VDDP

Data Sheet 105 V 1.1, 2009-03

4.3.3 Power-on Reset and PLL Timing

Figure 40 Power-on Reset Timing Table 41 Power-On Reset and PLL Ti ming (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Pad operating voltage VPAD CC 2.3 – – V On-Chip Oscillator start-up time tOSCST CC – – 500 ns Flash initialization time tFINIT CC – 160 – µs RESET hold time1) 1) RESET signal has to be active (low) until VDDC has reached 90% of its maximum value (typ. 2.5V). tRST SR – 500 – µs VDDP rise time PLL lock-in time tLOCK CC – – 200 µs PLL accumulated jitter DP ––0 . 7 n s 2) 2) PLL lock at 80 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 40 and P = 1. VDDP Pads VDDC VPAD OSC tOSCST PLL Reset Initialization Ready t o ReadFlash State PLL unlock PLL lock 2) 3) tLOCK tFINIT 1)Pad state undefined 2)ENPS control 3)As Programmed I)until EVR is stable II)until PLL is locked III) until Flash go to Ready-to-Read IV) CPU reset is released; Boot ROM software begin execution RESET tRST

Data Sheet 106 V 1.1, 2009-03

4.3.4 On-Chip Oscillator Characteristics

Table 42 On-Chip Oscillator Characteri stics (Operating Conditions apply) Parameter Symbol Limit Va lues Unit Test Conditions min. typ. max. Nominal frequency fNOM CC 9.75 10 10.25 MHz under nominal conditions1) after IFX-backend trimming 1) Nominal condition: VDDC =2 . 5V , TA =+2 5 °C. Long term frequency deviation2) 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. ∆fLT CC -5.0 – 5.0 % with respect to fNOM, over lifetime and temperature (-10°C to 85°C), for one device after trimming -6 – 0 % with respect to fNOM, over lifetime and temperature (-40°C to -10°C), for one device after trimming Short term frequency deviation ∆fST CC -1.0 – 1.0 % with respect to fNOM, from <10 ms to 100 ms

Data Sheet 107 V 1.1, 2009-03

4.3.5 JTAG Timing

Table 43 TCK Clock Timing (Ope rating Conditions apply; CL =5 0 p F ) Figure 41 TCK Clock Timing Parameter Symbol Limits Unit min max TCK clock period tTCK SR 50 − ns TCK high time t1 SR 20 − ns TCK low time t2 SR 20 − ns TCK clock rise time t3 SR − 4n s TCK clock fall time t4 SR − 4n s TCK

0.9 VDDP

0.1 VDDP

0.5 VDDP

Data Sheet 108 V 1.1, 2009-03 Table 44 JTAG Timing (Ope rating Conditions apply; CL =5 0 p F ) Figure 42 JTAG Timing Parameter Symbol Limits Unit min max TMS setup to TCK t1 SR 8.0 − ns TMS hold to TCK t2 SR 5.0 − ns TDI setup to TCK t1 SR 11.0 − ns TDI hold to TCK t2 SR 6.0 − ns TDO valid output from TCK t3 CC − 23 ns TDO high impedance to valid output from TCK t4 CC − 26 ns TDO valid output to high impedance from TCK t5 CC − 18 ns TMS TDI TCK TDO t4 t3 t5

Data Sheet 109 V 1.1, 2009-03

4.3.6 SSC Master Mode Timing

Table 45 SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF) SSC Master Mode Timing Parameter Symbol Limit Values Unit min. max. SCLK clock period t0 CC 2*T SSC 1) –n s MTSR delay from SCLK t1 CC 0 8 ns MRST setup to SCLK t2 SR 22 – ns MRST hold from SCLK t3 SR 0 – ns SSC_Tmg1 SCLK1) MTSR1) t1 t1 MRST1) Data valid 1) This timing is based on the following setup: CON.PH = CON.PO = 0.

Data Sheet 110 V 1.1, 2009-03

5 Package and Reliability

5.1 Package Parameters (PG-TSSOP-20)

Table 46 provides the thermal characteristics of the package. Table 46 Thermal Characteristics of the Package Parameter Symbol Limit Values Unit Notes Min. Max. Thermal resistance junction case top1) 1) The top and bottom thermal resistances between the case and the ambient (R TCAT, R TCAB) are to be combined with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (R TCAT, R TCAB) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: T J=TA+RTJA × PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances, by a) simply adding only the two bottom thermal resistances (junction case bottom and case ambient bottom), or b) by taking all four resistances into account, depending on the precision needed. RTJCT CC – 28.5 K/W – Thermal resistance junction case bottom1) RTJCB CC – 43.7 K/W –

Data Sheet 111 V 1.1, 2009-03

5.2 Package Outline

Figure 43 PG-TSSOP-20 Package Outline

Data Sheet 112 V 1.1, 2009-03

5.3 Quality Declaration

Table 47 shows the characteristics of the quality parameters in the XC864. Table 47 Quality Parameters Parameter Symbol Limit Values Unit Notes Min. Max. ESD susceptibility according to Human Body Model (HBM) VHBM – 2000 V Conforming to EIA/JESD22- A114-B ESD susceptibility according to Charged Device Model (CDM) pins VCDM – 500 V Conforming to JESD22-C101-C

Data Sheet 113 V 1.1, 2009-03

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