XC858CA

XC858CA INFINEON | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 124

Technical content

V1.0 2010-03 Microcontrollers 8-Bit XC858CA 8-Bit Single-Chip Microcontroller

81726 Munich, Germany

© 2010 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

V1.0 2010-03 Microcontrollers 8-Bit XC858CA 8-Bit Single-Chip Microcontroller

TriCore™ is a trademark of Infineon Technologies AG. XC858 Data Sheet Revision History: Page Subjects (major chan ges since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

Data Sheet I-1 V1.0, 2010-03 Table of Contents

Data Sheet I-2 V1.0, 2010-03

Data Sheet I-3 V1.0, 2010-03

Data Sheet 1 V1.0, 2010-03 XC858CA8-Bit Single-Chip Microcontroller

1 Summary of Features

The XC858 has the following features:

• High-performance XC800 Core – compatible with sta ndard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers
• On-chip memory – 8 Kbytes of Boot ROM – 256 bytes of RAM – 3 Kbytes of XRAM – 64/52/36 Kbytes of Flash; (includes memory protection strategy)
• I/O port supply at 5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator) (more features on next page) Figure 1 XC858 Functional Units Port 0 Port 1 Port 3 XC800 Core UART ADC 10-bit 8-channel Boot ROM 8K x 8 XRAM 3K x 8 RAM 256 x 8 On-Chip Debug Support Timer 0 16-bit Timer 1 16-bit Timer 2 Capture/ Compare Unit 16-bit UART 1SSC 8-bit Digital I/O 8-bit Digital I/O 8-bit Digital I/O Port 4 Port 5 MultiCAN Timer 21 16-bit Watchdog Timer 8-bit Digital I/O 8-bit Digital I/O Flash 36K/52K/64K x 8 8-bit Analog Input

Data Sheet 2 V1.0, 2010-03 Features: (continued)

• Power-on reset generation
• Brownout detection fo r core logic supply
• On-chip OSC and PLL for clock generation – Loss-of-Clock detection
• Power saving modes – slow-down mode – idle mode – power-down mode with wake-up ca pability via RXD or EXINT0 – clock gating contro l to each peripheral
• Programmable 16-bit Watchdog Timer (WDT)
• Five ports – Up to 40 pins as digital I/O – 8 dedicated analog inputs used as A/D converter input
• 8-channel, 10-bit ADC
• Four 16-bit timers – Timer 0 and Time r 1 (T0 and T1) – Timer 2 and Time r 21 (T2 and T21)
• MultiCAN with 2 nodes , 32 message objects
• Timer 2 Capture/compare unit for PWM signal generation (T2CCU)
• Two full-duplex serial in terfaces (UART and UART1)
• Synchronous serial channel (SSC)
• On-chip debug support – 1 Kbyte of monitor ROM (par t of the 8-Kbyte Boot ROM) – 64 bytes of monitor RAM
• PG-LQFP-64 pin package
• Temperature range T – SAF (-40 to 85 °C)

Data Sheet 3 V1.0, 2010-03 XC858 Variant Devices The XC858 product family features devices with different program memory sizes. The list of XC858 devices and th eir difference are summarized in Table 1. The type of package available is the LQFP-64. As this document refers to all the derivatives, some de scription may not apply to a specific product. For simplicity, all versions are referred to by the term XC858 throughout this document.

Ordering Information

The ordering code for Infineo n Technologies microcontrol lers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temper ature range, and the supply voltage
• The package and the type of delivery For the available ordering codes for the XC858, please refer to your responsible sales representative or your local distributor. Table 1 Device Summary Sales Type Device Type Program Memory (Kbytes) Power Supply (V) Temp- erature (°C) Quality Profile SAF-XC858CA-9FFI 5V Flash 36 5.0 -40 to 85 Industrial SAF-XC858CA-13FFI 5V Flash 52 5.0 -40 to 85 Industrial SAF-XC858CA-16FFI 5V Flash 64 5.0 -40 to 85 Industrial

General Device Information Data Sheet 4 V1.0, 2010-03

2 General Device Information

Chapter 2 contains the block diagram, pin configurations, definitions and functions of the XC858.

2.1 Block Diagram

The block diagram of the XC858 is shown in Figure 2. Figure 2 XC858 Block Diagram ADC Port 0Port 1Port 3 UART1 SSC Timer 2 Capture/ Compare Unit 8-Kbyte Boot ROM1) 256-byte RAM 64-byte monitor RAM 3-Kbyte XRAM 36/52/64-Kbyte Flash XC800 Core T0 & T1 UART 1) Includes 1-Kbyte monitor ROM P0.0 - P0.7 P1.0 - P1.7 P3.0 - P3.7 AN0 – AN7 VAREF VAGND Clock Generator

4 MHz

P4.0 - P4.7 P5.0 - P5.7 WDT OCDS TM

General Device Information Data Sheet 5 V1.0, 2010-03

2.2 Logic Symbol

The logic symbol of the XC858 is shown in Figure 3. Figure 3 XC858 Logic Symbol XC858 VDDP VSSP VDDC VSSC VAREF VAGND XTAL1 XTAL2 TMS MBC Port 0 8-Bit Port 1 8-Bit Port 3 8-Bit AN0 – AN7 Port 4 8-Bit Port 5 8-Bit RESET TM

General Device Information Data Sheet 6 V1.0, 2010-03

2.3 Pin Configuration

The pin configuration of the XC858 in Figure 4. Figure 4 XC858 Pin Configur ation, PG-LQFP-64 Package (top view) VDDP XC858 123 4 56789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RESET P3.5 P3.4 AN2 V DDP P1.3 P1.4 P5.0 P4.2 P4.1 P4.0 P1.2 VSSP P5.1 AN0 P0.3 P0.4 P0.5 P1.6 P1.7 VSSC VDDC XTA L2 XTA L1 TMS MBC P1.0 P1.1 P1.5 AN4 AN3 AN7 AN5 AN6 P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 VAREF VAGND P0.6 P0.7 P4.5 P4.4 P4.6 P4.7 P5.5 P5.6 P5.7 P5.4 VDDP P0.0 N.C. TM P5.3 P4.3 P5.2 VSSP P0.2 P0.1 AN1

General Device Information Data Sheet 7 V1.0, 2010-03

2.4 Pin Definitions and Functions

The functions and default states of the XC858 external pins are provided in Table 2. Table 2 Pin Definiti ons and Functions Symbol Pin Number (LQFP-64) Type Reset State Function P0 I/O Port 0 Port 0 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, UART, UART1, T2CCU, Timer 21, MultiCAN, SSC and External Interface. P0.0 17 Hi-Z TCK_0 CLKOUT_0 RXDO_1 JTAG Clock Input Clock Output UART Transmit Data Output P0.1 21 Hi-Z TDI_0 RXD_1 RXDC1_0 EXF2_1 JTAG Serial Data Input UART Receive Data Input MultiCAN Node 1 Receiver Input Timer 2 External Flag Output P0.2 18 PU TDO_0 TXD_1 TXDC1_0 JTAG Serial Data Output UART Transmit Data Output/Clock Output MultiCAN Node 1 Transmitter Output P0.3 63 Hi-Z SCK_1 RXDO1_0 A17 SSC Clock Input/Output UART1 Transmit Data Output Address Line 17 Output P0.4 64 Hi-Z MTSR_1 TXD1_0 A18 SSC Master Transmit Output/ Slave Receive Input UART1 Transmit Data Output/Clock Output Address Line 18 Output P0.5 1 Hi-Z MRST_1 EXINT0_0 T2EX1_1 RXD1_0 A19 SSC Master Receive Input/Slave Transmit Output External Interrupt Input 0 Timer 21 External Trigger Input UART1 Receive Data Input Address Line 19 Output

General Device Information Data Sheet 8 V1.0, 2010-03 P0.6 2 PU T2CC4_1 WR Compare Output Channel 4 External Data Write Control Output P0.7 62 PU CLKOUT_1 T2CC5_1 RD Clock Output Compare Output Channel 5 External Data Read Control Output Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number (LQFP-64) Type Reset State Function

General Device Information Data Sheet 9 V1.0, 2010-03 P1 I/O Port 1 Port 1 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, UART, Timer 0, Timer 1, T2CCU, Timer 21, MultiCAN, SSC and External Interface. P1.0 34 PU RXD_0 T2EX_0 RXDC0_0 UART Receive Data Input Timer 2 External Trigger Input MultiCAN Node 0 Receiver Input Address Line 8 Output P1.1 35 PU EXINT3_0 T0_1 TXD_0 TXDC0_0 External Interrupt Input 3 Timer 0 Input UART Transmit Data Output/Clock Output MultiCAN Node 0 Transmitter Output Address Line 9 Output P1.2 36 PU SCK_0 A10 SSC Clock Input/Output Address Line 10 Output P1.3 37 PU MTSR_0 SCK_2 TXDC1_3 A11 SSC Master Transmit Output/Slave Receive Input SSC Clock Input/Output MultiCAN Node 1 Transmitter Output Address Line 11 Output P1.4 38 PU MRST_0 EXINT0_1 RXDC1_3 MTSR_2 A12 SSC Master Receive Input/ Slave Transmit Output External Interrupt Input 0 MultiCAN Node 1 Receiver Input SSC Master Transmit Output/Slave Receive Input Address Line 12 Output Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number (LQFP-64) Type Reset State Function

General Device Information Data Sheet 10 V1.0, 2010-03 P1.5 39 PU EXINT5_0 T1_1 MRST_2 EXF2_0 RXDO_0 External Interrupt Input 5 Timer 1 Input SSC Master Receive Input/ Slave Transmit Output Timer 2 External Flag Output UART Transmit Data Output P1.6 10 PU EXINT6_0 RXDC0_2 T21_1 External Interrupt Input 6 MultiCAN Node 0 Receiver Input Timer 21 Input P1.7 11 PU T2_1 TXDC0_2 Timer 2 Input MultiCAN Node 0 Transmitter Output P1.5 and P1.6 can be used as a software chip select output for the SSC. Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number (LQFP-64) Type Reset State Function

General Device Information Data Sheet 11 V1.0, 2010-03 P3 I/O Port 3 Port 3 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for UART1, T2CCU, Timer 21, MultiCAN and External Interface. P3.0 43 Hi-Z RXDO1_1 T2CC0_1/ EXINT3_2 UART1 Transmit Data Output External Interrupt Input 3/T2CCU Capture/Compare Channel 0 P3.1 44 Hi-Z TXD1_1 UART1 Transmit Data Output/Clock Output P3.2 49 Hi-Z RXDC1_1 RXD1_1 T2CC1_1/ EXINT4_2 MultiCAN Node 1 Receiver Input UART1 Receive Data Input External Interrupt Input 4/T2CCU Capture/Compare Channel 1 P3.3 50 Hi-Z TXDC1_1 T2CC2_1/ EXINT5_2 A13 MultiCAN Node 1 Transmitter Output External Interrupt Input 5/T2CCU Capture/Compare Channel 2 Address Line 13 Output P3.4 51 Hi-Z RXDC0_1 T2EX1_0 T2CC3_1/ EXINT6_3 A14 MultiCAN Node 0 Receiver Input Timer 21 External Trigger Input External Interrupt Input 6/T2CCU Capture/Compare Channel 3 Address Line 14 Output P3.5 52 Hi-Z EXF21_0 TXDC0_1 A15 Timer 21 External Flag Output MultiCAN Node 0 Transmitter Output Address Line 15 Output P3.6 41 PU - P3.7 42 Hi-Z EXINT4_0 A16 External Interrupt Input 4 Address Line 16 Output Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number (LQFP-64) Type Reset State Function

General Device Information Data Sheet 12 V1.0, 2010-03 P4 I/O Port 4 Port 4 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for Timer 0, Timer 1, T2CCU, Timer 21, MultiCAN and External Interface. P4.0 59 Hi-Z RXDC0_3 T2CC0_0/ EXINT3_1 MultiCAN Node 0 Receiver Input External Interrupt Input 3/T2CCU Capture/Compare Channel 0 Data Line 0 Input/Output P4.1 60 Hi-Z TXDC0_3 T2CC1_0/ EXINT4_1 MultiCAN Node 0 Transmitter Output External Interrupt Input 4/T2CCU Capture/Compare Channel 1 Data Line 1 Input/Output P4.2 61 PU EXINT6_1 T21_0 External Interrupt Input 6 Timer 21 Input Data Line 2 Input/Output P4.3 40 Hi-Z T2EX_1 EXF21_1 Timer 2 External Trigger Input Timer 21 External Flag Output Data Line 3 Input/Output P4.4 45 Hi-Z T0_0 T2CC2_0/ EXINT5_1 Timer 0 Input External Interrupt Input 5/T2CCU Capture/Compare Channel 2 Data Line 4 Input/Output P4.5 46 Hi-Z T1_0 T2CC3_0/ EXINT6_2 Timer 1 Input External Interrupt Input 6/T2CCU Capture/Compare Channel 3 Data Line 5 Input/Output P4.6 47 Hi-Z T2_0 T2CC4_0 Timer 2 Input Compare Output Channel 4 Data Line 6 Input/Output P4.7 48 Hi-Z T2CC5_0 Compare Output Channel 5 Data Line 7 Input/Output Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number (LQFP-64) Type Reset State Function

General Device Information Data Sheet 13 V1.0, 2010-03 P5 I/O Port 5 Port 5 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for UART, UART1, T2CCU, JTAG and External Interface. P5.0 8 PU EXINT1_1 External Interrupt Input 1 Address Line 0 Output P5.1 9 PU EXINT2_1 External Interrupt Input 2 Address Line 1 Output P5.2 12 PU RXD_2 T2CC2_2/ EXINT5_3 UART Receive Data Input External Interrupt Input 5/T2CCU Capture/Compare Channel 2 Address Line 2 Output P5.3 13 PU EXINT1_0 TXD_2 T2CC5_2 External Interrupt Input 1 UART Transmit Data Output/Clock Output Compare Output Channel 5 Address Line 3 Output P5.4 14 PU EXINT2_0 RXDO_2 T2CC4_2 External Interrupt Input 2 UART Transmit Data Output Compare Output Channel 4 Address Line 4 Output P5.5 15 PU TDO_1 TXD1_2 T2CC0_2/ EXINT3_3 JTAG Serial Data Output UART1 Transmit Data Output/ Clock Output External Interrupt Input 3/T2CCU Capture/Compare Channel 0 Address Line 5 Output P5.6 19 PU TCK_1 RXDO1_2 T2CC1_2/ EXINT4_3 JTAG Clock Input UART1 Transmit Data Output External Interrupt Input 4/T2CCU Capture/Compare Channel 1 Address Line 6 Output Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number (LQFP-64) Type Reset State Function

General Device Information Data Sheet 14 V1.0, 2010-03 P5.7 20 PU TDI_1 RXD1_2 T2CC3_2/ EXINT6_4 JTAG Serial Data Input UART1 Receive Data Input External Interrupt Input 6/T2CCU Capture/Compare Channel 3 Address Line 7 Output Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number (LQFP-64) Type Reset State Function

General Device Information Data Sheet 15 V1.0, 2010-03 VDDP 7, 25, 55 – – I/O Port Supply ( 5.0 V) Also used by EVR and analog modules. All pins must be connected. VSSP 26, 54 – – I/O Ground All pins must be connected. VDDC 6– – Core Supply Monitor (2.5 V) VSSC 5– – Core Supply Ground VAREF 32 – – ADC Reference Voltage VAGND 31 – – ADC Reference Ground AN0 22 I Hi-Z Analog Input 0 AN1 23 I Hi-Z Analog Input 1 AN2 24 I Hi-Z Analog Input 2 AN3 27 I Hi-Z Analog Input 3 AN4 28 I Hi-Z Analog Input 4 AN5 29 I Hi-Z Analog Input 5 AN6 30 I Hi-Z Analog Input 6 AN7 33 I Hi-Z Analog Input 7 XTAL1 4 I Hi-Z External Oscillator Input (Feedback resistor required, normally NC) XTAL2 3 O Hi-Z External Oscillator Output (Feedback resistor required, normally NC) TMS 16 I PD JTAG Test Mode Select RESET 53 I PU Reset Input MBC 58 I PU Monitor & BootStrap Loader Control TM 57 – – Test Mode (External pull down device required) NC 56 – – No Connection Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number (LQFP-64) Type Reset State Function

Data Sheet 16 V1.0, 2010-03

3 Functional Description

Chapter 3 provides an overview of the XC858 functional description.

3.1 Processor Architecture

The XC858 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standar d 8051 processor. While t he standard 8051 processor is designed around a 12-clock machine cycle, the XC858 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. The XC858 CPU provides a r ange of debugging features, including basic stop/start, single-step execution, break point support and r ead/write access to the data memory, program memory and Special Function Registers (SFRs). Figure 5 shows the CPU functional blocks. Figure 5 CPU Block Diagram Register Interface ALU UART Core SFRs 16-bit Registers & Memory Interface Opcode Decoder State Machine & Power Saving Interrupt Controller Multiplier / Divider Opcode & Immediate Registers Timer 0 / Timer 1 Internal Data Memory External SFRs External Data Memory Program Memory fCCLK Memory Wait Reset Legacy External Interrupts (IEN0, IEN1) External Interrupts Non-Maskable Interrupt

Data Sheet 17 V1.0, 2010-03

3.2 Memory Organization

The XC858 CPU operates in the following address spaces:

• 8 Kbytes of Boot ROM program memory
• 256 bytes of intern al RAM data memory
• 3 Kbytes of XRAM memory (XRAM can be read/written as program memory or external data memory)
• A 128-byte Special Function Register area
• 64/52/36 Kbytes of Flash prog ram memory (Flash devices) Figure 6, Figure 7 and Figure 8 illustrates the memory address spaces of the XC858 with 64Kbytes, 52Kbytes and 36Kbytes embedded Flash respectively. Figure 6 Memory Map of XC858 with 64K Flash Memory in user mode External External Reserved Data Space 0' 0000H XRAM

3 KByte

0' FFFFH F' F000H F' FC00H 1' 0000H 1' FFFFH 2' 0000H 2' FFFFH 3' 0000H 3' FFFFH 4' 0000H 4' FFFFH 5' 0000H 5' FFFFH 6' 0000H 6' FFFFH 7' 0000H 7' FFFFH 8' 0000H 8' FFFFH 9' 0000H 9' FFFFH A' 0000H A' FFFFH B' 0000H B' FFFFH C' 0000H C' FFFFH D' 0000H D' FFFFH E' 0000H E' FFFFH F' 0000H F' FFFFH External External 2' FE00H Reserved Reserved Reserved 2' C000H 2' F000H 2' FC00H 2' FEC0H External External External 2' E000H Reserved 0' 0000H 2' FE00H P-Flash

60 KByte

8 KByte

Code Space Internal Data Space Memory Map User Mode D-Flash

4 KByte

0' FFFFH Reserved 0' F000H 1' 0000H 2' C000H 2' F000H 2' FC00H 1' FFFFH 2' 0000H 2' FFFFH 3' 0000H 3' FFFFH 4' 0000H 4' FFFFH 5' 0000H 5' FFFFH 6' 0000H 6' FFFFH 7' 0000H 7' FFFFH 8' 0000H 8' FFFFH 9' 0000H 9' FFFFH A' 0000H A' FFFFH B' 0000H B' FFFFH C' 0000H C' FFFFH D' 0000H D' FFFFH E' 0000H E' FFFFH F' 0000H F' FFFFH Bank 1 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank A Bank B Bank C Bank D Bank E Bank 2Bank 0 2' FEC0H Bank F Reserved Reserved Reserved 2' E000H Extension Stack RAM Memory Extension Stack Pointer (MEXSP) Special Function Registers Indirect Address Direct Address 00H Internal RAM 7FH Internal RAM 80H FFH

Data Sheet 18 V1.0, 2010-03 Figure 7 Memory Map of XC858 with 52K Flash Memory in user mode ExternalReserved External External 0000H F000H C000H E000H FC00H FFFFH FE00H Reserved P-Flash

48 KByte

2 KByte

Code Space Internal Data Space Memory Map User Mode FEC0H Extension Stack RAM Memory Extension Stack Pointer (MEXSP) Special Function Registers Indirect Address Direct Address 00H Internal RAM 7FH Internal RAM 80H FFH F000H FC00H 0000H FFFFH Data Space XRAM 1'0000H F’FFFFH 1'0000H F’FFFFH

Data Sheet 19 V1.0, 2010-03 Figure 8 Memory Map of XC858 with 36K Flash Memory in user mode ExternalReserved External External 0000H F000H C000H E000H FC00H FFFFH 8000H FE00H Reserved P-Flash

32 KByte

Code Space Internal Data Space Memory Map User Mode FEC0H Reserved Extension Stack RAM Memory Extension Stack Pointer (MEXSP) Special Function Registers Indirect Address Direct Address 00H Internal RAM 7FH Internal RAM 80H FFH F000H FC00H 0000H FFFFH Data Space XRAM 1'0000H F’FFFFH 1'0000H F’FFFFH

Data Sheet 20 V1.0, 2010-03

3.2.1 Memory Protection Strategy

The XC858 memory protection strategy includes:

• Basic protection: The user is able to block any external access via the boot option to any memory
• Read-out protection: The user is able to protect the contents in the Flash
• Flash program and erase protection These protection strategies are enabled by programming a valid password (16-bit non- one value) via Bootstrap Loader (BSL) mode 6.

3.2.1.1 Flash Memory Protection

As long as a valid password is available, all external access to the device, including the Flash, will be blocked. For additional security, the Flash hardware protection can be enabled to implement a second layer of read-out protection, as well as to enable program and erase protection. Flash hardware protection is available only for Flash devices and comes in two modes:

• Mode 0: Only the P-Flash is prot ected; the D-Flash is unprotected
• Mode 1: Both the P-Flash and D-Flash are protected The selection of each protection mode and the restrictions imposed are summarized in Table 3. Table 3 Flash Protection Modes Flash Protection Without hardware protection With hardware protection Hardware Protection Mode -0 1 Activation Program a valid password via BSL mode 6 Selection Bit 13 of password = 0 Bit 13 of password = 1 MSB of password = 0 Bit 13 of password = 1 MSB of password = 1 P-Flash

contents

Not possible Not possible Not possible

Data Sheet 21 V1.0, 2010-03 BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed password must be provided by the user. To disable the flash protection, a password match is required. A password match triggers an automatic erase of the protected P-Flash and D- Flash contents, including the programmed password. With a valid passwor d, the Flash hardware protection is then enabled or disabled upon next reset. For the other protec tion strategies, no reset is necessary. Although no protection scheme can be c onsidered infallible, the XC858 memory protection strategy provides a very high level of protec tion for a general purpose microcontroller. P-Flash program and erase Possible Possible only on the condition that MSB - 1 of password is set to 1 Possible only on the condition that MSB - 1 of password is set to 1 D-Flash Not possible Not possible Not possible D-Flash program Possible Possible Possible, on the condition that MSB - 1 of password is set to 1 D-Flash erase Possible Possible, on these conditions:

• MISC_CON.DFLASH EN bit is set to 1 prior to each erase operation; or
• the MSB - 1 of password is set to 1 Possible, on the condition that MSB - 1 of password is set to 1 Table 3 Flash Protection Modes (cont’d) Flash Protection Without hardware protection With hardware protection

Data Sheet 22 V1.0, 2010-03

3.2.2 Special Function Register

The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80H to FFH. All registers, except the program counter, reside in the SFR area. The SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than th e total number of registers required, address extension mechanisms ar e required to increa se the number of addressable SFRs. The address extension mechanisms include:

• Mapping
• P a g i n g

3.2.2.1 Address Extension by Mapping

Address extension is performed at the syst em level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80H to FFH, bringing the number of addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bi t RMAP in the system control register SYSCON0 at address 8F H. T o a c c e s s S F R s i n t h e mapped area, bit RMAP in SFR SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 9. As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus , before standard/ma pped registers are accessed, bit RMAP must be cleared/set, respectively, by software.

Data Sheet 23 V1.0, 2010-03 Figure 9 Address Extension by Mapping Module 1 SFRs …... SYSCON0.RMAP SFR Data (to/from CPU) rw Standard Area (RMAP = 0) …... 80H FFH 80H FFH Direct Internal Data Memory Address Mapped Area (RMAP = 1) Module 2 SFRs Module n SFRs Module (n+1) SFRs Module (n+2) SFRs Module m SFRs

Data Sheet 24 V1.0, 2010-03 Note: The RMAP bit should be cl eared/set by ANL or ORL in structions.The rest bits of SYSCON0 should not be modified.

3.2.2.2 Address Extension by Paging

Address extension is further performed at the module level by paging. With the address extension by mapping, the XC858 has a 256-SFR address r ange. However, this is still less than the total number of SFRs needed by the on-chi p peripherals. To meet this requirement, some peripherals have a built-i n local address extens ion mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bi t field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SF Rs per page, dependi ng on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 10. SYSCON0 System Control Register 0 Reset Value: 04 H 76543210

0 IMODE 0 1 0 RMAP

Field Bits Type Description RMAP 0r w Interrupt Node XINTR0 Enable

0 The access to the st andard SFR area is

1 The access to the m apped SFR area is

Returns 1 if read; should be written with 1. 0 [7:5], 3,1 r Reserved Returns 0 if read; should be written with 0.

Data Sheet 25 V1.0, 2010-03 Figure 10 Address Extension by Paging In order to access a register located in a page different from the actual one, the current page must be exited. This is done by reprog ramming the bit fi eld PAGE in the page register. Only then can the desired access be performed. If an interrupt routine is initiated be tween the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can:

• Save the contents of PAGE in STx be fore overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or SFR0 SFR1 SFRx …... PAGE 0 SFR0 SFR1 SFRy …... PAGE 1 …... SFR0 SFR1 SFRz …... PAGE q MOD_PAGE.PAGE SFR Address (from CPU) SFR Data (to/from CPU) rw Module

Data Sheet 26 V1.0, 2010-03

• Overwrite the contents of PAGE with the co ntents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt ro utine to restore the previous page setting before the interrupt occurred) Figure 11 Storage Elements for Paging With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write oper ations makes the system simp ler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The XC858 supports local address extension for:
• Parallel Ports
• Analog-to-Digital Converter (ADC)
• System Control Registers PAGE ST0 ST1 ST2 ST3 value update from CPU STNR

Data Sheet 27 V1.0, 2010-03 The page register has the following definition: MOD_PAGE Page Register for module MOD Reset Value: 00 H 76543210 OP STNR 0 PAGE ww rr w Field Bits Type Description PAGE [2:0] rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. STNR [5:4] w Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11 the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 ST0 is selected. 01 ST1 is selected. 10 ST2 is selected. 11 ST3 is selected.

Data Sheet 28 V1.0, 2010-03

3.2.3 Bit Protection Scheme

The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit field PASS closes access to writing of all prot ected bits. In both cases, the value of the bit field MODE is not changed even if PASSWD register is written with 98H or A8H. It can only be changed when bit field PASS is written with 11000B, for example, writing D0H to PASSWD register disables the bit protection scheme. Note that access is opened for maximum 32 CCLKs if the “close access” password is not written. If “open access” password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protecte d bits include the N- and K- Divider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the power- down and slow-down enable bits, PD and SD. OP [7:6] w Operation 0X Manual page mode. Th e value of STNR is ignored and PAGE is directly written.

10 New page programming with automatic page

saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. 0 3r Reserved Returns 0 if read; should be written with 0. Field Bits Type Description

Data Sheet 29 V1.0, 2010-03

3.2.3.1 Password Register

Password Register Reset Value: 07 H 76543210 PASS PROTECT _S MODE wr h r w Field Bits Type Description MODE [1:0] rw Bit Protection Scheme Control Bits

00 Scheme disabled - di rect access to the

protected bits is allowed.

11 Scheme enabled - the bi t field PASS has to be

written with the passwords to open and close the access to protected bits. (default) Others:Scheme Enabled. These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000B; only then, will the MODE[1:0] be registered. PROTECT_S 2r h Bit Protection Signal Status Bit This bit shows the status of the protection. 0 Software is able to writ e to all protected bits.

1 Software is unable to write to any protected

bits. PASS [7:3] w Password Bits The Bit Protection Scheme only recognizes three patterns. 11000B Enables writing of the bit field MODE. 10011B Opens access to writing of all protected bits. 10101B Closes access to writing of all protected bits

Data Sheet 30 V1.0, 2010-03

3.2.4 XC858 Register Overview

The SFRs of the XC858 are organized into groups according to their functional units. The Note: The addresses of the bitaddressable SFRs appear in bold typeface.

3.2.4.1 CPU Registers

The CPU SFRs can be accessed in both the standard and ma pped memory areas (RMAP = 0 or 1). Table 4 CPU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 or 1 81H SP Reset: 07 HStack Pointer Register Bit Field SP Type rw 82H DPL Reset: 00 HData Pointer Register Low Bit Field DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0 Type rw rw rw rw rw rw rw rw 83H DPH Reset: 00 HData Pointer Register High Bit Field DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0 Type rw rw rw rw rw rw rw rw 87H PCON Reset: 00 HPower Control Register Bit Field SMOD 0 GF1 GF0 0 IDLE Type rw r rw rw r rw 88H TCON Reset: 00 HTimer Control Register Bit Field TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Type rwh rw rwh rw rwh rw rwh rw 89H TMOD Reset: 00 HTimer Mode Register Bit Field GATE T1S T1M GATE T0S T0M Type rw rw rw rw rw rw 8AH TL0 Reset: 00 HTimer 0 Register Low Bit Field VAL Type rwh 8BH TL1 Reset: 00 HTimer 1 Register Low Bit Field VAL Type rwh 8CH TH0 Reset: 00 HTimer 0 Register High Bit Field VAL Type rwh 8DH TH1 Reset: 00 HTimer 1 Register High Bit Field VAL Type rwh 94H MEX1 Reset: 00 HMemory Extension Register 1 Bit Field CB NB Type r rw 95H MEX2 Reset: 00 H Memory Extension Register 2 Bit Field MCM MCB IB Type rw rw rw 96H MEX3 Reset: 00 H Memory Extension Register 3 Bit Field MCB1

0 MXB1

Data Sheet 31 V1.0, 2010-03

3.2.4.2 System Control Registers

The system control SFRs can be accessed in the mapped memory area (RMAP = 0). 97H MEXSP Reset: 7F HMemory Extension Stack Pointer Register Bit Field 0 MXSP Type r rwh 98H SCON Reset: 00 HSerial Channel Control Register Bit Field SM0 SM1 SM2 REN TB8 RB8 TI RI Type rw rw rw rw rw rwh rwh rwh 99H SBUF Reset: 00 HSerial Data Buffer Register Bit Field VAL Type rwh A2H EO Reset: 00 HExtended Operation Register Bit Field 0 TRAP_ EN

0 DPSE

A8H IEN0 Reset: 00 HInterrupt Enable Register 0 Bit Field EA 0 ET2 ES ET1 EX1 ET0 EX0 T y p e r w r r wr wr wr wr wr w B8H IP Reset: 00 HInterrupt Priority Register Bit Field 0 PT2 PS PT1 PX1 PT0 PX0 T y p e r r wr wr wr wr wr w B9H IPH Reset: 00 HInterrupt Priority High Register Bit Field 0 PT2H PSH PT1H PX1H PT0H PX0H T y p e r r wr wr wr wr wr w D0H PSW Reset: 00 HProgram Status Word Register Bit Field CY AC F0 RS1 RS0 OV F1 P Type rwh rwh rw rw rw rwh rw rh E0H ACC Reset: 00 HAccumulator Register Bit Field ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0 Type rw rw rw rw rw rw rw rw E8H IEN1 Reset: 00 HInterrupt Enable Register 1 Bit Field ECCIP ECCIP ECCIP ECCIP EXM EX2 ESSC EADC Type rw rw rw rw rw rw rw rw F0H B Reset: 00 HB Register Bit Field B7 B6 B5 B4 B3 B2 B1 B0 Type rw rw rw rw rw rw rw rw F8H IP1 Reset: 00 HInterrupt Priority 1 Register Bit Field PCCIP PCCIP PCCIP PCCIP PXM PX2 PSSC PADC Type rw rw rw rw rw rw rw rw F9H IPH1 Reset: 00 HInterrupt Priority 1 High Register Bit Field PCCIP PCCIP PCCIP PCCIP PXMH PX2H PSSC H PADC H Type rw rw rw rw rw rw rw rw Table 5 SCU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 or 1 8FH SYSCON0 Reset: 04 HSystem Control Register 0 Bit Field 0 IMOD E 0 1 0 RMAP Type r rw r r r rw Table 4 CPU Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0

Data Sheet 32 V1.0, 2010-03 RMAP = 0 BFH SCU_PAGE Reset: 00 HPage Register Bit Field OP STNR 0 PAGE Type w w r rwh RMAP = 0, PAGE 0 B3H MODPISEL Reset: 00 HPeripheral Input Select Register Bit Field 0 URRIS H JTAGT DIS JTAGT CKS EXINT 2IS EXINT 1IS EXINT 0IS URRIS T y p e r r wr wr wr wr wr wr w B4H IRCON0 Reset: 00 HInterrupt Request Register 0 Bit Field 0 EXINT EXINT EXINT EXINT EXINT EXINT EXINT Type r rwh rwh rwh rwh rwh rwh rwh B5H IRCON1 Reset: 00 HInterrupt Request Register 1 Bit Field 0 CANS RC2 CANS RC1 ADCS ADCS RIR TIR EIR Type r rwh rwh rwh rwh rwh rwh rwh B6H IRCON2 Reset: 00 HInterrupt Request Register 2 Bit Field 0 CANS RC3

0 CANS

B7H EXICON0 Reset: F0 HExternal Interrupt Control Register 0 Bit Field EXINT3 EXINT2 EXINT1 EXINT0 Type rw rw rw rw BAH EXICON1 Reset: 3F HExternal Interrupt Control Register 1 Bit Field 0 EXINT6 EXINT5 EXINT4 T y p e r r wr wr w BBH NMICON Reset: 00 HNMI Control Register Bit Field 0 NMI ECC NMI VDDP

0 NMI

Type r rw rw r rw rw rw rw BCH NMISR Reset: 00 HNMI Status Register Bit Field 0 FNMI ECC FNMI VDDP

0 FNMI

Type r rwh rwh r rwh rwh rwh rwh BDH BCON Reset: 20 HBaud Rate Control Register Bit Field BGSEL NDOV EN BRDIS BRPRE R Type rw rw rw rw rw BEH BG Reset: 00 HBaud Rate Timer/Reload Register Bit Field BR_VALUE Type rwh E9H FDCON Reset: 00 HFractional Divider Control Register Bit Field BGS SYNE N ERRS YN EOFS YN BRK NDOV FDM FDEN Type rw rw rwh rwh rwh rwh rw rw EAH FDSTEP Reset: 00 HFractional Divider Reload Register Bit Field STEP Type rw EBH FDRES Reset: 00 HFractional Divider Result Register Bit Field RESULT Type rh RMAP = 0, PAGE 1 Table 5 SCU Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0

Data Sheet 33 V1.0, 2010-03 B3H ID Reset: 49 HIdentity Register Bit Field PRODID VERID Type r r B4H PMCON0 Reset: 80 HPower Mode Control Register 0 Bit Field VDDP WARN WDT RST WKRS WK SEL SD PD WS Type rh rwh rwh rw rw rwh rw B5H PMCON1 Reset: 00 HPower Mode Control Register 1 Bit Field 0 CAN_ DIS

0 T2CC

U_DIS

0 SSC_

ADC_ DIS Type r rw r rw r rw rw B6H OSC_CON Reset: XX HOSC Control Register Bit Field PLLRD RES PLLBY P PLLPD 0 XPD OSC SS EORD RES EXTO SCR Type rwh rwh rw r rw rwh rwh rh B7H PLL_CON Reset: 18 HPLL Control Register Bit Field NDIV PLLR PLL_L OCK Type rw rh rh BAH CMCON Reset: 10 HClock Control Register Bit Field KDIV 0 FCCF G CLKREL Type rw r rw rw BBH PASSWD Reset: 07 HPassword Register Bit Field PASS PROT ECT_S MODE Type w rh rw BEH COCON Reset: 00 HClock Output Control Register Bit Field COUTS TLEN 0 COREL Type rw rw r rw E9H MISC_CON Reset: 00 HMiscellaneous Control Register Bit Field ADCE TR0_ MUX ADCE TR1_ MUX

0 DFLAS

EAH PLL_CON1 Reset: 20 HPLL Control Register 1 Bit Field NDIV PDIV Type rw rw EBH CR_MISC Reset: 00 H or 01H Reset Status Register Bit Field 0 T2CCF G

0 HDRS

T Type r rw r rwh RMAP = 0, PAGE 3 B3H XADDRH Reset: F0 HOn-chip XRAM Address Higher Order Bit Field ADDRH Type rw B4H IRCON3 Reset: 00 HInterrupt Request Register 3 Bit Field 0 CANS RC5 B5H IRCON4 Reset: 00 HInterrupt Request Register 4 Bit Field 0 CANS RC7 B6H MODIEN Reset: 07 HPeripheral Interrupt Enable Register Bit Field 0 CM5E N CM4E N RIREN TIREN EIREN Type r rw rw rw rw rw Table 5 SCU Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0

Data Sheet 34 V1.0, 2010-03

3.2.4.3 WDT Registers

The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).

3.2.4.4 Port Registers

The Port SFRs can be accessed in the standard memory area (RMAP = 0). B7H MODPISEL1 Reset: 00 HPeripheral Input Select Register Bit Field EXINT6IS UR1RIS T21EX IS Type rw rw rw r BAH MODPISEL2 Reset: 00 HPeripheral Input Select Register Bit Field 0 T2EXI S T21IS T2IS T1IS T0IS Type r rw rw rw rw rw BBH PMCON2 Reset: 00 HPower Mode Control Register 2 Bit Field 0 UART 1_DIS T21_D IS Type r rw rw BDH MODSUSP Reset: 01 HModule Suspend Control Register Bit Field 0 CCTS USP T21SU SP T2SUS P

0 WDTS

BEH MODPISEL3 Reset: 00 HPeripheral Input Select Register Bit Field 0 CIS SIS MIS T y p e r r wr wr w EAH MODPISEL4 Reset: 00 HPeripheral Input Select Register Bit Field 0 EXINT5IS EXINT4IS EXINT3IS T y p e r r wr wr w Table 6 WDT Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 1 BB H WDTCON Reset: 00 HWatchdog Timer Control Register Bit Field 0 WINB EN WDTP R

0 WDTE

N WDTR S WDTI N Type r rw rh r rw rwh rw BCH WDTREL Reset: 00 HWatchdog Timer Reload Register Bit Field WDTREL Type rw BDH WDTWINB Reset: 00 HWatchdog Window-Boundary Count Register Bit Field WDTWINB Type rw BEH WDTL Reset: 00 HWatchdog Timer Register Low Bit Field WDT Type rh BFH WDTH Reset: 00 HWatchdog Timer Register High Bit Field WDT Type rh Table 5 SCU Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0

Data Sheet 35 V1.0, 2010-03 Table 7 Port Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 B2H PORT_PAGE Reset: 00 HPage Register Bit Field OP STNR 0 PAGE Type w w r rwh RMAP = 0, PAGE 0 H P0_DATA Reset: 00 HP0 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 T y p e r w hr w hr w hr w hr w hr w hr w hr w h 86H P0_DIR Reset: 00 HP0 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_DATA Reset: 00 HP1 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 T y p e r w hr w hr w hr w hr w hr w hr w hr w h 91H P1_DIR Reset: 00 HP1 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_DATA Reset: 00 HP5 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 T y p e r w hr w hr w hr w hr w hr w hr w hr w h 93H P5_DIR Reset: 00 HP5 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_DATA Reset: 00 HP3 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 T y p e r w hr w hr w hr w hr w hr w hr w hr w h B1H P3_DIR Reset: 00 HP3 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C8H P4_DATA Reset: 00 HP4 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 T y p e r w hr w hr w hr w hr w hr w hr w hr w h C9H P4_DIR Reset: 00 HP4 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw RMAP = 0, PAGE 1 H P0_PUDSEL Reset: FF HP0 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 86H P0_PUDEN Reset: C4 HP0 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_PUDSEL Reset: FF HP1 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 91H P1_PUDEN Reset: FF HP1 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_PUDSEL Reset: FF HP5 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 93H P5_PUDEN Reset: FF HP5 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw

Data Sheet 36 V1.0, 2010-03 B0H P3_PUDSEL Reset: BF HP3 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B1H P3_PUDEN Reset: 40 HP3 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C8H P4_PUDSEL Reset: FF HP4 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C9H P4_PUDEN Reset: 04 HP4 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw RMAP = 0, PAGE 2 80H P0_ALTSEL0 Reset: 00 HP0 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 86H P0_ALTSEL1 Reset: 00 HP0 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_ALTSEL0 Reset: 00 HP1 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 91H P1_ALTSEL1 Reset: 00 HP1 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_ALTSEL0 Reset: 00 HP5 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 93H P5_ALTSEL1 Reset: 00 HP5 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_ALTSEL0 Reset: 00 HP3 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B1H P3_ALTSEL1 Reset: 00 HP3 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C8H P4_ALTSEL0 Reset: 00 HP4 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C9H P4_ALTSEL1 Reset: 00 HP4 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw RMAP = 0, PAGE 3 H P0_OD Reset: 00 HP0 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 86H P0_DS Reset: FF HP0 Drive Strength Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_OD Reset: 00 HP1 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw Table 7 Port Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0

Data Sheet 37 V1.0, 2010-03

3.2.4.5 ADC Registers

The ADC SFRs can be accessed in the standard memory area (RMAP = 0). 91H P1_DS Reset: FF HP1 Drive Strength Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_OD Reset: 00 HP5 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 93H P5_DS Reset: FF HP5 Drive Strength Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_OD Reset: 00 HP3 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B1H P3_DS Reset: FF HP3 Drive Strength Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C8H P4_OD Reset: 00 HP4 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C9H P4_DS Reset: FF HP4 Drive Strength Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw Table 8 ADC Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 H ADC_PAGE Reset: 00 HPage Register Bit Field OP STNR 0 PAGE Type w w r rw RMAP = 0, PAGE 0 CA H ADC_GLOBCTR Reset: 30 HGlobal Control Register Bit Field ANON DW CTC 0 Type rw rw rw r CBH ADC_GLOBSTR Reset: 00 HGlobal Status Register Bit Field 0 CHNR 0 SAMP LE BUSY Type r rh r rh rh CCH ADC_PRAR Reset: 00 HPriority and Arbitration Register Bit Field ASEN ASEN

0 ARBM CSM1 PRIO1 CSM0 PRIO0

Type rw rw r rw rw rw rw rw CDH ADC_LCBR Reset: B7 HLimit Check Boundary Register Bit Field BOUND1 BOUND0 Type rw rw CEH ADC_INPCR0 Reset: 00 HInput Class 0 Register Bit Field STC Type rw Table 7 Port Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0

Data Sheet 38 V1.0, 2010-03 CFH ADC_ETRCR Reset: 00 HExternal Trigger Control Register Bit Field SYNE SYNE ETRSEL1 ETRSEL0 Type rw rw rw rw RMAP = 0, PAGE 1 CAH ADC_CHCTR0 Reset: 00 HChannel Control Register 0 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CBH ADC_CHCTR1 Reset: 00 HChannel Control Register 1 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CCH ADC_CHCTR2 Reset: 00 HChannel Control Register 2 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CDH ADC_CHCTR3 Reset: 00 HChannel Control Register 3 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CEH ADC_CHCTR4 Reset: 00 HChannel Control Register 4 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CFH ADC_CHCTR5 Reset: 00 HChannel Control Register 5 Bit Field 0 LCC 0 RESRSEL Type r rw r rw D2H ADC_CHCTR6 Reset: 00 HChannel Control Register 6 Bit Field 0 LCC 0 RESRSEL Type r rw r rw D3H ADC_CHCTR7 Reset: 00 HChannel Control Register 7 Bit Field 0 LCC 0 RESRSEL Type r rw r rw RMAP = 0, PAGE 2 CA H ADC_RESR0L Reset: 00 HResult Register 0 Low Bit Field RESULT 0 VF DRC CHNR Type rh r rh rh rh CBH ADC_RESR0H Reset: 00 HResult Register 0 High Bit Field RESULT Type rh CCH ADC_RESR1L Reset: 00 HResult Register 1 Low Bit Field RESULT 0 VF DRC CHNR Type rh r rh rh rh CDH ADC_RESR1H Reset: 00 HResult Register 1 High Bit Field RESULT Type rh CEH ADC_RESR2L Reset: 00 HResult Register 2 Low Bit Field RESULT 0 VF DRC CHNR Type rh r rh rh rh CFH ADC_RESR2H Reset: 00 HResult Register 2 High Bit Field RESULT Type rh D2H ADC_RESR3L Reset: 00 HResult Register 3 Low Bit Field RESULT 0 VF DRC CHNR Type rh r rh rh rh D3H ADC_RESR3H Reset: 00 HResult Register 3 High Bit Field RESULT Type rh RMAP = 0, PAGE 3 Table 8 ADC Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 39 V1.0, 2010-03 CAH ADC_RESRA0L Reset: 00 HResult Register 0, View A Low Bit Field RESULT VF DRC CHNR Type rh rh rh rh CBH ADC_RESRA0H Reset: 00 HResult Register 0, View A High Bit Field RESULT Type rh CCH ADC_RESRA1L Reset: 00 HResult Register 1, View A Low Bit Field RESULT VF DRC CHNR Type rh rh rh rh CDH ADC_RESRA1H Reset: 00 HResult Register 1, View A High Bit Field RESULT Type rh CEH ADC_RESRA2L Reset: 00 HResult Register 2, View A Low Bit Field RESULT VF DRC CHNR Type rh rh rh rh CFH ADC_RESRA2H Reset: 00 HResult Register 2, View A High Bit Field RESULT Type rh D2H ADC_RESRA3L Reset: 00 HResult Register 3, View A Low Bit Field RESULT VF DRC CHNR Type rh rh rh rh D3H ADC_RESRA3H Reset: 00 HResult Register 3, View A High Bit Field RESULT Type rh RMAP = 0, PAGE 4 CAH ADC_RCR0 Reset: 00 HResult Control Register 0 Bit Field VFCT R WFR 0 IEN 0 DRCT R Type rw rw r rw r rw CBH ADC_RCR1 Reset: 00 HResult Control Register 1 Bit Field VFCT R WFR 0 IEN 0 DRCT R Type rw rw r rw r rw CCH ADC_RCR2 Reset: 00 HResult Control Register 2 Bit Field VFCT R WFR 0 IEN 0 DRCT R Type rw rw r rw r rw CDH ADC_RCR3 Reset: 00 HResult Control Register 3 Bit Field VFCT R WFR 0 IEN 0 DRCT R Type rw rw r rw r rw CEH ADC_VFCR Reset: 00 HValid Flag Clear Register Bit Field 0 VFC3 VFC2 VFC1 VFC0 Type r w w w w RMAP = 0, PAGE 5 CAH ADC_CHINFR Reset: 00 HChannel Interrupt Flag Register Bit Field CHINF CHINF CHINF CHINF CHINF CHINF CHINF CHINF Type rh rh rh rh rh rh rh rh CBH ADC_CHINCR Reset: 00 HChannel Interrupt Clear Register Bit Field CHINC CHINC CHINC CHINC CHINC CHINC CHINC CHINC T y p ewwwwwwww CCH ADC_CHINSR Reset: 00 HChannel Interrupt Set Register Bit Field CHINS CHINS CHINS CHINS CHINS CHINS CHINS CHINS T y p ewwwwwwww Table 8 ADC Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 40 V1.0, 2010-03 CDH ADC_CHINPR Reset: 00 HChannel Interrupt Node Pointer Register Bit Field CHINP CHINP CHINP CHINP CHINP CHINP CHINP CHINP Type rw rw rw rw rw rw rw rw CEH ADC_EVINFR Reset: 00 HEvent Interrupt Flag Register Bit Field EVINF EVINF EVINF EVINF

0 EVINF

CFH ADC_EVINCR Reset: 00 HEvent Interrupt Clear Flag Register Bit Field EVINC EVINC EVINC EVINC

0 EVINC

D2H ADC_EVINSR Reset: 00 HEvent Interrupt Set Flag Register Bit Field EVINS EVINS EVINS EVINS

0 EVINS

D3H ADC_EVINPR Reset: 00 HEvent Interrupt Node Pointer Register Bit Field EVINP EVINP EVINP EVINP

0 EVINP

RMAP = 0, PAGE 6 CAH ADC_CRCR1 Reset: 00 HConversion Request Control Register 1 Bit Field CH7 CH6 CH5 CH4 0 Type rwh rwh rwh rwh r CBH ADC_CRPR1 Reset: 00 HConversion Request Pending Register 1 Bit Field CHP7 CHP6 CHP5 CHP4 0 Type rwh rwh rwh rwh r CCH ADC_CRMR1 Reset: 00 HConversion Request Mode Register 1 Bit Field Rsv LDEV CLRP ND SCAN ENSI ENTR 0 ENGT Type r w w rw rw rw r rw CDH ADC_QMR0 Reset: 00 HQueue Mode Register 0 Bit Field CEV TREV FLUS H CLRV 0 ENTR 0 ENGT T y p ewwww rr wrr w CEH ADC_QSR0 Reset: 20 HQueue Status Register 0 Bit Field Rsv 0 EMPT Y EV 0 FILL Type r r rh rh r rh CFH ADC_Q0R0 Reset: 00 HQueue 0 Register 0 Bit Field EXTR ENSI RF V 0 REQCHNR Type rh rh rh rh r rh D2H ADC_QBUR0 Reset: 00 HQueue Backup Register 0 Bit Field EXTR ENSI RF V 0 REQCHNR Type rh rh rh rh r rh D2H ADC_QINR0 Reset: 00 HQueue Input Register 0 Bit Field EXTR ENSI RF 0 REQCHNR T y p ewww r w Table 8 ADC Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 41 V1.0, 2010-03

3.2.4.6 Timer 2 Compare/Capture Unit Registers

The Timer 2 Compare/Capture Unit SFRs can be accessed in the standard memory area (RMAP = 0). Table 9 T2CCU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 C7H T2_PAGE Reset: 00 HPage Register Bit Field OP STNR 0 PAGE Type w w r rwh RMAP = 0, PAGE 0 H T2_T2CON Reset: 00 HTimer 2 Control Register Bit Field TF2 EXF2 0 EXEN TR2 C/T2 CP/ RL2 Type rwh rwh r rw rwh rw rw C1H T2_T2MOD Reset: 00 HTimer 2 Mode Register Bit Field T2RE GS T2RH EN EDGE SEL PREN T2PRE DCEN Type rw rw rw rw rw rw C2H T2_RC2L Reset: 00 HTimer 2 Reload/Capture Register Low Bit Field RC2 Type rwh C3H T2_RC2H Reset: 00 HTimer 2 Reload/Capture Register High Bit Field RC2 Type rwh C4H T2_T2L Reset: 00 HTimer 2 Register Low Bit Field THL2 Type rwh C5H T2_T2H Reset: 00 HTimer 2 Register High Bit Field THL2 Type rwh C6H T2_T2CON1 Reset: 03 HTimer 2 Control Register 1 Bit Field 0 TF2EN EXF2E N Type r rw rw RMAP = 0, PAGE 1 C0H T2CCU_CCEN Reset: 00 HT2CCU Capture/Compare Enable Register Bit Field CCM3 CCM2 CCM1 CCM0 Type rw rw rw rw C1H T2CCU_CCTBSELReset: 00HT2CCU Capture/Compare Time Base Select Register Bit Field CASC CCTT OV CCTB CCTB CCTB CCTB CCTB CCTB T y p e r w r w h r wr wr wr wr wr w C2H T2CCU_CCTRELLReset: 00HT2CCU Capture/Compare Timer Reload Register Low Bit Field CCTREL Type rw C3H T2CCU_CCTRELHReset: 00HT2CCU Capture/Compare Timer Reload Register High Bit Field CCTREL Type rw C4H T2CCU_CCTL Reset: 00 HT2CCU Capture/Compare Timer Register Low Bit Field CCT Type rwh

Data Sheet 42 V1.0, 2010-03 C5H T2CCU_CCTH Reset: 00 HT2CCU Capture/Compare Timer Register High Bit Field CCT Type rwh C6H T2CCU_CCTCON Reset: 00HT2CCU CaptureCcompare Timer Control Register Bit Field CCTPRE CCTO VF CCTO VEN TIMSY N CCTS T Type rw rwh rw rw rw RMAP = 0, PAGE 2 C0H T2CCU_COSHDWReset: 00HT2CCU Capture/compare Enable Register Bit Field ENSH DW TXOV COOU COOU COOU COOU COOU COOU Type rwh rwh rwh rwh rwh rwh rwh rwh C1H T2CCU_CC0L Reset: 00 HT2CCU Capture/Compare Register 0 Low Bit Field CCVALL Type rwh C2H T2CCU_CC0H Reset: 00 HT2CCU Capture/compare Register 0 High Bit Field CCVALH Type rwh C3H T2CCU_CC1L Reset: 00 HT2CCU Capture/compare Register 1 Low Bit Field CCVALL Type rwh C4H T2CCU_CC1H Reset: 00 HT2CCU Capture/compare Register 1 High Bit Field CCVALH Type rwh C5H T2CCU_CC2L Reset: 00 HT2CCU Capture/compare Register 2 Low Bit Field CCVALL Type rwh C6H T2CCU_CC2H Reset: 00 HT2CCU Capture/compare Register 2 High Bit Field CCVALH Type rwh RMAP = 0, PAGE 3 C0H T2CCU_COCON Reset: 00 HT2CCU Compare Control Register Bit Field CCM5 CCM4 CM5F CM4F POLB POLA COMOD Type rw rw rwh rwh rw rw rw C1H T2CCU_CC3L Reset: 00 HT2CCU Capture/compare Register 3 Low Bit Field CCVALL Type rwh C2H T2CCU_CC3H Reset: 00 HT2CCU Capture/compare Register 3 High Bit Field CCVALH Type rwh C3H T2CCU_CC4L Reset: 00 HT2CCU Capture/compare Register 4 Low Bit Field CCVALL Type rwh C4H T2CCU_CC4H Reset: 00 HT2CCU Capture/compare Register 4 High Bit Field CCVALH Type rwh C5H T2CCU_CC5L Reset: 00 HT2CCU Capture/compare Register 5 Low Bit Field CCVALL Type rwh C6H T2CCU_CC5H Reset: 00 HT2CCU Capture/compare Register 5 High Bit Field CCVALH Type rwh Table 9 T2CCU Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0

Data Sheet 43 V1.0, 2010-03

3.2.4.7 Timer 21 Registers

The Timer 21 SFRs can be accessed in the mapped memory area (RMAP = 1).

3.2.4.8 UART1 Registers

The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1). RMAP = 0, PAGE 4 C2H T2CCU_CCTDTCLReset: 00HT2CCU Capture/Compare Timer Dead-Time Control Register Low Bit Field DTM Type rw C3H T2CCU_CCTDTCHReset: 00HT2CCU Capture/Compare Timer Dead-Time Control Register High Bit Field DTRE S DTR2 DTR1 DTR0 DTLEV DTE2 DTE1 DTE0 T y p e r w h r h r h r hr wr wr wr w Table 10 T21 Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 1 C0H T21_T2CON Reset: 00 HTimer 2 Control Register Bit Field TF2 EXF2 0 EXEN TR2 C/T2 CP/ RL2 Type rwh rwh r rw rwh rw rw C1H T21_T2MOD Reset: 00 HTimer 2 Mode Register Bit Field T2RE GS T2RH EN EDGE SEL PREN T2PRE DCEN Type rw rw rw rw rw rw rw rw C2H T21_RC2L Reset: 00 HTimer 2 Reload/Capture Register Low Bit Field RC2 Type rwh C3H T21_RC2H Reset: 00 HTimer 2 Reload/Capture Register High Bit Field RC2 Type rwh C4H T21_T2L Reset: 00 HTimer 2 Register Low Bit Field THL2 Type rwh C5H T21_T2H Reset: 00 HTimer 2 Register High Bit Field THL2 Type rwh C6H T21_T2CON1 Reset: 03 HTimer 2 Control Register 1 Bit Field 0 TF2EN EXF2E N Type r rw rw Table 9 T2CCU Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0

Data Sheet 44 V1.0, 2010-03

3.2.4.9 SSC Registers

The SSC SFRs can be accessed in the standard memory area (RMAP = 0). Table 11 UART1 Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 1 C8H SCON Reset: 00 HSerial Channel Control Register Bit Field SM0 SM1 SM2 REN TB8 RB8 TI RI Type rw rw rw rw rw rwh rwh rwh C9H SBUF Reset: 00 HSerial Data Buffer Register Bit Field VAL Type rwh CAH BCON Reset: 00 HBaud Rate Control Register Bit Field 0 BRPRE R Type r rw rw CBH BG Reset: 00 HBaud Rate Timer/Reload Register Bit Field BR_VALUE Type rwh CCH FDCON Reset: 00 HFractional Divider Control Register Bit Field 0 NDOV FDM FDEN Type r rwh rw rw CDH FDSTEP Reset: 00 HFractional Divider Reload Register Bit Field STEP Type rw CEH FDRES Reset: 00 HFractional Divider Result Register Bit Field RESULT Type rh CFH SCON1 Reset: 07 HSerial Channel Control Register Bit Field 0 NDOV EN TIEN RIEN Type r rw rw rw Table 12 SSC Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 A9H SSC_PISEL Reset: 00 HPort Input Select Register Bit Field 0 CIS SIS MIS Type r rw rw rw AAH SSC_CONL Reset: 00 HControl Register Low Programming Mode Bit Field LB PO PH HB BM Type rw rw rw rw rw AAH SSC_CONL Reset: 00 HControl Register Low Operating Mode Bit Field 0 BC Type r rh ABH SSC_CONH Reset: 00 HControl Register High Programming Mode Bit Field EN MS 0 AREN BEN PEN REN TEN Type rw rw r rw rw rw rw rw ABH SSC_CONH Reset: 00 HControl Register High Operating Mode Bit Field EN MS 0 BSY BE PE RE TE Type rw rw r rh rwh rwh rwh rwh

Data Sheet 45 V1.0, 2010-03

3.2.4.10 MultiCAN Registers

The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0).

3.2.4.11 OCDS Registers

The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1). ACH SSC_TBL Reset: 00 HTransmitter Buffer Register Low Bit Field TB_VALUE Type rw ADH SSC_RBL Reset: 00 HReceiver Buffer Register Low Bit Field RB_VALUE Type rh AEH SSC_BRL Reset: 00 HBaud Rate Timer Reload Register Low Bit Field BR_VALUE Type rw AFH SSC_BRH Reset: 00 HBaud Rate Timer Reload Register High Bit Field BR_VALUE Type rw Table 13 CAN Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 H ADCON Reset: 00 HCAN Address/Data Control Register Bit Field V3 V2 V1 V0 AUAD BSY RWEN Type rw rw rw rw rw rh rw D9H ADL Reset: 00 HCAN Address Register Low Bit Field CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 Type rwh rwh rwh rwh rwh rwh rwh rwh DAH ADH Reset: 00 HCAN Address Register High Bit Field 0 CA13 CA12 CA11 CA10 Type r rwh rwh rwh rwh DBH DATA0 Reset: 00 HCAN Data Register 0 Bit Field CD Type rwh DCH DATA1 Reset: 00 HCAN Data Register 1 Bit Field CD Type rwh DDH DATA2 Reset: 00 HCAN Data Register 2 Bit Field CD Type rwh DEH DATA3 Reset: 00 HCAN Data Register 3 Bit Field CD Type rwh Table 12 SSC Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0

Data Sheet 46 V1.0, 2010-03 Table 14 OCDS Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 1 E9H MMCR2 Reset: 8U HMonitor Mode Control 2 Register Bit Field STMO DE EXBC DSUS P MBCO N ALTDI MMEP MMOD E JENA Type rw rw rw rwh rw rwh rh rh EAH MEXTCR Reset: 0U HMemory Extension Control Register Bit Field 0 BANKBPx Type r rw EBH MMWR1 Reset: 00 HMonitor Work Register 1 Bit Field MMWR1 Type rw ECH MMWR2 Reset: 00 HMonitor Work Register 2 Bit Field MMWR2 Type rw F1H MMCR Reset: 00 HMonitor Mode Control Register Bit Field MEXIT MEXIT 0 MSTE P MRAM S_P MRAM S TRF RRF Type w rwh r rw w rwh rh rh F2H MMSR Reset: 00 HMonitor Mode Status Register Bit Field MBCA M MBCIN EXBF SWBF HWB3 F HWB2 F HWB1 F HWB0 F Type rw rwh rwh rwh rwh rwh rwh rwh F3H MMBPCR Reset: 00 HBreakpoints Control Register Bit Field SWBC HWB3C HWB2C HWB1 C HWB0C Type rw rw rw rw rw F4H MMICR Reset: 00 HMonitor Mode Interrupt Control Register Bit Field DVEC T DRET R COMR ST MSTS EL MMUI E_P MMUI E RRIE_ P RRIE Type rwh rwh rwh rh w rw w rw F5H MMDR Reset: 00 HMonitor Mode Data Transfer Register Receive Bit Field MMRR Type rh F6H HWBPSR Reset: 00 HHardware Breakpoints Select Register Bit Field 0 BPSEL BPSEL Type r w rw F7H HWBPDR Reset: 00 HHardware Breakpoints Data Register Bit Field HWBPxx Type rw

Data Sheet 47 V1.0, 2010-03

3.2.4.12 Flash Registers

The Flash SFRs can be accessed in the mapped memory area (RMAP = 1). Table 15 Flash Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 1 D1H FCON Reset: 10 HP-Flash Control Register Bit Field 0 FBSY YE 1 NVST R MAS1 ERAS E PROG Type r rh rwh r rw rw rw rw D2H EECON Reset: 10 HD-Flash Control Register Bit Field 0 EEBS Y YE 1 NVST R MAS1 ERAS E PROG Type r rh rwh r rw rw rw rw D3H FCS Reset: 80 HFlash Control and Status Register Bit Field 1 SBEIE FTEN 0 EEDE RR EESE RR FDER R FSER R Type r rw rwh r rwh rwh rwh rwh D4H FEAL Reset: 00 HFlash Error Address Register, Low Byte Bit Field ECCEADDR Type rh D5H FEAH Reset: 00 HFlash Error Address Register, High Byte Bit Field ECCEADDR Type rh D6H FTVAL Reset: 78 HFlash Timer Value Register Bit Field MODE OFVAL Type rw rw DDH FCS1 Reset: 00 HFlash Control and Status Register 1 Bit Field 0 EEAB ORT Type r rwh

Data Sheet 48 V1.0, 2010-03

3.3 Flash Memory

The Flash memory provides an embedded user-programm able non-volatile memory, allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V supply from the Embedded Voltage Regu lator (EVR) and does not require additional programming or erasing voltage. The pagination of the Flash memory allows each page to be erased independently.

Features

• In-System Programming (ISP) via UART
• In-Application Programming (IAP)
• Error Correction Code (ECC) for dynamic correction of single-bit errors
• Background program a nd erase operations for CPU load minimization
• Support for aborti ng erase operation
• Minimum program width
• of 1-byte for D-Flash and 2-bytes for P-Flash
• 1-page minimum erase width
• 1-byte read access
• Flash is deliver ed in erased state (read all ones)
• Operating supply vo ltage: 2.5 V ± 7.5 %
• Read access time: 1 × tCCLK =3 8 n s1)
• Program time for 1 wordline: 1.6 ms2)
• Page erase time: 20 ms
• Mass erase time: 200 ms 1) Values shown here are typical values. fsys = 144 MHz ± 7.5% ( fCCLK = 24 MHz ± 7.5 %) is the maximum frequency range for Flash read access. 2) Values shown here are typical values. fsys = 144 MHz ± 7.5% (fCCLK = 24 MHz ± 7.5 %) is the typical frequency range for Flash programming and erasing. fsysmin is used for obtaining the worst case timing.

Data Sheet 49 V1.0, 2010-03 Table 16 shows the Flash data retention and endurance targets for Industrial profile. Table 16 Flash Data Retention and Endurance for Industrial Profile (Operating Conditions apply) Retention Endurance 1)2) 1) In Program Flash, one cycle refers to the programming of all pages in the flash bank and a mass erase. 2) In Data Flash, one cycle refers to the programming of all wordlines in a page and a page erase. Size Remarks Program Flash 15 years 1000 cycles up to 60 Kbytes Data Flash 15 years 1000 cycles 4 Kbytes 10 years 10,000 cycles 4 Kbytes 5 years 30,000 cycles 4 Kbytes 1 year 100,000 cycles 4 Kbytes

Data Sheet 50 V1.0, 2010-03

3.3.1 Flash Bank Pagination

The XC858 product family offers Flash devices with 64 Kbytes, 52 Kbytes or 36Kbyte of embedded Flash memory. Each Flash device consists of a Program Flash (P-Flash) and a single Data Flash (D-Flash) bank. P-Flash has 120 pages of 8 wordlines per page with 64 bytes per wordline. D-Flash has 64 pages of 2 wordlines per page with 32 bytes per wordline. Both types can be used for code and data stora ge. The label “Data” neither implies that the D-Flash is mapped to the data memory re gion, nor that it can only be used for data storage. It is used to dist inguish the different page width and wordline of each Flash bank. The internal structure of eac h Flash bank represents a page architecture for flexible erase capability. The minimu m erase width is always a co mplete page. The D-Flash bank is divided into smaller size for extended erasing and repr ogramming capability; even numbers for each page size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements.

Data Sheet 51 V1.0, 2010-03

3.4 Interrupt System

The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interr upt functions supporte d by the core, e.g., configurable interrupt prio rity and interrupt masking, the XC858 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional stat us registers for detecting and determining the interrupt source.

3.4.1 Interrupt Source

Figure 12 to Figure 16 give a general overview of the interrupt sources and nodes, and their corresponding control and status flags. Figure 12 Non-Maskable In terrupt Request Sources 0073 H NMIWDT NMICON.0 WDT Overflow >=1 Non Maskable Interrupt NMIPLL NMICON.1 PLL Loss of Clock NMIFLASH Flash Timer Overflow FNMIWDT NMIISR.0 FNMIPLL NMIISR.1 FNMIFLASH NMIISR.2 NMIVDDP NMICON.5 VDDP Pre-Warning FNMIVDDP NMIISR.5 NMIECC NMICON.6 Flash ECC Error FNMIECC NMIISR.6 NMICON.2

Data Sheet 52 V1.0, 2010-03 Figure 13 Interrupt Request Sources (Part 1) Highest Lowest Priority Level Bit-addressable Request flag is cleared by hardware 000B HET0 IEN0.1 TF0 TCON.5 Timer 0 Overflow 001B HET1 IEN0.3 TF1 TCON.7 Timer 1 Overflow IP.1/ IPH.1 IP.3/ IPH.3

0023 HES

IEN0.4 IP.4/ IPH.4 >=1 RI SCON.0 TI SCON.1 UART Transmit

0003 HEX0

IEN0.0 IE0 TCON.1 IP.0/ IPH.0 0013 H IP.2/ IPH.2 IT0 TCON.0 EX1 IEN0.2 IE1 TCON.3 IT1 TCON.2 IEN0.7 EA P o l l i n g S e q u e n c e UART Receive EXINT0 EXICON0.0/1 EINT0 EXINT1 EXICON0.2/3 EINT1

Data Sheet 53 V1.0, 2010-03 Figure 14 Interrupt Request Sources (Part 2) Highest Lowest Priority Level Bit- addressable Request flag is cleared by hardware 002BH IP.5/ IPH.5 P o l l i n g S e q u e n c e

0033 HEADC

IEN1.0 IP1.0/ IPH1.0 >=1 ADCSRC0 IRCON1.3 ADCSRC 1 IRCON1.4 CANSRC 1 IRCON1.5 ET2 IEN0.5 >=1 TF2 T2_T2CON.7 EXF2 T2_T2CON.6 Timer 2 Overflow EXEN2 T2_T2CON.3 CANSRC 0 IRCON2.0 NDOV FDCON.2 Normal Divider Overflow SYNEN FDCON.6 EOFSYN FDCON.4 End of Syn Byte ERRSYN FDCON.5 Syn Byte Error IEN0.7 EA CANSRC2 IRCON1.6 T2EX EDGES EL T2_T2MOD.5 >=1 EXF2EN T2_T2CON1.0 TF2EN T2_T2CON1.1 CCTOVF T2CCU_CCTCON .3 CCT Overflow CCTOVEN T2CCU_CCTCON .2 NDOVEN BCON.5 MultiCAN Node 0 ADC Service Request 0 ADC Service Request 1 MultiCAN Node 1 MultiCAN Node 2

Data Sheet 54 V1.0, 2010-03 Figure 15 Interrupt Request Sources (Part 3) Highest Lowest Priority Level Bit-addressable Request flag is cleared by hardware P o l l i n g S e q u e n c e 003B HESSC IEN1.1 IP1.1/ IPH1.1 >=1TIR IRCON1.1 RIR IRCON1.2 EIR IRCON1.0 IEN0.7 EA 0043 H IP1.2/ IPH1.2 EXINT2 EXICON0.4/5 EXINT2 IRCON0.2 EINT2 EX2 IEN1.2 >=1 >=1 RI UART1_SCON.0 TI UART1_SCON.1 UART1 NDOVUART1 Normal Divider Overflow UART1_FDCON.2 EIREN MODIEN.0 TIREN MODIEN.1 RIREN MODIEN.2 NDOVEN UART1_SCON1.2 TF2 T21_T2CON.7 EXF2 T21_T2CON.6 Timer 21 Overflow EXEN2 T21_T2CON.3 T21EX EDGES EL T21_T2MOD.5 >=1 EXF2EN T21_T2CON1.0 TF2EN T21_T2CON1.1 RIEN UART1_SCON1.0 TIEN UART1_SCON1.1 SSC Error SSC Transmit SSC Receive

Data Sheet 55 V1.0, 2010-03 Figure 16 Interrupt Request Sources (Part 4) IEN0.7 Highest Lowest Priority Level Bit- addressable Request flag is cleared by hardware P o l l i n g S e q u e n c e EA 004B HEXM IEN1.3 IP1.3/ IPH1.3 >=1 EXINT5 EXICON1.2/3 EXINT5 IRCON0.5 T2CC2/ EINT5 EXINT4 EXICON1.0/1 EXINT4 IRCON0.4 T2CC1/ EINT4 EXINT3 EXICON0.6/7 EXINT3 IRCON0.3 T2CC0/ EINT3 EXINT6 EXICON1.4/5 EXINT6 IRCON0.6 T2CC3/ EINT6 CANSRC3 IRCON2.4 MultiCAN Node 3 CM4F T2CCU_COCON.4 Compare Channel 4 CM4EN MODIEN.3 CM5F T2CCU_COCON.5 Compare Channel 5 CM5EN MODIEN.4

Data Sheet 56 V1.0, 2010-03 Figure 17 Interrupt Request Sources (Part 5) Highest Lowest Priority Level P o l l i n g S e q u e n c e IEN0.7 Bit-addressable Request flag is cleared by hardware EA 0053 H IP1.4/ IPH1.4 005B H IP1.5/ IPH1.5 0063 H IP1.6/ IPH1.6 006B H IP1.7/ IPH1.7 ECCIP0 IEN1.4 ECCIP1 IEN1.5 ECCIP 2 IEN1.6 ECCIP 3 IEN1.7 CANSRC 4 IRCON3.1 MultiCAN Node 4 CANSRC 5 IRCON3.5 MultiCAN Node 5 CANSRC 6 IRCON4.1 MultiCAN Node 6 CANSRC7 IRCON4.5 MultiCAN Node 7 IRCON4.4

Data Sheet 57 V1.0, 2010-03

3.4.2 Interrupt Source and Vector

Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to. This vector is accessed to service the corresponding interrupt node request. The interrupt service of each inte rrupt source can be in dividually enabled or disabled via an enable bit. The assignment of the XC858 interrupt sources to the interrupt vector a ddress and the corresponding inte rrupt node enable bits are summarized in Table 17. Table 17 Interrupt Vector Addresses Interrupt Source Vector Address Assignment for XC858 Enable Bit SFR NMI 0073 H Watchdog Timer NMI NMIWDT NMICON PLL NMI NMIPLL Flash Timer NMI NMIFLASH V DDP Prewarning NMI NMIVDDP Flash ECC NMI NMIECC XINTR0 0003 H External Interrupt 0 EX0 IEN0 XINTR1 000B H Timer 0 ET0 XINTR2 0013 H External Interrupt 1 EX1 XINTR3 001B H Timer 1 ET1 XINTR4 0023 H UART ES XINTR5 002B H T2CCU ET2 UART Fractional Divider (Normal Divider Overflow) MultiCAN Node 0

Data Sheet 58 V1.0, 2010-03 XINTR6 0033 H MultiCAN Nodes 1 and 2 EADC IEN1 ADC[1:0] XINTR7 003B H SSC ESSC XINTR8 0043 H External Interrupt 2 EX2 T21 UART1 UART1 Fractional Divider (Normal Divider Overflow) XINTR9 004B H External Interrupt 3 EXM External Interrupt 4 External Interrupt 5 External Interrupt 6 T2CCU MultiCAN Node 3 XINTR10 0053 H MultiCAN Node 4 ECCIP0 XINTR11 005B H MultiCAN Node 5 ECCIP1 XINTR12 0063 H MultiCAN Node 6 ECCIP2 XINTR13 006B H MultiCAN Node 7 ECCIP3 Table 17 Interrupt Vector Addresses (cont’d) Interrupt Source Vector Address Assignment for XC858 Enable Bit SFR

Data Sheet 59 V1.0, 2010-03

3.4.3 Interrupt Priority

An interrupt that is currentl y being serviced can only be in terrupted by a higher-priority interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of the highest priority cannot be interrupted by any other interrupt request. If two or more requests of different priority levels ar e received simultaneously, the request of the highest priority is serviced first. If requests of th e same prio rity are received simultaneously, then an internal polling sequence determines which request is serviced first. Thus, within ea ch priority level, there is a second priority structure determined by the polling sequence shown in Table 18. Table 18 Priority Structur e within Interrupt Level Source Level Non-Maskable Interrupt (NMI) (highest) External Interrupt 0 1 Timer 0 Interrupt 2 External Interrupt 1 3 Timer 1 Interrupt 4 UART Interrupt 5 T2CCU,UART Normal Divider Overflow, MultiCAN Interrupt ADC, MultiCAN Interrupt 7 SSC Interrupt 8 External Interrupt 2, Timer 21, UART1, UART1 Normal Divider Overflow Interrupt External Interrupt [6:3], MultiCAN Interrupt 10 MultiCAN interrupt 11 MultiCAN Interrupt 12 MultiCAN Interrupt 13 MultiCAN Interrupt 14

Data Sheet 60 V1.0, 2010-03

3.5 Parallel Ports

The XC858 has 40 port pins organized into fi ve parallel ports: Port 0 (P0), Port 1 (P1), Port 3 (P3), Port 4 (P4) and Port 5 (P5). Each pin has a pair of internal pull-up and pull- down devices that can be individually enabled or disabled. These ports are bidirectional and can be used as g eneral purpose input/ output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When co nfigured as an output, the open drain mode can be selected. Bidirectional Port Features

• Configurable pin direction
• Configurable pull-up /pull-down devices
• Configurable open drain mode
• Configurable drive strength
• Transfer of data through digital inpu ts and outputs (general purpose I/O)
• Alternate input/output for on-chip peripherals

Data Sheet 62 V1.0, 2010-03

3.6 Power Supply System with Embedded Voltage Regulator

The XC858 microcontroller requires two different levels of power supply:

• 5.0 V for the Embedded Voltag e Regulator (EVR) and Ports
• 2.5 V for the core, memory, on-ch ip oscillator, and peripherals Figure 19 shows the XC858 power supply system. A power supply of 5.0 V must be provided from the external power supply pi n. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the pow er consumption of the whole chip and the complexity of the application board design. The EVR consists of a main voltage regula tor and a low power voltage regulator. In active mode, both voltage regulators are enabled. In power-down mode, the main voltage regulator is switched off, while the low power voltage re gulator continues to function and provide power supply to the system with low power consumption. Figure 19 XC858 Power Supply System EVR Features
• Input voltage ( VDDP): 5.0 V
• Output voltage ( VDDC): 2.5 V ± 7.5%
• Low power voltage regulator provided in power-down mode
• VDDP prewarning detection
• VDDC brownout detection On-chip OSC CPU & Memory VDDC (2.5V) VDDP (5.0V ) VSSP GPIO Ports (P0-P5) EVR Peripheral logic FLASH ADC PLL XTAL1& XTAL2

Data Sheet 63 V1.0, 2010-03

3.7 Reset Control

The XC858 has five types of reset: power-on reset, hard ware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC858 is first powered up, the status of certain pins (see Table 20) must be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired b oot option, which cannot be modified until the next power-on reset or hardware reset. Th is guarantees stable conditions during the normal operation of the device. The second type of reset in XC858 is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode . A reset input pin RESET is provided for the hardware reset. The Watchdog Timer (WDT) module is also capable of resetting the device if it detects a malfunction in the system. Another type of reset that needs to be detected is a re set while the device is in power-down mode (wake-up reset). While the contents of the static RAM are undefined after a power-on reset, they are well defin ed after a wake-up reset from power-down mode.

3.7.1 Module Reset Behavior

Table 19 lists the functions of the XC858 and th e various reset types that affect these functions. The symbol “■” signifies that the particular function is reset to its default state. Table 19 Effect of Reset on Device Functions Module/ Function Wake-Up Reset Watchdog Reset Hardware Reset Power-On Reset Brownout Reset On-Chip Static RAM Not affected, Reliable Not affected, Reliable Not affected, Reliable Affected, un- reliable Affected, un- reliable Oscillator, PLL ■ Not affected ■■■ EVR The voltage regulator is switched on Not affected Not affected ■■ NMI Disabled Disabled ■■■

Data Sheet 64 V1.0, 2010-03

3.7.2 Booting Scheme

When the XC858 is reset, it must identify the type of configuration with which to start the different modes once the re set sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0 .0 collectively select t he different boot options. Table 20 shows the available boot options in the XC858. Note: The boot options are valid only with the default set of UART and JTAG pins. Table 20 XC858 Boot Selection 1) 1) In addition to the pins MBC, TMS and P0.0, TM pin also requires an external pull down for all the boot options. MBC TMS P0.0 Type of Mode PC Start Value 1 0 X User Mode 2); on-chip OSC/PLL non-bypassed 2) BSL mode is automatically entered if no valid password is installed and data at memory address 0000H equals zero. 0000H 0 0 X BSL Mode; (UART/ MultiCAN Mode 3)4) and Alternate BSL Mode5)); on-chip OSC/PLL non- bypassed 3) UART or MultiCAN BSL is decoded by firmware based on th e protocol for product variant with MultiCAN. If no MultiCAN variant, UART BSL is used. 4) In MultiCAN BSL mode, the clock source is switched to XTAL by firmware, bypassing the on-chip oscillator. This avoids any frequency invariance with the on-chip oscillator and allows other frequency clock input, thus ensuring accurate baud rate detection (especially at high bit rates). 5) Alternate BSL Mode is a user defined BSL code programmed in Flash. It is entered if the AltBSLPassword is valid. 0000H 0 1 0 OCDS Mode; on-chip OSC/PLL non- bypassed 0000H 1 1 0 User (JTAG) Mode 6); on-chip OSC/PLL non- bypassed (normal) 6) Normal user mode with standard JTAG (T CK,TDI,TDO) pins for hot-attach purpose. 0000H

Data Sheet 65 V1.0, 2010-03

3.8 Clock Generation Unit

The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the XC858. The power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is directly proportional to the frequency. During user program execution, the fr equency can be programmed fo r an optimal ratio between performance and power cons umption. Therefore the power consumption can be adapted to the actual application state.

• Phase-Locked Loop (PLL) for multiplyin g clock source by different factors
• P L L B a s e M o d e
• Prescaler Mode
• P L L M o d e
• Power-down mode support The CGU consists of an oscillator circuit and a PLL. In the XC858, the oscillator can be from either of these two sources: the on-chip oscillator (4 MHz) or the external oscillator (2 MHz to 20 MHz). The term “oscillator” is used to refer to both on-chip oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be used by default.The external oscillator can be selected via software. In addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows emergency routines to be executed for system recovery or to perform system shut down.

Data Sheet 66 V1.0, 2010-03 Figure 20 CGU Block Diagram Direct Drive (PLL Bypass Operation) During PLL bypass operation, the system clock has the same frequency as the external clock source. (3.1) PLL Mode The CPU clock is derived from the oscillato r clock, divided by the NR factor (PDIV), multiplied by the NF factor (NDIV), and divided by the OD factor (KDIV). PLL output must PLL PLL core lock detect NF:1 NR:1 fvco fn fpOSC fosc OD:1 fSYS NDIV PLL_LOCK PLLBYPKDIVPDIV Wrapper PLL watchdog External oscillator watchdog PLLPD EXTOSCR OSCSS PLLR Switching circuitry OSCSYS ff =

Data Sheet 67 V1.0, 2010-03 not be bypassed for this PLL mode. Th e PLL mode is used during normal system operation. (3.2) System Frequency Selection For the XC858, the value of NF, NR and OD can be selected by bits NDIV, PDIV and KDIV respectively for different oscillator inputs inorder to obtain the required fsys. But the combination of these factors must fulfill the following condition:

• 100 MHz < f VCO <1 7 5M H z
• 800 kHz < f OSC / (2 * NR) < 8 MHz Table 21 provides examples on how the typica l system frequency of fsys = 144 MHz and maximum fre quency of 160 MHz (CPU clock = 24 MHz)can be obtained for the different oscillator sources.

3.8.1 Recommended External Oscillator Circuits

The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output. When using a crystal, a proper external oscillator circuitr y must be con nected to both pins, XTAL1 and XTAL2. Th e crystal frequency can be wit hin the range of 2 MHz to 20 MHz. Additionally, it is necessa ry to have two load capacitances CX1 and CX2, and depending on the crystal type, a series resistor RX2, to limit the current. A test resistor RQ may be temporarily inserted to measure the oscillation allowance (negative resistance) of the oscillator circuitry. RQ values are typically specif ied by the crystal vendor. An external feedback resistor Rf is also required in the external oscillator circuitry. The exact values and related operating range are dependent on the crystal frequency and have to be determined and optimized together with the crystal vendor using the negative Table 21 System frequency ( fsys =1 4 4M H z ) Oscillator fosc N P K fsys On-chip 4 MHz 72 2 1 144 MHz

4 MHz 80 2 1 160 MHz

External 8 MHz 72 4 1 144 MHz

6 MHz 72 3 1 144 MHz

4 MHz 72 2 1 144 MHz

NFxff OSCSYS =

Data Sheet 68 V1.0, 2010-03 resistance method. Oscillation measurement with the final target system is strongly recommended to verify the i nput amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is left open (unconnected). The oscillator can also be us ed in combination with a ceramic re sonator. The final circuitry must also be verifi ed by the res onator vendor. Figure 21 shows the recommended external oscillator circuitries fo r both operating mode s, external crystal mode and external input clock mode. Figure 21 External Os cillator Circuitry Note: For crystal operation, it is st rongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. XC858 Oscillator VSS CX1 2 - 20 MHz CX2 XTAL1 XTAL2 XC858 Oscillator XTAL 1 XTAL 2 External Clock Signal fOSC fOSC Fundamental Mode Crystal RX2 RQ VSS Rf

Data Sheet 69 V1.0, 2010-03

3.8.2 Clock Management

The CGU generates all clock signals required within the mi crocontroller from a single clock, fsys. During normal syst em operation, the typical fr equencies of the different modules are as follow:

• CPU clock: CCLK, SCLK = 24 MHz
• MultiCAN clock : MCANCLK = 24 or 48 MHz
• T2CCU clock : T2CCUCLK = 24 or 48 MHz
• Peripheral clock: PCLK = 24 MHz In addition, different clock frequencies can be output to pin CLKOUT (P0.0 or P0.7). The clock output frequency, which is derived from the clock output divider (bit COREL), can further be divided by 2 using toggle latch (bit TL EN is set to 1). Th e resulting output frequency has a 50% duty cycle. Figure 22 shows the clock distribution of the XC858. Figure 22 Clock Generation from fsys PLL NF,NR,OD fsys CLKREL CCLK SCLK PCLK CORE Peripherals On-chip OSC CLKOUT fosc COREL COUTS Toggle Latch TLEN MultiCAN MCAN CLK FCCFG SD T2CCU T2CCU CLK T2CCFG FCLKOSCSS External OSC

Data Sheet 70 V1.0, 2010-03 For power saving purposes, the clocks may be disabled or slowed down according to Table 22. Table 22 System frequency ( fsys =1 4 4M H z ) Power Saving Mode Action Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all th e peripherals are divided by a common programmable factor defined by bit field CMCON.CLKREL. Power-down Oscillator an d PLL are switched off.

Data Sheet 71 V1.0, 2010-03

3.9 Power Saving Modes

The power saving modes of the XC858 prov ide flexible power consumption through a combination of techniques, including:

• Stopping the CPU clock
• Stopping the clocks of i ndividual system components
• Reducing clock speed of some peripheral components
• Power-down of the entire system with fast restart capability After a reset, the ac tive mode (normal operating m ode) is selected by default (see Figure 23) and the system runs in the main system clock frequency. From active mode, different power saving modes can be selected by software. They are:
• Idle mode
• Slow-down mode
• Power-down mode Figure 23 Transition betw een Power Saving Modes POWER-DOWN IDLE ACTIVE SLOW-DOWN set PD bit set PD bit set IDLE bit set IDLE bit set SD bit clear SD bit any interrupt & SD=0 EXINT0/RXD pin & SD=0 EXINT0/RXD pin & SD=1 any interrupt & SD=1

Data Sheet 72 V1.0, 2010-03

3.10 Watchdog Timer

The Watchdog Timer (WDT) provides a high ly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an XC858 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an acci dental malfunction of the XC858 will be aborted in a user-specified time period. In debug mode, the WDT is def ault suspended and stops counting. Therefore, there is no need to refresh the WDT during debugging.

• 16-bit Watchdog Timer
• Programmable reload value fo r upper 8 bits of timer
• Programmable window boundary
• Selectable input frequency of fPCLK/2 or fPCLK/128
• Time-out detection wit h NMI generation and reset prewarning activation (after which a system reset will be performed) The WDT is a 16-bit timer incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog service access in order to modify the watchdog expire time per iod. The lower 8 bits are reset on each service access. Figure 24 shows the block diagram of the WDT unit. Figure 24 WDT Block Diagram WDTREL MUX WDT Low Byte 1:2 Clear WDT Control 1:128 WDT High Byte FNMIWDT WDTIN fPCLK Logic ENWDT ENWDT_P WDTRST Overflow/Time-out Control & Window-boundary control WDTWINB

Data Sheet 73 V1.0, 2010-03 If the WDT is not serviced before the timer overflow, a system malfunction is assumed. As a result, the WDT NMI is triggered (asse rt FNMIWDT) and the reset prewarning is entered. The prewarni ng period lasts for 30 H count, after which the system is reset (assert WDTRST). The WDT has a “programmable window boundary” which disallows any refresh during the WDT’s count-up. A refr esh during this win dow boundary constitutes an invalid access to the WDT, causing the reset prewarning to be entered but without triggering the WDT NMI. The system will still be reset after the prewarning period is over. The window boundary is from 0000H to the value obtained from the concatenation of WDTWINB and 00H. After being serviced, the WDT continues counting up from the value (<WDTREL> * 28). The time period for an overflow of the WDT is programmable in two ways:

• The input frequency to the WDT can be selected to be either fPCLK/2 or fPCLK/128
• The reload value WDTREL for the high by te of WDT can be programmed in register WDTREL The period, PWDT, between servicing the WDT and the next overflow can be determined by the following formula: (3.3) If the Window-Boundary Refresh featur e of the WDT is enabled, the period PWDT between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL, see Figure 25. This period can be calculated using the same formula by replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB cannot be smaller than WDTREL. PWDT 2 1W D T I N+ 6×() 216 WDTREL– 28×()× fPCLK

Data Sheet 74 V1.0, 2010-03 Figure 25 WDT Timing Diagram Table 23 lists the possible watchdog time ranges that can be achieved using a certain module clock. Some numbers are rounded to 3 significant digits.

3.11 UART and UART1

The XC858 provides two Universal Asyn chronous Receiver/Transmitter (UART and UART1) modules for full-duplex asynchron ous reception/transmission. Both are also receive-buffered, i.e., they can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost.

• Full-duplex asynchronous modes – 8-bit or 9-bit data frames, LSB first – Fixed or vari able baud rate
• Receive buffered
• Multiprocessor communication Table 23 Watchdog Time Ranges Reload value In WDTREL Prescaler for fPCLK 2 (WDTIN = 0) 128 (WDTIN = 1)

24 MHz 24 MHz

FFH 21.3 µs1 . 3 7 m s 7FH 2.75 ms 176 ms 00H 5.46 ms 350 ms WDTREL WDTWINB time Count FFFFH No refresh allowed Refresh allowed

Data Sheet 75 V1.0, 2010-03

• Interrupt generation on the completion of a data transmission or reception The UART modules can operate in the four modes shown in Table 24. There are several ways to generate the baud rate clock for the serial port, depending on the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at fPCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock and can be configured to eitherfPCLK/32 or fPCLK/64. For UART1 module, only fPCLK/64 is available. The variable baud rate is set by the underflow rate on the dedicated baud-rate generator. For UART module, t he variable baud rate alter natively can be set by the overflow rate on Timer 1.

3.11.1 Baud-Rate Generator

Both UART modules have their own dedicat ed baud-rate generator, which is based on a programmable 8-bit reload value, and in cludes divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud rates based on its input clock fPCLK, see Figure 26. Table 24 UART Modes Operating Mode Baud Rate Mode 0: 8-bit shift register fPCLK/2 Mode 1: 8-bit shift UART Variable Mode 2: 9-bit shift UART fPCLK/32 or fPCLK/641) 1) For UART1 module, the baud rate is fixed at f PCLK/64. Mode 3: 9-bit shift UART Variable

Data Sheet 76 V1.0, 2010-03 Figure 26 Baud-rate Generator Circuitry The baud rate timer is a count-down timer a nd is clocked by eith er the output of the fractional divider ( fMOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate generation, the fractional di vider must be configured to fractional divider mode (FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit reload value in register BG and one clock pulse is generated for the serial channel. Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12. The baud rate (fBR) value is dependent on the following parameters:

• Input clock fPCLK
• Prescaling factor (2 BRPRE) defined by bit field BRPRE in register BCON
• Fractional divider (STEP/256 ) defined by register FDSTEP (to be considered only if fractional divider is enab led and operatin g in fractional divider mode)
• 8-bit reload value (BR_VAL UE) for the baud rate timer defined by register BG FDSTEP FDM Adder FDRES FDEN&FDM clk Fractional Divider Prescaler NDOV ‘0’ FDEN (overflow) fBR 8-Bit Baud Rate Timer 8-Bit Reload Value R fDIV fDIVfPCLK fMOD

Data Sheet 77 V1.0, 2010-03 The following formulas calculate the final baud rate without and with the fractional divider respectively: (3.4) (3.5) The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud. Table 25 lists the various commonly used baud rates with their corresponding parameter settings and deviation errors. The fractiona l divider is disabled and a module clock of 24 MHz is used. The fractional divider allows baud rates of higher accuracy (lower deviation error) to be generated. Table 26 lists the resulting de viation errors from ge nerating a baud rate of 57.6 kHz, using different module clock freque ncies. The fractional divider is enabled (fractional divider mode) and the corresponding parameter settings are shown. Table 25 Typical Baud rates for UART with Fractional Divider disabled Baud rate Prescaling Factor (2BRPRE) Reload Value (BR_VALUE + 1) Deviation Error 19.2 kBaud 1 (BRPRE=000 B) 7 8 ( 4 E H)0 . 1 7 % 9600 Baud 1 (BRPRE=000 B) 156 (9C H)0 . 1 7 % 4800 Baud 2 (BRPRE=001 B) 156 (9C H)0 . 1 7 % 2400 Baud 4 (BRPRE=010 B) 156 (9C H)0 . 1 7 % baud rate fPCLK 16 2 BRPRE BR_VALUE 1+()×× baud rate fPCLK 16 2 BRPRE BR_VALUE 1+()××

Data Sheet 78 V1.0, 2010-03

3.11.2 Baud Rate Generation using Timer 1

In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the variable baud rates. In theo ry, this timer could be used in any of its modes. But in practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the required b aud rate. The baud rate is determined by the Timer 1 overflow rate and the value of SMOD as follows: (3.6)

3.12 Normal Divider Mode (8-bit Auto-reload Timer)

Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider mode, while at the same time disables baud rate generation (see Figure 26). Once the fractional divider is enabled (FDEN = 1), it f unctions as an 8-bit auto-reload timer (with no relation to baud rate generation) and counts up from the reload value with each input clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit field STEP in register FDSTEP defines the reload value. At eac h timer overflow, an overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP. The output frequency in normal divider mode is derived as follows: (3.7) Table 26 Deviation Error for UART wi th Fractional Divider enabled fPCLK Prescaling Factor (2BRPRE) Reload Value (BR_VALUE + 1) STEP Deviation Error 24 MHz 1 6 (6 H) 59 (3B H) +0.03 % 12 MHz 1 3 (3 H) 59 (3B H) +0.03 % 8M H z 1 2 ( 2 H) 59 (3B H) +0.03 % 6M H z 1 6 ( 6 H) 236 (EC H) +0.03 % Mode 1, 3 baud rate 2SMOD fPCLK× fMOD fDIV

Data Sheet 79 V1.0, 2010-03

3.13 High-Speed Synchronous Serial Interface

The High-Speed Synchronou s Serial Interface (SSC ) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master m ode), using its own 16-bit bau d-rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices or devices using other synchronous serial interfaces.

• Master and slave mode operation – Full-duplex or ha lf-duplex operation
• Transmit and receive buffered
• Flexible data format – Programmable number of data bits: 2 to 8 bits – Programmable shift directi on: LSB or MSB shift first – Programmable clock polarity: idle lo w or high state for the shift clock – Programmable clock/data phase: data shift with leading or trailing edge of the shift clock
• Variable baud rate
• Compatible with Serial Pe ripheral Interface (SPI)
• Interrupt generation – On a transmitter empty condition – On a receiver full condition – On an error condition (receive, p hase, baud rate, transmit error) Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR (Master Transmit/Slave Re ceive) and MRST (Ma ster Receive/Slave Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin SCLK. Transmission and reception of data are double-buffered. Figure 27 shows the block diagram of the SSC.

Data Sheet 80 V1.0, 2010-03 Figure 27 SSC Block Diagram PCLK SS_CLK RIR TIR EIR Receive Int. Request Transmit Int. Request Error Int. Request ControlStatus TXD(Master) RXD(Slave) Shift Clock MS_CLK RXD(Master) TXD(Slave) Internal Bus Baud-rate Generator Clock Control SSC Control Block Register CON Pin Control16-Bit Shift Register Transmit Buffer Register TB Receive Buffer Register RB

Data Sheet 81 V1.0, 2010-03

3.14 Timer 0 and Timer 1

Timer 0 and Timer 1 can func tion as both timers or count ers. When functioning as a timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are incremented in response to a 1-to-0 transition (falling edge) at their respective external input pins, T0 or T1. Timer 0 and 1 are fully compat ible and can be configured in four different operating modes for use in a vari ety of applications, see Table 27. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions are specialized. Table 27 Timer 0 and Timer 1 Modes Mode Operation 0 13-bit timer The timer is essentially an 8-bit counter with a divide-by-32 prescaler. This mode is included solely for compatibility with Intel 8048 devices. 1 16-bit timer The timer registers, TLx and THx, are concatenated to form a 16-bit counter. 2 8-bit timer with auto-reload The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow.

3 Timer 0 operates as two 8-bit timers

The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and retains its count even if enabled.

Data Sheet 82 V1.0, 2010-03

3.15 Timer 2 and Timer 21

Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode, see Table 28. As a timer, the timers count with an input clock of PCLK/12 (if prescaler is disabled). As a counter, they count 1-to-0 transitions on pin T2. In the counter mode, the maximum resolution for the count is PCLK/24 (if prescaler is disabled). Table 28 Timer 2 Modes Mode Description Auto-reload Up/Down Count Disabled

• Count up only
• Start counting from 16-bit reload value, overflow at FFFFH
• Reload event confi gurable for trigger by overflow condition only, or by negative/positive edge at input pin T2EX as well
• Programmble reload value in register RC2
• Interrupt is generate d with reload event Up/Down Count Enabled
• Count up or down, direction dete rmined by level at input pin T2EX
• No interrupt is generated
• Count up – Start counting from 16-bit re load value, overflow at FFFF H – Reload event triggered by overflow condition – Programmble reload value in register RC2
• Count down – Start counting from FFFF H, underflow at value defined in register RC2 – Reload event trigger ed by underflow condition – Reload value fixed at FFFF H Channel capture
• Count up only
• Start counting from 0000 H, overflow at FFFFH
• Reload event triggered by overflow condition
• Reload value fixed at 0000 H
• Capture event triggered by falling/rising edge at pin T2EX
• Captured timer value st ored in register RC2
• Interrupt is gene rated with reload or capture event

Data Sheet 83 V1.0, 2010-03

3.16 Timer 2 Capture/Compare Unit

The T2CCU (Timer 2 Capture/Compare Unit) consists of the standard Timer 2 unit and a Capture/compare unit (CCU). The Capture/Compare Timer (CCT) is part of the CCU. Control is available in th e T2CCU to select individual ly for each of its 16-bit capture/compare channel, either the Timer 2 or the Capt ure/Compare Timer (CCT) as the time base. Both timers have a resolution of 16 bits.The clock frequency of T2CCU, fT2CCU, could be set at PCLK frequency or 2 times the PCLK frequency. The T2CCU can be used for various digital si gnal generation and event capturing like pulse generation, pul se width modulation, pulse width meas uring etc. Target applications include various automotive control as well as industrial (frequency generation, digital-to-analog conversion, process control etc.). T2CCU Features

• Option to select individually for each channel, either Timer 2 or Capture/Compare Timer as time base
• Extremely flexible Capture/Compare Time r count rate by cascading with Timer 2
• Capture/Compare Timer may be ‘reset’ immediately by triggering overflow event
• 16-bit resolution
• Six compare channels in total
• Four capture channels mu ltiplexed with the compare channels, in total
• Shadow register for each compare register – Transfer via software control or on timer overflow.
• Compare Mode 0: Compare output signal c hanges from the inactive level to active level on compare match. Returns to inactive level on timer overflow. – Active level can be defined by regi ster bit for channel groups A and B. – Support of 0% to 100% duty cycle in compare mode 0.
• Compare Mode 1: Full control of the software on the compare output signal level, for the next compare match.
• Concurrent Compare Mo de with channel 0
• Capture Mode 0: Capture on any external event (rising/falling/both edge) at the 4 pins T2CC0 to T2CC3.
• Capture Mode 1: Capture upon writing to the low byte of the corresponding channel capture register.
• Capture mode 0 or 1 can be established independently on the 4 capture channels.

Data Sheet 84 V1.0, 2010-03

3.17 Controller Area Network (MultiCAN)

The MultiCAN module contains two Fu ll-CAN nodes operat ing independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 B active. Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Both CAN nodes share a common set of message objects, where each message object may be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects may be combined to build gateways between the CAN nodes or to setup a FIFO buffer. The message objects are organized in double chained lists, where each CAN node has it’s own list of message objects. A CAN node stores frames only into message objects that are allocated to the list of the CAN node. It only transmits messages from objects of this list. A powerful, command driven list controller performs all list operations. The bit timings for the CAN nodes are derived from the peripheral clock ( fCAN) and are programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects each CAN node to a bus transceiver. Figure 28 Overview of the MultiCAN

• Compliant to ISO 11898. MultiCAN Module Kernel Mult iCAN_XC8_overview Port ControlCAN Node 0 CAN Control Message Object Buffer Objects CAN Node 1 TXDC0 RXDC0 TXDC1 RXDC1Linked List Control fCANClock Control Address Decoder & Data control Access Mediator Interrupt Controller CANSRC[7:0] A[13: 2] D[31:0]

Data Sheet 85 V1.0, 2010-03

• CAN functionality according to CAN specification V2.0 B active.
• Dedicated control registers ar e provided for each CAN node.
• A data transfer rate up to 1 MBaud is supported.
• Flexible and powerful message transfer c ontrol and error hand ling capabilities are implemented.
• Advanced CAN bus bit timing analysis and baud rate detection can be performed for each CAN node via the frame counter.
• Full-CAN functionality: A set of 32 message objects can be individually – allocated (assigned ) to any CAN node – configured as transmit or receive object – setup to handle frames with 11-bit or 29-bit identifier – counted or assigned a time stamp via a frame counter – configured to remote monitoring mode
• Advanced Accept ance Filtering: – Each message object provid es an individual acceptan ce mask to filter incoming frames. – A message object can be configured to accept only standard or only extended frames or to accept both standard and extended frames. – Message objects can be grouped into 4 priority classes. – The selection of the message to be transmitted first can be performed on the basis of frame identifier, IDE bit and RTR bit according to CAN arbitration rules.
• Advanced Message Ob ject Functionality: – Message Objects can be combined to build FIFO message buffers of arbitrary size, which is only limited by the total number of message objects. – Message objects can be linked to form a gateway to automatically transfer frames between 2 different CAN buses. A single gateway can link any two CAN nodes. An arbitrary number of gateways may be defined.
• Advanced Data Management: – The Message objects are org anized in double chained lists. – List reorganizations may be performed an y time, even during full operation of the CAN nodes. – A powerful, command driven list contro ller manages the organ ization of the list structure and ensures consistency of the list. – Message FIFOs are based on the list structure and can easily be scaled in size during CAN operation. – Static Allocation Commands offer compatibility with TwinCAN applications, which are not list based.
• Advanced Interrupt Handling: – Up to 8 interrupt output lines are available. Most interrupt requests can be individually routed to one of the 8 interrupt output lines. – Message postprocessing notifications c an be flexibly aggregated into a dedicated register field of 64 notification bits.

Data Sheet 86 V1.0, 2010-03

3.18 Analog-to-Digital Converter

The XC858 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert t he analog voltage levels from up to eight different sources. The analog input channels of the ADC are available at AN0 - AN7.

• Successive approximation
• 8-bit or 10-bit resolution
• Eight analog channels
• Four independent result registers
• Result data protection for slow CPU access (wait-for-read mode)
• Single conversion mode
• Autoscan functionality
• Limit checking for conversion results
• Data reduction filter (accumulation of up to 2 conversion results)
• Two independent conversion request sources with programmable priority
• Selectable conversion request trigger
• Flexible interrupt generation wi th configurable service nodes
• Programmable sample time
• Programmable clock divider
• Cancel/restart feature for running conversions
• Integrated sample and hold circuitry
• Compensation of offset errors
• Low power modes

3.18.1 ADC Clocking Scheme

A common module clock fADC generates the various clock signals used by the analog and digital parts of the ADC module:

• fADCA is input clock for the analog part.
• fADCI is internal clock for the analog part (defines the time base for conversion length and the sample time). This clock is generated internally in the analog part, based on the input clock fADCA to generate a correct duty cycle for the analog components.
• fADCD is input clock for the digital part. Figure 29 shows the clocking scheme of the ADC module. The prescaler ratio is selected by bit field CTC in register GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required.

Data Sheet 87 V1.0, 2010-03 Figure 29 ADC Clocking Scheme For module clock fADC = 24 MHz, the analog clock fADCI frequency can be selected as shown in Table 29. During slow-down mode, fADC may be reduced further, for example, to 12 MHz or 6 MHz. However, it is important to note that the conversion error could increase due to loss of charges on the capacitors, if fADC becomes too low during slow-down mode.

3.18.2 ADC Conversion Sequence

The analog-to-digital conversion procedure consists of the following phases: Table 29 fADCI Frequency Selection Module Clock fADC CTC Prescaling Ratio Analog Clock fADCI

24 MHz 00 B ÷2 1 2M H z

01B ÷3 8M H z 10B ÷4 6M H z 11B (default) ÷ 32 750 kHz analog components fADCI fADC= fPCLK MUX arbiter registers interrupts analog part digital part fADCD fADCA 32÷ clock prescaler CTC

Data Sheet 88 V1.0, 2010-03

• Synchronization phase ( tSYN)
• Sample phase ( tS)
• Conversion phase
• Write result phase ( tWR) Figure 30 ADC Conversion Timing tS tCONV tWR SAMPLE Bit BUSY Bit Conversion PhaseSample Phase Write Result Phase conversion start trigger Source interrupt Result interrupt tSYN Channel interrupt fADCI

Data Sheet 89 V1.0, 2010-03

3.19 On-Chip Debug Support

The On-Chip Debug Support (OCDS ) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles:

• Use the built-in debug func tionality of the XC800 Core
• Add a minimum of hardware overhead
• Provide support for mo st of the operations by a Monitor Program
• Use standard interfaces to communicate with the Host (a Debugger)
• Set breakpoints on instruction addre ss and on address ra nge within the Program Memory
• Set breakpoints on internal RAM address range
• Support unlimited software brea kpoints in Flash/RAM code region
• Process external breaks via JTAG and upon activating a dedicated pin
• Step through the program code The OCDS functional blocks are shown in Figure 31. The Monitor Mode Control (MMC) block at the center of OCDS system brings together control sign als and supports the overall functionality. The MMC communicates with the XC800 Core, primarily via the Debug Interface, and also receives reset and clock signals. After processing memory address and control signals from the core, the MMC provides proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for work-data and Monitor-stack). The OCDS system is a ccessed through the JTAG 1), which is an interface dedicated exclusively for testing a nd debugging activities and is not normally used in an application. The dedica ted MBC pin is used for exter nal configuration and debugging control. Note: All the debug functionality described here can normally be used only after XC858 has been started in OCDS mode. 1) The pins of the JTAG port can be assigned to either t he primary port (Port 0) or either of the secondary ports (Ports 1 and 2/Port 5). User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.

Data Sheet 90 V1.0, 2010-03 Figure 31 OCDS Block Diagram

3.19.1 JTAG ID Register

This is a read-only register located inside the JTAG module, and is used to recognize the device(s) connected to the JTAG interface. Its content is shifted out when INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is also true immediately after reset. The JTAG ID register contents for the XC858 Flash devices are given in Table 30. Table 30 JTAG ID Summary Device Type Device Name JTAG ID Flash XC858CA-16FF 1018 2083 H XC858CA-13FF 1018 3083 H XC858CA-9FF 1018 4083 H JTAG Module Monitor & Bootstrap loader Control line JTAG Memory Control Unit User Program Memory XC800 Core PROG & IRAM Addresses Debug Interface Reset Clock TMS TCK TDI TDO TCK TDI TDO Control Memory Control Debug Interface System Control Unit Boot/ Monitor ROM Monitor RAM User Internal RAM Reset Reset Clock PROG Data Monitor Mode Control MBC - parts of OCDS SuspendControl OCDS_XC886C-Block_Diagram-UM-v0.2

Data Sheet 91 V1.0, 2010-03

3.20 Chip Identification Number

The XC858 identity (ID) register is located at Page 1 of address B3 H. The value of ID register is 49 H. However, for easy identificati on of product variants, the Chip Identification Number, which is an unique number assigned to each product variant, is available. The differentiati on is based on the product, variant type and device step information. Two methods are provided to read a device’s chip identification number:

• In-application subroutine, GET_CHIP_INFO
• Bootstrap loader (BSL) mode A Table 31 lists the chip identification numbers of available XC858 Flash device variants. Table 31 Chip Identification Number Product Variant Chip Id entification Number AC-Step Flash Devices XC858CA-16FF 4B5800C3 H XC858CA-13FF 4B5904C3 H XC858CA- 9FF 4B5A08C3 H

Data Sheet 92 V1.0, 2010-03

4 Electrical Parameters

Chapter 4 provides the characteristics of the electrical par ameters which are implementation-specific for the XC858.

4.1 General Parameters

The general parameters are described here to aid the us ers in interpreting the parameters mainly in Section 4.2 and Section 4.3.

4.1.1 Parameter Interpretation

The parameters listed in this section repr esent partly the characteristics of the XC858 and partly its requirements on the system. To aid interpre ting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the “Symbol” column:

• CC These parameters indicate Controller Characteristics, which are distinctive features of the XC858 and must be regarded for a system design.
• SR These parameters indicate System Requirements, which must be provided by the microcontroller system in which the XC858 is designed in.

Data Sheet 93 V1.0, 2010-03

4.1.2 Absolute Maximum Rating

Maximum ratings are the extreme limits to which the XC858 can be subjected to without permanent damage. Note: Stresses above thos e listed under “Absolute Ma ximum Ratings” may cause permanent damage to the device. This is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for exten ded periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the voltage on VDDP pin with respect to ground ( VSS) must not exceed the values defined by the absolute maximum ratings. Table 32 Absolute Maximu m Rating Parameters Parameter Symbol Limit Values Unit Notes min. max. Ambient temperature TA -40 85 °C under bias Storage temperature TST -65 150 °C Junction temperature TJ -40 120 °C under bias Voltage on power supply pin with respect to VSS VDDP -0.5 6 V Voltage on any pin with respect to VSS VIN -0.5 V DDP + 0.5 or max. 6 V Whatever is lower Input current on any pin during overload condition IIN -10 10 mA Absolute sum of all input currents during overload condition Σ|IIN|– 5 0 m A

Data Sheet 94 V1.0, 2010-03

4.1.3 Operating Conditions

The following operating conditi ons must not be exceeded in order to ensure correct operation of the XC 858. All parameters mentioned in the following table refer to these operating conditions, unless otherwise noted. Table 33 Operating Condition Parameters Parameter Symbol Limit Values Unit Notes/ Conditionsmin. max. Digital power supply voltage VDDP 4.5 5.5 V 5V Device Digital ground voltage VSS 0V CPU Clock Frequency1) 1) fCCLK is the input frequency to the XC800 core. Please refer to Figure 22 for detailed description. fCCLK 24 MHz Ambient temperature TA -40 85 °C SAF-XC858

Data Sheet 95 V1.0, 2010-03

4.2 DC Parameters

The electrical characteristics of the DC Parameters are detailed in this section.

4.2.1 Input/Output Characteristics

Table 34 provides the characteristics of the input/output pins of the XC858. Table 34 Input/Output Characteristi cs (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max. VDDP = 5 V Range Output low voltage VOL CC – 0.6 V IOL = 9 mA (DS = 0)1) IOL =1 2m A ( D S=1 )2) Output high voltage VOH CC 2.4 – V IOH = -20 mA (DS = 0)1) IOH = -25 mA (DS = 1)2) Input low voltage VIL SR -0.3 0.8 V CMOS Mode Input high voltage VIH SR 2.2 VDDP V CMOS Mode Input Hysteresis HYS CC 0.35 – V CMOS Mode 3)4) Input low voltage at XTAL1 VILX SR -0.3 0.8 V Input high voltage at XTAL1 VIHX SR 3.4 VDDP V Pull-up current IPU SR – -20 µA VIH,min -88 – µA VIL,max Pull-down current IPD SR – 10 µA VIL,max 66 – µA VIH,min Input leakage current IOZ1 CC -1 1 µA0 < VIN < VDDP, TA ≤85°C5) Overload current on any pin IOV SR -5 5 mA Absolute sum of overload currents Σ|IOV|S R – 2 5 m A 6) Voltage on any pin during VDDP power off VPO SR – 0.3 V 7)

Data Sheet 96 V1.0, 2010-03 Maximum current per pin (excluding VDDP and VSS) IM SR SR – 25 mA Maximum current for all pins (excluding VDDP and VSS) Σ|IM|S R – 1 5 0 m A Maximum current into VDDP IMVDDP SR – 200 mA 6) Maximum current out of VSS IMVSS SR – 200 mA 6) 1) DS = 0 refers to the pin having a weak drive st rength which is programmable via Px_DS register. 2) DS = 1 refers to the pin having a strong drive st rength which is programmable via Px_DS register. 3) Not subjected to production test, verified by design/char acterization. Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. 4) P0.1 has a minimum input hysteresis of 0.25V. 5) An additional error current ( IINJ) will flow if an overload current flows through an adjacent pin. TMS pin and RESET pin have internal pull devices and are not included in the input leakage current characteristic. 6) Not subjected to production test, verified by design/characterization. 7) Not subjected to production test, verified by design/char acterization. However, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin when VDDP is powered off. Table 34 Input/Output Characteristi cs (Operating Conditions apply) (cont’d) Parameter Symbol Limit Values Unit Test Conditions min. max.

Data Sheet 97 V1.0, 2010-03

4.2.2 Supply Threshold Characteristics

Table 35 provides the characteristics of the supply threshold in the XC858. Figure 32 Supply Th reshold Parameters Table 35 Supply Threshold Parameters (Operating Conditions apply) Parameters Symbol Limit Values Unit min. typ. max. VDDC brownout voltage1) 1) Detection is enabled in both active and power-down mode. VDDCBO CC 1.7 1.9 2.2 V RAM data retention voltage VDDCRDR C C 1 . 2 ––V VDDP prewarning voltage VDDPPW CC 3.8 4.2 4.5 V Power-on reset voltage1)2) 2) The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage. VDDCPOR CC 1.7 1.9 2.2 V VDDP VDDC VDDPPW VDDCPOR VDDCBO 5.0V 2.5V VDDCRDR

Data Sheet 98 V1.0, 2010-03

4.2.3 ADC Characteristics

The values in the table be low are given for an analog power supply between 4.5 V to 5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case, the analog parameters may show a reduced performance. All ground pins (VSS) must be externally connected to one single star point in the sy stem. The voltage difference between the ground pins must not exceed 200mV. Table 36 ADC Characteristics (O perating Conditions apply; VDDP = 5V Range) Parameter Symbol Limit Values Unit Test Conditions/ Remarksmin. typ . max. Analog reference voltage VAREF SR VAGND + 1 VDDP VDDP + 0.05 V 1) Analog reference ground VAGND SR VSS - 0.05 VSS VAREF - 1 V 1) Analog input voltage range VAIN SR VAGND – VAREF V ADC clocks fADC – 24 – MHz module clock 1) fADCI –– 1 4 2) MHz internal analog clock 1) See Figure 29 Sample time tS CC (2 + INPCR0.STC) × tADCI µs 1) Conversion time tC CC See Section 4.2.3.1 µs 1) Differential Nonlinearity |EADNL| CC – – 1.5 LSB 10-bit conversion Integral Nonlinearity |EAINL| CC – – 2.5 LSB 10-bit conversion Offset |EAOFF| CC – – 3 LSB 10-bit conversion Gain |EAGAIN| CC – – 2.5 LSB 10-bit conversion Switched capacitance at the reference voltage input CAREFSW CC – 10 14 pF 1)3) Switched capacitance at the analog voltage inputs CAINSW CC – 4 5 pF 1)4)

Data Sheet 99 V1.0, 2010-03 Input resistance of the reference input RAREF CC – 1 2 k Ω 1) Input resistance of the selected analog channel RAIN CC – 1 3 k Ω 1) 1) Not subjected to production test, verified by design/characterization. 2) This value includes the maximum oscillator deviation. 3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this, smaller capacitances are successively switched to the reference voltage. 4) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2. Table 36 ADC Characteristics (O perating Conditions apply; VDDP = 5V Range) Parameter Symbol Limit Values Unit Test Conditions/ Remarksmin. typ . max.

Data Sheet 100 V1.0, 2010-03 Figure 33 ADC Input Circuits VAGNDx REXT Analog Input Circuitry VAIN CEXT ANx CAINSW RAIN, On VAGNDx Reference Voltage Input Circuitry CAREFSW RAREF, OnVAREFx VAREF

Data Sheet 101 V1.0, 2010-03

4.2.3.1 ADC Conversion Timing

Conversion time, tC = tADC × ( 1 + r × ( 3+n+S T C ) ) , w h e r e r=C T C+2 f o r C T C=0 0B, 01B or 10B, r = 32 for CTC = 11B, CTC = Conversion Time Control (GLOBCTR.CTC), STC = Sample Time Control (INPCR0.STC), n = 8 or 10 (for 8-bit and 10-bit conversion respectively), tADC =1/ fADC

Data Sheet 102 V1.0, 2010-03

4.2.4 Power Supply Current

Table 37 and Table 38 provide the characteristics of the power supply current in the XC858. Table 37 Power Supply Curre nt Parameters (Operating Conditions apply; VDDP = 5V range) Parameter Symbol Limit Values Unit Test Conditions typ.1) 1) The typical IDDP values are based on preliminary measurements and are to be used as reference only. These values are periodically measured at TA =+2 5 °C and VDDP =5 . 0V . max.2) 2) The maximum IDDP values are measured under worst case conditions (TA =+8 5 °C and VDDP =5 . 5V ) . VDDP = 5V Range Active Mode IDDP 37.5 45 mA 3) 3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz with on- chip oscillator of 4 MHz, RESET = VDDP; all other pins are disconnected, no load on ports. Idle Mode IDDP 29.2 35 mA 4) 4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 24 MHz, RESET = VDDP; all other pins are disconnected, no load on ports. Active Mode with slow-down enabled IDDP 10 15 mA 5) 5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals running at 1 MHz by setting CLKREL in CMCON to 1000B, RESET = VDDP; all other pins are disconnected, no load on ports. Idle Mode with slow-down enabled IDDP 9.2 14 mA 6) 6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 1 MHz by setting CLKREL in CMCON to 1000B, RESET = VDDP; all other pins are disconnected, no load on ports.

Data Sheet 103 V1.0, 2010-03 Table 38 Power Down Current (O perating Conditions apply; VDDP = 5V range) Parameter Symbol Limit Values Unit Test Conditions typ.1) 1) The typical IPDP values are based on preliminary measurements and are to be used as reference only. These values are measured at VDDP =5 . 0V . max.2) 2) The maximum IPDP values are measured at VDDP =5 . 5V . VDDP = 5V Range Power-Down Mode IPDP 20 60 µA TA =+2 5 °C3)4) 3) IPDP has a maximum value of 350 µA a t T A=+8 5°C. 4) IPDP is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. -2 0 0 µA TA =+8 5 °C4)5) 5) Not subjected to production test, verified by design/characterization.

Data Sheet 104 V1.0, 2010-03

4.3 AC Parameters

The electrical characteristics of the AC Parameters are detailed in this section.

4.3.1 Testing Waveforms

The testing waveforms for rise /fall time, output delay an d output high impedance are shown in Figure 34, Figure 35 and Figure 36. Figure 34 Rise/Fall Time Parameters Figure 35 Testing Waveform, Output Delay Figure 36 Testing Waveform, Output High Impedance 10% 90% 10% 90% VSS VDDP tR tF VDDE / 2 Test Points VDDE / 2 VSS VDDP VLoad + 0.1 V VOH - 0.1 VTiming Reference PointsVLoad - 0.1 V VOL - 0.1 V

Data Sheet 105 V1.0, 2010-03

4.3.2 Output Rise/Fall Times

Table 39 provides the characteristics of the output rise/fall times in the XC858. Figure 37 Rise/Fall Times Parameters Table 39 Output Rise/Fall Times Parame ters (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max. VDDP = 5V Range Rise/fall times t R, tF –1 0 n s 2 0 p F . 1) 2)3) 1) Rise/Fall time measurements are taken with 10% - 90% of pad supply. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 3) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.125 ns/pF. tR 10% 90% 10% 90% tF VSS VDDP

Data Sheet 106 V1.0, 2010-03

4.3.3 Power-on Reset and PLL Timing

Table 40 provides the characteristics of th e power-on reset and PLL timing in the XC858. Figure 38 Power-on Reset Timing Table 40 Power-On Reset and PLL Timi ng (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. typ. max. On-Chip Oscillator start-up time tOSCST CC – – 500 ns 1) 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. PLL lock-in in time tLOCK CC – – 200 µs 1) PLL accumulated jitter DP ––1 . 8 n s 1)2) 2) PLL lock at 144 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 72 and P = 1. VDDP Pads VDDC VPAD OSC tOSCST PLL PLL unlock PLL lock tLOCK Pad state undefined 2)Pull/Input 3)As Programmed I)until EVR is stable II)until PLL is locked III) Reset is released and start of program

Data Sheet 107 V1.0, 2010-03

4.3.4 On-Chip Oscillator Characteristics

Table 41 provides the characteristics of the on-chip oscillator in the XC858. Table 41 On-chip Oscillator Characteri stics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Nominal frequency fNOM CC 3.88 4 4.12 MHz under nominal conditions1) after IFX-backend trimming 1) Nominal condition: VDDC =2 . 5V , TA =+2 5 °C. Long term frequency deviation ∆fLT CC -5 – 5 % with respect to fNOM, over lifetime and temperature (-40°C to 85°C), for one given device after trimming Short term frequency deviation fST CC -1.0 – 1.0 % with respect to fNOM, over core supply voltage (2.5 V ± 7.5%), for one given device after trimming

Data Sheet 108 V1.0, 2010-03

4.3.5 External Data Memory Characteristics

Table 42 shows the timing of the external data memory read cycle. Figure 39 External Data Memory Read Cycle Table 42 External Data Memory Read Ti ming (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions Min. Max. RD pulse width t1 CC 2* fCCLK -1 7 - n s 1) 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. Address valid to RD t2 CC fCCLK -1 2 - n s 1) RD to valid data in t3 SR - 1.5* fCCLK -2 7 n s 1) Address to valid data in t4 SR - 3* fCCLK -7 n s 1) Data hold after RD t5 SR 0.5* fCCLK -17 - ns 1) DATA ADDRESS RD Addresses D[7:0] VALID t3t2

Data Sheet 109 V1.0, 2010-03 Table 43 shows the timing of the external data memory write cycle. Figure 40 External Data Memory Write Cycle Table 43 External Data Memory Write Timing (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions Min. Max. WR pulse width t1 CC fCCLK -1 0 - n s 1) 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. Address valid to WR t2 CC 2* fCCLK -7 - n s 1) Data valid to WR transition t3 SR fCCLK -5 - n s 1) Data setup before WR t4 SR 9* fCCLK -1 3 - n s 1) Data hold after WR t5 SR 6* fCCLK -3 - n s 1) DATA ADDRESS WR Addresses D[7:0] VALID t1t2

Data Sheet 110 V1.0, 2010-03

4.3.6 External Clock Drive XTAL1

Table 44 shows the parameters that define the external clock supply for XC858. These timing parameters are based on the direct XTAL1 drive of clock input signals. They are not applicable if an external crystal or ceramic resonator is considered. Figure 41 External Clock Drive XTAL1 Table 44 External Clock Drive Character istics (Operating Conditions apply) Parameter Symbol Limit Va lues Unit Test Conditions Min. Max. Oscillator period tosc SR 50 500 ns 1)2) 1) The clock input signals with 45-55% duty cycle are used. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. High time t1 SR 15 - ns 2)3) 3) The clock input signal must reach the defined levels VILX and VIHX. Low time t2 SR 15 - ns 2)3) Rise time t3 SR - 10 ns 2)3) Fall time t4 SR - 10 ns 2)3) t3 t4 tOSC

0.5 VDDC

Data Sheet 111 V1.0, 2010-03

4.3.7 JTAG Timing

Table 45 provides the characteristics of the JTAG timing in the XC858. Figure 42 TCK Clock Timing Table 45 TCK Clock Timing (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits Unit Test Conditions min max TCK clock period tTCK SR 50 - ns 1) 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. TCK high time t1 SR 20 - ns 1) TCK low time t2 SR 20 - ns 1) TCK clock rise time t3 SR - 4 ns 1) TCK clock fall time t4 SR - 4 ns 1) Table 46 JTAG Timing (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits Unit Test Conditions min max TMS setup to TCK t1 SR 8 - ns 1) TMS hold to TCK t2 SR 0 - ns 1) TDI setup to TCK t1 SR 8 - ns 1) TDI hold to TCK t2 SR 4 - ns 1) TDO valid output from TCK t3 CC - 24 ns 1) TCK

0.9 VDDP

0.1 VDDP

0.5 VDDP

Data Sheet 112 V1.0, 2010-03 Figure 43 JTAG Timing TDO high impedance to valid output from TCK t4 CC - 18 ns 1) TDO valid output to high impedance from TCK t5 CC - 21 ns 1) 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. Table 46 JTAG Timing (Operating Conditions apply; CL = 50 pF) (cont’d) Parameter Symbol Limits Unit Test Conditions min max TMS TDI TCK TDO t4 t3 t5

Data Sheet 113 V1.0, 2010-03

4.3.8 SSC Master Mode Timing

Table 47 provides the characteristics of the SSC timing in the XC858. Figure 44 SSC Master Mode Timing Table 47 SSC Master Mode Timing (Ope rating Conditions apply; CL = 50 pF) Parameter Symbol Limit Values Unit Test Conditions min. max. SCLK clock period t0 CC 2*T SSC –n s 1)2) 1) T SSCmin =T CPU =1 / fCPU. When fCPU = 24 MHz, t0 = 83.3ns. TCPU is the CPU clock period. 2) 1Not all parameters are 100% tested, but are veri fied by design/characterization and test correlation. MTSR delay from SCLK t1 CC 0 5 ns 2) MRST setup to SCLK t2 SR 13 – ns 2) MRST hold from SCLK t3 SR 0 – ns 2) SSC_Tmg1 SCLK1) MTSR1) t1 t1 MRST1) Data valid 1) This timing is based on the following setup: CON.PH = CON.PO = 0.

Package and Quality Declaration Data Sheet 114 V1.0, 2010-03

5 Package and Quality Declaration

Chapter 5 provides the information of the XC858 package and reliability section.

5.1 Package Parameters

Table 48 provides the thermal ch aracteristics of the PG -LQFP-64-4 package used in XC858. Table 48 Thermal Characteristics of the Packages Parameter Symbol Limit Values Unit Notes Min. Max. Thermal resistance junction case1) 1) The thermal resistances between the case and the ambient ( RTCA) , the lead and the ambient (RTLA) are to be combined with the thermal resistances between the junction and the case ( RTJC), the junction and the lead (RTJL) given above, in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient ( RTCA), the lead and the ambient ( RTLA) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ=TA+RTJA ×PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances, by a) simply adding only the two thermal resistances (junction lead and lead ambient), or b) by taking all four resistances into account, depending on the precision needed. RTJC CC - 13.8 K/W - Thermal resistance junction lead1) RTJL CC - 34.6 K/W -

Package and Quality Declaration Data Sheet 115 V1.0, 2010-03

5.2 Package Outline

Figure 45 shows the package outlines of the XC858. Figure 45 PG-LQFP-64 -4 Package Outline

Package and Quality Declaration Data Sheet 116 V1.0, 2010-03

5.3 Quality Declaration

Table 49 shows the characteristics of the quality parameters in the XC858. Table 49 Quality Parameters Parameter Symbol Limit Values Unit Notes Min. Max. ESD susceptibility according to Human Body Model (HBM) VHBM - 2000 V Conforming to EIA/JESD22- A114-B ESD susceptibility according to Charged Device Model (CDM) pins VCDM - 500 V Conforming to JESD22-C101-C

www.infineon.com Published by Infineon Technologies AG