XC2263N

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V1.6 2014-06 Microcontrollers 16/32-Bit Architecture XC2261N/68N, XC2263N/64N/65N 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Value Line

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© 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

V1.6 2014-06 Microcontrollers 16/32-Bit Architecture XC2261N/68N, XC2263N/64N/65N 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Value Line

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Data Sheet 4 V1.6, 2014-06 Trademarks C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG. XC226xN Data Sheet Revision History: V1.6 2014-06 Previous Versions: V1.5, 2013-02 V1.4, 2011-07 V1.3, 2010-04 V1.2, 2009-12 V1.1, 2009-07 V1.0, 2009-03 Preliminary Page Subjects (major changes since last revision)

9 Added XC2268N-40FxLR to Basic Device Types

10 Moved XC2263N-24FxL, XC2263N-40FxL, XC2265N-40FxL and

XC2268N-40FxL from Basic to Special Device Types

126 Added package type PG-LQFP-100-15

We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Table of Contents Data Sheet 5 V1.6, 2014-06 Table of Contents

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Table of Contents Data Sheet 6 V1.6, 2014-06

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Summary of Features Data Sheet 7 V1.6, 2014-06 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC226xN (XC2000 Family)

1 Summary of Features

For a quick overview and easy reference, the features of the XC226xN are summarized here.

• High-performance CPU with five-stage pipeline and MPU – 12.5 ns instruction cycle @ 80 MHz CPU clock (single-cycle execution) – One-cycle 32-bit addition and subtraction with 40-bit result – One-cycle multiplication (16 × 16 bit) – Background division (3 2 / 16 bit) in 21 cycles – One-cycle multiply-and-accumulate (MAC) instructions – Enhanced Boolean bit manipulation facilities – Zero-cycle jump execution – Additional instructions to support HLL and operating systems – Register-based design with mult iple variable register banks – Fast context switching support with two additional local register banks – 16 Mbytes total linear address space for code and data – 1,024 Bytes on-chip special function re gister area (C166 Family compatible) – Integrated Memory Protection Unit (MPU)
• Interrupt system with 16 priority levels providing 96 interrupt nodes – Selectable external inputs for interrupt generation and wake-up – Fastest sample-rate 12.5 ns
• Eight-channel in terrupt-driven single-cycle data transfer with Peripheral Event Controller (PEC), 24-bit pointers cover total address space
• Clock generation from internal or external clock sources, using on-chip PLL or prescaler
• Hardware CRC-Checker with Programmabl e Polynomial to Supervise On-Chip Memory Areas
• On-chip memory modules – 8 Kbytes on-chip stand-by RAM (SBRAM) – 2 Kbytes on-chip dual-port RAM (DPRAM) – Up to 16 Kbytes on-chip data SRAM (DSRAM) – Up to 16 Kbytes on-chip program/data SRAM (PSRAM) – Up to 320 Kbytes on-chip pr ogram memory (Flash memory) – Memory content protection through Error Correction Code (ECC)

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Summary of Features Data Sheet 8 V1.6, 2014-06

• On-Chip Peripheral Modules – Two synchronizable A/D Converters with up to 16 channels, 10-bit resolution, conversion time below 1 μs, optional data preprocessing (data reduction, range check), broken wire detection – 16-channel general purpose capture/compare unit (CC2) – Two capture/compare units for flexible PWM signal generation (CCU6x) – Multi-functional general purpose timer unit with 5 timers – Up to 6 serial interface channels to be used as UART, LIN, high-speed synchronous channel (SPI/QSPI), IIC bus interface (10-bit addressing, 400 kbit/s), IIS interface – On-chip MultiCAN interface (Rev. 2.0B active) with up to 256 message objects (Full CAN/Basic CAN) on up to 6 CAN nodes and gateway functionality – On-chip system timer and on-chip real time clock
• Up to 12 Mbytes external address space for code and data – Programmable external bus characte ristics for different address ranges – Multiplexed or demultiplexed external address/data buses – Selectable address bus width – 16-bit or 8-bit data bus width – Four programmable chip-select signals
• Single power supply from 3.0 V to 5.5 V
• Power reduction and wake-up modes with flexible power management
• Programmable watchdog timer and oscillator watchdog
• Up to 76 general purpose I/O lines
• On-chip bootstrap loaders
• Supported by a full range of development tools including C compilers, macro- assembler packages, emulators, evalua tion boards, HLL debuggers, simulators, logic analyzer disassemblers, programming boards
• On-chip debug support via Device Acce ss Port (DAP) or JTAG interface
• 100-pin Green LQFP package, 0.5 mm (19.7 mil) pitch

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Summary of Features Data Sheet 9 V1.6, 2014-06

Ordering Information

The ordering code for an Infineon microcontroller provides an exact reference to a specific product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the temperature range: – SAF-…: -40°C to 85°C – SAH-…: -40°C to 110°C – SAK-…: -40°C to 125°C
• the package and the type of delivery. For ordering codes for the XC226xN please contact your sales representative or local distributor. This document describes several derivatives of the XC226xN group: Basic Device Types are readily available and Special Device Types are only available on request. As this document refers to all of these derivatives, some descriptions may not apply to a specific product, in particular to the special device types. For simplicity the term XC226xN is used for all derivatives throughout this document.

1.1 Basic Device Types

Basic device types are available and can be ordered through Infineon’s direct and/or distribution channels. Table 1 Synopsis of XC226xN Basic Device Types Derivative1) 1) x is a placeholder for available speed grade in MHz. Flash Memory2) 2) Specific information about the on-chip Flash memory in Table 3. PSRAM DSRAM 3) All derivatives additionally provide 8 Kbytes SBRAM and 2 Kbytes DPRAM. Capt./Comp . Modules ADC Chan. 4) Specific information about the available channels in Table 5. Analog input channels are listed for each Analog/Digital Converter module separately (ADC0 + ADC1). Interfaces4) XC2268N-40FxLR 320 Kbytes 16 Kbytes

16 Kbytes

11 + 5 6 CAN Nodes, 6 Serial Chan.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Summary of Features Data Sheet 10 V1.6, 2014-06

1.2 Special Device Types

Special device types are only available for high-volume applications on request. Table 2 Synopsis of XC226xN Special Device Types Derivative1) 1) x is a placeholder for available speed grade in MHz. Flash Memory2) 2) Specific information about the on-chip Flash memory in Table 3. PSRAM DSRAM 3) All derivatives additionally provide 8 Kbytes SBRAM and 2 Kbytes DPRAM. Capt./Comp. Modules ADC4) Chan. 4) Specific information about the available channels in Table 5. Analog input channels are listed for each Analog/Digital Converter module separately (ADC0 + ADC1). Interfaces4) XC2261N-24FxL 192 Kbytes 4 Kbytes

4 Kbytes

11 + 0 1 CAN Node, 2 Serial Chan. XC2263N-16FxL 128 Kbytes 4 Kbytes 11 + 5 1 CAN Node, 4 Serial Chan. XC2263N-24FxL 192 Kbytes 8 Kbytes

8 Kbytes

11 + 5 1 CAN Node, 4 Serial Chan. XC2263N-40FxL 320 Kbytes 8 Kbytes 11 + 5 1 CAN Node, 4 Serial Chan. XC2264N-16FxL 128 Kbytes 4 Kbytes 8 + 0 2 CAN Node, 4 Serial Chan. XC2264N-24FxL 192 Kbytes 8 Kbytes 8 + 0 2 CAN Node, 4 Serial Chan. XC2264N-40FxL 320 Kbytes 16 Kbytes 8 + 0 2 CAN Node, 4 Serial Chan. XC2265N-16FxL 128 Kbytes 4 Kbytes 11 + 5 3 CAN Node, 6 Serial Chan. XC2265N-24FxL 192 Kbytes 8 Kbytes 11 + 5 3 CAN Node, 6 Serial Chan. XC2265N-40FxL 320 Kbytes 8 Kbytes 11 + 5 3 CAN Node, 6 Serial Chan. XC2268N-40FxL 320 Kbytes 16 Kbytes 11 + 5 6 CAN Nodes, 6 Serial Chan.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Summary of Features Data Sheet 11 V1.6, 2014-06

1.3 Definition of Feature Variants

The XC226xN types are offered with several Flash memory sizes. Table 3 and Table 4 describe the location of the available Flash memory. The XC226xN types are offered wit h different interface options. Table 5 lists the available channels for each option. Table 3 Continuous Flash Memory Ranges Total Flash Size 1st Range 1) 1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH). 2nd Range 3rd Range

320 Kbytes C0’0000 H …

C0’EFFFH C1’0000H … C4’FFFFH n.a.

192 Kbytes C0’0000 H …

C0’EFFFH C1’0000H … C1’FFFFH C4’0000H … C4’FFFFH

128 Kbytes C0’0000H …

C0’EFFFH C4’0000H … C4’FFFFH n.a. Table 4 Flash Memory Module Allocation (in Kbytes) Total Flash Size Flash 0 1) The uppermost 4-Kbyte sector of the first Flas h segment is reserved for internal use (C0’F000H to C0’FFFFH). Flash 1 320 256 64 192 128 64 128 64 64 Table 5 Interface Channel Association Total Number Available Channels / Message Objects

11 ADC0 channels CH0, CH2 … CH5, CH8 … CH11, CH13, CH15

8 ADC0 channels CH0, CH2 … CH4, CH8, CH10, CH13, CH15

5 ADC1 channels CH0, CH2, CH4 … CH6

1 CAN node CAN0

2 CAN nodes CAN0, CAN1

3 CAN nodes CAN0, CAN1, CAN2

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Summary of Features Data Sheet 12 V1.6, 2014-06 The XC226xN types are offered with several SRAM memory sizes. Figure 1 shows the allocation rules for PSRAM and DSRAM. Note that the rules differ:

• PSRAM allocation starts from the lower address
• DSRAM allocation starts from the higher address For example 8 Kbytes of PSRAM will be allocated at E0’0000h-E0’1FFFh and 8 Kbytes of DSRAM will be at 00’C000h-00’DFFFh. Figure 1 SRAM Allocation

6 CAN nodes CAN0, CAN1, CAN2,CAN3, CAN4, CAN5

2 serial channels U0C0, U0C1 4 serial channels U0C0, U0C1, U1C0, U1C1 6 serial channels U0C0, U0C1, U1C0, U1C1, U2C0, U2C1 Table 5 Interface Channel Association Total Number Available Channels / Message Objects MC_XC_SRAM_ALLOCATION Available PSRAM Reserved for PSRAM E0'0000h (E8'0000h) Available DSRAM Reserved for DSRAM E7'FFFFh (EF'FFFFh) 00'8000h 00'DFFFh

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 13 V1.6, 2014-06

2 General Device Information

The XC226xN series (16/32-Bit Single-Chip Microcontroller with 32-Bit Performance) is a part of the In fineon XC2000 Family of full-feature single- chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 80 million instructions per second) with extended peripheral functionality and enhanced IO c apabilities. Optimized peripherals can be adapted flexibly to meet the application requirements. These derivatives utilize clock generation via PLL and internal or external clock sources. On-chip memory modules include program Flash, program RAM, and data RAM. Figure 2 XC226xN Logic Symbol MC_XY_LOGSYMB100 Port 0 8 bit Port 1 8 bit Port 2 14 bit Port 4 4 bit Port 6 3 bit Port 7 5 bit VAGND (1) VAREF (1) VDDP (9) VSS (4) JTAG 4 bit TRST Debug 2 bit XTAL1 XTAL2 ESR0 ESR1 Port 10 16 bit Port 15 5 bit Port 5 11 bit TESTM PORST via Port Pins VDDI 1 (3) VDDIM (1)

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 14 V1.6, 2014-06

2.1 Pin Configuration and Definition

The pins of the XC226xN are described in detail in Table 6, which includes all alternate functions. For further explanations please refer to the footnotes at the end of the table. The following figure summarizes all pins, showing their locations on the four sides of the package. Figure 3 XC226xN Pin Configuration (top view) MC_XY_PIN100 VDDPB 25 P5 .3 24 P5 .2 23 P5 .0 22 VAGN D 21 P15.5 18 VDDPA P15.0 15 P15.4 P6 .2 13 P6 .1 12 P6 .0 11 VDDIM 10 P7.3 7 P7.2 4 TESTM 3 VDDPB 2 VSS 1 P7.0 TRST VAR EF P15.6 100 VDDP B ESR 0 ESR 1 POR ST XT AL 1 XT AL 2 P1 .7 P1 .6 P1 .5 P1 0 .15 P1 .4 P1 0 .14 V DDI 1 P1 .3 P1 0 .13 P1 0 .12 P1 .2 P1 0 .11 P1 0 .10 P1 .1 P1 0 .9 P1 0 .8 P1 .0 VDDP B VSS 45P2. 4 VSS VDD PB P5. 8 P5. 9 P5 .10 P5 .11 P5 .13 P5.15 P2 .12 P2 .11 V DDI 1 P2. 0 P2. 1 P2. 2 P4. 0 P2. 3 P4. 1 P2. 5 P4. 2 P2. 6 P4. 3 VDD PB

51 VSS

P0. 0 P2. 7 P0. 1 P2. 8 P2. 9 P0. 2 P10.0 P10.1 P10.2 P0. 4 V DDI1 P2. 13 P2. 10 P10.3 P0. 5 P10.4 P10.5 P0. 6 P10.6 P10.7 P0. 7 VDDPB LQFP-100 P7.4 P7.1 P15.2 P0.3 P5. 4 P5. 5

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 15 V1.6, 2014-06 Key to Pin Definitions

• Ctrl.: The output signal for a port pin is selected by bit field PC in the associated register Px_IOCRy. Output O0 is selected by setting the respective bit field PC to 1x00B, output O1 is selected by 1x01B, etc. Output signal OH is controlled by hardware.
• Type: Indicates the pad type and its power supply domain (A, B, M, 1). – St: Standard pad – Sp: Special pad e.g. XTALx – DP: Double pad - can be used as standard or high speed pad – In: Input only pad – PS: Power supply pad Table 6 Pin Definitions and Functions Pin Symbol Ctrl. Type Function

3 TESTM

Enables factory test modes, must be held HIGH for normal operation (connect to VDDPB). An internal pull-up device will hold this pin high when nothing is driving it. 4 P7.2 O0 / I St/B Bit 2 of Port 7, General Purpose Input/Output EMUX0 O1 St/B External Analog MUX Control Output 0 (ADC1) TxDC4 O2 St/B CAN Node 4 Transmit Data Output TxDC5 O3 St/B CAN Node 5 Transmit Data Output TDI_C IH St/B JTAG Test Data Input If JTAG pos. C is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. 5T R S T II n / B Test-System Reset Input For normal system operation, pin TRST should be held low. A high level at this pin at the rising edge of PORST activates the XC226xN’s debug system. In this case, pin TRST must be driven low once to reset the debug system. An internal pull-down device will hold this pin low when nothing is driving it.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 16 V1.6, 2014-06 6 P7.0 O0 / I St/B Bit 0 of Port 7, General Purpose Input/Output T3OUT O1 St/B GPT12E Timer T3 Toggle Latch Output T6OUT O2 St/B GPT12E Timer T6 Toggle Latch Output TDO_A OH / IH St/B JTAG Test Data Output / DAP1 Input/Output If DAP pos. 0 or 2 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. ESR2_1 I St/B ESR2 Trigger Input 1 RxDC4B I St/B CAN Node 4 Receive Data Input 7 P7.3 O0 / I St/B Bit 3 of Port 7, General Purpose Input/Output EMUX1 O1 St/B External Analog MUX Control Output 1 (ADC1) U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output U0C0_DOUT O3 St/B USIC0 Channel 0 Shift Data Output TMS_C IH St/B JTAG Test Mode Selection Input If JTAG pos. C is selected during start-up, an internal pull-up device will hold this pin low when nothing is driving it. U0C1_DX0F I St/B USIC0 Channel 1 Shift Data Input 8 P7.1 O0 / I St/B Bit 1 of Port 7, General Purpose Input/Output EXTCLK O1 St/B Programmable Clock Signal Output TXDC4 O2 St/B CAN Node 4 Transmit Data Output BRKIN_C IS t / B OCDS Break Signal Input Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 17 V1.6, 2014-06 9 P7.4 O0 / I St/B Bit 4 of Port 7, General Purpose Input/Output EMUX2 O1 St/B External Analog MUX Control Output 2 (ADC1) U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output U0C1_SCLK OUT O3 St/B USIC0 Channel 1 Shift Clock Output TCK_C IH St/B DAP0/JTAG Clock Input If JTAG pos. C is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. If DAP pos. 2 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. U0C0_DX0D I St/B USIC0 Channel 0 Shift Data Input U0C1_DX1E I St/B USIC0 Channel 1 Shift Clock Input 11 P6.0 O0 / I DA/A Bit 0 of Port 6, General Purpose Input/Output EMUX0 O1 DA/A External Analog MUX Control Output 0 (ADC0) TxDC2 O2 DA/A CAN Node 2 Transmit Data Output BRKOUT O3 DA/A OCDS Break Signal Output ADCx_REQG TyG ID A / A External Request Gate Input for ADC0/1 U1C1_DX0E I DA/A USIC1 Channel 1 Shift Data Input 12 P6.1 O0 / I DA/A Bit 1 of Port 6, General Purpose Input/Output EMUX1 O1 DA/A External Analog MUX Control Output 1 (ADC0) T3OUT O2 DA/A GPT12E Timer T3 Toggle Latch Output U1C1_DOUT O3 DA/A USIC1 Channel 1 Shift Data Output ADCx_REQT RyE ID A / A External Request Trigger Input for ADC0/1 RxDC2E I DA/A CAN Node 2 Receive Data Input ESR1_6 I DA/A ESR1 Trigger Input 6 Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 18 V1.6, 2014-06 13 P6.2 O0 / I DA/A Bit 2 of Port 6, General Purpose Input/Output EMUX2 O1 DA/A External Analog MUX Control Output 2 (ADC0) T6OUT O2 DA/A GPT12E Timer T6 Toggle Latch Output U1C1_SCLK OUT O3 DA/A USIC1 Channel 1 Shift Clock Output U1C1_DX1C I DA/A USIC1 Channel 1 Shift Clock Input 15 P15.0 I In/A Bit 0 of Port 15, General Purpose Input ADC1_CH0 I In/A Analog Input Channel 0 for ADC1 16 P15.2 I In/A Bit 2 of Port 15, General Purpose Input ADC1_CH2 I In/A Analog Input Channel 2 for ADC1 T5INA I In/A GPT12E Timer T5 Count/Gate Input 17 P15.4 I In/A Bit 4 of Port 15, General Purpose Input ADC1_CH4 I In/A Analog Input Channel 4 for ADC1 T6INA I In/A GPT12E Timer T6 Count/Gate Input 18 P15.5 I In/A Bit 5 of Port 15, General Purpose Input ADC1_CH5 I In/A Analog Input Channel 5 for ADC1 T6EUDA I In/A GPT12E Timer T6 External Up/Down Control Input 19 P15.6 I In/A Bit 6 of Port 15, General Purpose Input ADC1_CH6 I In/A Analog Input Channel 6 for ADC1

20 VAREF - PS/A Reference Voltage for A/D Converters ADC0/1

21 VAGND - PS/A Reference Ground for A/D Converters ADC0/1

22 P5.0 I In/A Bit 0 of Port 5, General Purpose Input ADC0_CH0 I In/A Analog Input Channel 0 for ADC0 23 P5.2 I In/A Bit 2 of Port 5, General Purpose Input ADC0_CH2 I In/A Analog Input Channel 2 for ADC0 TDI_A I In/A JTAG Test Data Input Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 19 V1.6, 2014-06 24 P5.3 I In/A Bit 3 of Port 5, General Purpose Input ADC0_CH3 I In/A Analog Input Channel 3 for ADC0 T3INA I In/A GPT12E Timer T3 Count/Gate Input 28 P5.4 I In/A Bit 4 of Port 5, General Purpose Input ADC0_CH4 I In/A Analog Input Channel 4 for ADC0 T3EUDA I In/A GPT12E Timer T3 External Up/Down Control Input TMS_A I In/A JTAG Test Mode Selection Input 29 P5.5 I In/A Bit 5 of Port 5, General Purpose Input ADC0_CH5 I In/A Analog Input Channel 5 for ADC0 CCU60_T12 HRB II n / A External Run Control Input for T12 of CCU60 30 P5.8 I In/A Bit 8 of Port 5, General Purpose Input ADC0_CH8 I In/A Analog Input Channel 8 for ADC0 ADC1_CH8 I In/A Analog Input Channel 8 for ADC1 CCU6x_T12H RC II n / A External Run Control Input for T12 of CCU60/1 CCU6x_T13H RC II n / A External Run Control Input for T13 of CCU60/1 U2C0_DX0F I In/A USIC2 Channel 0 Shift Data Input 31 P5.9 I In/A Bit 9 of Port 5, General Purpose Input ADC0_CH9 I In/A Analog Input Channel 9 for ADC0 ADC1_CH9 I In/A Analog Input Channel 9 for ADC1 CC2_T7IN I In/A CAPCOM2 Timer T7 Count Input 32 P5.10 I In/A Bit 10 of Port 5, General Purpose Input ADC0_CH10 I In/A Analog Input Channel 10 for ADC0 ADC1_CH10 I In/A Analog Input Channel 10 for ADC1 BRKIN_A II n / A OCDS Break Signal Input U2C1_DX0F I In/A USIC2 Channel 1 Shift Data Input CCU61_T13 HRA II n / A External Run Control Input for T13 of CCU61 Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 20 V1.6, 2014-06 33 P5.11 I In/A Bit 11 of Port 5, General Purpose Input ADC0_CH11 I In/A Analog Input Channel 11 for ADC0 ADC1_CH11 I In/A Analog Input Channel 11 for ADC1 34 P5.13 I In/A Bit 13 of Port 5, General Purpose Input ADC0_CH13 I In/A Analog Input Channel 13 for ADC0 35 P5.15 I In/A Bit 15 of Port 5, General Purpose Input ADC0_CH15 I In/A Analog Input Channel 15 for ADC0 RxDC2F I In/A CAN Node 2 Receive Data Input 36 P2.12 O0 / I St/B Bit 12 of Port 2, General Purpose Input/Output U0C0_SELO O1 St/B USIC0 Channel 0 Select/Control 4 Output U0C1_SELO O2 St/B USIC0 Channel 1 Select/Control 3 Output TXDC2 O3 St/B CAN Node 2 Transmit Data Output READY IH St/B External Bus Interface READY Input 37 P2.11 O0 / I St/B Bit 11 of Port 2, General Purpose Input/Output U0C0_SELO O1 St/B USIC0 Channel 0 Select/Control 2 Output U0C1_SELO O2 St/B USIC0 Channel 1 Select/Control 2 Output BHE /WRH OH St/B External Bus Interf. High-Byte Control Output Can operate either as Byte High Enable (BHE ) or as Write strobe for High Byte (WRH). 39 P2.0 O0 / I St/B Bit 0 of Port 2, General Purpose Input/Output TxDC5 O1 St/B CAN Node 5 Transmit Data Output AD13 OH / IH St/B External Bus Interface Address/Data Line 13 RxDC0C I St/B CAN Node 0 Receive Data Input T5INB I St/B GPT12E Timer T5 Count/Gate Input Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 21 V1.6, 2014-06 40 P2.1 O0 / I St/B Bit 1 of Port 2, General Purpose Input/Output TxDC0 O1 St/B CAN Node 0 Transmit Data Output AD14 OH / IH St/B External Bus Interface Address/Data Line 14 RxDC5C I St/B CAN Node 5 Receive Data Input T5EUDB I St/B GPT12E Timer T5 External Up/Down Control Input ESR1_5 I St/B ESR1 Trigger Input 5 41 P2.2 O0 / I St/B Bit 2 of Port 2, General Purpose Input/Output TxDC1 O1 St/B CAN Node 1 Transmit Data Output AD15 OH / IH St/B External Bus Interface Address/Data Line 15 ESR2_5 I St/B ESR2 Trigger Input 5 42 P4.0 O0 / I St/B Bit 0 of Port 4, General Purpose Input/Output CC2_CC24 O3 / I St/B CAPCOM2 CC24IO Capture Inp./ Compare Out. CS0 OH St/B External Bus Interface Chip Select 0 Output 43 P2.3 O0 / I St/B Bit 3 of Port 2, General Purpose Input/Output U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output CC2_CC16 O3 / I St/B CAPCOM2 CC16IO Capture Inp./ Compare Out. A16 OH St/B External Bus Interface Address Line 16 ESR2_0 I St/B ESR2 Trigger Input 0 U0C0_DX0E I St/B USIC0 Channel 0 Shift Data Input U0C1_DX0D I St/B USIC0 Channel 1 Shift Data Input RxDC0A I St/B CAN Node 0 Receive Data Input 44 P4.1 O0 / I St/B Bit 1 of Port 4, General Purpose Input/Output TxDC2 O2 St/B CAN Node 2 Transmit Data Output CC2_CC25 O3 / I St/B CAPCOM2 CC25IO Capture Inp./ Compare Out. CS1 OH St/B External Bus Interface Chip Select 1 Output T4EUDB I St/B GPT12E Timer T4 External Up/Down Control Input ESR1_8 I St/B ESR1 Trigger Input 8 Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 22 V1.6, 2014-06 45 P2.4 O0 / I St/B Bit 4 of Port 2, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output TxDC0 O2 St/B CAN Node 0 Transmit Data Output CC2_CC17 O3 / I St/B CAPCOM2 CC17IO Capture Inp./ Compare Out. A17 OH St/B External Bus Interface Address Line 17 ESR1_0 I St/B ESR1 Trigger Input 0 U0C0_DX0F I St/B USIC0 Channel 0 Shift Data Input RxDC1A I St/B CAN Node 1 Receive Data Input 46 P2.5 O0 / I St/B Bit 5 of Port 2, General Purpose Input/Output U0C0_SCLK OUT O1 St/B USIC0 Channel 0 Shift Clock Output TxDC0 O2 St/B CAN Node 0 Transmit Data Output CC2_CC18 O3 / I St/B CAPCOM2 CC18IO Capture Inp./ Compare Out. A18 OH St/B External Bus Interface Address Line 18 U0C0_DX1D I St/B USIC0 Channel 0 Shift Clock Input ESR1_10 I St/B ESR1 Trigger Input 10 47 P4.2 O0 / I St/B Bit 2 of Port 4, General Purpose Input/Output TxDC2 O2 St/B CAN Node 2 Transmit Data Output CC2_CC26 O3 / I St/B CAPCOM2 CC26IO Capture Inp./ Compare Out. CS2 OH St/B External Bus Interface Chip Select 2 Output T2INA I St/B GPT12E Timer T2 Count/Gate Input 48 P2.6 O0 / I St/B Bit 6 of Port 2, General Purpose Input/Output U0C0_SELO O1 St/B USIC0 Channel 0 Select/Control 0 Output U0C1_SELO O2 St/B USIC0 Channel 1 Select/Control 1 Output CC2_CC19 O3 / I St/B CAPCOM2 CC19IO Capture Inp./ Compare Out. A19 OH St/B External Bus Interface Address Line 19 U0C0_DX2D I St/B USIC0 Channel 0 Shift Control Input RxDC0D I St/B CAN Node 0 Receive Data Input ESR2_6 I St/B ESR2 Trigger Input 6 Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 23 V1.6, 2014-06 49 P4.3 O0 / I St/B Bit 3 of Port 4, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output CC2_CC27 O3 / I St/B CAPCOM2 CC27IO Capture Inp./ Compare Out. CS3 OH St/B External Bus Interface Chip Select 3 Output RxDC2A I St/B CAN Node 2 Receive Data Input T2EUDA I St/B GPT12E Timer T2 External Up/Down Control Input 53 P0.0 O0 / I St/B Bit 0 of Port 0, General Purpose Input/Output U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output CCU61_CC6 O3 St/B CCU61 Channel 0 IOutput A0 OH St/B External Bus Interface Address Line 0 U1C0_DX0A I St/B USIC1 Channel 0 Shift Data Input CCU61_CC6 0INA IS t / B CCU61 Channel 0 Input ESR1_11 I St/B ESR1 Trigger Input 11 54 P2.7 O0 / I St/B Bit 7 of Port 2, General Purpose Input/Output U0C1_SELO O1 St/B USIC0 Channel 1 Select/Control 0 Output U0C0_SELO O2 St/B USIC0 Channel 0 Select/Control 1 Output CC2_CC20 O3 / I St/B CAPCOM2 CC20IO Capture Inp./ Compare Out. A20 OH St/B External Bus Interface Address Line 20 U0C1_DX2C I St/B USIC0 Channel 1 Shift Control Input RxDC1C I St/B CAN Node 1 Receive Data Input ESR2_7 I St/B ESR2 Trigger Input 7 Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 24 V1.6, 2014-06 55 P0.1 O0 / I St/B Bit 1 of Port 0, General Purpose Input/Output U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output TxDC0 O2 St/B CAN Node 0 Transmit Data Output CCU61_CC6 O3 St/B CCU61 Channel 1 Output A1 OH St/B External Bus Interface Address Line 1 U1C0_DX0B I St/B USIC1 Channel 0 Shift Data Input CCU61_CC6 1INA IS t / B CCU61 Channel 1 Input U1C0_DX1A I St/B USIC1 Channel 0 Shift Clock Input 56 P2.8 O0 / I DP/B Bit 8 of Port 2, General Purpose Input/Output U0C1_SCLK OUT O1 DP/B USIC0 Channel 1 Shift Clock Output EXTCLK O2 DP/B Programmable Clock Signal Output CC2_CC21 O3 / I DP/B CAPCOM2 CC21IO Capture Inp./ Compare Out. A21 OH DP/B External Bus Interface Address Line 21 U0C1_DX1D I DP/B USIC0 Channel 1 Shift Clock Input 57 P2.9 O0 / I St/B Bit 9 of Port 2, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output TxDC1 O2 St/B CAN Node 1 Transmit Data Output CC2_CC22 O3 / I St/B CAPCOM2 CC22IO Capture Inp./ Compare Out. A22 OH St/B External Bus Interface Address Line 22 CLKIN1 I St/B Clock Signal Input 1 TCK_A IH St/B DAP0/JTAG Clock Input If JTAG pos. A is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. If DAP pos. 0 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 25 V1.6, 2014-06 58 P0.2 O0 / I St/B Bit 2 of Port 0, General Purpose Input/Output U1C0_SCLK OUT O1 St/B USIC1 Channel 0 Shift Clock Output TxDC0 O2 St/B CAN Node 0 Transmit Data Output CCU61_CC6 O3 St/B CCU61 Channel 2 Output A2 OH St/B External Bus Interface Address Line 2 U1C0_DX1B I St/B USIC1 Channel 0 Shift Clock Input CCU61_CC6 2INA IS t / B CCU61 Channel 2 Input 59 P10.0 O0 / I St/B Bit 0 of Port 10, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output CCU60_CC6 O2 St/B CCU60 Channel 0 Output AD0 OH / IH St/B External Bus Interface Address/Data Line 0 CCU60_CC6 0INA IS t / B CCU60 Channel 0 Input ESR1_2 I St/B ESR1 Trigger Input 2 U0C0_DX0A I St/B USIC0 Channel 0 Shift Data Input U0C1_DX0A I St/B USIC0 Channel 1 Shift Data Input 60 P10.1 O0 / I St/B Bit 1 of Port 10, General Purpose Input/Output U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output CCU60_CC6 O2 St/B CCU60 Channel 1 Output AD1 OH / IH St/B External Bus Interface Address/Data Line 1 CCU60_CC6 1INA IS t / B CCU60 Channel 1 Input U0C0_DX1A I St/B USIC0 Channel 0 Shift Clock Input U0C0_DX0B I St/B USIC0 Channel 0 Shift Data Input Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 26 V1.6, 2014-06 61 P0.3 O0 / I St/B Bit 3 of Port 0, General Purpose Input/Output U1C0_SELO O1 St/B USIC1 Channel 0 Select/Control 0 Output U1C1_SELO O2 St/B USIC1 Channel 1 Select/Control 1 Output CCU61_COU T60 O3 St/B CCU61 Channel 0 Output A3 OH St/B External Bus Interface Address Line 3 U1C0_DX2A I St/B USIC1 Channel 0 Shift Control Input RxDC0B I St/B CAN Node 0 Receive Data Input 62 P10.2 O0 / I St/B Bit 2 of Port 10, General Purpose Input/Output U0C0_SCLK OUT O1 St/B USIC0 Channel 0 Shift Clock Output CCU60_CC6 O2 St/B CCU60 Channel 2 Output AD2 OH / IH St/B External Bus Interface Address/Data Line 2 CCU60_CC6 2INA IS t / B CCU60 Channel 2 Input U0C0_DX1B I St/B USIC0 Channel 0 Shift Clock Input 63 P0.4 O0 / I St/B Bit 4 of Port 0, General Purpose Input/Output U1C1_SELO O1 St/B USIC1 Channel 1 Select/Control 0 Output U1C0_SELO O2 St/B USIC1 Channel 0 Select/Control 1 Output CCU61_COU T61 O3 St/B CCU61 Channel 1 Output A4 OH St/B External Bus Interface Address Line 4 U1C1_DX2A I St/B USIC1 Channel 1 Shift Control Input RxDC1B I St/B CAN Node 1 Receive Data Input ESR2_8 I St/B ESR2 Trigger Input 8 Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 27 V1.6, 2014-06 65 P2.13 O0 / I St/B Bit 13 of Port 2, General Purpose Input/Output U2C1_SELO O1 St/B USIC2 Channel 1 Select/Control 2 Output RxDC2D I St/B CAN Node 2 Receive Data Input 66 P2.10 O0 / I St/B Bit 10 of Port 2, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output U0C0_SELO O2 St/B USIC0 Channel 0 Select/Control 3 Output CC2_CC23 O3 / I St/B CAPCOM2 CC23IO Capture Inp./ Compare Out. A23 OH St/B External Bus Interface Address Line 23 U0C1_DX0E I St/B USIC0 Channel 1 Shift Data Input CAPINA I St/B GPT12E Register CAPREL Capture Input 67 P10.3 O0 / I St/B Bit 3 of Port 10, General Purpose Input/Output CCU60_COU T60 O2 St/B CCU60 Channel 0 Output AD3 OH / IH St/B External Bus Interface Address/Data Line 3 U0C0_DX2A I St/B USIC0 Channel 0 Shift Control Input U0C1_DX2A I St/B USIC0 Channel 1 Shift Control Input 68 P0.5 O0 / I St/B Bit 5 of Port 0, General Purpose Input/Output U1C1_SCLK OUT O1 St/B USIC1 Channel 1 Shift Clock Output U1C0_SELO O2 St/B USIC1 Channel 0 Select/Control 2 Output CCU61_COU T62 O3 St/B CCU61 Channel 2 Output A5 OH St/B External Bus Interface Address Line 5 U1C1_DX1A I St/B USIC1 Channel 1 Shift Clock Input U1C0_DX1C I St/B USIC1 Channel 0 Shift Clock Input RXDC3E I St/B CAN Node 3 Receive Data Input Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 28 V1.6, 2014-06 69 P10.4 O0 / I St/B Bit 4 of Port 10, General Purpose Input/Output U0C0_SELO O1 St/B USIC0 Channel 0 Select/Control 3 Output CCU60_COU T61 O2 St/B CCU60 Channel 1 Output AD4 OH / IH St/B External Bus Interface Address/Data Line 4 U0C0_DX2B I St/B USIC0 Channel 0 Shift Control Input U0C1_DX2B I St/B USIC0 Channel 1 Shift Control Input ESR1_9 I St/B ESR1 Trigger Input 9 70 P10.5 O0 / I St/B Bit 5 of Port 10, General Purpose Input/Output U0C1_SCLK OUT O1 St/B USIC0 Channel 1 Shift Clock Output CCU60_COU T62 O2 St/B CCU60 Channel 2 Output U2C0_DOUT O3 St/B USIC2 Channel 0 Shift Data Output AD5 OH / IH St/B External Bus Interface Address/Data Line 5 U0C1_DX1B I St/B USIC0 Channel 1 Shift Clock Input 71 P0.6 O0 / I St/B Bit 6 of Port 0, General Purpose Input/Output U1C1_DOUT O1 St/B USIC1 Channel 1 Shift Data Output TxDC1 O2 St/B CAN Node 1 Transmit Data Output CCU61_COU T63 O3 St/B CCU61 Channel 3 Output A6 OH St/B External Bus Interface Address Line 6 U1C1_DX0A I St/B USIC1 Channel 1 Shift Data Input CCU61_CTR APA IS t / B CCU61 Emergency Trap Input U1C1_DX1B I St/B USIC1 Channel 1 Shift Clock Input Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 29 V1.6, 2014-06 72 P10.6 O0 / I St/B Bit 6 of Port 10, General Purpose Input/Output U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output TxDC4 O2 St/B CAN Node 4 Transmit Data Output U1C0_SELO O3 St/B USIC1 Channel 0 Select/Control 0 Output AD6 OH / IH St/B External Bus Interface Address/Data Line 6 U0C0_DX0C I St/B USIC0 Channel 0 Shift Data Input U1C0_DX2D I St/B USIC1 Channel 0 Shift Control Input CCU60_CTR APA IS t / B CCU60 Emergency Trap Input 73 P10.7 O0 / I St/B Bit 7 of Port 10, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output CCU60_COU T63 O2 St/B CCU60 Channel 3 Output AD7 OH / IH St/B External Bus Interface Address/Data Line 7 U0C1_DX0B I St/B USIC0 Channel 1 Shift Data Input CCU60_CCP OS0A IS t / B CCU60 Position Input 0 RxDC4C I St/B CAN Node 4 Receive Data Input T4INB I St/B GPT12E Timer T4 Count/Gate Input 74 P0.7 O0 / I St/B Bit 7 of Port 0, General Purpose Input/Output U1C1_DOUT O1 St/B USIC1 Channel 1 Shift Data Output U1C0_SELO O2 St/B USIC1 Channel 0 Select/Control 3 Output TxDC3 O3 St/B CAN Node 3 Transmit Data Output A7 OH St/B External Bus Interface Address Line 7 U1C1_DX0B I St/B USIC1 Channel 1 Shift Data Input CCU61_CTR APB IS t / B CCU61 Emergency Trap Input Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 30 V1.6, 2014-06 78 P1.0 O0 / I St/B Bit 0 of Port 1, General Purpose Input/Output U1C0_MCLK OUT O1 St/B USIC1 Channel 0 Master Clock Output U1C0_SELO O2 St/B USIC1 Channel 0 Select/Control 4 Output A8 OH St/B External Bus Interface Address Line 8 ESR1_3 I St/B ESR1 Trigger Input 3 T6INB I St/B GPT12E Timer T6 Count/Gate Input 79 P10.8 O0 / I St/B Bit 8 of Port 10, General Purpose Input/Output U0C0_MCLK OUT O1 St/B USIC0 Channel 0 Master Clock Output U0C1_SELO O2 St/B USIC0 Channel 1 Select/Control 0 Output U2C1_DOUT O3 St/B USIC2 Channel 1 Shift Data Output AD8 OH / IH St/B External Bus Interface Address/Data Line 8 CCU60_CCP OS1A IS t / B CCU60 Position Input 1 U0C0_DX1C I St/B USIC0 Channel 0 Shift Clock Input BRKIN_B IS t / B OCDS Break Signal Input T3EUDB I St/B GPT12E Timer T3 External Up/Down Control Input Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 31 V1.6, 2014-06 80 P10.9 O0 / I St/B Bit 9 of Port 10, General Purpose Input/Output U0C0_SELO O1 St/B USIC0 Channel 0 Select/Control 4 Output U0C1_MCLK OUT O2 St/B USIC0 Channel 1 Master Clock Output AD9 OH / IH St/B External Bus Interface Address/Data Line 9 CCU60_CCP OS2A IS t / B CCU60 Position Input 2 TCK_B IH St/B DAP0/JTAG Clock Input If JTAG pos. B is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. If DAP pos. 1 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. T3INB I St/B GPT12E Timer T3 Count/Gate Input 81 P1.1 O0 / I St/B Bit 1 of Port 1, General Purpose Input/Output U1C0_SELO O2 St/B USIC1 Channel 0 Select/Control 5 Output U2C1_DOUT O3 St/B USIC2 Channel 1 Shift Data Output A9 OH St/B External Bus Interface Address Line 9 ESR2_3 I St/B ESR2 Trigger Input 3 U2C1_DX0C I St/B USIC2 Channel 1 Shift Data Input Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 32 V1.6, 2014-06 82 P10.10 O0 / I St/B Bit 10 of Port 10, General Purpose Input/Output U0C0_SELO O1 St/B USIC0 Channel 0 Select/Control 0 Output CCU60_COU T63 O2 St/B CCU60 Channel 3 Output AD10 OH / IH St/B External Bus Interface Address/Data Line 10 U0C0_DX2C I St/B USIC0 Channel 0 Shift Control Input U0C1_DX1A I St/B USIC0 Channel 1 Shift Clock Input TDI_B IH St/B JTAG Test Data Input If JTAG pos. B is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. 83 P10.11 O0 / I St/B Bit 11 of Port 10, General Purpose Input/Output U1C0_SCLK OUT O1 St/B USIC1 Channel 0 Shift Clock Output BRKOUT O2 St/B OCDS Break Signal Output AD11 OH / IH St/B External Bus Interface Address/Data Line 11 U1C0_DX1D I St/B USIC1 Channel 0 Shift Clock Input RxDC2B I St/B CAN Node 2 Receive Data Input TMS_B IH St/B JTAG Test Mode Selection Input If JTAG pos. B is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 33 V1.6, 2014-06 84 P1.2 O0 / I St/B Bit 2 of Port 1, General Purpose Input/Output U1C0_SELO O2 St/B USIC1 Channel 0 Select/Control 6 Output U2C1_SCLK OUT O3 St/B USIC2 Channel 1 Shift Clock Output A10 OH St/B External Bus Interface Address Line 10 ESR1_4 I St/B ESR1 Trigger Input 4 CCU61_T12 HRB IS t / B External Run Control Input for T12 of CCU61 U2C1_DX0D I St/B USIC2 Channel 1 Shift Data Input U2C1_DX1C I St/B USIC2 Channel 1 Shift Clock Input 85 P10.12 O0 / I St/B Bit 12 of Port 10, General Purpose Input/Output U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output TxDC2 O2 St/B CAN Node 2 Transmit Data Output TDO_B OH / IH St/B JTAG Test Data Output / DAP1 Input/Output If DAP pos. 1 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. AD12 OH / IH St/B External Bus Interface Address/Data Line 12 U1C0_DX0C I St/B USIC1 Channel 0 Shift Data Input U1C0_DX1E I St/B USIC1 Channel 0 Shift Clock Input 86 P10.13 O0 / I St/B Bit 13 of Port 10, General Purpose Input/Output U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output TxDC3 O2 St/B CAN Node 3 Transmit Data Output U1C0_SELO O3 St/B USIC1 Channel 0 Select/Control 3 Output WR /WRL OH St/B External Bus Interface Write Strobe Output Active for each external write access, when WR active for ext. writes to the low byte, when WRL. U1C0_DX0D I St/B USIC1 Channel 0 Shift Data Input Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 34 V1.6, 2014-06 87 P1.3 O0 / I St/B Bit 3 of Port 1, General Purpose Input/Output U1C0_SELO O2 St/B USIC1 Channel 0 Select/Control 7 Output U2C0_SELO O3 St/B USIC2 Channel 0 Select/Control 4 Output A11 OH St/B External Bus Interface Address Line 11 ESR2_4 I St/B ESR2 Trigger Input 4 89 P10.14 O0 / I St/B Bit 14 of Port 10, General Purpose Input/Output U1C0_SELO O1 St/B USIC1 Channel 0 Select/Control 1 Output U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output RD OH St/B External Bus Interface Read Strobe Output ESR2_2 I St/B ESR2 Trigger Input 2 U0C1_DX0C I St/B USIC0 Channel 1 Shift Data Input RxDC3C I St/B CAN Node 3 Receive Data Input 90 P1.4 O0 / I St/B Bit 4 of Port 1, General Purpose Input/Output U1C1_SELO O2 St/B USIC1 Channel 1 Select/Control 4 Output U2C0_SELO O3 St/B USIC2 Channel 0 Select/Control 5 Output A12 OH St/B External Bus Interface Address Line 12 U2C0_DX2B I St/B USIC2 Channel 0 Shift Control Input RxDC5A I St/B CAN Node 5 Receive Data Input 91 P10.15 O0 / I St/B Bit 15 of Port 10, General Purpose Input/Output U1C0_SELO O1 St/B USIC1 Channel 0 Select/Control 2 Output U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output U1C0_DOUT O3 St/B USIC1 Channel 0 Shift Data Output ALE OH St/B External Bus Interf. Addr. Latch Enable Output U0C1_DX1C I St/B USIC0 Channel 1 Shift Clock Input Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 35 V1.6, 2014-06 92 P1.5 O0 / I St/B Bit 5 of Port 1, General Purpose Input/Output U1C1_SELO O2 St/B USIC1 Channel 1 Select/Control 3 Output BRKOUT O3 St/B OCDS Break Signal Output A13 OH St/B External Bus Interface Address Line 13 U2C0_DX0C I St/B USIC2 Channel 0 Shift Data Input 93 P1.6 O0 / I St/B Bit 6 of Port 1, General Purpose Input/Output U1C1_SELO O2 St/B USIC1 Channel 1 Select/Control 2 Output U2C0_DOUT O3 St/B USIC2 Channel 0 Shift Data Output A14 OH St/B External Bus Interface Address Line 14 U2C0_DX0D I St/B USIC2 Channel 0 Shift Data Input 94 P1.7 O0 / I St/B Bit 7 of Port 1, General Purpose Input/Output U1C1_MCLK OUT O2 St/B USIC1 Channel 1 Master Clock Output U2C0_SCLK OUT O3 St/B USIC2 Channel 0 Shift Clock Output A15 OH St/B External Bus Interface Address Line 15 U2C0_DX1C I St/B USIC2 Channel 0 Shift Clock Input RxDC4E I St/B CAN Node 4 Receive Data Input

95 XTAL2 O Sp/M Crystal Oscillator Amplifier Output

96 XTAL1 I Sp/M Crystal Oscillator Amplifier Input

To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Voltages on XTAL1 must comply to the core supply voltage VDDIM. ESR2_9 I St/B ESR2 Trigger Input 9 Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 36 V1.6, 2014-06

97 PORST II n / B Power On Reset Input

A low level at this pin resets the XC226xN completely. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 120 ns. An internal pull-up device will hold this pin high when nothing is driving it.

98 ESR1

O0 / I St/B External Service Request 1 After power-up, an internal weak pull-up device holds this pin high when nothing is driving it. RxDC0E I St/B CAN Node 0 Receive Data Input U1C0_DX0F I St/B USIC1 Channel 0 Shift Data Input U1C0_DX2C I St/B USIC1 Channel 0 Shift Control Input U1C1_DX0C I St/B USIC1 Channel 1 Shift Data Input U1C1_DX2B I St/B USIC1 Channel 1 Shift Control Input U2C1_DX2C I St/B USIC2 Channel 1 Shift Control Input

99 ESR0

O0 / I St/B External Service Request 0 After power-up, ESR0 operates as open-drain bidirectional reset with a weak pull-up. U1C0_DX0E I St/B USIC1 Channel 0 Shift Data Input U1C0_DX2B I St/B USIC1 Channel 0 Shift Control Input

10 VDDIM - PS/M Digital Core Supply Voltage for Domain M

Decouple with a ceramic capacitor, see Data Sheet for details. 38, 64, VDDI1 - PS/1 Digital Core Supply Voltage for Domain 1 Decouple with a ceramic capacitor, see Data Sheet for details. All VDDI1 pins must be connected to each other.

14 VDDPA - PS/A Digital Pad Supply Voltage for Domain A

Connect decoupling capacitors to adjacent VDDP/VSS pin pairs as close as possible to the pins. Note: The A/D_Converters and ports P5, P6 and P15 are fed from supply voltage VDDPA. Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 37 V1.6, 2014-06 25, 27, 50, 52, 75, 77, 100 VDDPB - PS/B Digital Pad Supply Voltage for Domain B Connect decoupling capacitors to adjacent VDDP/VSS pin pairs as close as possible to the pins. Note: The on-chip voltage regulators and all ports except P5, P6 and P15 are fed from supply voltage VDDPB. 26, 51, VSS - PS/-- Digital Ground All VSS pins must be connected to the ground-line or ground-plane. Note: Also the exposed pad is connected internally to VSS. To improve the EMC behavior, it is recommended to connect the exposed pad to the board ground. For thermal aspects, please refer to the Data Sheet. Board layout examples are given in an application note. 1) To generate the reference clock output for bus timing measurement, fSYS must be selected as source for EXTCLK and P2.8 must be selected as output pin. Also the high-speed clock pad must be enabled. This configuration is referred to as reference clock output signal CLKOUT. Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line General Device Information Data Sheet 38 V1.6, 2014-06

2.2 Identification Registers

The identification regi sters describe the current versio n of the XC226xN and of its modules. Table 7 XC226xN Identification Registers Short Name Value Address Notes SCU_IDMANUF 1820 H 00’F07EH SCU_IDCHIP 3001 H 00’F07CH marking EES-AA or ES-AA 3002H 00’F07CH marking AA, AB SCU_IDMEM 304F H 00’F07AH SCU_IDPROG 1313 H 00’F078H JTAG_ID 0018’B083H --- marking EES-AA or ES-AA 1018’B083H --- marking AA, AB

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 39 V1.6, 2014-06

3 Functional Description

The architecture of the XC226xN combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a well-balanced design. On-chip memory blocks allow the design of co mpact systems-on-silicon with maximum performance suited for computing, control, and communication. The on-chip memory blocks (program co de memory and SRAM, dual-port RAM, data SRAM) and the generic peripherals are connected to the CPU by separate high-speed buses. Another bus, the LXBus, connects additional on-chip resources and external resources. This bus structure enhances overall system performance by enabling the concurrent operation of several subsystems of the XC226xN. The block diagram gives an overview of the on-chip components and the advanced internal bus structure of the XC226xN. Figure 4 Block Diagram DPRAM CPU PMU DMU ADC0 Module 8-/10- Bit RTC MCHK Interrupt & PEC EBC LXBus Control External Bus Control DSRAM System Functions Clock, Reset, Power Control, StandBy RAM OCDS Debug Support Interrupt Bus Peripheral Data Bus Analog and Digital General Purpose IO (GPIO) Ports MC_N-SERIES_BLOCKDIAGRAM GPT Timers CC2 Module Chan. LXBus WDT Multi CAN CCU6x Modules 3+1 Chan. each USICx Modules Chan. each PSRAM Flash Memory IMB MAC Unit MPU ADC1 Module 8-/10- Bit

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 40 V1.6, 2014-06

3.1 Memory Subsystem and Organization

The memory space of the XC226xN is configured in the von Neumann architecture. In this architecture all internal and extern al resources, including code memory, data memory, registers and I/O ports, are organized in the same linear address space. Table 8 XC226xN Memory Map 1) Address Area Start Loc. End Loc. Area Size 2) Notes IMB register space FF’FF00 H FF’FFFFH 256 Bytes Reserved F0’0000 H FF’FEFFH < 1 Mbyte Minus IMB registers Reserved for EPSRAM E8’4000 H EF’FFFFH 496 Kbytes Mirrors EPSRAM Emulated PSRAM E8’0000 H E8’3FFFH up to Reserved for PSRAM E0’4000 H E7’FFFFH 496 Kbytes Mirrors PSRAM PSRAM E0’0000 H E0’3FFFH up to Reserved for Flash C5’0000 H DF’FFFFH 1,728 Kbytes Flash 1 C4’0000 H C4’FFFFH 64 Kbytes Flash 0 C0’0000 H C3’FFFFH 256 Kbytes3) Minus res. seg. External memory area 40’0000H BF’FFFFH 8 Mbytes External IO area4) 21’0000H 3F’FFFFH 1,984 Kbytes Reserved 20’BC00H 20’FFFFH 17 Kbytes USIC0–2 alternate regs. 20’B000 H 20’BBFFH 3 Kbytes Accessed via EBC MultiCAN alternate regs. 20’8000H 20’AFFFH 12 Kbytes Accessed via EBC Reserved 20’5800 H 20’7FFFH 10 Kbytes USIC0–2 registers 20’4000 H 20’57FFH 6 Kbytes Accessed via EBC Reserved 20’6800 H 20’7FFFH 6 Kbytes MultiCAN registers 20’0000 H 20’3FFFH 16 Kbytes Accessed via EBC External memory area 01’0000H 1F’FFFFH 1984 Kbytes SFR area 00’FE00H 00’FFFFH 0.5 Kbytes Dualport RAM (DPRAM) 00’F600H 00’FDFFH 2 Kbytes Reserved for DPRAM 00’F200 H 00’F5FFH 1 Kbytes ESFR area 00’F000 H 00’F1FFH 0.5 Kbytes XSFR area 00’E000 H 00’EFFFH 4 Kbytes Data SRAM (DSRAM) 00’A000 H 00’DFFFH 16 Kbytes

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 41 V1.6, 2014-06 This common memory space consists of 16 Mbytes organized as 256 segments of 64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the register spaces (ESFR/SFR) additionally are directly bit addressable. The internal data memory areas and the Special Function Register areas (SFR and ESFR) are mapped into segment 0, the system segment. The Program Management Unit (PMU) handles all code fetches and, therefore, controls access to the program memories such as Flash memory and PSRAM. The Data Management Unit (DMU) handles al l data transfers and, therefore, controls access to the DSRAM and the on-chip peripherals. Both units (PMU and DMU) are connected to the high-speed system bus so that they can exchange data. This is required if operands are read from program memory, code or data is written to the PSRAM, code is fetched from external memory, or data is read from or written to external resources. These include peripherals on the LXBus such as USIC or MultiCAN. The system bus allows concurrent two-way communication for maximum transfer performance. Up to 16 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data. The PSRAM is accessed via the PM U and is optimized for code fetches. A section of the PSRAM with programmable size can be write-protected. Note: The actual size of the PSRAM depends on the quoted device type. Reserved for DSRAM 00’8000 H 00’9FFFH 8 Kbytes External memory area 00’0000H 00’7FFFH 32 Kbytes 1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate external bus accesses. 2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”. 3) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH). 4) Several pipeline optimizations are not active within the ex ternal IO area. This is necessary to control external peripherals properly. Table 8 XC226xN Memory Map (cont’d)1) Address Area Start Loc. End Loc. Area Size 2) Notes

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 42 V1.6, 2014-06 Up to 16 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user data. The DSRAM is accessed via a separate interface and is optimized for data access. Note: The actual size of the DSRAM depends on the quoted device type.

2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined

variables, for the system stack, and for general purpose register banks. A register bank can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, …, RL7, RH7) General Purpose Registers (GPRs). The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR, any location in the DPRAM is bit addressable.

8 Kbytes of on-chip Stand-By SRAM (SBRAM) provide storage for system-relevant

user data that must be preserved while the major part of the device is powered down. The SBRAM is accessed via a specific interface and is powered in domain M. 1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are word-wide registers which are used to control and monitor functions of the different on-chip units. Unused SFR addresses are reserved for future members of the XC2000 Family. In order to ensure upward compatibility they should either not be accessed or written with zeros. In order to meet the requirements of desi gns where more memory is required than is available on chip, up to 12 Mbytes (approximately, see Table 8) of external RAM and/or ROM can be connected to the microcontroller. The External Bus Interface also provides access to external peripherals. The on-chip Flash memory stores code, constant data, and control data. The

320 Kbytes of on-chip Flash memory consist of 1 module of 64 Kbytes (preferably for

data storage) and 1 module of 256 Kbytes. Each module is organized in 4-Kbyte sectors. The uppermost 4-Kbyte sector of segment 0 (located in Flash module 0) is used internally to store operation control parameters and protection information. Note: The actual size of the Flash memory depends on the chosen device type. Each sector can be separately write protected 1), erased and programmed (in blocks of 128 Bytes). The complete Flash area can be read-protected. A user-defined password sequence temporarily unlocks protected areas. The Flash modules combine 128-bit read access with protected and efficient writing algorithms for programming and erasing. Dynamic error correction provides extremely high read data security for all read access operations. Access to different Flash modules can be executed in parallel. For Flash parameters, please see Section 4.6. 1) To save control bits, sectors are clustered for protection purposes, they remain separate for programming/erasing.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 43 V1.6, 2014-06 Memory Content Protection The contents of on-chip memories can be protected against soft errors (induced e.g. by radiation) by activating the parity mechanism or the Error Correction Code (ECC). The parity mechanism can detect a single-bit error and prevent the software from using incorrect data or executing incorrect instructions. The ECC mechanism can detect and automatically correct single-bit errors. This supports the stable operation of the system. It is strongly recommended to activate the ECC mechanism wherever possible because this dramatically increases the robustness of an application against such soft errors.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 44 V1.6, 2014-06

3.2 External Bus Controller

All external memory access operations are performed by a special on-chip External Bus Controller (EBC). The EBC also controls access to resources connected to the on-chip LXBus (MultiCAN and the USIC modules). The LXBus is an internal representation of the external bus that allows access to in tegrated peripherals and modules in the same way as to external components. The EBC can be programmed either to Single Chip Mode, when no external memory is required, or to an external bus mode with the following selections1):

• Address Bus Width with a range of 0 … 24-bit
• Data Bus Width 8-bit or 16-bit
• Bus Operation Multiplexed or Demultiplexed The bus interface uses Port 10 and Port 2 for addresses and data. In the demultiplexed bus modes, the lower addresses are output separately on Port 0 and Port 1. The number of active segment address lines is selectable , restricting the external address space to 8 Mbytes … 64 Kbytes. This is required when interface lines shall be assigned to Port 2. External CS signals (address windows plus default) can be generated and output on Port 4 in order to save external glue logic. External modules can be directly connected to the common address/data bus and their individual select lines. Important timing characteristics of the ex ternal bus interface are programmable (with registers TCONCSx/FCONCSx) to allow the user to adapt it to a wide range of different types of memories and external peripherals. Access to very slow memories or modules with varying access times is supported by a special ‘Ready’ function. The active level of the control input signal is selectable. In addition, up to four independent address windows may be defined (using registers ADDRSELx) to control access to resources with different bus characteristics. These address windows are arranged hierarchically where window 4 overrides window 3, and window 2 overrides window 1. All accesses to locations not covered by these four address windows are controlled by TCONCS0/FCONCS0. The currently active window can generate a chip select signal. The external bus timing is based on t he rising edge of the reference clock output CLKOUT. The external bus protocol is compatible with that of the standard C166 Family. 1) Bus modes are switched dynamically if several addr ess windows with different mode settings are used.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 45 V1.6, 2014-06

3.3 Central Processing Unit (CPU)

The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction- fetch pipeline, a 16-bit arithmetic and logi c unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing three register banks, and dedicated SFRs. The ALU features a multiply-and-div ide unit, a bit-mask generator, and a barrel shifter. Figure 5 CPU Block Diagram DPRAM CPU IPIP RF GPRs R14 R15 GPRs R14 R15 IFU Injection/ Exception Handler ADU MAC mca04917_x.vsd CPUCON1 CPUCON2 CSP IP Return StackFIFO Branch Unit Prefetch Unit VECSEG TFR +/- IDX0 IDX1 QX0 QX1 QR0 QR1 DPP0 DPP1 DPP2 DPP3 SPSEG SP STKOV STKUN +/- MRW MCW MSW MAL +/- MAH Multiply Unit ALU Division Unit Multiply Unit Bit-Mask-Gen. Barrel-Shifter +/- MDC PSW MDH ZEROS MDL ONES GPRs R14 R15 CP WB Buffer 2-Stage Prefetch Pipeline 5-Stage Pipeline GPRs R14 R15 PMU DMU DSRAM EBC Peripherals PSRAM Flash/ROM

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 46 V1.6, 2014-06 With this hardware most XC226xN instructions are executed in a single machine cycle of 12.5 ns @ 80-MHz CPU clock. For example, shift and rotate instructions are always processed during one ma chine cycle, no matter how m any bits are shifted. Also, multiplication and most MA C instructions execute in one cycle. All multiple-cycle instructions have been optimized so that they can be executed very fast; for example, a 32-/16-bit division is started within 4 cycle s while the remaining cycles are executed in the background. Another pipeline optimization, the branch target prediction, eliminates the execution time of branch instructions if the prediction was correct. The CPU has a register context consisting of up to three register banks with 16 word- wide GPRs each at its disposal. One of these register banks is physically allocated within the on-chip DPRAM area. A Context Pointer (CP) register determines the base address of the active register bank accessed by the CPU at any time. The number of these register bank copies is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 32 Kwords is provided for storage of temporary data. The system stack can be allocated to any location within the address space (preferably in the on-chip RAM area); it is accessed by the CPU with the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared with the stack pointer value during each stack access to detect stack overflow or underflow. The high performance of the CPU hardware implementation can be best utilized by the programmer with the highly efficient XC226xN instruction set. This includes the following instruction classes:

• Standard Arithmetic Instructions
• DSP-Oriented Arithmetic Instructions
• Logical Instructions
• Boolean Bit Manipulation Instructions
• Compare and Loop Control Instructions
• Shift and Rotate Instructions
• Prioritize Instruction
• Data Movement Instructions
• System Stack Instructions
• Jump and Call Instructions
• Return Instructions
• System Contro l Instructions
• Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 47 V1.6, 2014-06

3.4 Memory Protection Unit (MPU)

The XC226xN’s Memory Protection Unit (MPU) protects user-specified memory areas from unauthorized read, write, or instruct ion fetch accesses. The MPU can protect the whole address space including the peripheral area. This completes established mechanisms such as the register securi ty mechanism or stack overrun/underrun detection. Four Protection Levels support flexible system programming where operating system, low level drivers, and applications run on separate levels. Each protection level permits different access restrictions for instructions and/or data. Every access is checked (if the MPU is enabled) and an access violating the permission rules will be marked as invalid and leads to a protection trap. A set of protection registers for each protec tion level specifies the address ranges and the access permissions. Applications requ iring more than 4 protection levels can dynamically re-program the protection registers.

3.5 Memory Checker Module (MCHK)

The XC226xN’s Memory Checker Module calculates a checksum (fractional polynomial division) on a block of data, often called Cyclic Redundancy Code (CRC). It is based on a 32-bit linear feedback shift register and may, therefore, also be used to generate pseudo-random numbers. The Memory Checker Module is a 16-bit parallel input signature compression circuitry which enables error detection within a block of data stored in me mory, registers, or communicated e.g. via serial communication lines. It reduces the probability of error masking due to repeated error patterns by calculating the signature of blocks of data. The polynomial used for operation is configurable, so most of the commonly used polynomials may be used. Also, the block size for generating a CRC result is configurable via a local counter. An interrupt may be generated if testing the current data block reveals an error. An autonomous CRC compare circuitry is included to enable redundant error detection, e.g. to enable higher safety integrity levels. The Memory Checker Module provides enhanced fault detection (beyond parity or ECC) for data and instructions in volatile and non volatile memories. This is especially important for the safety and reliability of embedded systems.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 48 V1.6, 2014-06

3.6 Interrupt System

The architecture of the XC226xN supports several mechanisms for fast and flexible response to service requests; these can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). Using a standard interrupt service the curr ent program execution is suspended and a branch to the interrupt vector table is performed. With the PEC just one cycle is ‘stolen’ from the current CPU activity to perform the PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source pointer, the destination pointer, or both. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source-related vector location. PEC services are particularly well suited to supporting the transmission or reception of blocks of data. The XC226xN has eight PEC channels, each wi th fast interrupt-driven data transfer capabilities. With a minimum interrupt response time of 7/11 1) CPU clocks, the XC226xN can react quickly to the occurrence of non-deterministic events. Interrupt Nodes and Source Selection The interrupt system provides 96 physica l nodes with separate control register containing an interrupt request flag, an interrupt enable flag and an interrupt priority bit field. Most interrupt sources are assigned to a dedicated node. A particular subset of interrupt sources shares a set of nodes. The source selection can be programmed using the interrupt source selection (ISSR) registers. External Request Unit (ERU) A dedicated External Request Unit (ERU) is provided to route and preprocess selected on-chip peripheral and external interrupt requests. The ERU features 4 programmable input channels with event trigger logic (ETL ) a routing matrix and 4 output gating units (OGU). The ETL features rising edge, falli ng edge, or both edges event detection. The OGU combines the detected interrupt ev ents and provides filtering capabilities depending on a programmable pattern match or miss. Trap Processing The XC226xN provides efficient mechanisms to identify and process exceptions or error conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware trap causes an immediate system reaction similar to a standard interrupt service (branching 1) Depending if the jump cache is used or not.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 49 V1.6, 2014-06 to a dedicated vector table location). The occurrence of a hardware trap is also indicated by a single bit in the trap flag register (TFR). Unless another higher-priority trap service is in progress, a hardware trap will interrupt any ongoing program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Depending on the package option up to 3 External Service Request (ESR) pins are provided. The ESR unit processes their i nput values and allows to implement user controlled trap functions (System Requests SR0 and SR1). In this way reset, wakeup and power control can be efficiently realized. Software interrupts are supported by the ‘TRAP’ instruction in combination with an individual trap (interrupt) number. Alternatively to emulate an interrupt by software a program can trigger interrupt requests by wr iting the Interrupt Request (IR) bit of an interrupt control register.

3.7 On-Chip Debug Support (OCDS)

The On-Chip Debug Support system built into the XC226xN provides a broad range of debug and emulation features. User software running on the XC226xN can be debugged within the target system environment. The OCDS is controlled by an external debugging device via the debug interface. This either consists of the 2-pin Device Access Port (DAP) or of the JTAG port conforming to IEEE-1149. The debug interface can be completed with an optional break interface. The debugger controls the OCDS with a set of dedicated registers accessible via the debug interface (DAP or JTAG). In addition the OCDS system can be controlled by the CPU, e.g. by a monitor program. An inject ion interface allows the execution of OCDS- generated instructions by the CPU. Multiple breakpoints can be triggered by on-chip hardware, by software, or by an external trigger input. Single stepping is su pported, as is the in jection of arbitrary instructions and read/write access to the complete internal address space. A breakpoint trigger can be answered with a CPU halt, a mo nitor call, a data transfer, or/and the activation of an external signal. Tracing of data can be obtained via the debug interface, or via the external bus interface for increased performance. Tracing of program execution is supported by the XC2000 Family emulation device. With this device the DAP can operate on clock rates of up to 20 MHz. The DAP interface uses two interface signals, the JTAG interface uses four interface signals, to communicate with external circ uitry. The debug interface can be amended with two optional break lines.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 50 V1.6, 2014-06

3.8 Capture/Compare Unit (CC2)

The CAPCOM unit supports generation and control of timing sequences on up to 16 channels with a maximum resolution of one system clock cycle (eight cycles in staggered mode). The CAPCOM unit is typically used to handle high-speed I/O tasks such as pulse and waveform generation, pulse width modulation (PWM), digital to analog (D/A) conversion, software timing, or time recording with respect to external events. Two 16-bit timers with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs allow event scheduling for the captur e/compare registers relative to external events. The capture/compare register array cont ains 16 dual purpose capture/compare registers, each of which may be individual ly allocated to either CAPCOM timer and programmed for capture or compare function. All registers have each one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘captured’) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. Table 9 Compare Modes Compare Modes Function Mode 0 Interrupt-only compare mode; Several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; Several compare events per timer period are possible

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 51 V1.6, 2014-06 When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘captured’) into the capture/compare register in response to an external event at the port pin associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the compare mode selected. Mode 2 Interrupt-only compare mode; Only one compare interrupt per timer period is generated Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow; Only one compare event per timer period is generated Double Register Mode Two registers operate on one pin; Pin toggles on each compare match; Several compare events per timer period are possible Single Event Mode Generates single edges or pulses; Can be used with any compare mode Table 9 Compare Modes (cont’d) Compare Modes Function

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 52 V1.6, 2014-06 Figure 6 CAPCOM Unit Block Diagram Sixteen 16-bit Capture/ Compare Registers Mode Control (Capture or Compare ) Input Control Input Control MC_CAPCOM2_BLOCKDIAG CC16IRQ CC31IRQ CC17IRQ T7IRQ T8IRQ CC16IO CC17IO T7IN T6OUF fCC T6OUF fCC Reload Reg . T7REL Timer T7 Timer T8 Reload Reg . T8REL CC31IO

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 53 V1.6, 2014-06

3.9 Capture/Compare Units CCU6x

The XC226xN types feature the CCU60, CCU61 unit(s). CCU6 is a high-resolution capture and compare unit with application-specific modes. It provides inputs to start the timers synchr onously, an important feature in devices with several CCU6 modules. The module provides two independent timers (T12, T13), that can be used for PWM generation, especially for AC motor control. Additionally, special control modes for block commutation and multi-phase machines are supported. Timer 12 Features

• Three capture/compare channels, where each channel can be used either as a capture or as a compare channel.
• Supports generation of a three-phase PWM (six outputs, individual signals for high- side and low-side switches)
• 16-bit resolution, maximum count frequency = peripheral clock
• Dead-time control for each channel to avoid short circuits in the power stage
• Concurrent update of the required T12/13 registers
• Center-aligned and edge-aligned PWM can be generated
• Single-shot mode supported
• Many interrupt request sources
• Hysteresis-like control mode
• Automatic start on a HW event (T 12HR, for synchronization purposes) Timer 13 Features
• One independent compare channel with one output
• 16-bit resolution, maximum count frequency = peripheral clock
• Can be synchronized to T12
• Interrupt generation at period match and compare match
• Single-shot mode supported
• Automatic start on a HW event (T 13HR, for synchronization purposes) Additional Features
• Block commutation for brushless DC drives implemented
• Position detection via Hall sensor pattern
• Automatic rotational speed measurement for block commutation
• Integrated error handling
• Fast emergency stop without CPU load via external signal (CTRAP
• Control modes for multi-channel AC drives
• Output levels can be selected and adapted to the power stage

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 54 V1.6, 2014-06 Figure 7 CCU6 Block Diagram Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined. Timer T13 can work in compare mode only. The multi-channel control unit generates output patterns that can be modulated by timer T12 and/or timer T13. The modulation sources can be selected and combined for signal modulation. mc_ccu6_blockdiagram.vsd Channel 0 Channel 1 Channel 2 T12 Dead- time Control Input / Output Control CC62 COUT62 CC61 COUT61 CC60 COUT60 COUT63 CTRAP Channel 3T13 CCPOS0 2 2 21 start compare capt ur e Multi- channel Control Trap Control compare com par e com par e com par e trap i nput CCPOS1 CCPOS2 output select output select H a ll in p u t CCU6 Module Kernel fSYS Interrupts TxHR

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 55 V1.6, 2014-06

3.10 General Purpose Timer (GPT12E) Unit

The GPT12E unit is a very flexible multif unctional timer/counter structure which can be used for many different timing tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT12E unit incorporates five 16-bit timers organized in two separate modules, GPT1 and GPT2. Each timer in each module may either operate independently in a number of different modes or be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation: Time r, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the system clock and divided by a programmable prescaler. Counter Mode allows timer clocking in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes each timer has one associated port pin (TxIN) which serves as a gate or clock input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles. The counting direction (up/down) for each timer can be programmed by software or altered dynamically by an external signal on a port pin (TxEUD), e.g. to facilitate position tracking. In Incremental Interface Mode the GPT1 ti mers can be directly connected to the incremental position sensor signals A and B through their respective inputs TxIN and TxEUD. Direction and counting signals are internally derived from these two input signals, so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL ) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware components. It may also be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to the basic operating modes, T2 and T4 may be configured as reload or capture register for timer T3. A timer used as capture or reload register is stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at the associated input pin (TxIN). Timer T3 is reloaded with th e contents of T2 or T4, triggered either by an external signal or a selectable state tr ansition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be continuously generated without software intervention.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 56 V1.6, 2014-06 Figure 8 Block Diagram of GPT1 MC_GPT_BLOCK1 Aux. Timer T2 2n:1 Mode Control Capture U/D Basic ClockfGPT T3CON.BPS1 T3OTL T3OUT Toggle Latch T2IN T2EUD Reload Core Timer T3 Mode Control T3IN T3EUD U/D Interrupt Request (T3IRQ) Mode Control U/D Aux. Timer T4T4EUD T4IN Reload Capture Interrupt Request (T4IRQ) Interrupt Request (T2IRQ)

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 57 V1.6, 2014-06 With its maximum resolution of 2 system clock cycles, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The counting direction (up/down) for each timer can be programmed by software or altered dynamically with an external signal on a port pin (TxEUD1)). Concatenation of the timers is supported with the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, and/or it may be output on pin T6OUT. The overflows/underflows of timer T6 can also be used to clock the CAPCOM2 timers and to initiate a reload from the CAPREL register. The CAPREL register can capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN); timer T5 may optionally be cleared after the capture procedure. This allows the XC226xN to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL ) can also be generated upon transitions of GPT1 timer T3 inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode. 1) Exception: T5EUD is not connected to a pin.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 58 V1.6, 2014-06 Figure 9 Block Diagram of GPT2 MC_GPT_BLOCK2 GPT2 Timer T5 2n:1 Mode Control GPT2 CAPREL T3IN/ T3EUD CAPREL Mode Control Mode Control Reload Clear U/D Capture Clear U/DT5IN CAPIN Interrupt Request (T5IRQ) Interrupt Request (T6IRQ) Interrupt Request (CRIRQ) Basic ClockfGPT T6CON.BPS2 T6IN GPT2 Timer T6 T6OTL T6OUT T6OUF Toggle FF T6EUD T5EUD

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 59 V1.6, 2014-06

3.11 Real Time Clock

The Real Time Clock (RTC) module of the XC226xN can be clocked with a clock signal selected from internal sources or external sources (pins). The RTC basically consists of a chain of divider blocks:

• Selectable 32:1 and 8:1 dividers (on - off)
• The reloadable 16-bit timer T14
• The 32-bit RTC timer block (accessible via registers RTCH and RTCL) consisting of: – a reloadable 10-bit timer – a reloadable 6-bit timer – a reloadable 6-bit timer – a reloadable 10-bit timer All timers count up. Each timer can generate an interrupt request. All requests are combined to a common node request. Figure 10 RTC Block Diagram Note: The registers associated with the RTC are only affected by a power reset. CNT-Register REL-Register

10 Bits6 Bits6 Bits10 BitsT14

T14REL 10 Bits6 Bits6 Bits10 Bits MUX 8: REFCLK

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 60 V1.6, 2014-06 The RTC module can be used for different purposes:

• System clock to determine the current time and date
• Cyclic time-based interrupt, to provide a system time tick independent of CPU frequency and other resources
• 48-bit timer for long-term measurements
• Alarm interrupt at a defined time

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 61 V1.6, 2014-06

3.12 A/D Converters

For analog signal measurement, up to two 10-bit A/D converters (ADC0, ADC1) with 11 + 5 multiplexed input channels and a sample and hold circuit have been integrated on-chip. 4 inputs can be converted by both A/D converters. Conversions use the successive approximation method. The sample time (to charge the capacitors) and the conversion time are programmable so that t hey can be adjusted to the external circuit. The A/D converters can also operate in 8-bi t conversion mode, further reducing the conversion time. Several independent conversion result regist ers, selectable inte rrupt requests, and highly flexible conversion sequences provide a high degree of programmability to meet the application requirements. Both modules can be synchronized to allow parallel sampling of two input channels. For applications that require more analog input channels, external analog multiplexers can be controlled automatically. For app lications that require fewer analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converters of the XC226xN support two types of request sources which can be triggered by several internal and external events.

• Parallel requests are activated at the sa me time and then executed in a predefined sequence.
• Queued requests are executed in a user-defined sequence. In addition, the conversion of a specific channel can be inserted into a running sequence without disturbing that sequence. All requests are arbitrated according to the priority level assigned to them. Data reduction features reduce the number of required CPU access operations allowing the precise evaluation of analog inputs (high conversion rate) even at a low CPU speed. Result data can be reduced by limit checking or accumulation of results. The Peripheral Event Controller (PEC) can be used to control the A/D converters or to automatically store conversion results to a table in memory for later evaluation, without requiring the overhead of enter ing and exiting interrupt routines for each data transfer. Each A/D converter contains eight result registers which can be concatenated to build a result FIFO. Wait-f or-read mode can be enabled for each result register to prevent the loss of conversion data. In order to decouple analog inputs from digital noise and to avoid input trigger noise, those pins used for analog input can be disconnected from the digital input stages. This can be selected for each pin separately with the Port x Digital Input Disable registers. The Auto-Power-Down feature of the A/D converters minimizes the power consumption when no conversion is in progress. Broken wire detection for each channel and a multiplexer test mode provide information to verify the proper operation of the analog signal sources (e.g. a sensor system).

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 62 V1.6, 2014-06

3.13 Universal Serial Interf ace Channel Modules (USIC)

The XC226xN features the USIC modules USIC0, USIC1, USIC2. Each module provides two serial communication channels. The Universal Serial Interface Channel (USIC) module is based on a generic data shift and data storage structure which is identi cal for all supported serial communication protocols. Each channel supports complete full-duplex operation with a basic data buffer structure (one transmit buffer and two receive buffer stages). In addition, the data handling software can use FIFOs. The protocol part (generation of shift clock/da ta/control signals) is independent of the general part and is handled by protocol-specific preprocessors (PPPs). The USIC’s input/output lines are connected to pins by a pin routing unit. The inputs and outputs of each USIC channel can be assigned to different interface pins, providing great flexibility to the application software. All assignments can be made during runtime. Figure 11 General Structure of a USIC Module The regular structure of the USIC module brings the following advantages:

• Higher flexibility through configuration wi th same look-and-feel for data management
• Reduced complexity for low-level dr ivers serving different protocols
• Wide range of protocols with improved performances (baud rate, buffer handling) USIC_basic.vsd Bus Interface DBU DBU Control 0 Control 1 DSU DSU PPP_A PPP_B PPP_C PPP_D PPP_A PPP_B PPP_C PPP_D Pin Routing Shell Buffer & Shift Structure Protocol Preprocessors PinsBus fsys Fractional Dividers Baud rate Generators

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 63 V1.6, 2014-06 Target Protocols Each USIC channel can receive and transmit data frames with a selectable data word width from 1 to 16 bits in each of the following protocols:

• UART (asynchronous serial channel) – module capability: maximum baud rate = fSYS / 4 – data frame length programmable from 1 to 63 bits – MSB or LSB first
• LIN Support (Local Interconnect Network) – module capability: maximum baud rate = fSYS / 16 – checksum generation under software control – baud rate detection possible by built-in capture event of baud rate generator
• SSC/SPI (synchronous serial channel with or without data buffer) – module capability: maximum baud rate = fSYS / 2, limited by loop delay – number of data bits programmable from 1 to 63, more with explicit stop condition – MSB or LSB first – optional control of slave select signals
• IIC (Inter-IC Bus) – supports baud rates of 100 kbit/s and 400 kbit/s
• IIS (Inter-IC Sound Bus) – module capability: maximum baud rate = fSYS / 2 Note: Depending on the selected functions (such as digital filters, input synchronization stages, sample point adjustment, etc.), the maximum achievable baud rate can be limited. Please note that there may be additional delays, such as internal or external propagation delays and driver delays (e.g. for collision detection in UART mode, for IIC, etc.).

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 64 V1.6, 2014-06

3.14 MultiCAN Module

The MultiCAN module contains independently operating CAN nodes with Full-CAN functionality which are able to exchange Da ta and Remote Frames using a gateway function. Transmission and reception of CAN frames is handled in accordance with CAN specification V2.0 B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. All CAN nodes share a common set of mess age objects. Each message object can be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the CAN nodes or to set up a FIFO buffer. Note: The number of CAN nodes and message objects depends on the selected device type. The message objects are organized in doubl e-chained linked lists, where each CAN node has its own list of message objects. A CAN node stores frames only into message objects that are allocated to its own message object list and it transmits only messages belonging to this message object list. A powerful, command-driven list controller performs all message object list operations. Figure 12 Block Diagram of MultiCAN Module mc_multican_block.vsd MultiCAN Module Kernel Interrupt Control fCAN Port Control CAN Control Message Object Buffer CAN Node 0 Linked List Control Clock Control Address Decoder CAN Node n TXDCn RXDCn TXDC0 RXDC0 ... ... ...

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 65 V1.6, 2014-06 MultiCAN Features

• CAN functionality conforming to CAN specification V2.0 B active for each CAN node (compliant to ISO 11898)
• Independent CAN nodes
• Set of independent message objects (shared by the CAN nodes)
• Dedicated control registers for each CAN node
• Data transfer rate up to 1 Mbit/s, individually programmable for each node
• Flexible and powerful message transfer control and error handling capabilities
• Full-CAN functionality for message objects: – Can be assigned to one of the CAN nodes – Configurable as transmit or receive objects, or as message buffer FIFO – Handle 11-bit or 29-bit identifiers with programmable acceptance mask for filtering – Remote Monitoring Mode, and frame counter for monitoring
• Automatic Gateway Mode support
• 16 individually programmable interrupt nodes
• Analyzer mode for CAN bus monitoring

3.15 System Timer

The System Timer consists of a programmable prescaler and two concatenated timers (10 bits and 6 bits). Both timers can gener ate interrupt requests. The clock source can be selected and the timers can also run during power reduction modes. Therefore, the System Timer enables the software to maintain the current time for scheduling functions or for the implementation of a clock.

3.16 Watchdog Timer

The Watchdog Timer is one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after an application reset of the chip. It can be disabled and enabled at any time by exec uting the instructions DISWDT and ENWDT respectively. The software has to service the Watchdog Timer before it overflows. If this is not the case because of a hardware or software failure, the Watchdog Timer overflows, generating a prewarning interrupt and then a reset request. The Watchdog Timer is a 16-bit timer clock ed with the system clock divided by 16,384 or 256. The Watchdog Timer register is set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the Watchdog Timer is reloaded and the prescaler is cleared. Time intervals between 3.2 μs and 13.4 s can be monitored (@ 80 MHz). The default Watchdog Timer interval after power-up is 6.5 ms (@ 10 MHz).

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 66 V1.6, 2014-06

3.17 Clock Generation

The Clock Generation Unit can generate the system clock signal fSYS for the XC226xN from a number of external or internal clock sources:

• External clock signals with pad voltage or core voltage levels
• External crystal or resonator using the on-chip oscillator
• On-chip clock source for oper ation without crystal/resonator
• Wake-up clock (ultra-low-power) to further reduce power consumption The programmable on-chip PLL with multiple prescalers generates a clock signal for maximum system performance from standard crystals, a clock input signal, or from the on-chip clock source. See also Section 4.7.2. The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency falls below a certain limit or stops completely. In this case, the system can be supplied with an emergency clock to enable operation even after an external clock failure. All available clock signals can be output on one of two selectable pins.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 67 V1.6, 2014-06

3.18 Parallel Ports

The XC226xN provides up to 76 I/O lines wh ich are organized into 7 input/output ports and 2 input ports. All port lines are bit-addressable, and all input/output lines can be individually (bit-wise) configured via port control registers. This configuration selects the direction (input/output), push/pull or open-drain operation, activation of pull devices, and edge characteristics (shape) and driver char acteristics (output current) of the port drivers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. During the internal reset, all port pins are configured as inputs without pull devices active. All port lines have alternate input or out put functions associat ed with them. These alternate functions can be programmed to be assigned to various port pins to support the best utilization for a given application. For this reason, certain functions appear several times in Table 10. All port lines that are not used for alternate functions may be used as general purpose I/O lines. Table 10 Summary of the XC226xN’s Ports Port Width I/O Connected Modules P0 8 I/O EBC (A7...A0), CCU6, USIC, CAN P1 8 I/O EBC (A15...A8), CCU6, USIC P2 14 I/O EBC (READY, BHE CAN, CC2, GPT12E, USIC, DAP/JTAG P4 4 I/O EBC (CS 3...CS0), CC2, CAN, GPT12E, USIC P5 11 I Analog Inputs, CCU6, DAP/JTAG, GPT12E, CAN P6 3 I/O ADC, CAN, GPT12E P7 5 I/O CAN, GPT12E, SCU, DAP/JTAG, CCU6, ADC, USIC P10 16 I/O EBC (ALE, RD DAP/JTAG, CAN P15 5 I Analog Inputs, GPT12E

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 68 V1.6, 2014-06

3.19 Power Management

The XC226xN provides the means to control the power it consumes either at a given time or averaged over a certain duration. Three mechanisms can be used (and partly in parallel):

• Supply Voltage Management permits the temporary reduction of the supply voltage of major parts of the logic or even its complete disconnection. This drastically reduces the power consumed because it eliminat es leakage current, particularly at high temperature. Several power reduction modes provide th e best balance of power reduction and wake-up time.
• Clock Generation Management controls the frequency of internal and external clock signals. Clock signals for currently inactive parts of logic are disabled automatically. The user can drastically reduce the consumed power by reducing the XC226xN system clock frequency. External circuits can be controlled using the programmable frequency output EXTCLK.
• Peripheral Management permits temporary disabling of peripheral modules. Each peripheral can be disabled and enabled separ ately. The CPU can be switched off while the peripherals can continue to operate. Wake-up from power reduction modes can be triggered either externally with signals generated by the external system, or inter nally by the on-chip wake-up timer. This supports intermittent operation of the XC 226xN by generating cyclic wake-up signals. Full performance is available to quickly react to action requests while the intermittent sleep phases greatly reduce the average system power consumption. Note: When selecting the supply voltage and the clock source and generation method, the required parameters must be carefully written to the respective bit fields, to avoid unintended intermediate states. Recommended sequences are provided which ensure the intended operation of power supply system and clock system. Please refer to the Programmer’s Guide.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 69 V1.6, 2014-06

3.20 Instruction Set Summary

Table 11 lists the instructions of the XC226xN. The addressing modes that can be used with a specific instruction, the function of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “Instruction Set Manual”. This document also provides a detailed description of each instruction. Table 11 Instruction Set Summary Mnemonic Description Bytes ADD(B) Add word (byte) operands 2 / 4 ADDC(B) Add word (byte) operands with Carry 2 / 4 SUB(B) Subtract word (byte) operands 2 / 4 SUBC(B) Subtract word (byte) operands with Carry 2 / 4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16- × 16-bit) DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2 / 4 OR(B) Bitwise OR, (word/byte operands) 2 / 4 XOR(B) Bitwise exclusive OR, (word/byte operands) 2 / 4 BCLR/BSET Clear/Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND/BOR/BXOR AND/OR/XOR dire ct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/BFLDL Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data CMP(B) Compare word (byte) operands 2 / 4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4 PRIOR Determine number of sh ift cycles to normalize direct word GPR and store result in direct word GPR SHL/SHR Shift left/right direct word GPR 2

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 70 V1.6, 2014-06 ROL/ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2 MOV(B) Move word (byte) data 2 / 4 MOVBS/Z Move byte operand to word op. with sign/zero extension 2 / 4 JMPA/I/R Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 JB(C) Jump relative if direct bit is set (and clear bit) 4 JNB(S) Jump relative if direct bit is not set (and set bit) 4 CALLA/I/R Call absolute/indirect/relativ e subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine TRAP Call interrupt service routine via immediate trap number 2 PUSH/POP Push/pop direct word r egister onto/from system stack 2 SCXT Push direct word register onto system stack and update register with word operand RET(P) Return from intra-segment subroutine (and pop direct word register from system stack) RETS Return from inter-segment subroutine 2 RETI Return from interrupt service subroutine 2 SBRK Software Break 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Unused instruction1) 4 SRVWDT Service Watchdog Timer 4 DISWDT/ENWDT Disable/Enable Watchdog Timer 4 EINIT End-of-Initialization Register Lock 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4 EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4 Table 11 Instruction Set Summary (cont’d) Mnemonic Description Bytes

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Functional Description Data Sheet 71 V1.6, 2014-06 NOP Null operation 2 CoMUL/CoMAC Multiply (and accumulate) 4 CoADD/CoSUB Add/Subtract 4 Co(A)SHR (Arithmetic) Shift right 4 CoSHL Shift left 4 CoLOAD/STORE Load accumulator/Store MAC register 4 CoCMP Compare 4 CoMAX/MIN Maximum/Minimum 4 CoABS/CoRND Absolute value/Round accumulator 4 CoMOV Data move 4 CoNEG/NOP Negate accumulator/Null operation 4 1) The Enter Power Down Mode instruction is not used in the XC226xN, due to the enhanced power control scheme. PWRDN will be correctly decoded, but will trigger no action. Table 11 Instruction Set Summary (cont’d) Mnemonic Description Bytes

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 72 V1.6, 2014-06

4 Electrical Parameters

The operating range for the XC226xN is defined by its electrical parameters. For proper operation the specified limits must be respected when integrating the device in its target environment.

4.1 General Parameters

These parameters are valid for all subsequent descriptions, unless otherwise noted. Note: Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other c onditions above those indicated in the operational sections of this specificatio n is not implied. Exposure to absolute maximum rating conditions for an extended time may affect device reliability. During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the voltage on VDDP pins with respect to ground ( VSS) must not exceed the values defined by the absolute maximum ratings. Table 12 Absolute Maximum Rating Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Output current on a pin when high value is driven IOH SR -30 −− mA Output current on a pin when low value is driven IOL SR −− 30 mA Overload current IOV SR -10 − 10 mA 1) 1) Overload condition occurs if the input voltage VIN is out of the absolute maximum rating range. In this case the current must be limited to the listed values by design measures. Absolute sum of overload currents Σ|IOV| SR −− 100 mA 1) Junction Temperature TJ SR -40 − 150 °C Storage Temperature TST SR -65 − 150 °C Digital supply voltage for IO pads and voltage regulators VDDP SR -0.5 − 6.0 V Voltage on any pin with respect to ground (Vss) VIN SR -0.5 − VDDP + 0.5 V VIN≤ VDDP(max)

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 73 V1.6, 2014-06

4.1.1 Operating Conditions

The following operating conditions must not be exceeded to ensure correct operation of the XC226xN. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Note: Typical parameter values refer to room temperature and nominal supply voltage, minimum/maximum para meter values also include conditions of minimum/maximum temperature and minimum/maximum supply voltage. Additional details are described where applicable. Table 13 Operating Conditions Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Voltage Regulator Buffer Capacitance for DMP_M CEVRM SR 1.0 − 4.7 μF 1) Voltage Regulator Buffer Capacitance for DMP_1 CEVR1 SR 0.47 − 2.2 μF 2)1) External Load Capacitance CL SR − 203) − pF pin out driver= default System frequency fSYS SR −− 80 MHz 5) Overload current for analog inputs IOVA SR -2 − 5 mA not subject to production test Overload current for digital inputs IOVD SR -5 − 5 mA not subject to production test Overload current coupling factor for analog inputs7) KOVA CC − 2.5 x 1.5 x - IOV< 0 mA; not subject to production test − 1.0 x 1.0 x - IOV> 0 mA; not subject to production test

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 74 V1.6, 2014-06 Overload current coupling factor for digital I/O pins KOVD CC − 1.0 x 3.0 x - IOV< 0 mA; not subject to production test − 1.0 x 10-4 5.0 x - IOV> 0 mA; not subject to production test Absolute sum of overload currents IOV| SR −− 50 mA not subject to production test Digital core supply voltage for domain M8) VDDIM CC − 1.5 − Digital core supply voltage for domain 1 VDDI1 CC − 1.5 − Digital supply voltage for IO pads and voltage regulators VDDP SR 3.0 − 5.5 V Digital ground voltage VSS SR − 0 − V 1) To ensure the stability of the voltage regulators the EVRs must be buffered with ceramic capacitors. Separate buffer capacitors with the recomended values shall be connected as close as possible to each VDDIM and VDDI1 pin to keep the resistance of the board tracks below 2 Ohm. Connect all VDDI1 pins together. The minimum capacitance value is required for proper operation under all conditions (e.g. temperature). Higher values slightly increase the startup time. 2) Use one Capacitor for each pin. 3) This is the reference load. For bigger capacitive loads, use the derating factors listed in the pad properties section. 4) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output current may lead to increased delays or reduced driving capability (CL). 5) The operating frequency range may be reduced for specific device types. This is indicated in the device 6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: VOV > VIHmax (IOV > 0) or VOV < VILmin ((IOV < 0). The absolute sum of input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified limits. Proper operation under overload conditions depen ds on the application. Overload conditions must not occur on pin XTAL1 (powered by VDDIM). Table 13 Operating Conditions (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 75 V1.6, 2014-06

4.2 Voltage Range definitions

The XC226xN timing depends on the supply voltage. If such a dependency exists the timing values are given for 2 voltage ar eas commonly used. T he voltage areas are defined in the following tables.

4.2.1 Parameter Interpretation

The parameters listed in the following includ e both the characteristics of the XC226xN and its demands on the system. To aid in correctly in terpreting the pa rameters when evaluating them for a design, they are marked accordingly in the column “Symbol”: CC (Controller Characteristics): The logic of the XC226xN provides signals with the specified characteristics. SR (System Requirement): The external system must pr ovide signals with the specif ied characteristics to the XC226xN. 7) An overload current ( IOV) through a pin injects a certain error current ( IINJ) into the adjacent pins. This error current adds to the respective pins leakage current (IOZ). The amount of error current depends on the overload current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse compared to the polarity of the overload current that produces it.The total current through a pin is |ITOT| = |IOZ| + (|IOV| KOV). The additional error current may distort the input voltage on analog inputs. 8) Value is controlled by on-chip regulator Table 14 Upper Voltage Range Definition Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Digital supply voltage for IO pads and voltage regulators VDDP SR 4.5 5 5.5 V Table 15 Lower Voltage Range Definition Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Digital supply voltage for IO pads and voltage regulators VDDP SR 3.0 3.3 4.5 V

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 76 V1.6, 2014-06

4.3 DC Parameters

These parameters are static or average values that may be exceeded during switching transitions (e.g. output current). The XC226xN can operate within a wide supply voltage range from 3.0 V to 5.5 V. However, during operation this supply volt age must remain within 10 percent of the selected nominal supply voltage. It cannot vary across the full operating voltage range. Because of the supply voltage restrictio n and because electrical behavior depends on the supply voltage, the parameters are specified separately for the upper and the lower voltage range. During operation, the supply voltages may only change with a maximum speed of dV/dt < 1 V/ms. Leakage current is strongly dependent on t he operating temperature and the voltage level at the respective pin. The maximum values in the following tables apply under worst case conditions, i.e. maximum temperature and an input level equal to the supply voltage. The value for the leakage current in an a pplication can be determined by using the respective leakage derating formula (see tables) with values from that application. The pads of the XC226xN are designed to operate in various driver modes. The DC parameter specifications refer to the pad current limits specified in Section 4.7.4.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 77 V1.6, 2014-06 Pullup/Pulldown Device Behavior Most pins of the XC226xN feature pullup or pulldown devices. For some special pins these are fixed; for the port pins they can be selected by the application. The specified current values indicate how to load the respective pin depending on the intended signal level. Figure 13 shows the current paths. The shaded resistors shown in the figure may be required to compensate system pull currents that do not match the given limit values. Figure 13 Pullup/Pulldown Current Definition MC _XC2X_ PULL VDDP VSS Pullup Pulldown

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 78 V1.6, 2014-06

4.3.1 DC Parameters for Upper Voltage Area

Keeping signal levels within the limits spec ified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. Note: Operating Conditions apply. Table 16 is valid under the following conditions: VDDP≤ 5.5 V; VDDPtyp. 5 V; VDDP≥ 4.5 V Table 16 DC Characteristics for Upper Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Pin capacitance (digital inputs/outputs). To be doubled for double bond pins. CIO CC −− 10 pF not subject to production test Input Hysteresis2) HYS CC 0.11 x VDDP −− V RS=0O h m Absolute input leakage current on pins of analog ports |IOZ1| CC − 10 200 nA VIN> VSS ; VIN< VDDP Absolute input leakage current for all other pins. To be doubled for double bond pins. 3)1)4) |IOZ2| CC − 0.2 5 μA TJ≤ 110 °C; VIN> VSS ; VIN< VDDP − 0.2 15 μA TJ≤ 150 °C; VIN> VSS ; VIN< VDDP Pull Level Force Current5) |IPLF| SR 250 −−μ A VIN≥ VIHmin(pull down_enabled); VIN≤ VILmax(pull up_enabled) Pull Level Keep Current6) |IPLK| SR −− 30 μA VIN≥ VIHmin(pull up_enabled); VIN≤ VILmax(pull down_enabled) Input high voltage (all except XTAL1) VIH SR 0.7 x VDDP − VDDP + 0.3 V Input low voltage (all except XTAL1) VIL SR -0.3 − 0.3 x VDDP V

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 79 V1.6, 2014-06 Output High voltage7) VOH CC VDDP - 1.0 −− V IOH≥ IOHmax VDDP - 0.4 −− V IOH≥ IOHnom Output Low Voltage7) VOL CC −− 0.4 V IOL≤ IOLnom −− 1.0 V IOL≤ IOLmax 1) Because each double bond pin is connected to two pads (standard pad and high-speed pad), it has twice the normal value. For a list of affected pins refer to the pin definitions table in chapter 2. 2) Not subject to production test - ve rified by design/characterization. H ysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot suppress switching due to external system noise under all conditions. 3) If the input voltage exceeds the respecti ve supply voltage due to ground bouncing (VIN < VSS) or supply ripple (VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the leakage current. An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to the definition of the overload coupling factor KOV. 4) The given values are worst-case val ues. In production test, this leakage current is only tested at 125 °C; other values are ensured by correlation. For derating, plea se refer to the following descriptions: Leakage derating depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level (DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) ( μA]. This voltage derating formula is an approximation which applies for maximum temperature. 5) Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device. 6) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level. 7) The maximum deliverable output current of a port driv er depends on the selected output driver mode. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage is determined by the external circuit. 8) As a rule, with decreasing output current the out put levels approach the respective supply level ( VOL->VSS, VOH->VDDP). However, only the levels for nominal output currents are verified. Table 16 DC Characteristics for Upper Voltage Range (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 80 V1.6, 2014-06

4.3.2 DC Parameters for Lower Voltage Area

Keeping signal levels within the limits spec ified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. Note: Operating Conditions apply. Table 17 is valid under the following conditions: VDDP≥ 3.0 V; VDDPtyp. 3.3 V; VDDP≤ 4.5 V Table 17 DC Characteristics for Lower Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Pin capacitance (digital inputs/outputs). To be doubled for double bond pins.1) CIO CC −− 10 pF not subject to production test Input Hysteresis2) HYS CC 0.07 x VDDP −− V RS=0O h m Absolute input leakage current on pins of analog ports |IOZ1| CC − 10 200 nA VIN> VSS ; VIN< VDDP Absolute input leakage current for all other pins. To be doubled for double bond pins. 3)1)4) |IOZ2| CC − 0.2 2.5 μA TJ≤ 110 °C; VIN> VSS ; VIN< VDDP − 0.2 8 μA TJ≤ 150 °C; VIN> VSS ; VIN< VDDP Pull Level Force Current5) |IPLF| SR 150 −−μ A VIN≥ VIHmin(pull down) ; VIN≤ VILmax(pull up) Pull Level Keep Current6) |IPLK| SR −− 10 μA VIN≥ VIHmin(pull up) ; VIN≤ VILmax(pull down) Input high voltage (all except XTAL1) VIH SR 0.7 x VDDP − VDDP + 0.3 V Input low voltage (all except XTAL1) VIL SR -0.3 − 0.3 x VDDP V

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 81 V1.6, 2014-06 Output High voltage7) VOH CC VDDP - 1.0 −− V IOH≥ IOHmax VDDP - 0.4 −− V IOH≥ IOHnom Output Low Voltage7) VOL CC −− 0.4 V IOL≤ IOLnom −− 1.0 V IOL≤ IOLmax 1) Because each double bond pin is connected to two pads (standard pad and high-speed pad), it has twice the normal value. For a list of affected pins refer to the pin definitions table in chapter 2. 2) Not subject to production test - ve rified by design/characterization. H ysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot suppress switching due to external system noise under all conditions. 3) If the input voltage exceeds the respecti ve supply voltage due to ground bouncing (VIN < VSS) or supply ripple (VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the leakage current. An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to the definition of the overload coupling factor KOV. 4) The given values are worst-case val ues. In production test, this leakage current is only tested at 125 °C; other values are ensured by correlation. For derating, plea se refer to the following descriptions: Leakage derating depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level (DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) ( μA]. This voltage derating formula is an approximation which applies for maximum temperature. 5) Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN <= VIL for a pullup; VPIN >= VIH for a pulldown. 6) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN >= VIH for a pullup; VPIN <= VIL for a pulldown. 7) The maximum deliverable output current of a port driv er depends on the selected output driver mode. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage is determined by the external circuit. 8) As a rule, with decreasing output current the out put levels approach the respective supply level ( VOL->VSS, VOH->VDDP). However, only the levels for nominal output currents are verified. Table 17 DC Characteristics for Lower Voltage Range (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 82 V1.6, 2014-06

4.3.3 Power Consumption

The power consumed by the XC226xN depends on several factors such as supply voltage, operating frequency, active circuits, and operating temperature. The power consumption specified here consists of two components:

• The switching current IS depends on the device activity
• The leakage current ILK depends on the device temperature To determine the actual power consumption, always both components, switching current IS and leakage current ILK must be added: IDDP = IS + ILK. Note: The power consumption values are not subject to production test. They are verified by design/characterization. To determine the total power consumpti on for dimensioning the external power supply, also the pad driver currents must be considered. The given power consumption parameters and their values refer to specific operating conditions:
• Active mode: Regular operation, i.e. peripherals are active, code execution out of Flash.
• Stopover mode: Crystal oscillator and PLL stopped, Flash switched off, clock in domain DMP_1 stopped.
• Standby mode: Voltage domain DMP_1 switched off completely, power supply control switched off. DMP_M domain is supplied by ultra lo w power electronic voltage regulator (ULPEVR). The alternate regulator EVR_M is switched off. Note: The maximum values cover the comp lete specified operating range of all manufactured devices. The typical values refer to average devices under typical conditions, such as nominal supply voltage, room temperature, application-oriented activity. After a power reset, the decoupling capacitors for VDDIM and VDDI1 are charged with the maximum possible current. For additional information, please refer to Section 5.2, Thermal Considerations. Note: Operating Conditions apply.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 83 V1.6, 2014-06 Active Mode Power Supply Current The actual power supply current in active mode not only depends on the system frequency but also on the configuration of the XC226xN’s subsystem. Besides the power consumed by the device logic the power supply pins also provide the current that flows through the pin output drivers. A small current is consumed because the drivers’ input stages are switched. The IO power domains can be supplied separately. Power domain A (VDDPA) supplies the A/D converters and Port 6. Power domain B (VDDPB) supplies the on-chip EVVRs and all other ports. Table 18 Switching Power Consumption Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Power supply current (active) with all peripherals active and EVVRs on ISACT CC − 6 + 0.6 x fSYS 1) fSYS in MHz 8 + 1.0 x fSYS mA power_mode= active ; voltage_range= both 2)3)4) 2) The pad supply voltage pins ( VDDPB) provide the input current for the on-chip EVVRs and the current consumed by the pin output drivers. A small current is consumed because t he drivers input stages are switched. In Fast Startup Mode (with the Flash modules deactivated), the typical current is reduced to 3 + 0.6 x fSYS. 3) Please consider the additional conditions described in section "Active Mode Power Supply Current". 4) The pad supply voltage has only a minor influence on this parameter. Power supply current in standby mode ISSB CC − 45 125 μA power_mode= standby ; voltage_range= lower 5) 5) These values are valid if the voltage validation circuits for VDDPB (SWD) and VDDIM (PVC_M) are off. Leaving SWD and PVC_M active adds another 90 μA. − 70 220 μA power_mode= standby ; voltage_range= upper 5) Power supply current in stopover mode, EVVRs on ISSO CC − 0.7 2.0 mA power_mode= stopover ; voltage_range= both 4)

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 84 V1.6, 2014-06 During operation domain A draws a maximu m current of 1.5 mA for each active A/D converter module from VDDPA. In Fast Startup Mode (with the Flash modules deactivated), the typical current is reduced to 3 + 0.6×fSYS mA. Figure 14 Supply Current in Active Mode as a Function of Frequency Note: Operating Conditions apply. MC_XC2XN_IS fSYS [MHz] IS [mA] 20 40 80 60 100 ISACTtyp ISACTmax

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 85 V1.6, 2014-06 Note: A fraction of the leakage current flows through domain DMP_A (pin VDDPA). This current can be calculated as 7,000 × e-α, with α = 5000 / (273 + 1.3 × TJ). For TJ = 150°C, this results in a current of 160 μA. Leakage Power Consumption Calculation The leakage power consumption can be calculated according to the following formulas: ILK0 = 500,000 × e-α with α = 3000 / (273 + B × TJ) Parameter B must be replaced by

• 1.0 for typical values
• 1.6 for maximum values I LK1 = 530,000 × e-α with α = 5000 / (273 + B × TJ) Parameter B must be replaced by
• 1.0 for typical values
• 1.3 for maximum values Table 19 Leakage Power Consumption Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Leakage supply current (DMP_1 off)1) 1) The supply current caused by leak age depends mainly on the junction temperature and the supply voltage. The temperature difference between the junction temperature TJ and the ambient temperature TA must be taken into account. As this fraction of the supply current does not depend on device activity, it must be added to other power consumption values. ILK0 CC − 20 35 μA TJ=2 5° C2) − 115 330 μA TJ=8 5° C2) − 270 880 μA TJ=1 2 5° C2) − 420 1,450 μA TJ=1 5 0° C2) Leakage supply current (DMP_1 powered)1) ILK1 CC − 0.03 0.04 mA TJ=2 5° C2) 2) All inputs (including pins configured as inputs) are set at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP and all outputs (including pins configured as outputs) are disconnected. − 0.5 1.2 mA TJ=8 5° C2) − 1.9 5.5 mA TJ=1 2 5° C2) − 3.9 12.2 mA TJ=1 5 0° C2)

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 86 V1.6, 2014-06 Figure 15 Leakage Supply Current as a Function of Temperature MC_XC2XN_ILK150 TJ [°C] ILK [mA] 0 50 150 100-50 ILK0max ILK0typ ILK1max ILK1typ

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 87 V1.6, 2014-06

4.4 Analog/Digital Converter Parameters

These parameters describe the conditions for optimum ADC performance. Note: Operating Conditions apply. Table 20 ADC Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Switched capacitance at an analog input CAINSW CC −− 4 pF not subject to production test Total capacitance at an analog input CAINT CC −− 10 pF not subject to production test Switched capacitance at the reference input CAREFSW CC −− 7 pF not subject to production test Total capacitance at the reference input CAREFT CC −− 15 pF not subject to production test Differential Non-Linearity Error |EADNL| CC − 0.8 1 LSB Gain Error |EAGAIN| CC − 0.4 0.8 LSB Integral Non-Linearity | EAINL| CC − 0.8 1.2 LSB Offset Error | EAOFF| CC − 0.5 0.8 LSB Analog clock frequency fADCI SR 0.5 − 16.5 MHz voltage_range= lower 0.5 − 20 MHz voltage_range= upper Input resistance of the selected analog channel RAIN CC −− 2k O h m not subject to production test Input resistance of the reference input RAREF CC −− 2k O h m not subject to production test

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 88 V1.6, 2014-06 Broken wire detection delay against VAGND2) tBWG CC −− 503) Broken wire detection delay against VAREF tBWR CC −− 504) Conversion time for 8-bit result tc8 CC (11+ S TC) x tADCI + 2 x tSYS Conversion time for 10-bit result tc10 CC (13+ S TC) x tADCI + 2 x tSYS Total Unadjusted Error |TUE| CC − 12L S B 5) Wakeup time from analog powerdown, fast mode tWAF CC −− 4 μs Wakeup time from analog powerdown, slow mode tWAS CC −− 15 μs Analog reference ground VAGND SR VSS - 0.05 − 1.5 V Analog input voltage range VAIN SR VAGND − VAREF V 6) Analog reference voltage VAREF SR VAGND + 1.0 − VDDPA + 0.05 V 1) These parameter values cover the complete operating range. Under relaxed operating conditions (temperature, supply voltage) typical values can be us ed for calculation. At room temperature and nominal supply voltage the following typical values can be used: CAINTtyp = 12 pF, CAINStyp = 5 pF, RAINtyp = 1.0 kOhm, CAREFTtyp = 15 pF, CAREFStyp = 10 pF, RAREFtyp = 1.0 kOhm. 2) This parameter includes the sample time (also the a dditional sample time specified by STC), the time to determine the digital result and the time to load the result register with the conversion result. Values for the basic clock tADCI depend on programming. 3) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 500 μs. Result below 10% (66H) Table 20 ADC Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 89 V1.6, 2014-06 Figure 16 Equivalent Circuitry for Analog Inputs 4) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 10 μs. This function is influenced by le akage current, in particular at high temperature. Result above 80% (332H) 5) TUE is tested at VAREF = VDDPA = 5.0 V, VAGND = 0 V. It is verified by design for all other voltages within the defined voltage range. The specified TUE is valid only if the absolute sum of input overload currents on analog port pins (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the measurement time. 6) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. A/D Converter MCS05570 RSource VAIN CExt CAINT CAINS- RAIN, On CAINS

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 90 V1.6, 2014-06 Sample time and conversion time of the XC226xN’s A/D converters are programmable. The timing above can be calculated using Table 21. The limit values for fADCI must not be exceeded when selecting the prescaler value. Converter Timing Example A: Converter Timing Example B: Table 21 A/D Converter Computation Table GLOBCTR.5-0 (DIVA) A/D Converter Analog Clock fADCI INPCRx.7-0 (STC) Sample Time tS 1) The selected sample time is doubled if broken wire detection is active (due to the presampling phase). 000000B fSYS 00H tADCI × 2 000001B fSYS / 2 01H tADCI × 3 000010B fSYS / 3 02H tADCI × 4 : fSYS / (DIVA+1) : tADCI × (STC+2) 111110B fSYS / 63 FEH tADCI × 256 111111B fSYS / 64 FFH tADCI × 257 Assumptions: fSYS = 80 MHz (i.e. tSYS = 12.5 ns), DIVA = 03H, STC = 00H Analog clock fADCI = fSYS / 4 = 20 MHz, i.e. tADCI = 50 ns Sample time tS = tADCI × 2 = 100 ns Conversion 10-bit: tC10 = 13 × tADCI + 2 × tSYS = 13 × 50 ns + 2 × 12.5 ns = 0.675 μs Conversion 8-bit: tC8 = 11 × tADCI + 2 × tSYS = 11 × 50 ns + 2 × 12.5 ns = 0.575 μs Assumptions: fSYS = 40 MHz (i.e. tSYS = 25 ns), DIVA = 02H, STC = 03H Analog clock fADCI = fSYS / 3 = 13.3 MHz, i.e. tADCI = 75 ns Sample time tS = tADCI × 5 = 375 ns Conversion 10-bit: tC10 = 16 × tADCI + 2 × tSYS = 16 × 75 ns + 2 × 25 ns = 1.25 μs Conversion 8-bit: tC8 = 14 × tADCI + 2 × tSYS = 14 × 75 ns + 2 × 25 ns = 1.10 μs

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 91 V1.6, 2014-06

4.5 System Parameters

The following parameters specify several aspects which are important when integrating the XC226xN into an application system. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 22 Various System Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Short-term deviation of internal clock source frequency1) ΔfINT CC -1 − 1% ΔTJ ≤ 10°C Internal clock source frequency fINT CC 4.8 5.0 5.2 MHz Wakeup clock source frequency fWU CC 400 − 700 kHz FREQSEL= 00 210 − 390 kHz FREQSEL= 01 140 − 260 kHz FREQSEL= 10 110 − 200 kHz FREQSEL= 11 Startup time from power- on with code execution from Flash tSPO CC 1.5 2.0 2.4 ms fWU= 500 kHz Startup time from standby mode with code execution from Flash tSSB CC 2.6 3.8 4.1 ms fWU= 140 kHz 1.6 2.1 2.5 ms fWU= 500 kHz Startup time from stopover mode with code execution from PSRAM tSSO CC 11 / fWU − 12 / fWU μs Core voltage (PVC) supervision level VPVC CC VLV - 0.03 VLV VLV + 0.074) V 5) Supply watchdog (SWD) supervision level VSWD CC VLV - 0.106) VLV VLV + 0.15 V voltage_range= lower 5) VLV - 0.15 VLV VLV + 0.15 V voltage_range= upper 5) VLV - 0.30 VLV VLV + 0.30 V VLV = 5.5 V 5)

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 92 V1.6, 2014-06 Conditions for tSPO Timing Measurement The time required for the transition from Power-on to Base mode is called tSPO. It is measured under the following conditions: Precondition: The pad supply is valid, i.e. VDDPB is above 3.0V and remains above 3.0V even though the XC226xN is starting up. No debugger is attached. Start condition: Power-on reset is removed (PORST = 1). End condition: External pin toggle caused by first user instruction executed from FLASH after startup. Conditions for tSSB Timing Measurement The time required for the transition from Standby to Base mode is called tSSB. It is measured under the following conditions: Precondition: The Standby mode has been entered using the procedure defined in the Programmer’s Guide. Start condition: Pin toggle on ESR pin triggering the startup sequence. End condition: External pin toggle caused by first user instruction executed from FLASH after startup. Conditions for tSSO Timing Measurement The time required for the transition from Stopover to Stopover Waked-Up mode is called tSSO. It is measured under the following conditions: Precondition: The Stopover mode has been entered using the procedure defined in the Programmer’s Guide. Start condition: Pin toggle on ESR pin triggering the startup sequence. End condition: External pin toggle caused by first user instruction executed from PSRAM after startup. 1) The short-term frequency deviation refe rs to a timeframe of a few hours and is measured relative to the current frequency at the beginning of the respective timeframe. This parameter is useful to determine a time span for re-triggering a LIN synchronization. 2) This parameter is tested for the fastest and the slowes t selection. The medium selections are not subject to production test - verified by design/characterization 3) fWU in MHz 4) This value includes a hysteresis of approximately 50 mV for rising voltage. 5) VLV = selected SWD voltage level 6) The limit VLV - 0.10 V is valid for the OK1 level. The limit for the OK2 level is VLV - 0.15 V.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 93 V1.6, 2014-06 Coding of bit fields LEVxV in SWD Configuration Registers After power-on the supply watch dog is precon figured to operate in the lower voltage range. Coding of bit fields LEVxV in PVC Configuration Registers The core voltages are controlled internally to the nominal value of 1.5 V; a variation of ±10 % is allowed. These operation conditions limit the possible PVC monitoring values to the predefined reset values shown in Table 24. Table 23 Coding of bit fields LEVxV in Register SWDCON0 Code Voltage Level Notes 1) 1) The indicated default levels for LEV1V and LEV2V are selected automatically after a power-on reset. 0000B - out of valid operation range 0001B 3.0 V LEV1V: reset request 0010B - 0101B 3.1 V- 3.4 V step width is 0.1 V 0110B 3.6 V 0111B 4.0 V 1000B 4.2 V 1001B 4.5 V LEV2V: no request 1010B - 1110B 4.6 V - 5.0 V step width is 0.1 V 1111B 5.5 V Table 24 Coding of bit fields LEVxV in Registers PVCyCONz Code Voltage Level Notes 1) The indicated default levels for LEV1V and LEV2V are selected automatically after a power-on reset. 000B-011B - out of valid operation range 100B 1.35 V LEV1V: reset request 101B 1.45 V LEV2V: interrupt request2) 2) Due to variations of the tolerance of both the Embedded Voltage Regulators (EVR) and the PVC levels, this interrupt can be triggered inadvertently, even though the core voltage is within the normal range. It is, therefore, recommended not to use this warning level. 110B - 111B - out of valid operation range

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 94 V1.6, 2014-06

4.6 Flash Memory Parameters

The XC226xN is delivered with all Flash sectors erased and with no protection installed. The data retention time of the XC226xN’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 25 Flash Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Parallel Flash module program/erase limit depending on Flash read activity NPP SR −−2 1) 1) The unused Flash module(s) can be erased/programmed wh ile code is executed and/or data is read from only one Flash module or from PSRAM. The Flash modu le that delivers code/data can, of course, not be erased/programmed. NFL_RD≤ 1 −−1 2) NFL_RD>1 Flash erase endurance for security pages NSEC SR 10 −− cycles tRET≥ 20 years Flash wait states3) NWSFLAS H SR 1 −− fSYS≤ 8M H z 2 −− fSYS≤ 13 MHz 3 −− fSYS≤ 17 MHz 4 −− fSYS>1 7M H z Erase time per sector/page tER CC − 74) 8.0 ms Programming time per page tPR CC − 34) 3.5 ms Data retention time tRET CC 20 −− years NER≤ 1,000 cycl es Drain disturb limit NDD SR 32 −− cycles Number of erase cycles NER SR −−15.000 cycles tRET≥ 5y e a r s ; Valid for Flash module 1 (up to 64 kbytes) −−1.000 cycles tRET≥ 20 years

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 95 V1.6, 2014-06 Access to the XC226xN Flash modules is controlled by the IM B. Built-in prefetch mechanisms optimize the performance for sequential access. Flash access waitstates only affect non-sequential access. Due to prefetch mechanisms, the performance for sequential access (depending on the software structure) is only partially influenced by waitstates. 2) Flash module 1 can be erased/programmed while code is executed and/or data is read from Flash module 0. 3) Value of IMB_IMBCTRL.WSFLASH. 4) Programming and erase times depend on the internal Fl ash clock source. The control state machine needs a few system clock cycles. This increases the stated dur ations noticably only at extremely low system clock frequencies.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 96 V1.6, 2014-06

4.7 AC Parameters

These parameters describe the dynamic behavior of the XC226xN.

4.7.1 Testing Waveforms

These values are used for characterization and production testing (except pin XTAL1). Figure 17 Input Output Waveforms Figure 18 Floating Waveforms MCD05556C

0.3 VDDP

(driven by tester) Output Signal (measured) Hold time Output delay Output delay Hold time Output timings refer to the rising edge of CLKOUT. Input timings are calculated from the time, when the input signal reaches VIH or VIL, respectively.

0.2 VDDP

0.8 VDDP

0.7 VDDP

VLoad + 0.1 V VLoad - 0.1 V VOH - 0.1 V VOL + 0.1 V For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH /VOL level occurs ( IOH / IOL = 20 mA).

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 97 V1.6, 2014-06

4.7.2 Definition of Internal Timing

The internal operation of the XC226xN is controlled by the internal system clock fSYS. Because the system clock signal fSYS can be generated from a number of internal and external sources using different mechanism s, the duration of the system clock periods (TCSs) and their variation (as well as th e derived external timing) depend on the mechanism used to generate fSYS. This must be considered when calculating the timing for the XC226xN. Figure 19 Generation Mechanisms for the System Clock Note: The example of PLL operation shown in Figure 19 uses a PLL factor of 1:4; the example of prescaler operation uses a divider factor of 2:1. The specification of the external timing (AC Characteristics) depends on the period of the system clock (TCS). M C_XC2X_CLOCKGEN Phase Locked Loop Operation (1:N) fIN Direct Clock Drive (1:1) Prescaler Operation (N:1) fSYS fIN fSYS fIN fSYS TCS TCS TCS

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 98 V1.6, 2014-06 Direct Drive When direct drive operation is selected (SYSCON0.CLKSEL = 11B), the system clock is derived directly from the input clock signal CLKIN1: fSYS = fIN. The frequency of fSYS is the same as the frequency of fIN. In this case the high and low times of fSYS are determined by the duty cycle of the input clock fIN. Selecting Bypass Operation from the XTAL11) input and using a divider factor of 1 results in a similar configuration. Prescaler Operation When prescaler operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 1B), the system clock is derived either from the crystal oscillat or (input clock signal XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1): fSYS = fOSC / K1. If a divider factor of 1 is selected, the frequency of fSYS equals the frequency of fOSC. In this case the high and low times of fSYS are determined by the duty cycle of the input clock fOSC (external or internal). The lowest system clock fr equency results from selecting the maximum value for the divider factor K1: fSYS = fOSC / 1024.

4.7.2.1 Phase Locked Loop (PLL)

When PLL operation is sele cted (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 0B), the on-chip phase locked loop is enabled and provides the system clock. The PLL multiplies the input frequency by the factor F (fSYS = fIN × F). F is calculated from the input divider P (= PDIV+1), the multiplication factor N (= NDIV+1), and the output divider K2 (= K2DIV+1): The input clock can be derived either from an external source at XTAL1 or from the on- chip clock source. The PLL circuit synchronizes the system clock to the input clock. This synchronization is performed smoothly so that the system clock frequency does not change abruptly. Adjustment to the input clock continuously changes the frequency of fSYS so that it is locked to fIN. The slight variation causes a jitter of fSYS which in turn affects the duration of individual TCSs. 1) Voltages on XTAL1 must comply to the core supply voltage VDDIM.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 99 V1.6, 2014-06 The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the minimum TCS possible under the given circumstances. The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is constantly adjusting its output frequency to correspond to the input frequency (from crystal or oscillator), the accumulated jitte r is limited. This means that the relative deviation for periods of more than one TCS is lower than for a single TCS (see formulas and Figure 20). This is especially important for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the respective timeframe. The VCO outp ut clock is divided by the output prescaler K2 to generate the system clock signal fSYS. The number of VCO cycles is K2 × T, where T is the number of consecutive fSYS cycles (TCS). The maximum accumulated jitter (long-term jitter) DTmax is defined by: DTmax [ns] = ±(220 / (K2 × fSYS) + 4.3) This maximum value is applicable, if either the number of clock cycles T > (fSYS / 1.2) or the prescaler value K2 > 17. In all other cases for a timeframe of T × TCS the accumulated jitter D T is determined by: fSYS in [MHz] in all formulas. Example, for a period of 3 TCSs @ 33 MHz and K2 = 4: D max = ±(220 / (4 × 33) + 4.3) = 5.97 ns (Not applicable directly in this case!) = 1.7 ns Example, for a period of 3 TCSs @ 33 MHz and K2 = 2: Dmax = ±(220 / (2 × 33) + 4.3) = 7.63 ns (Not applicable directly in this case!) = 1.4 ns

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 100 V1.6, 2014-06 Figure 20 Approximated Accumulated PLL Jitter Note: The specified PLL jitter values are va lid if the capacitive load per pin does not exceed CL =2 0p F . The maximum peak-to-peak noise on the pad supply voltage (measured between VDDPB pin 100 and VSS pin 1) is limited to a peak-to-peak voltage of VPP = 50 mV. This can be achieved by appropriate blocking of the supply voltage as close as possible to the supply pins and using PCB supply and ground planes. PLL frequency band selection Different frequency bands can be selected for the VCO so that the operation of the PLL can be adjusted to a wide range of input and output frequencies: MC_XC 2X_JITTER Cycles T0 Acc. jitter DT 20 40 60 80 100 ns fSYS = 66 MHz fVCO = 132 MHz fVCO = 66 MHz ±9 fSYS = 33 MHz

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 101 V1.6, 2014-06

4.7.2.2 Wakeup Clock

When wakeup operation is selected (SYSCON0.CLKSEL = 00 B), the system clock is derived from the low-frequency wakeup clock source: fSYS = fWU. In this mode, a basic functionality can be maintained without requiring an external clock source and while minimizing the power consumption.

4.7.2.3 Selecting and Changing the Operating Frequency

When selecting a clock source and the clock generation method, the required parameters must be carefully written to t he respective bit fields, to avoid unintended intermediate states. Many applications change the fr equency of the system clock ( fSYS) during operation in order to optimize system performance and power consumption. Changing the operating frequency also changes the switching currents, which influences the power supply. To ensure proper operation of the on-chip EVRs while they generate the core voltage, the operating frequency shall only be changed in certain steps. This prevents overshoots and undershoots of the supply voltage. To avoid the indicated problems, recommended sequences are provided which ensure the intended operation of the clock system interacting with the power system. Please refer to the Programmer’s Guide. Table 26 System PLL Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. VCO output frequency fVCO CC 50 − 110 MHz VCOSEL= 00b; VCOmode= controlled 10 − 40 MHz VCOSEL= 00b; VCOmode= free running 100 − 160 MHz VCOSEL= 01b; VCOmode= controlled 20 − 80 MHz VCOSEL= 01b; VCOmode= free running

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 102 V1.6, 2014-06

4.7.3 External Clock Input Parameters

These parameters specify the external clock generation for the XC226xN. The clock can be generated in two ways:

• By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2.
• By supplying an external clock signal – This clock signal can be supplied either to pin XTAL1 (core voltage domain) or to pin CLKIN1 (IO voltage domain). If connected to CLKIN1, the input signal must reach the defined input levels VIL and VIH. If connected to XTAL1, a minimum amplitude VAX1 (peak-to-peak voltage) is sufficient for the operation of the on-chip oscillator. Note: The given clock timing parameters ( t1 … t4) are only valid for an external clock input signal. Note: Operating Conditions apply. Table 27 External Clock Input Characteristics Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Oscillator frequency fOSC SR 4 − 40 MHz Input= Clock Signal 4 − 16 MHz Input= Crystal or Ceramic Resonator XTAL1 input current absolute value IIL| CC −− 20 μA Input clock high time t1 SR 6 −− ns Input clock low time t2 SR 6 −− ns Input clock rise time t3 SR − 88n s Input clock fall time t4 SR − 88n s Input voltage amplitude on XTAL1 VAX1 SR 0.3 x VDDIM −− V fOSC≥ 4M H z ; fOSC<1 6M H z 0.4 x VDDIM −− V fOSC≥ 16 MHz; fOSC< 25 MHz 0.5 x VDDIM −− V fOSC≥ 25 MHz; fOSC≤ 40 MHz Input voltage range limits for signal on XTAL1 VIX1 SR -1.7 + VDDIM − 1.7 V 2)

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 103 V1.6, 2014-06 Figure 21 External Clock Drive XTAL1 Note: For crystal or ceramic resonator operation, it is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimum parameters for oscillator operation. The manufacturers of crystals and ceramic resonato rs offer an oscillator evaluation service. This evaluation checks the crystal/resonator specification limits to ensure a reliable oscillator operation. 1) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by VIX1. 2) Overload conditions must not occur on pin XTAL1. MC_EXTCLOCK tOSC = 1/fOSC VOFF VAX1 0.1 VAX 1

0.9 VAX 1

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 104 V1.6, 2014-06

4.7.4 Pad Properties

The output pad drivers of t he XC226xN can operate in several user-selectable modes. Strong driver mode allows controlling ex ternal components requiring higher currents such as power bridges or LEDs. Reducing the driving power of an output pad reduces electromagnetic emissions (E ME). In strong driver mode, selecting a slower edge reduces EME. The dynamic behavior, i.e. the rise time and fall time, depends on the applied external capacitance that must be charged and discharged. Timing values are given for a capacitance of 20 pF, unless otherwise noted. In general, the performance of a pad driver depends on the available supply voltage VDDP. Therefore the following tables list the pad parameters for the upper voltage range and the lower voltage range, respectively. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 28 is valid under the following conditions: VDDP≤ 5.5 V; VDDPtyp. 5 V; VDDP≥ 4.5 V Table 28 Standard Pad Paramete rs for Upper Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Maximum output driver current (absolute value)1) IOmax CC −− 4.0 mA Driver_Strength =M e d i u m −− 10 mA Driver_Strength =S t r o n g −− 0.5 mA Driver_Strength =W e a k Nominal output driver current (absolute value) IOnom CC −− 1.0 mA Driver_Strength =M e d i u m −− 2.5 mA Driver_Strength =S t r o n g −− 0.1 mA Driver_Strength =W e a k

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 105 V1.6, 2014-06 Rise and Fall times (10% - 90%) tRF CC −− 23 + 0.6 x CL ns CL≥ 20 pF; CL≤ 100 pF; Driver_Strength =M e d i u m −− 11.6 + 0.22 x CL ns CL≥ 20 pF; CL≤ 100 pF; Driver_Strength =S t r o n g; Driver_Edge= Medium −− 4.2 + 0.14 x CL ns CL≥ 20 pF; CL≤ 100 pF; Driver_Strength =S t r o n g; Driver_Edge= Sharp −− 20.6 + 0.22 x CL ns CL≥ 20 pF; CL≤ 100 pF; Driver_Strength =S t r o n g; Driver_Edge= Slow −− 212 + 1.9 x CL ns CL≥ 20 pF; CL≤ 100 pF; Driver_Strength =W e a k 1) An output current above | IOXnom| may be drawn from up to three pins at the same time. For any group of 16 neighboring output pins, the total output current in each direction (ΣIOL and Σ-IOH) must remain below 50 mA. Table 28 Standard Pad Paramete rs for Upper Voltage Range (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 106 V1.6, 2014-06 Table 29 Standard Pad Paramete rs for Lower Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Maximum output driver current (absolute value)1) IOmax CC −− 2.5 mA Driver_Strength =M e d i u m −− 10 mA Driver_Strength =S t r o n g −− 0.5 mA Driver_Strength =W e a k Nominal output driver current (absolute value) IOnom CC −− 1.0 mA Driver_Strength =M e d i u m −− 2.5 mA Driver_Strength =S t r o n g −− 0.1 mA Driver_Strength =W e a k

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 107 V1.6, 2014-06 Rise and Fall times (10% - 90%) tRF CC −− 37 + 0.65 x CL ns CL≥ 20 pF; CL≤ 100 pF; Driver_Strength =M e d i u m −− 24 + 0.3 x CL ns CL≥ 20 pF; CL≤ 100 pF; Driver_Strength =S t r o n g; Driver_Edge= Medium −− 6.2 + 0.24 x CL ns CL≥ 20 pF; CL≤ 100 pF; Driver_Strength =S t r o n g; Driver_Edge= Sharp −− 34 + 0.3 x CL ns CL≥ 20 pF; CL≤ 100 pF; Driver_Strength =S t r o n g; Driver_Edge= Slow −− 500 + 2.5 x CL ns CL≥ 20 pF; CL≤ 100 pF; Driver_Strength =W e a k 1) An output current above | IOXnom| may be drawn from up to three pins at the same time. For any group of 16 neighboring output pins, the total output current in each direction (ΣIOL and Σ-IOH) must remain below 50 mA. Table 29 Standard Pad Paramete rs for Lower Voltage Range (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 108 V1.6, 2014-06

4.7.5 External Bus Timing

The following parameters specify the behavior of the XC226xN bus interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Figure 22 CLKOUT Signal Timing Note: The term CLKOUT refers to the reference clock output signal which is generated by selecting fSYS as the source signal for the clock output signal EXTCLK on pin P2.8 and by enabling the high-speed clock driver on this pin. Table 30 Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. CLKOUT Cycle Time1) 1) The CLKOUT cycle time is influenced by PLL jitter. For longer periods the relative deviation decreases (see PLL deviation formula). t5 CC − 1 / fSYS − ns CLKOUT high time t6 CC 3 −− CLKOUT low time t7 CC 3 −− CLKOUT rise time t8 CC −− 3n s CLKOUT fall time t9 CC −− 3 MC_X_EBCCLKOUT CLKOUT t5 t6 t7 t8

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 109 V1.6, 2014-06 Variable Memory Cycles External bus cycles of the XC226xN are executed in five consecutive cycle phases (AB, C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx registers) to adapt the external bus cycles to the res pective external module (memory, peripheral, etc.). The duration of the access phase can optiona lly be controlled by the external module using the READY handshake input. This table provides a summary of the phases and the ranges for their length. Note: The bandwidth of a parameter (from minimum to maximum value) covers the whole operating range (temperature, voltage) as well as process variations. Within a given device, however, this bandwidth is smaller than the specified range. This is also due to interdependencies between certain parameters. Some of these interdependencies are described in additional notes (see standard timing). Note: Operating Conditions apply. Table 32 is valid under the following conditions: CL= 20 pF; voltage_range= upper ; voltage_range= upper Table 31 Programmable Bus Cycle Phases (see timing diagrams) Bus Cycle Phase Parameter Valid Values Unit Address setup phase, the standard duration of this phase (1 … 2 TCS) can be extended by 0 … 3 TCS if the address window is changed tpAB 1 … 2 (5) TCS Command delay phase tpC 0 … 3 TCS Write Data setup/MUX Tristate phase tpD 0 … 1 TCS Access phase tpE 1 … 32 TCS Address/Write Data hold phase tpF 0 … 3 TCS Table 32 External Bus Timing for Upper Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Output valid delay for RD WR(L/H) t10 CC − 71 3 n s Output valid delay for BHE, ALE t11 CC − 71 4 n s Address output valid delay for A23 ... A0 t12 CC − 81 4 n s

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 110 V1.6, 2014-06 Table 33 is valid under the following conditions: CL= 20 pF; voltage_range= lower ; voltage_range= lower Address output valid delay for AD15 ... AD0 (MUX mode) t13 CC − 81 5 n s Output valid delay for CS t14 CC − 71 3 n s Data output valid delay for AD15 ... AD0 (write data, MUX mode) t15 CC − 81 5 n s Data output valid delay for D15 ... D0 (write data, DEMUX mode) t16 CC − 81 5 n s Output hold time for RD, WR(L/H) t20 CC -2 6 8 ns Output hold time for BHE, ALE t21 CC -2 6 10 ns Address output hold time for AD15 ... AD0 t23 CC -3 6 8 ns Output hold time for CS t24 CC -3 6 11 ns Data output hold time for AD0 t25 CC -3 6 8 ns Input setup time for READY, D15 ... D0, AD15 ... AD0 t30 SR 25 15 − ns Input hold time READY, t31 SR 0 -7 − ns 1) Read data are latched with the same internal cloc k edge that triggers the address change and the rising edge of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can change after the rising edge of RD. Table 32 External Bus Timing for Upper Voltage Range (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 111 V1.6, 2014-06 Table 33 External Bus Timing for Lower Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Output valid delay for RD, WR(L/H) t10 CC − 11 20 ns Output valid delay for BHE, ALE t11 CC − 10 21 ns Address output valid delay for A23 ... A0 t12 CC − 11 22 ns Address output valid delay for AD15 ... AD0 (MUX mode) t13 CC − 10 22 ns Output valid delay for CS t14 CC − 10 13 ns Data output valid delay for AD15 ... AD0 (write data, MUX mode) t15 CC − 10 22 ns Data output valid delay for D15 ... D0 (write data, DEMUX mode) t16 CC − 10 22 ns Output hold time for RD, WR(L/H) t20 CC -2 8 10 ns Output hold time for BHE, ALE t21 CC -2 8 10 ns Address output hold time for AD15 ... AD0 t23 CC -3 8 10 ns Output hold time for CS t24 CC -3 8 11 ns Data output hold time for AD0 t25 CC -3 8 10 ns Input setup time for READY, D15 ... D0, AD15 ... AD0 t30 SR 29 17 − ns Input hold time READY, 1) Read data are latched with the same internal cloc k edge that triggers the address change and the rising edge of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can change after the rising edge of RD. t31 SR 0 -9 − ns

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 112 V1.6, 2014-06 Figure 23 Multiplexed Bus Cycle CLKOUT tpAB tpC tpD tpE tpF ALE t21 t11 A23-A16, BHE, CSx t11/t12/t14 RD WR(L/H) t20 t10 Data InAD15-AD0 (read) t30 t31 MC_X_EBCMUX AD15-AD0 (write) t13 t15 t25 t13 t23 Data OutLow Address High Address Low Address t24

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 113 V1.6, 2014-06 Figure 24 Demultiplexed Bus Cycle

4.7.5.1 Bus Cycle Control with the READY Input

The duration of an external bus cycle can be controlled by the external circuit using the READY input signal. The polarity of this input signal can be selected. Synchronous READY permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal CLKOUT. An asynchronous READY signal puts no timing constraints on the input signal but incurs a minimum of one waitstate due to the addi tional synchronization stage. The minimum Address tpAB tpC tpD tpE tpF t21 t11 t11/t12/t14 t20 t10 Data In t30 t31 MC_X_EBCDEMUX t16 t25 CLKOUT ALE A23-A0, BHE, CSx RD WR(L/H) D15-D0 (read) D15-D0 (write) Data Out t24

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 114 V1.6, 2014-06 duration of an asynchronous READY signal for safe synchronization is one CLKOUT period plus the input setup time. An active READY signal can be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If the next bus cycle is controlled by READY, an active READY signal must be disabled before the first valid sample point in the next bus cycle. This sample point depends on the programmed phases of the next cycle. Figure 25 READY Timing MC_X_EBCREADY READY Asynchron . Not Rdy READY Data Out t25 t30 D15-D0 (write) READY Synchronous Not Rdy READY Data InD15-D0 (read) t10 RD, WR tpD tpE tpRDY tpF CLKOUT t20 t30 t31 t31 t30 t31 t30 t31 t30 t31

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 115 V1.6, 2014-06 Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”) a READY-controlled waitstate is inserted (tpRDY), sampling the READY input active at the indicated sampling point (“Ready”) terminates the currently running bus cycle. Note the different sampling points for synchronous and asynchronous READY. This example uses one mandatory wait state (see tpE) before the READY input value is used.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 116 V1.6, 2014-06

4.7.6 Synchronous Serial Interface Timing

The following parameters are applicable for a USIC channel operated in SSC mode. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 34 is valid under the following conditions: CL=2 0p F ; SSC=m a s t e r; voltage_range= upper Table 35 is valid under the following conditions: CL=2 0p F ; SSC=m a s t e r; voltage_range= lower Table 34 USIC SSC Master Mode Timing for Upper Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Slave select output SELO active to first SCLKOUT transmit edge t1 CC tSYS - 81) 1) tSYS = 1 / fSYS −− ns Slave select output SELO inactive after last SCLKOUT receive edge t2 CC tSYS - 61) −− ns Data output DOUT valid time t3 CC -6 − 9n s Receive data input setup time to SCLKOUT receive edge t4 SR 31 −− ns Data input DX0 hold time from SCLKOUT receive edge t5 SR -4 −− ns

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 117 V1.6, 2014-06 Table 36 is valid under the following conditions: CL=2 0p F ; SSC= slave ; voltage_range= upper Table 35 USIC SSC Master Mode Timing for Lower Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Slave select output SELO active to first SCLKOUT transmit edge t1 CC tSYS - 101) 1) tSYS = 1 / fSYS −− ns Slave select output SELO inactive after last SCLKOUT receive edge t2 CC tSYS - 91) −− ns Data output DOUT valid time t3 CC -7 − 11 ns Receive data input setup time to SCLKOUT receive edge t4 SR 40 −− ns Data input DX0 hold time from SCLKOUT receive edge t5 SR -5 −− ns Table 36 USIC SSC Slave Mode Timi ng for Upper Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Select input DX2 setup to first clock input DX1 transmit edge t10 SR 7 −− ns Select input DX2 hold after last clock input DX1 receive edge t11 SR 7 −− ns Receive data input setup time to shift clock receive edge t12 SR 7 −− ns

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 118 V1.6, 2014-06 Table 37 is valid under the following conditions: CL=2 0p F ; SSC= slave ; voltage_range= lower Data input DX0 hold time from clock input DX1 receive edge1) t13 SR 5 −− ns Data output DOUT valid time t14 CC 7 − 33 ns 1) These input timings are valid for asyn chronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0). Table 37 USIC SSC Slave Mode Timi ng for Lower Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Select input DX2 setup to first clock input DX1 transmit edge 1) These input timings are valid for asyn chronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0). t10 SR 7 −− ns Select input DX2 hold after last clock input DX1 receive edge t11 SR 7 −− ns Receive data input setup time to shift clock receive edge t12 SR 7 −− ns Data input DX0 hold time from clock input DX1 receive edge t13 SR 5 −− ns Data output DOUT valid time t14 CC 8 − 41 ns Table 36 USIC SSC Slave Mode Timi ng for Upper Voltage Range (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 119 V1.6, 2014-06 Figure 26 USIC - SSC Master/Slave Mode Timing Note: This timing diagram shows a standard configuration where the slave select signal is low-active and the serial clock signal is not shifted and not inverted. t2t1 USIC_SSC_TMGX.VSD Clock Output SCLKOUT Data Output DOUT t3 t3 Data valid First Transmit Edge Data Input DX0 Select Output SELOx Active Master Mode Timing Slave Mode Timing t11t10 Clock Input DX1 Data Output DOUT t14 t14 Datavalid Data Input DX0 Select Input DX2 Active t13 t12 Transmit Edge: with this clock edge, transmit data is shifted to transmit data output. Receive Edge : with this clock edge , receive data at receive data input is latched. Receive Edge Last Receive Edge InactiveInactive Transmit Edge InactiveInactive First Transmit Edge Receive Edge Transmit Edge Last Receive Edge Data valid Datavalid t12 t13 Drawn for BRGH.SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal .

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 120 V1.6, 2014-06

4.7.7 Debug Interface Timing

The debugger can communicate with the XC226xN either via the 2-pin DAP interface or via the standard JTAG interface. Debug via DAP The following parameters are applicable for communication through the DAP debug interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 38 is valid under the following conditions: CL= 20 pF; voltage_range= upper Table 39 is valid under the following conditions: CL= 20 pF; voltage_range= lower Table 38 DAP Interface Timing for Upper Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. DAP0 clock period1) 1) See the DAP chapter for clock rate restrictions in the Active::IDLE protocol state. t11 SR 25 −− ns DAP0 high time t12 SR 8 −− ns DAP0 low time1) t13 SR 8 −− ns DAP0 clock rise time t14 SR −− 4n s DAP0 clock fall time t15 SR −− 4n s DAP1 setup to DAP0 rising edge t16 SR 6 −− ns DAP1 hold after DAP0 rising edge t17 SR 6 −− ns DAP1 valid per DAP0 clock period 2) The Host has to find a suitable sampling point by analyzing the sync telegram response. t19 CC 17 20 − ns

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 121 V1.6, 2014-06 Figure 27 Test Clock Timing (DAP0) Table 39 DAP Interface Timing for Lower Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. DAP0 clock period1) 1) See the DAP chapter for clock rate restrictions in the Active::IDLE protocol state. t11 SR 25 −− ns DAP0 high time t12 SR 8 −− ns DAP0 low time1) t13 SR 8 −− ns DAP0 clock rise time t14 SR −− 4n s DAP0 clock fall time t15 SR −− 4n s DAP1 setup to DAP0 rising edge t16 SR 6 −− ns DAP1 hold after DAP0 rising edge t17 SR 6 −− ns DAP1 valid per DAP0 clock period 2) The Host has to find a suitable sampling point by analyzing the sync telegram response. t19 CC 12 17 − ns MC_DAP0

0.9 VDDP

0.5 VDDP

0.1 VDDP

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 123 V1.6, 2014-06 Table 41 is valid under the following conditions: CL= 20 pF; voltage_range= lower TCK low time t3 SR 16 −− ns TCK clock rise time t4 SR −− 8n s TCK clock fall time t5 SR −− 8n s TDI/TMS setup to TCK rising edge t6 SR 6 −− ns TDI/TMS hold after TCK rising edge t7 SR 6 −− ns TDO valid from TCK falling edge (propagation delay) t8 CC − 25 29 ns TDO high impedance to valid output from TCK falling edge 3)2) t9 CC − 25 29 ns TDO valid output to high impedance from TCK falling edge t10 CC − 25 29 ns TDO hold after TCK falling edge t18 CC 5 −− ns 1) Under typical conditions, the JTAG interface can operate at transfer rates up to 20 MHz. 2) The falling edge on TCK is used to generate the TDO timing. 3) The setup time for TDO is given implicitly by the TCK cycle time. Table 41 JTAG Interface Timing for Lower Voltage Range Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. TCK clock period t1 SR 50 −− ns TCK high time t2 SR 16 −− ns TCK low time t3 SR 16 −− ns TCK clock rise time t4 SR −− 8n s TCK clock fall time t5 SR −− 8n s TDI/TMS setup to TCK rising edge t6 SR 6 −− ns Table 40 JTAG Interface Timing for Upper Voltage Range (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 124 V1.6, 2014-06 Figure 30 Test Clock Timing (TCK) TDI/TMS hold after TCK rising edge t7 SR 6 −− ns TDO valid from TCK falling edge (propagation delay) t8 CC − 32 36 ns TDO high impedance to valid output from TCK falling edge 2)1) t9 CC − 32 36 ns TDO valid output to high impedance from TCK falling edge t10 CC − 32 36 ns TDO hold after TCK falling edge t18 CC 5 −− ns 1) The falling edge on TCK is used to generate the TDO timing. 2) The setup time for TDO is given implicitly by the TCK cycle time. Table 41 JTAG Interface Timing for Lower Voltage Range (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. MC_JTAG _TCK

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Electrical Parameters Data Sheet 125 V1.6, 2014-06 Figure 31 JTAG Timing t6 t7 t6 t7 t9 t8 t10 TCK TMS TDI TDO MC_JTAG t18

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Package and Reliability Data Sheet 126 V1.6, 2014-06

5 Package and Reliability

The XC2000 Family devices use the pack age type PG-LQFP (Plastic Green - Low Profile Quad Flat Package). The following sp ecifications must be regarded to ensure proper integration of the XC226xN in its target environment.

5.1 Packaging

These parameters specify the packaging rather than the silicon. Note: To improve the EMC behavior, it is recommended to connect the exposed pad to the board ground, independent of the thermal requirements. Board layout examples are given in an application note. Package Compatibility Considerations The XC226xN is a member of the XC2000 Fa mily of microcontrollers. It is also compatible to a certain extent with members of similar families or subfamilies. Each package is optimized for the device it houses. Therefore, there may be slight differences between packages of the same pi n-count but for different device types. In particular, the size of the Exposed Pad (if present) may vary. If different device types are considered or planned for an application, it must be ensured that the board layout fits all packages under consideration. Table 42 Package Parameters (PG-LQFP-100-8/-15) Parameter Symbol Limit Values Unit Notes Min. Max. Exposed Pad Dimension Ex × Ey – 5.2 × 5.2 mm – Power Dissipation PDISS –0 .8 W – Thermal resistance Junction-Ambient RΘJA – 54 K/W No thermal via 1) 1) Device mounted on a 4-layer board without thermal vias; exposed pad not soldered.

49 K/W 4-layer, no pad 2)

2) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad not soldered.

27 K/W 4-layer, pad 3)

3) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad soldered to the board.

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Package and Reliability Data Sheet 127 V1.6, 2014-06 Package Outlines Figure 32 PG-LQFP-100-8/-15 (Plastic Green Thin Quad Flat Package) All dimensions in mm. You can find complete information about Infineon packages, packing and marking in our Infineon Internet Page “Packages”: http://www.infineon.com/packages 1) Does not include plastic or metal protrusion of 0.25 max. per side PG-LQFP-100-3, -4, -8-PO V11 0.5 0.22 A-B0.08 M C C D 100x 100x ±0.05 1.6 MAX. ±0.05 ±0.05 C 0.1 0.08 1.4 ±0.150.6 H 7˚ MAX. +0.05 -0.060.15 A B Index Marking 100 D 14 1)

0.2 A-B D 100x

4xDA-B0.2 H 14 1) Bottom View 100 Exposed Diepad Ey Ex

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Package and Reliability Data Sheet 128 V1.6, 2014-06

5.2 Thermal Considerations

When operating the XC226xN in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage. The maximum heat that can be dissipated dep ends on the package and its integration into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The power dissipation must be limited so that the average junction temperature does not exceed 150 °C. The difference between junction temperature and ambient temperature is determined by ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA The internal power consumption is defined as PINT = VDDP × IDDP (switching current and leakage current). The static external power consumption caused by the output drivers is defined as PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL) The dynamic external power consumption caused by the output drivers (PIODYN) depends on the capacitive load connected to the respective pins and their switching frequencies. If the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation:

• Reduce VDDP, if possible in the system
• Reduce the system frequency
• Reduce the number of output pins
• Reduce the load on active output drivers

XC2261N/68N, XC2263N/64N/65N XC2000 Family / Value Line Package and Reliability Data Sheet 129 V1.6, 2014-06

5.3 Quality Declarations

The operation lifetime of the XC226xN depends on the applied temperature profile in the application. For a typical example, please refer to Table 44; for other profiles, please contact your Infineon counterpart to calculate the specific lifetime within your application. Table 43 Quality Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Operation lifetime tOP CC −− 20 a See Table 44 and Table 45 ESD susceptibility according to Human Body Model (HBM) VHBM SR −− 2 000 V EIA/JESD22- A114-B Moisture sensitivity level MSL CC −− 3 − JEDEC J-STD-020C Table 44 Typical Usage Temperature Profile Operating Time (Sum = 20 years) Operating Temperat. Notes 1 200 h TJ = 150°C Normal operation 3 600 h TJ = 125°C Normal operation 7 200 h TJ = 110°C Normal operation 12 000 h TJ = 100°C Normal operation 7 × 21 600 h TJ = 0…10°C, …, 60…70°C Power reduction Table 45 Long Time Storage Temperature Profile Operating Time (Sum = 20 years) Operating Temperat. Notes 2 000 h TJ = 150°C Normal operation 16 000 h TJ = 125°C Normal operation 6 000 h TJ = 110°C Normal operation 151 200 h TJ ≤ 150°C No operation

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