X9241A XICOR | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 18

Technical content

REV 1.1.13 12/09/02 Characteristics subject to change without notice. 1 of 18 www.xicor.com X9241A Quad Digitally Controlled Potentiometer (XDCP

FEATURES

  • Four potentiometers in one package
  • 2-wire serial interface
  • Register oriented format —Direct read/write/transfer of wiper positions —Store as many as four positions per potentiometer
  • Terminal Voltages: +5V, -3.0V
  • Cascade resistor arrays
  • Low power CMOS
  • High Reliability —Endurance–100,000 data changes per bit per register —Register data retention–100 years
  • 16-bytes of nonvolatile memory
  • 3 resistor array values —2K Ω to 50K Ω mask programmable —Cascadable for values of 500 Ω to 200K Ω
  • Resolution: 64 taps each pot
  • 20-lead plastic DIP, 20-lead TSSOP and 20-lead SOIC packages

DESCRIPTION

The X9241A integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Low Power/2-Wire Serial Bus BLOCK DIAGRAM Data R1R0 R3R2 VH0/RH0 VL0/RL0 VW0/RW0 Wiper Counter Register (WCR) VH1/RH1 VL1/RL1 VW1/RW1 Register Array Pot 1 Wiper Counter Register (WCR) R1R0 R3R2 SCL SDA Interface and Control Circuitry VH2/ VL2/RL2 VW2/RW2 VH3/RH3 VL3/RL3 VW3/RW3 Register Array Pot 2 Wiper Counter Register (WCR) R1R0 R3R2 Register Array Pot 3 Wiper Counter Register (WCR) R1R0 R3R2 VCC VSS RH2 A PPLICATION N OTE A V A I L A B L E AN20 • AN42–48 • AN50-53 • AN73 • AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135

Characteristics subject to change without notice. 2 of 18REV 1.1.13 12/09/02 www.xicor.com PIN DESCRIPTIONS Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9241A. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Address The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9241A. Potentiometer Pins V H H ), V L L The R H and R L inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. V W W The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. PIN CONFIGURATION PIN NAMES PRINCIPLES OF OPERATION The X9241A is a highly integrated microcircuit incorporating four resistor arrays, their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Symbol Description SCL Serial Clock SDA Serial Data A0–A3 Address V V Potentiometer Pins (terminal equivalent) V Potentiometer Pins (wiper equivalent) VW0/RW0 VH1/RH1 SDA VSS VCC SCL DIP/SOIC/TSSOP X9241A VL0/RL0 VH0/RH0 VW1/RW1 VL1/RL1 VW3/RW3 VL3/RL3 VH3/RH3 VW2/RW2 VL2/RL2 VH2/RH2

Characteristics subject to change without notice. slave device in all applications. byte the X9241A will respond with a final acknowledge. select, and enable, one of sixty-four switches. Figure 1. Slave Address for the X9241A to respond with an acknowledge.

master can then proceed with the next operation. Figure 2. Instruction Byte Format oriented instruction is issued. potentiometers and one of their associated registers. sequence of operations is shown in Figure 4.

Figures 5 and 6 respectively. Figure 3. Two-Byte Instruction Sequence Figure 4. Three-Byte Instruction Sequence Figure 5. Increment/Decrement Instruction Sequence

0101 A 3 A 2 A 1 A 0

0101 A 3 A 2 A 1 A 0 I3 I2 I1 I0 P1 P0 R1 R0

Figure 6. Increment/Decrement Timing Limits Table 1. Instruction Set

Figure 7. Acknowledge Response from Receiver of the register organization and array operation follows. Registers (WCR), one for each XDCP potentiometer. from the value present at power-down. nonvolatile operation and will take a maximum of 10ms. store system parameters or user preference data.

Figure 8. Detailed Potentiometer Block Diagram lower order array (See Figure 9). set to “1”, pot 2 will be cascaded to pot 3. WCR or by using the Increment/Decrement command.

Figure 9. Cascading Arrays

Voltage on SCK, SCL or any address input with respect to V Voltage on any VH/RH, VW/RW or VL/RL I COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Product Temperature Range Min. Max. Supply Voltage X9241A Commercial Industrial 0°C –40°C +70°C +85°C 5V ±10% 5V ±10% ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol Parameter Limits Unit Test ConditionMin. Typ. Max. RTOTAL End to end resistance –20 +20 % Power rating 50 mW 25°C, each pot IW Wiper current mA See Note 7, 8 RW Wiper resistance 40 130 Ω Wiper Current = ± 1mA See Note 7 VTERM Voltage on any VH/RH, VW/RW or VL/RL Pin –3.0 +5 V Noise ≤120 dBV Ref: 1KHz See Note 5 Resolution(4) 1.6 0.4 % See Note 5 Absolute linearity(1) ±1 MI (3) Rw(n)(actual)–Rw(n)(expected) Relative linearity(2) ±0.2 MI (3) Rw(n + 1)–[Rw(n) + MI] Temperature Coefficient of RTOTAL ±300 ppm/°C See Note 5 Ratiometric temperature coefficient ±20 ppm/C See Note 5 CH/CL/CW Potentiometer capacitances 15/15/25 pF See Circuit #3 and Note 5 lAL RH, RI, RW leakage current 0.1 1 µA V IN = VTERM. Device is in stand-by mode.

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a poten- tiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (RH–RL)/63, single pot (4) Max. = all four arrays cascaded together, Typical = individual array resolutions. ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING POWER-UP REQUIREMENTS (Power Up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First Vcc, then the potentiometer pins. It is suggested that Vcc reach 90% of its final value before power is applied to the potentiometer pins. The Vcc ramp rate specification should be met, and any glitches or slope changes in the Vcc line should be held to <100mV if possible. Also, Vcc should not reverse polarity by more than 0.5V. Notes: (5) This parameter is guaranteed by characterization or sample testing. (6) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are guaranteed by design. (7) This parameter is guaranteed by design. (8) Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve. (9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to the device. Symbol Parameter Limits Unit Test ConditionMin. Typ. Max. lCC Supply current (active) 3 mA f SCL = 100kHz, SDA = Open, Other Inputs = VSS ISB VCC current (standby) 200 500 µA SCL = SDA = V CC, Addr. = VSS ILI Input leakage current 10 µA V IN = VSS to VCC ILO Output leakage current 10 µA V OUT = VSS to VCC VIH Input HIGH voltage 2 V CC + 1 V VIL Input LOW voltage –1 0.8 V VOL Output LOW voltage 0.4 V I OL = 3mA Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 Years Symbol Parameter Max. Unit Test Condition CI/O (5) Input/output capacitance (SDA) 19 pF V I/O = 0V CIN (5) Input capacitance (A0, A1, A2, A3 and SCL) 12 pF V IN = 0V Symbol Parameter Min. Typ. Max. Unit tPUR (6) Power-up to initiation of read operation 1 ms tPUW (6) Power-up to initiation of write operation 5 ms tRVCC VCC Power up ramp rate 0.2 50 V/msec

A.C. CONDITIONS OF TEST SYMBOL TABLE Equivalent A.C. Test Circuit Circuit #3 SPICE Macro Model Guidelines for Calculating Typical Values of Bus Pull-Up Resistors DCP Wiper Current De-rating Curve Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 1533Ω 100pF SDA Output RH CH 10pF CW RL CL RW RTOTAL 25pF 10pF Macro Model 120 100 20 40 60 80 100 120 Bus Capacitance (pF) Min. Resistance Max. Resistance RMAX =CBUS tR RMIN = IOL MIN VCC MAX =1.8KΩ Resistance (KΩ) 20 40 60 70 80 90 Ambient Temperature (°C) Maximum DCP Wiper Current 5010 30

0.022 (0.559) 0.014 (0.356) (3.81) 0.150 (2.92) 0.1150 0.10 (BSC) (2.54) 1.060 (26.92) 0.980 (24.89) 0.900 (23.66) Ref. Pin 1 Index 0.195 (4.95) 0.115 (2.92) 0.015 (0.38) Pin 1 Seating Plane 0.070 (1.778) 0.045 (1.143) 0.280 (7.11) 0.240 (6.096) 0.005 (0.127) 15° 20-Lead Plastic Dual In-Line Package Type P 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.014 (0.356) 0.008 (0.2032) 0.300 (7.62) (BSC) NOTE:

0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) Pin 1 Pin 1 Index 0.050 (1.27) 0.496 (12.60) 0.508 (12.90) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4X) 7° 20-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.420" 0.050" Typical 0.050" Typical 0.030" Typical

20 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.007 (0.18) 0.011 (0.28) 0°–8° X 45°

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .260 (6.6) .252 (6.4) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

Characteristics subject to change without notice. 18 of 18 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale onl y. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Xicor, Inc. 2000 Patents Pending REV 1.1.13 12/09/02 www.xicor.com

Ordering Information

Blank = 5V ±10% Temperature Range Blank = Commercial = 0 to +70°C I = Industrial = –40 to +85°C Package P = 20-Lead Plastic DIP S = 20-Lead SOIC V = 20-Lead TSSOP Potentiometer Organization Pot 0 Pot 1 Pot 2 Pot 3 Y = 2K 2K 2K 2K W = 10K 10K 10K 10K U = 50K 50K 50K 50K M = 2K 10K 10K 50K Y P T VX9241A