X4003 XICOR | Alldatasheet

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Technical content

REV 1.1.3 4/30/02 Characteristics subject to change without notice. 1 of 18 www.xicor.com X4003/X4005 CPU Supervisor

FEATURES

  • Selectable watchdog timer —Select 200ms, 600ms, 1.4s, off
  • L o w V CC detection and reset assertion —Five standard reset threshold voltages —Adjust low V CC reset threshold voltage using special programming sequence —Reset signal valid to V CC = 1V
  • Low power CMOS —12µA typical standby current, watchdog on —800nA typical standby current watchdog off —3mA active current
  • 400kHz I C interface
  • 1.8V to 5.5V power supply operation
  • Available packages —8-lead SOIC —8-lead MSOP

DESCRIPTION

These devices combine three popular functions, Power- on Reset Control, Watchdog Timer, and Supply Voltage Supervision. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET /RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a select- able time out interval, the device activates the RESET RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the minimum V CC trip point. RESET/RESET is asserted until V CC returns to proper operating level and stabilizes. Five industry stan- dard V TRIP thresholds are available; however, Xicor’s unique circuits allow the threshold to be reprogrammed to meet custom requirements, or to fine-tune the thresh- old for applications requiring higher precision. BLOCK DIAGRAM Data Register Command Decode & Control Logic SDA SCL VCC Reset & Watchdog Timebase Power on and Generation RESET (X4003) Reset Low Voltage Control Register Watchdog Transition Detector WP VCC Threshold Reset logic RESET (X4005) VTRIP Watchdog Timer Reset

Characteristics subject to change without notice. 2 of 18REV 1.1.3 4/30/02 www.xicor.com PIN CONFIGURATION NC VSS VCC SDA SCL3 8NC WP RESET 8-Pin JEDEC SOIC, MSOP PIN DESCRIPTION Pin (SOIC/DIP) Pin TSSOP Pin (MSOP) Name Function 1 3 NC No internal connections 2 4 NC No internal connections 3 5 2 RESET RESET Reset Output RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever V CC falls below the minimum V CC sense level. It will remain active until V CC rises above the minimum V CC sense level for 250ms. RESET/ RESET goes active if the watchdog timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge of SDA, while SCL also toggles from HIGH to LOW followed by a stop condition resets the watchdog timer. RESET /RESET goes active on power up and remains active for 250ms after the power supply stabilizes. 46 3 V SS Ground 5 7 4 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA while SCL also toggles from HIGH to LOW follow by a stop condition resets the watchdog timer. The absence of this procedure with- in the watchdog time out period results in RESET /RESET going active. 6 8 5 SCL Serial Clock. The serial clock controls the serial bus timing for data input and output. 71 6 W P Write Protect. WP HIGH prevents changes to the watchdog timer setting. 82 1 V CC Supply voltage

Characteristics subject to change without notice. active. This signal provides several benefits. to operate with insufficient voltage. stabilization of the oscillator. tion prior to initialization of the circuit. RESET, allowing the system to begin operation. signal remains active until the voltage drops below 1V. Figure 1. Watchdog Restart the application of a nonvolatile control signal. point before setting the new value.

Characteristics subject to change without notice. Figure 4. V

The state of the control register can be read at any time by performing a serial read operation. Only one byte is read by each register read operation. The X4003/X4005 resets itself after the first byte is read. The master should supply a stop condition to be con- sistent with the bus protocol, but a stop is not required to end this operation. RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to “1” prior to a write to the control register. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the control register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes the control register will be ignored (no acknowledge will be issued after the data byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writ- ing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 control the period of the watch- dog timer. The options are shown below. Writing to the Control Register Changing any of the nonvolatile bits of the control register requires the following steps: – Write a 02H to the control register to set the write enable latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation pre- ceeded by a start and ended with a stop.) – Write a 06H to the control register to set both the register write enable latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop.) – Write a value to the control register that has all the control bits set to the desired state. This can be rep- resented as 0xy0 0010 in binary, where xy are the WD bits. (Operation preceeded by a start and ended with a stop.) Since this is a nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (0xy0 0110) then the RWEL bit is set, but the WD1 and WD0 bits remain unchanged. Writing a second byte to the control reg- ister is not allowed. Doing so aborts the write opera- tion and returns a NACK. – A read operation occurring between any of the previ- ous operations will not interrupt the register write operation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device consist- ing of [02H, 06H, 02H] will reset all of the nonvolatile bits in the control register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set. SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data trans- fers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Serial Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 5. 7 6543 2 1 0

0 WD1 WD0 0 0 RWEL WEL 0

WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 Disabled (factory setting)

master must first perform a “dummy” write operation. the device and then by the eight bit control register. acknowledge, and data transfer sequences. – The device is in the low power standby state. – SDA pin is the input mode. /RESET signal is active for tPURST. Figure 9. Control Register Read Sequence – The WEL bit must be set to allow a write operation. nated if in-progress when RESET/RESET go active.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C Option Supply Voltage Limits –1.8 1.8V to 3.6V –2.7 and –2.7A 2.7V to 5.5V Blank and –4.5A 4.5V to 5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Notes: (1) The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte. (3) V IL min. and VIH max. are for reference only and are not tested. Symbol Parameter VCC = 1.8 to 3.6V V CC = 2.7 to 5.5V Unit Test ConditionsMin Max Min Max ICC (1) Active supply current read control register 0.5 1.0 mA f SCL = 400kHznonvolatile, SDA = OpenI CC2 (1) Active supply current write control register 1.5 3.0 mA ICC3 (2) Operating current AC (WDT off) 11 µ A ICC4 (2) Operating current DC (WDT off) 1 1 µA V SDA = VSCL = VCC Others = GND or VSB ICC5 (2) Operating current DC (WDT on) 10 20 µA ILI Input leakage current 10 10 µA V IN = GND to VCC ILO Output leakage current 10 10 µA V SDA = GND to VCC Device is in Standby(2) VIL (3) Input LOW voltage -0.5 V CC x 0.3 -0.5 V CC x 0.3 V VIH (3) Input HIGH voltage V CC x 0.7 V CC + 0.5 V CC x 0.7 V CC + 0.5 V VHYS Schmitt trigger input hysteresis fixed input level VCC related level 0.2 .05 x VCC 0.2 .05 x VCC V IOL = 1.8mA (1.8–3.6V)

CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V) Note: (4) This parameter is periodically sampled and not 100% tested. Symbol Parameter Max. Unit Test Conditions COUT (4) Output capacitance (SDA, RESET/RESET) 8 pF V OUT = 0V CIN (4) Input capacitance (SCL, WP) 6 pF V IN = 0V EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS 4.6KΩ RESET 100pF SDA 1533Ω 100pF For VOL = 0.4V and IOL = 3 mA RESET Input pulse levels 0.1V CC to 0.9VCC Input rise and fall times 10ns Input and output timing levels 0.5VCC Output load Standard output load A.C. CHARACTERISTICS (Continued)(Over recommended operating conditions, unless otherwise specified) Notes: (5) Typical values are for TA = 25°C and VCC = 5.0V (6) Cb = total capacitance of one bus line in pF . Symbol Parameter 100kHz 400kHz UnitMin. Max. Min. Max. fSCL SCL clock frequency 0 100 0 400 kHz tIN Pulse width suppression time at inputs n/a n/a 50 ns tAA SCL LOW to SDA data out valid 0.1 0.9 0.1 0.9 µs tBUF Time the bus free before start of new transmission 4.7 1.3 µs tLOW Clock LOW time 4.7 1.3 µs tHIGH Clock HIGH time 4.0 0.6 µs tSU:STA Start condition setup time 4.7 0.6 µs tHD:STA Start condition hold time 4.0 0.6 µs tSU:DAT Data in setup time 250 100 ns tHD:DAT Data in hold time 5.0 0 µs tSU:STO Stop condition setup time 0.6 0.6 µs tDH Data output hold time 50 50 ns tR SDA and SCL rise time 1000 20 +.1Cb (6) 300 ns tF SDA and SCL fall time 300 20 +.1Cb (6) 300 ns tSU:WP WP setup time 0.4 0.6 µs tHD:WP WP hold time 0 0 µs Cb Capacitive load for each bus line 400 400 pF

Nonvolatile Write Cycle Timing Note: (7) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Symbol Parameter Min. Typ. (1) Max. Unit tWC (7) Write cycle time 5 10 ms tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtA tR tHD:WP SCL SDA IN WP tSU:WP Clk 1 Clk 9 Slave Address Byte Start SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition

Power-Up and Power-Down Timing RESET/RESET Output Timing Note: (8) This parameter is periodically sampled and not 100% tested. SDA vs. RESET/RESET Timing Symbol Parameter Min. Typ. Max. Unit VTRIP Reset trip point voltage, X4003–4.5A, X4005–4.5A Reset trip point voltage, X4003, X4005 Reset trip point voltage, X4003–2.7A, X4005–2.7A Reset trip point voltage, X4003–2.7, X4005–2.7 Reset trip point voltage, X4003–1.8, X4005–1.8 4.5 4.25 2.85 2.55 1.7 4.62 4.38 2.92 2.62 1.75 4.75 4.5 3.0 2.7 1.8 V V V t PURST Power-up reset time out 100 200 400 ms tRPD (8) VCC detect to reset/output 500 ns tF (8) VCC fall time 10 ms tR (8) VCC rise time 0.1 ns VRVALID Reset valid VCC 1V VCC tPURST tPURST tR tF tRPD RESET

0 Volts

VTRIP Programming Timing Diagram VTRIP Programming Parameters Symbol Parameter Min. Typ. Max. Unit tWDO Watchdog time out period, WD1 = 1, WD0 = 1 (factory setting) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 OFF 200 600 1.4 300 800 ms ms sec t CST CS pulse width to reset the watchdog 400 ns tRST Reset time out 100 200 400 ms Parameter Description Min. Max. Unit tVPS VTRIP program enable voltage setup time 1 µs tVPH VTRIP program enable voltage hold time 1 µs tTSU VTRIP setup time 1 µs tTHD VTRIP hold (stable) time 10 ms tWC VTRIP write cycle time 10 ms tVPO VTRIP program enable voltage off time (between successive adjustments) 0 µs tRP VTRIP program recovery period (between successive adjustments) 10 ms VP Programming voltage 15 18 V VTRAN VTRIP programmed voltage range 1.7 5.0 V Vta1 Initial VTRIP program voltage accuracy (VCC applied–VTRIP) (Programmed at 25°C.) -0.1 +0.4 V Vta2 Subsequent VTRIP program voltage accuracy [(VCC applied–Vta1)–VTRIP. Programmed at 25°C.) -25 +25 mV Vtr VTRIP program voltage repeatability (Successive program operations. Programmed at 25°C.) -25 +25 mV Vtv VTRIP program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested. VCC (VTRIP) WP tTSUtTHD tVPH tVPS VP VTRIP tVPO SCL SDA A0h01h or 03h00h tRP

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" Typical 0.050" Typical 0.030" Typical

8 PlacesFOOTPRINT

0.118 ± 0.002 (3.00 ± 0.05) 0.040 ± 0.002 (1.02 ± 0.05) 0.150 (3.81) Ref. 0.193 (4.90) 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7° Typ. R 0.014 (0.36) 0.118 ± 0.002 (3.00 ± 0.05) 8-Lead Miniature Small Outline Gull Wing Package Type M NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS) 0.220" 0.0256" Typical 0.025" Typical 0.020" Typical Ref.

Ordering Information

(Active LOW) Part Number RESET (Active HIGH) -40–85°C X4003S8I–4.5A X4005S8I–4.5A 8L MSOP -40–85°C X4003M8I–4.5A X4005M8I–4.5A 4.5–5.5V 4.25–4.5 8L SOIC 0–70°C X4003S8 X4005S8 -40–85°C X4003S8I X4005S8I 8L MSOP -40–85°C X4003M8I X4005M8I -40–85°C X4003S8I–2.7A X4005S8I–2.7A 8L MSOP -40–85°C X4003M8I–2.7A X4005M8I–2.7A -40–85°C X4003S8I–2.7 X4005S8I–2.7 8L MSOP -40–85°C X4003M8I–2.7 X4005M8I–2.7 8L MSOP 0–70°C X4003M8–1.8 X4005M8–1.8 8-Lead TSSOP ACI/ACR = –4.5A (0 to70°C) EYWW XXXXX ACK/ACT = No Suffix (0 to 70°C) ACM/ACV = –2.7A (0 to 70°C) ACO/ACX = –2.7 (0 to 70°C) 8-Lead SOIC X4003/05 X XX Blank = 8-Lead SOIC Blank = No Suffix (0 to +70°C) I = No Suffix (-40 to +85°C)ACP/ACY = –1.8 (0 to 70°C) AN = –2.7A (0 to +70°C) AL = –4.5A (0 to +70°C)

Characteristics subject to change without notice. 18 of 18 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale onl y. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Xicor, Inc. 2000 Patents Pending REV 1.1.3 4/30/02 www.xicor.com