X9241AMSZ

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Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 17

Technical content

Features

• Four potentiometers in one package
• 2-wire serial interface
• Register oriented format - Direct read/write/transfer of wiper positions - Store as many as four positions per potentiometer
• Terminal Voltages: +5V, -3.0V
• Cascade resistor arrays
• Low power CMOS
• High Reliability - Endurance–100,000 data changes per bit per register - Register data retention–100 years
• 16-bytes of nonvolatile memory
• 3 resistor array values - Cascadable for values of 4kto 200k
• Resolution: 64 taps each pot
• 20 Ld plastic DIP, 20 Ld TSSOP and 20 Ld SOIC packages
• Pb-free available (RoHS compliant) Block Diagram DATA R1R0 R3R2 VH0/RH0 VL0/RL0 VW0/RW0 WIPER COUNTER REGISTER (WCR) VH1/RH1 VL1/RL1 VW1/RW1 REGISTER ARRAY POT 1 WIPER COUNTER REGISTER (WCR) R1R0 R3R2 SCL SDA INTERFACE AND CONTROL CIRCUITRY VH2/ VL2/RL2 VW2/RW2 VH3/RH3 VL3/RL3 VW3/RW3 REGISTER ARRAY POT 2 WIPER COUNTER REGISTER (WCR) R1R0 R3R2 REGISTER ARRAY POT 3 WIPER COUNTER REGISTER (WCR) R1R0 R3R2 VCC VSS RH2

FN8164 Rev 7.00 Page 2 of 17 August 17, 2015

Ordering Information

(V) POTENTIOMETER ORGANIZATION (k) TEMP RANGE (°C) PACKAGE (RoHS Compliant) X9241AMPZ (Note) (No longer available, recommended replacement: X9241AMSZT1) X9241AMPZ 5 ±10% 2/10/50 Pot 0 = 2k Pot 1 = 10k Pot 2 = 10k Pot 3 = 50k 0 to +70 20 Ld PDIP* X9241AMPIZ (Note) (No longer available, recommended replacement: X9241AMSZT1) X9241AMPIZ -40 to +85 20 Ld PDIP* X9241AMSZ* (Note) X9241AMS Z 0 to +70 20 Ld SOIC X9241AMSIZ* (Note) X9241AMSI Z -40 to +85 20 Ld SOIC X9241AMVZ (Note) X9241AM VZ 0 to +70 20 Ld TSSOP X9241AMVIZ* (Note) X9241AM VIZ -40 to +85 20 Ld TSSOP X9241AWPIZ (Note) X9241AWPIZ 10 Pot 0 = 10k Pot 1 = 10k Pot 2 = 10k Pot 3 = 10k 0 to +70 20 Ld PDIP X9241AWSZ* (Note) X9241AWS Z 0 to +70 20 Ld SOIC X9241AWSIZ* (Note) X9241AWSI Z -40 to +85 20 Ld SOIC X9241AWVZ* (Note) X9241AW VZ 0 to +70 20 Ld TSSOP X9241AWVIZ* (Note) X9241AW VIZ -40 to +85 20 Ld TSSOP X9241AYPZ (Note) (No longer available, recommended replacement: X9241AYSIZ) X9241AYPZ 2 Pot 0 = 2k Pot 1 = 2k Pot 2 = 2k Pot 3 = 2k 0 to +70 20 Ld PDIP*** X9241AYSZ* (Note) X9241AYS Z 0 to +70 20 Ld SOIC X9241AYSIZ* (Note) X9241AYSI Z -40 to +85 20 Ld SOIC X9241AYVZ (Note) (No longer available, recommended replacement: X9241AYVIZ) X9241AY VZ 0 to +70 20 Ld TSSOP X9241AYVIZ* (Note) X9241AY VIZ -40 to +85 20 Ld TSSOP X9241AUPZ (Note) X9241AUPZ 5 ±10% 50 Pot 0 = 50k Pot 1 = 50k Pot 2 = 50k Pot 3 = 50k 0 to +70 20 Ld PDIP* X9241AUPIZ (Note) X9241AUPIZ -40 to +85 20 Ld PDIP* X9241AUSZ* (Note) X9241AUS Z 0 to +70 20 Ld SOIC X9241AUSIZ* (Note) X9241AUSI Z -40 to +85 20 Ld SOIC X9241AUVZ* (Note) (No longer available, recommended replacement: X9241AUSZT1) X9241AU VZ 0 to +70 20 Ld TSSOP X9241AUVIZ* (Note) X9241AU VIZ -40 to +85 20 Ld TSSOP *Add "T1" suffix for tape and reel. ***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN8164 Rev 7.00 Page 3 of 17 August 17, 2015 Pin Descriptions Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9241A. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Address The Address inputs are used to set the least significant 4-bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9241A. Potentiometer Pins VH/RH(VH0/RH0 TO VH3/RH3), VL/RL (VL0/RL0 TO VL3/RL3) The RH and RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW/RW (VW0/RW0 TO VW3/RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Pinout X9241A (20 LD DIP, SOIC, TSSOP) TOP VIEW Principles of Operation The X9241A is a highly integrated microcircuit incorporating four resistor arrays, their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9241A supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9241A will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (t LOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9241A are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (t HIGH). The X9241A continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting 8-bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the 8-bits of data. See Figure 7. The X9241A will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9241A will respond with a final acknowledge. Array Description The X9241A is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in Pin Names SYMBOL DESCRIPTION SCL Serial Clock SDA Serial Data A0 to A3 Address VW0/RW0 VH1/RH1 SDA VSS VCC SCL X9241A VL0/RL0 VH0/RH0 VW1/RW1 VL1/RL1 VW3/RW3 VL3/RL3 VH3/RH3 VW2/RW2 VL2/RL2 VH2/RH2 VH0/RH0 to VH3/RH3, VL0/RL0 to VL3/RL3 Potentiometer Pins (terminal equivalent) VW0/RW0 to VW3/RW3 Potentiometer Pins (wiper equivalent) Pin Names SYMBOL DESCRIPTION

nonvolatile memory and takes a minimum of tWR to complete. potentiometers and one of their associated registers. Four instructions require a three-byte sequence to complete. operations is shown in Figure 4. move one resistor segment towards the VH/RH terminal.

0101 A 3 A 2 A 1 A 0 A I3 I2 I1 I0 P1 P0 R1 R0

FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE

1. 1/0 = data is one or zero
2. X = Not applicable or don’t care; that is, a data register is not involved in the operation and need not be addressed (typical).

FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS TABLE 1. INSTRUCTION SET

FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER

organization and array operation follows. contents of its Data Register zero (DR0) upon power-up. FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM

The X9241A provides a mechanism for cascading the arrays. to the VH/RH of the lower order array (See Figure 9). (Cascade Mode) and DW (Disable Wiper, normal operation). WCR2 is set to “1”, pot 2 will be cascaded to pot 3. wiper terminal will be electrically isolated and float. Increment/Decrement command. L/RL, VH/RH and the wipers are the same in these cases. FIGURE 9. CASCADING ARRAYS

FN8164 Rev 7.00 Page 10 of 17 August 17, 2015 Absolute Maximum Ratings Thermal Information Supply Voltage (VCC) Limits Voltage on SCK, SCL or any address Voltage on any VH/RH, VW/RW or VL/RL http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Analog Specifications (Over recommended operating conditions unless otherwise stated). SYMBOL PARAMETER TEST CONDITION LIMITS UNIT MIN (Note 11) TYP MAX (Note 11) RTOTAL End to end resistance -20 +20 % RW Wiper resistance Wiper Current = (V H - VL)/RTOTAL 40 130  VTERM Voltage on any VH/RH, VW/RW or VL/RL Pin -3.0 +5 V Noise Ref: 1kHz (Note 7) 120 dBV Resolution (Note 7) 1.6 % Absolute linearity (Note 3) R w(n)(actual) - Rw(n)(expected) ±1 MI (Note 5) Relative linearity (Note 4) R w(n + 1) - [Rw(n) + MI] ±0.2 MI (Note 5) Temperature coefficient of RTOTAL (Note 7) ±300 ppm/°C Ratiometric temperature coefficient (Note 7) ±20 ppm/C CH/CL/CW Potentiometer capacitances See Circuit #3 and (Note 7) 15/15/25 pF lAL RH, RI, RW leakage current V IN = VTERM. Device is in stand-by mode. 0.1 1 µA SYMBOL PARAMETER TEST CONDITION LIMITS UNIT MIN (Note 11) TYP MAX (Note 11) lCC Supply current (active) f SCL = 100kHz, Write/Read to WCR, Other Inputs = VSS 3m A ISB VCC current (standby) SCL = SDA = V CC, Addr. = VSS 200 500 µA ILI Input leakage current V IN = VSS to VCC 10 µA ILO Output leakage current V OUT = VSS to VCC 10 µA VIH Input HIGH voltage 2 V VIL Input LOW voltage 0.8 V VOL Output LOW voltage I OL = 3mA 0.4 V NOTES: 3. Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 4. Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 5. MI = RTOT/63 or (RH – RL)/63, single pot 6. Max = all four arrays cascaded together, Typical = individual array resolutions.

FN8164 Rev 7.00 Page 11 of 17 August 17, 2015 Power-up Requirements (Power Up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First VCC, then the potentiometer pins. It is suggested that Vcc reach 90% of its final value before power is applied to the potentiometer pins. The VCC ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. Also, VCC should not reverse polarity by more than 0.5V. NOTES: 7. Limits should be considered typical and are not production tested. 8. Limits established by characterization and are not production tested. 9. Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve. 10. Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to the device. 11. Parts are 100% tested at either +70°C or +85°C. Over temperature limits established by characterization and are not production tested. Symbol Table Endurance and Data Retention PARAMETER MIN UNIT Minimum endurance 100,000 Data changes per bit per register Data retention 100 Years Capacitance SYMBOL PARAMETER TEST CONDITION TYP UNIT CI/O (Note 7) Input/output capacitance (SDA) V I/O = 0V 19 pF CIN (Note 7) Input capacitance (A0, A1, A2, A3 and SCL) V IN = 0V 12 pF Power-up Timing SYMBOL PARAMETER MIN (Note 11) TYP MAX (Note 11) UNIT tPUR (Note 8) Power-up to initiation of read operation 1 ms tPUW (Note 8) Power-up to initiation of write operation 5 ms tRVCC VCC Power up ramp rate 0.2 50 V/ms AC Conditions of Test Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 Input pulse levels V CC x 0.1 to VCC x 0.9 WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

FIGURE 10. INPUT BUS TIMING

FN8164 Rev 7.00 Page 14 of 17 August 17, 2015 About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE August 17, 2015 FN8164.7 - Ordering Information Table on page 2. - Added Revision History beginning with Rev 1. - Added About Intersil Verbiage.

FN8164 Rev 7.00 Page 15 of 17 August 17, 2015 Thin Shrink Small Outline Package Family (TSSOP) N (N/2)+1 (N/2) TOP VIEW AD 0.20 C B A N/2 LEAD TIPSB E1E

0.25 CABM

H PIN #1 I.D. 0.05 eC 0.10 C N LEADS SIDE VIEW

0.10 CABMb

c SEE DETAIL “X” END VIEW DETAIL X 0° - 8° GAUGE PLANE 0.25 LA1 A SEATING PLANE MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY SYMBOL MILLIMETERS TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD Rev. F 2/07 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M -1994.

FN8164 Rev 7.00 Page 16 of 17 August 17, 2015 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL INCHES TOLERANCE NOTESSO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) N 8 14 16 16 20 24 28 Reference - Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

FN8164 Rev 7.00 Page 17 of 17 August 17, 2015 X9241A Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Plastic Dual-In-Line Packages (PDIP) MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL INCHES TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20 N 8 14 16 18 20 Reference Rev. C 2/07 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. D L A e b NOTE 5 SEATING PLANE L N PIN #1 INDEXE1

12 N / 2

E eB eA c