X84161 ICMIC | Alldatasheet

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Technical content

©Xicor, Inc. 1994, 1997Patents Pending 7008-1.2 8/26/97 T2/C0/D0 SH 1 Characteristics subject to change without notice 16K/64K/128K MPS TM EEPROM µ Port Saver EEPROM

FEATURES

  • Up to 10MHz data transfer rate
  • 25ns Read Access Time
  • Direct Interface to Mi croprocessors and Microcontrollers —Eliminates I/O port requirements — No interface glue logic required —Eliminates need for parallel to serial converters
  • Low Power CMOS —1.8V–3.6V, 2.5V–5.5V and 5V ±10% Versions —Standby Current Less than 1 µ A — Active Current Less than 1mA
  • Byte or Page Write Capable — 32 -Byte Page Write Mode
  • Typical Nonvolatile Write Cycle Time: 2ms
  • High Reliability — 100,000 Endurance Cycles —Guaranteed Data Retention: 100 Years

DESCRIPTION

The µ Port Saver memories need no serial ports or special hardware and connect to the processor memory bus. Replacing bytewide data memory, the µ Port Saver uses bytewide memory control functions, takes a fraction of the board space and consumes much less power. Replacing serial memories, the µ Port Saver provides all the serial benefits, such as low cost, low power, low volt age, and small package size while releasing I/Os for more important uses . The µ Port Saver memory outputs data within 25ns of an active read signal. This is less than the read access time of most hosts and provides “no-wait-state” operation. This prevents bottlenecks on the bus. With rates to 10 MHz, the µ Port Saver supplies data faster than required by most host read cycle specifications. This eliminates the need for software NOPs. The µ Port Saver memories communicate over one line of the data bus using a sequence of standard bus read and write operations. This “bit serial” interface allows the µ Port Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit systems. A Write Protect (WP) pin prevents inadvertent writes to the memory. Xicor EEPROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. BLOC K DIAGRAM CE I/O H.V. GENERATION TIMING & CONTROL EEPROM COMMAND DECODE AND CONTROL LOGIC X DEC Y DECODE DATA REGISTER WP 7008 FRM F02.1 OE WE ARRAY 16K x 8 P0/CS P1/CLK P2/DI P3/DO System Connection Internal Block Diagram µ P µ C Ports 8K x 8 2K x 8 Saved DSP ASIC A15 OE WE MPS RISC X84161/641/129 This X84161/641/129 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. ICmic IC MICROSYSTEMS TM

Chip Enable (CE ) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, the chip is dese- lected, the I/O pin is in the high impedance state, and unless a nonvolatile write operation is underway, the device is in the standby power mode. Output Enable (OE ) The Output Enable input must be LOW to enable the out- put buffer and to read data from the device on the I/O line. Write Enable (WE ) The Wr ite Enable input must be LOW to write either data or command sequences to the device. Data In/Data Out (I/O) Data and command sequences are serially written to or serially read from the device through the I/O pin. Write Protect (WP ) When the Wr ite Protect input is LOW , nonvolatile writes to the device are disabled. When WP is HIGH, all func- tions, including nonvolatile writes, operate normally. If a nonvolatile write cycle is in progress, WP going LOW will have no effect on the cycle already underway, but will inhibit any additional nonvolatile write cycles. PIN CONFIGURATIONS: Drawings are to the same scale, actual package sizes are shown in inches: V CC NC OE WE CE I/O WP V SS 8-LEAD SOIC

7008 FRM F01

7008 FRM T01

V CC Supply Voltage V SS Ground NC No Connect PACKAGE SELECTION GUIDE

7008 FRM T0A

V SS NC NC NC OE WE NC NC I/O CE NC V CC NCNC CE CE NC NC NC NC NC NC X84161 X84641 X84129 .190 in. .230 in. .230 in. .390 in. .250 in. .394 in. .252 in. . 252 in. X84129 X84641 NC NC NC OENC V CC CE I/O 8-LEAD TSSOP X84161 .114 in. .252 in. WE WP VSS 8-LEAD PDIP

receive data and commands serially. the l/O line is active whenever both OE and CE are LOW . never both LOW while CE is LOW . read sequentially by continuing to issue read cycles. ma y be continued indefinitely. time to interrupt or end a sequential read or page load. Figure 1. Read Sequence

A nonvolatile write sequence consists of sending a reset sequence, a 16-bit address, up to 32 bytes of data, and then a special “start nonvolatile write cycle” command sequence. The reset sequence is issued first (as described in the Reset Sequence section) to set an internal write enable latch. The address is written serially by issuing 16 separate write cycles (WE and CE LOW , OE HIGH) to the part without any read cycles between the writes. The address is sent serially, most significant bit first, on the l/O pin. Up to 32 bytes of data are written by issuing a m ultiple of 8 write cycles. Again, no read cycles are allowed between writes. The nonvolatile write cycle is initiated by issuing a special read/write “1”/read sequence. The first read cycle ends the page load, then the write “1” followed by a read starts the nonvolatile write cycle. The device recognizes 32- byte pages (e.g., beginning at addresses XXXXXX00000 for X84161). When sending data to the part, attempts to exceed the upper address of the page will result in the address counter “wrapping-around” to the first address on the page, where data loading can continue. For this reason, sending more than 256 consecutive data bits will result in overwriting previous data. A nonvolatile write cycle will not start if a partial or incom- plete write sequence is issued. The internal write enable latch is reset when the nonvolatile write cycle is com- pleted and after an invalid write to prevent inadvertent writes. Note that this sequence is fully static, with no spe- cial timing restrictions. The processor is free to perform other tasks on the bus whenever the chip enable pin (CE is HIGH. Nonvolatile Write Status The status of a nonvolatile write cycle can be determined at any time by simply reading the state of the l/O pin on the device. This pin is read when OE and CE are LOW and WE is HIGH. During a nonvolatile write cycle the l/O pin is LOW . When the nonvolatile write cycle is complete, the l/O pin goes HIGH. A reset sequence can also be issued during a nonvolatile write cycle with the same result: I/O is LOW as long as a nonvolatile write cycle is in progress, and l/O is HIGH when the nonvolatile write cycle is done. Figure 2: Write Sequence CE OE WE I/O (IN) "0" "0" "1" RESET LOAD ADDRESS LOAD DATA START NONVOLATILE WRITE A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 I/O (OUT) 7008 FRM F05.1 WHEN ACCESSING: X84161 ARRAY: A15–A11=0 X84641 ARRAY: A15–A13=0 X84129 ARRAY: A15–A14=0 A15 A14 A13 A12 A11 A10 A9

The device enters an idle state, which draws minimal cur- rent when: —an illegal sequence is entered. The following are the more common illegal sequences:

  • Read/Write/Write—any time
  • Read/Write ‘1’—When writing the address or writing data.
  • Wr ite ‘1’—when reading data
  • Read/Read/Write ‘1’—after data is written to device, but before entering the NV write sequence. —the device powers-up; —a nonvolatile write operation completes. While a sequential read is in progress, the device remains in an active state. This state draws more current than the idle state, but not as much as during a read itself. To go back to the lowest power condition, an invalid condition is created by writing a ‘1’ after the last bit of a read operation. Write Protection The following circuitry has been included to prevent inadvertent nonvolatile writes: —The internal Wr ite Enable latch is reset upon pow er-up. —A reset sequence must be issued to set the internal write enable latch before starting a write sequence. —A special “start nonvolatile write” command sequence is required to start a nonvolatile write cycle. —The internal Wr ite Enable latch is reset automatically at the end of a nonvolatile write cycle. —The internal Wr ite Enable latch is reset and remains reset as long as the WP pin is LOW , which blocks all nonvolatile write cycles. —The internal Wr ite Enable latch resets on an invalid write operation. SYMBOL TABLE W AVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

ABSOLUTE MAXIMUM RATINGS* C to +135 C C to +150 C Terminal Voltage with Respect to V SS C RECOMMENDED OPERATING CONDITIONS

7008 FRM T02

*COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci- fication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

7008 FRM T03

Temperature Min. Max. Commercial 0 C +70 C Industrial –40 C +85 C Military† –55 C +125 C Supply Voltage Limits X84161/641/129 5V 10% X84161/641/129 – 2.5 2.5V to 5.5V X84161/641/129 – 1.8 1.8V to 3.6V D.C. OPERATING CHARACTERISTICS (V CC = 5V 10%) (Over the recommended operating conditions, unless otherwise specified.) 7008 FRM T04.2 Notes: (1) V IL Min. and V IH Max. are for reference only and are not tested. Symbol Parameter Limits Units Test ConditionsMin. Max. I CC1 V CC Supply Current (Read) 1 mA OE = V IL , WE = V IH I/O = Open, CE clocking @ 10MHz I CC2 V CC Supply Current (Write) 2 mA I CC During Nonvolatile Write Cycle All Inputs at CMOS Levels I SB1 V CC Standby Current 1 m A CE = V CC , Other Inputs = V CC or V SS I LI Input Leakage Current 10 m A V IN = V SS to V CC I LO Output Leakage Current 10 m A V OUT = V SS to V CC V lL (1) Input LOW Voltage –0.5 V CC x 0.3 V V IH (1) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V IOL = 2.1mA VOH Output HIGH Voltage VCC – 0.8 V IOH = –1mA Notes: † Contact factory for Military availability

D.C. OPERATING CHARACTERISTICS (V CC = 2.5V to 5.5V) (Over the recommended operating conditions, unless otherwise specified.) 7008 FRM T05.1 D.C. OPERATING CHARACTERISTICS (V CC = 1.8V to 3.6V) (Over the recommended operating conditions, unless otherwise specified.) 7008 FRM T05.1 Notes: (1) VIL Min. and VIH Max. are for reference only and are not tested. Symbol Parameter Limits Units Test ConditionsMin. Max. ICC1 VCC Supply Current (Read) 500 mA OE = VIL, WE = VIH, I/O = Open, CE clocking @ 5MHz ICC2 VCC Supply Current (Write) 2 mA ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels ISB1 VCC Standby Current 1 mA CE = VCC , Other Inputs = VCC or VSS ILI Input Leakage Current 10 mA VIN = VSS to VCC ILO Output Leakage Current 10 mA VOUT = VSS to VCC VlL (1) Input LOW Voltage –0.5 VCC x 0.3 V VIH (1) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V IOL = 1mA, VCC = 3V VOH Output HIGH Voltage VCC – 0.4 V IOH = –400mA, VCC = 3V Symbol Parameter Limits Units Test ConditionsMin. Max. ICC1 VCC Supply Current (Read) 300 mA OE = VIL, WE = VIH, I/O = Open, CE clocking @ 3MHz ICC2 VCC Supply Current (Write) 1 mA ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels ISB1 VCC Standby Current 1 mA CE = VCC , Other Inputs = VCC or VSS ILI Input Leakage Current 10 mA VIN = VSS to VCC ILO Output Leakage Current 10 mA VOUT = VSS to VCC VlL (1) Input LOW Voltage –0.5 VCC x 0.3 V VIH (1) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V IOL = 0.5mA, VCC = 2V VOH Output HIGH Voltage VCC – 0.2 V IOH = –250mA, VCC = 2V

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V

7008 FRM T06

Notes: (2) Periodically sampled, but not 100% tested. POWER-UP TIMING

7008 FRM T07

Notes: (3) Time delays required from the time the VCC is stable until the specific operation can be initiated. Periodically sampled, but not 100% tested. A.C. CONDITIONS OF TEST

7008 FRM T08

EQUIVALENT A.C. LOAD CIRCUITS Symbol Parameter Max. Units Test Conditions C I/O (2) Input/Output Capacitance 8 pF VI/O = 0V C IN (2) Input Capacitance 6 pF VIN = 0V Symbol Parameter Max. Units tPUR (3) Power-up to Read Operation 2 ms tPUW (3) Power-up to Write Operation 5 ms Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 5ns Input and Output Timing Levels VCC x 0.5 30pF 2.06KW 3.03KW OUTPUT

7008 FRM F06

2.39KW 4.58KW OUTPUT

7008 FRM F07

2.8KW 5.6KW OUTPUT

A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits – X84161/641/129† Notes: (4) Periodically sampled, but not 100% tested. tHZ and tOHZ are measured from the point where CE or OE goes HIGH (whichever occurs first) to the time when I/O is no longer being driven into a 5pF load. †Contact factory for 10MHz X84129 availabilityRead Cycle Symbol Parameter VCC = 5V–10% VCC = 2.5V – 5.5VVCC = 1.8V – 3.6V tRC Read Cycle Time 100 200 330 ns tCE CE Access Time 25 50 70 ns tOE OE Access Time 25 50 70 ns tOE L OE Pulse Width 50 60 90 ns tOE H OE High Recovery Time 50 60 90 ns tLOW CE LOW Time 50 70 90 ns tHIGH CE HIGH Time 50 120 180 ns tLZ (4) CE LOW to Output In Low Z 0 0 0 ns tHZ (4) CE HIGH to Output In High Z 0 25 0 30 0 35 ns tOLZ (4) OE LOW to Output In Low Z 0 0 0 ns tOHZ (4) OE HIGH to Output In High Z 0 25 0 30 0 35 ns tOH Output Hold from CE or OE HIGH 0 0 0 ns tWES WE HIGH Setup Time 25 25 25 ns tWEH WE HIGH Hold Time 25 25 25 ns CE WE tWES OE

7008 FRM F08

Write Cycle Limits – X84161/641/129

7008 FRM T10

Notes: (5) tNVWC is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the “start nonvolatile write cycle” sequence until the self-timed, internal nonvolatile write cycle is completed. (6) Data is latched into the X84161/641/129 on the rising edge of CE or WE , whichever occurs first. (7)Periodically sampled, but not 100% tested. Symbol Parameter VCC = 5V –10% VCC = 2.5V – 5.5VVCC = 1.8V – 3.6V tNVWC (5) Nonvolatile Write Cycle Time 5 5 5 ms tWC Write Cycle Time 100 200 330 ns tWP WE Pulse Width 25 40 70 ns tWPH WE HIGH Recovery Time 65 150 200 ns tCS Write Setup Time 0 0 0 ns tCH Write Hold Time 0 0 0 ns tCP CE Pulse Width 25 40 70 ns tCPH CE HIGH Recovery Time 65 150 200 ns tOES OE HIGH Setup Time 25 25 50 ns tOEH OE HIGH Hold Time 25 25 50 ns tDS (6) Data Setup Time 12 20 30 ns tDH (6) Data Hold Time 5 5 5 ns tWPSU (7) WP HIGH Setup 100 100 150 ns tWPHD (7) WP HIGH Hold 100 100 150 ns

7008 FRM F09

7008 FRM F10

NO TE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2.PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEA TING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.020 (0.51) TYP .0.010 (0.25) 15° 8-LEAD PLASTIC DU AL IN-LINE PA CKA GE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL .073 (1.84) MAX. 0.325 (8.25) 0.300 (7.62)

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 3926 FRM F22.1 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.250" 0.050"TYPICAL 0.050" TYPICAL 0.030" TYPICAL

8 PLACESFOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FRM F26

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) PIN 1 PIN 1 INDEX 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 14-LEAD PLASTIC SMALL OUTLINE GULL WING P A CKA GE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"Typical 0.050"Typical 0.030"Typical

14 PlacesFOO TPRINT

0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45°

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8-LEAD PLASTIC, TSSOP , PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane DetailA (20X)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20-LEAD PLASTIC, TSSOP PACKAGE TYPE V .169 (4.3) .025 (.65) BSC .252 (6.4) .300 (6.6) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30)

3926 FRM F45

See Detail “A” .031 (.80) .041 (1.05) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane DetailA (20X)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 28-LEAD PLASTIC, TSSOP PACKAGE TYPE V .169 (4.3) .025 (.65) BSC .394 (10.0) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) See Detail “A” .031 (.80) .041 (1.05) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane DetailA (20X)

ORDERING INFORMATION

*PART MARK CONVEN TION Device X84161/641/129 X X Temperature Range Blank = Commercial = 0 °C to +70 °C I = Industrial = –40 °C to +85 °C Military = –55 °C to +125 °C (contact factory) LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perfor m, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2.A critical component is any component of a life support device or system whose failure to pe rform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. G -X VCC Range Blank = 4.5V to 5.5V, 10 MHz 2.5 = 2.5V to 5.5V, 5 MHz 1.8 = 1.8V to 3.6V, 3 MHz Packages: X84161 P = 8-Lead PDIP S8 = 8-Lead SOIC V8 = 8 -Lead TSSOP X84641 P = 8-Lead PDIP S8 = 8-Lead SOIC V20 = 20 -Lead TSSOP X84129 P = 8-Lead PDIP S14 = 14-Lead SOIC V28 = 28 -Lead TSSOP 8-Lead TSSOP AG = 1.8 to 3.6V, 0 to +70 °C EYWW 8161XXG AH = 1.8 to 3.6V, -40 to +85 °C F = 2.5 to 5.5V, 0 to +70 °C G = 2.5 to 5.5V, -40 to +85 °C Blank = 4.5 to 5.5V, 0 to +70 °C I = 4.5 to 5.5V, -40 to +85 °C 8-Lead SOIC/PDIP X84641 X G XX Blank = 8-Lead SOIC AG = 1.8 to 3.6V, 0 to +70 °C AH = 1.8 to 3.6V, -40 to +85 °C F = 2.5 to 5.5V, 0 to +70 °C G = 2.5 to 5.5V, -40 to +85 °C Blank = 4.5 to 5.5V, 0 to +70 °C I = 4.5 to 5.5V, -40 to +85 °C P = 8-Lead PDIP G = RoHS compliant lead free *All parts and package types not included will receive standard marking. G = RoHS compliant lead free G = RoH S Compliant Lead -Free package Blank = Standard package. Non lead-free