X25320V

X25320 ICMIC | Alldatasheet

Document overview

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Technical content

©Xicor, Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice 3063-3.9 6/11/96 T4/C1/D0 NS Direct Write™ and Block Lock™ Protection is a trademark of X icor, Inc. SPI Serial E 2PROM With Block Lock TM Protection

FEATURES

• 2MHz Clock Rate
• SPI Modes (0,0 & 1,1)
• 4K X 8 Bits — 32 Byte Page Mode
• Low Power CMOS —<1 µ A Standby Current — <5mA Active Current During Write
• 2.7V To 5.5V Power Supply
• Block Lock Protection — Protect 1/4, 1/2 or all of E 2PROM Array
• Built-in Inadvertent Write Protection — Power -Up/Power -Down protection circuitry — Write Enable Latch — Write Protect Pin
• Self-Timed Write Cycle — 5ms Write Cycle Time (Typical)
• High Reliability — Endurance: 100,000 cycles — Data Retention: 100 Years — ESD protection: 2000V on all pins
• 8-Lead PDlP Package
• 8-Lead SOIC Package
• 14 -Lead TSSOP Package

DESCRIPTION

The X25320 is a CMOS 32768-bit serial E 2PROM, internally organized as 4K x 8. The X25320 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is con- trolled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25320 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25320 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25320 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25320 utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. FUNCTIONAL DIAGRAM COMMAND DECODE AND CONTROL LOGIC WRITE CONTROL AND TIMING LOGIC WRITE PROTECT LOGIC X DECODE LOGIC 4K BYTE ARRAY

32 X 256

64 X 256

3063 ILL F01

This X25320 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. ICmic IC MICROSYSTEMS TM

3063 PGM T01

Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select ( CS ) When CS is HIGH, the X25320 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25320 will be in the standby power mode. CS LOW enables the X25320, placing it in the active power mode. It should be noted that after power-on, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect ( WP ) When WP is LOW and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25320 status register are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvola- tile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25320 status register. If the internal write cycle has already been initiated, WP going LOW will have no effect on a write. The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25320 in a system with WP pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “1”. Hold ( HOLD ) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. PIN CONFIGURATION DIP/SOIC TSSOP X25320 X25320 3063 ILL F02.2 CS SO WP VSS VCC HOLD SCK SI CS SO NC NC NC WP VSS VCC HOLD NC NC NC SCK SI

(SPI) of many popular microcontroller families. WP input is “Don’t Care” if WPEN is set “0”. WPEN, BP0 and BP1 are set by the WRSR instruction. progress. During a write, all other bits are set to “1”. when set to a “0”, the latch is reset. tion. The X25320 is divided into four 8192-bit segments. One, two, or all four of the segments may be protected. unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated below.

3063 PGM T03

Table 1. Instruction Set

3063 PGM T04

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

3063 PGM T02

The Write-Protect-Enable (WPEN) is available for the X25320 as a nonvolatile enable bit for the WP pin. WPEN WP WEL Blocks Blocks Register

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 LOW 0 Protected Protected Protected

1 LOW 1 Protected Writable Protected

X HIGH 0 Protected Protected Protected X HIGH 1 Protected Writable Writable 3063 PGM T05.1 The Write Protect (WP) pin and the nonvolatile Write Protect Enable (WPEN) bit in the Status Register control the programmable hardware write protect feature. Hard- ware write protection is enabled when WP pin is LOW, and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is HIGH or the WPEN bit is “0”. When the chip is hardware write protected, nonvolatile writes are disabled to the Status Register, including the Block Protect bits and the WPEN bit itself, as well as the block -protected sections in the memory array. Only the sections of the memory array that are not block-protected can be written. Note: Since the WPEN bit is write protected, it cannot be changed back to a “0”, as long as the WP pin is held LOW. Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK. Read Sequence When reading from the E 2PROM memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25320, followed by the 16- bit address of which the last 12 are used. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($0FFF) the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the read E 2PROM array operation sequence illustrated in Figure 1. To read the status register the CS line is first pulled LOW to select the device followed by the 8-bit RDSR instruc- tion. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. The read status register sequence is illustrated in Figure 2. Write Sequence Prior to any attempt to write data into the X25320, the “write enable” latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the X25320. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the E 2PROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 32 bytes of data to the X25320. The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. For the write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of data byte N is clocked in. If it is brought HIGH at any other time the write operation will not be completed. Refer to Figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which CS going HIGH are valid. To write to the status register, the WRSR instruction is followed by the data to be written. Data bits 0, 1, 4, 5 and 6 must be “0”. This sequence is shown in Figure 6. While the write is in progress following a status register or E2PROM write sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be HIGH. Hold Opera tion The HOLD input should be HIGH (at V IH ) under normal operation. If a data transfer is to be interrupted HOLD can be pulled LOW to suspend the transfer until it can be resumed. The only restriction is the SCK input must be LOW when HOLD is first pulled LOW and SCK must also be LOW when HOLD is released. The HOLD input may be tied HIGH either directly to V CC or tied to V CC through a resistor.

Figure 1. Read E 2PROM Array Operation Sequence

• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset. Data Protection The following circuitry has been included to prevent inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “writ e enable” latch.
• CS must come HIGH at the proper clock count in order to start a write cycle.

Figure 2. Read Status Register Operation Sequence

3063 ILL F03

3063 ILL F04

Figure 3. Write Enable Latch Sequence Figure 4. Byte Write Operation Sequence

3063 ILL F06

3063 ILL F05

Figure 5. Page Write Operation Sequence Figure 6. Write Status Register Operation Sequence

3063 ILL F07

3063 ILL F08

Notes: (1) V IL min. and V IH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. (3) t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS* Lead Temperature POWER -UP TIMING Symbol Parameter Min. Max. Units t PUR (3) Power-up to Read Operation 1 ms t PUW (3) Power-up to Write Operation 5 ms

3063 PGM T09

RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0°C +70 °C Industrial –40 °C +85 °C Military –55 °C +125 °C 3063 PGM T06.1 Supply Voltage Limits X25320 5V ±10% X25320-2.7 2.7V to 5.5V 3063 PGM T07.1 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions I CC V CC Supply Current (Active) 5 mA SCK = V CC x 0.1/V CC x 0.9 @ 2MHz, SO = Open, CS = V SS I SB V CC Supply Current (Standby) 1 ∝ A CS = V CC , V IN = V SS or V CC I LI Input Leakage Current 10 ∝ A V IN = V SS to V CC I LO Output Leakage Current 10 ∝ A V OUT = V SS to V CC V IL (1) Input LOW Voltage –1 V CC x 0.3 V V IH (1) Input HIGH Voltage V CC x 0.7 V CC + 0.5 V V OL1 Output LOW Voltage 0.4 V V CC = 5V, I OL = 3mA V OH1 Output HIGH Voltage V CC – 0.8 V V CC = 5V, I OH = -1.6mA V OL2 Output LOW Voltage 0.4 V V CC = 3V, I OL = 1.5mA V OH2 Output HIGH Voltage V CC – 0.3 V V CC = 3V, I OH = -0.4mA 3063 PGM T08.3 CAPACITANCE T A = +25 °C, f = 1MHz, V CC = 5V. Symbol Test Max. Units Conditions C OUT (2) Output Capacitance (SO) 8 pF V OUT = 0V C IN (2) Input Capacitance (SCK, SI, CS, WP, HOLD) 6 pF V IN = 0V 3063 PGM T10.1

EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS Input Pulse Levels V CC x 0.1 to V CC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level V CC x 0.5

3063 PGM T11

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing Symbol Parameter Min. Max. Units f SCK Clock Frequency 0 2 MHz t CYC Cycle Time 500 ns t LEAD CS Lead Time 250 ns t LAG CS Lag Time 250 ns t WH Clock HIGH Time 200 ns t WL Clock LOW Time 200 ns t SU Data Setup Time 50 ns t H Data Hold Time 50 ns t RI (4) Data In Rise Time 2 ∝ s t FI (4) Data In Fall Time 2 ∝ s t HD HOLD Setup Time 100 ns t CD HOLD Hold Time 100 ns t CS CS Deselect Time 2.0 ∝ s t WC (5) Write Cycle Time 10 ms 3063 PGM T12.2 Data Output Timing Symbol Parameter Min. Max. Units f SCK Clock Frequency 0 2 MHz t DIS Output Disable Time 250 ns t V Output Valid from Clock LOW 200 ns t HO Output Hold Time 0 ns t RO (4) Output Rise Time 100 ns t FO (4) Output Fall Time 100 ns t LZ (4) HOLD HIGH to Output in Low Z 100 ns t HZ (4) HOLD LOW to Output in High Z 100 ns 3063 PGM T13.2 Notes: (4) This parameter is periodically sampled and not 100% tested. (5) t WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. OUTPUT 3063 ILL F09.1 1.44K Ο 1.95K Ο 100pF OUTPUT 1.64K Ο 4.63K Ο 100pF

3063 ILL F11

MSB OUT MSB–1 OUT LSB OUT ADDR LSB IN tCYC tV t HO t WL tWH tDIS 3063 ILL F10.1 tLAG

3063 ILL F12.1 tLZ HOLD tCD tHZ tCD tHD WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

3926 FHD F01

NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MIL LIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) TYP. 0.010 (0.25) 15 ° 8-LEAD PLASTIC DUAL IN -LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62)

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8 ° X 45 ° 3926 FHD F22.1 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN M ILLIMETERS) 0.250" 0.050" TYPICAL 0.050" TYPICAL 0.030" TYPICAL

8 PLACES FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN M ILLIMETERS) 14 -LEAD PLASTIC, TSSOP PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) BSC .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8 ° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

3926 FHD F32

ORDERING INFORMATION

Blank = 5V ±10% 2.7 = 2.7V to 5.5V Temperature Range Blank = Commercial = 0 °C to +70 °C I = Industrial = –40 °C to +85 °C M = Military = –55 °C to +125 °C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC V = 14-Lead TSSOP LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. X25320 XG X Part Mark Convention Blank = 8-Lead SOIC P = 8-Lead Plastic DIP V = 14 -Lead TSSOP G = RoHS compliant lead free Blank = 5V ±10%, 0 °C to +70 °C F = 2.7V to 5.5V, 0 °C to +70 °C G = 2.7V to 5.5V, –40 °C to +85 ° G = RoHS Compliant Lead -Free package Blank = Standard package. Non lead-free