X46402V8-2.9

X46402 XICOR | Alldatasheet

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Ó Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending 9900-3003 5 1/11/00 CM Characteristics subject to change without notice Preliminary Information 64K X46402 Functional Diagram Command Decode and Control Logic HV Generation Timing and Control X Decoder Y Decoder Data Register Write ControlWP SCL SDA Vcc V2FAIL (Vcc) Control Signal V2MON RESET Password Logic EEPROM Array (64Kbits) Write Password Area 2K, 4K, All, None) (Bytes) POWER ON AND GENERATION V2TRIP RESET LOW VOLTAGE VTRIP RESET & WATCHDOG TIMEBASE Control WATCHDOG TIMER RESET OTP array 1 Passwords No Password Area OTP array 2 Dual Voltage CPU Supervisor with 64K Password Protected EEPROM

FEATURES

• Dual Voltage Detection and Reset Assertion —Low Vcc Monitor —Low V2MON Monitor —Low Vcc Block of EEPROM Writes —RESET Signal Valid down to Vcc=1V
• Selectable Watchdog Timer —150ms, 450ms, 1s, 5s, 10s, 20s, 1min, OFF
• Volatile Flag shows Watchdog/Low Voltage Reset
• 64kbit 2-wire Serial EEPROM —1MHz Serial Interface speed —64-Byte Page Write Mode
• Two 64-Byte OTP memory blocks —Requires 64-bit OTP password to write
• Adjustable size Password Protected Array —64 Bit Read and Write Array Passwords —Non-password protected array area
• 8 count tamper counter for invalid passwords
• Operates at 2.5-3.7V
• 8L TSSOP package

DESCRIPTION

The X46402 combines several functions into one device. The first is a dual voltage CPU supervisor plus 64Kbit serial EEPROM memory with password protected write and read operations. The size of the password protected area is selectable by 3 control bits. A Write Protect (WP) pin in conjunction with a WPEN bit provides hardware OTP control of the configuration of the array. Password protected areas require 64 bit read or write passwords prior to access. The eighth illegal password entry (regardless of the number of correct entries) sets an OTP tamper bit. This bit is one of the 32 bits in the Device ID. A secondary voltage monitor circuit activates a V2F AIL pin when the secondary supply voltage drops below a V2trip voltage. This circuit is primarily intended to detect the immediate loss of the battery supply. A low Vcc voltage detect circuit activates a RESET pin when Vcc drops below a V TRIP voltage. This signal also blocks read or write operations. A watchdog timer with the time period controlled by three bits provides several possible time out periods from 150ms to 1 minute.

X46402 Preliminary Information PACKAGE/PINOUTS PIN NAMES PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with other open drain or open collector out- puts. An open drain requires the use of a pull-up resistor. Write Protect (WP) The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the Watchdog Timer control and the memory write protect bits. Reset Output (RESET RESET is an active LOW, open drain output which goes active whenever Vcc falls below the minimum Vtrip sense level. It will remain active until Vcc rises above the mini- mum Vtrip sense level for 150ms. RESET goes active if the Watchdog Timer is enabled and there is no start bit before the end of the selectable Watchdog time-out period. A serial start bit will reset the Watchdog Timer. RESET also goes active on power up at 1V and remains active for 150ms after the power supply stabilizes. V2 Voltage Fail Output (V2FAIL) V2FAIL is an active LOW, open drain output which goes active whenever V2MON falls below the minimum V2trip sense level. It will remain active until V2MON rises above the minimum V2MON sense level. DEVICE OPERATION Power On Reset Application of power to the X46402 activates a Power On Reset Circuit. This circuit goes active at 1V and pulls the RESET pin active. This signal prevents the system micro- processor from starting to operate with insufficient volt- age or prior to stabilization of the oscillator. When Vcc exceeds the device V TRIP value for 200ms (nominal) the circuit releases RESET allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X46402 monitors the V CC and V2MON levels and compares these with internal, preset voltages. When the internal low voltage detect circuitry senses that V2MON is low, the V2F AIL pin goes active. Typically this would be used by the processor as an interrupt to stop the execution of the code or to do housekeeping in prep- aration for an impending power failure. When the internal low voltage detect circuitry senses that Vcc is low, the following happens: —The RESET pin goes active. —The Flag bit in the control register is set to zero. —Communication to the device is interrupted and any command is aborted. If a serial nonvolatile store is in progress when power fails, the circuitry does not stop the nonvolatile store operation, but attempts to com- plete the operation. The RESET and V2FAIL signals remain active until Vcc voltage drops below 1V. RESET remains active until Vcc returns and exceeds V TRIP for 200ms. V2FAIL remains active until immediately after V2MON returns and exceeds it’s minimum voltage. Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the Start bit. The microprocessor must send a start bit periodically to prevent a RESET sig- nal. The start bit must occur prior to the expiration of the watchdog time-out period. The state of three nonvolatile control bits in the Control Register determines the watch- dog timer period. The microprocessor can change these watchdog bits, or they may be “locked” by tying the WP pin HIGH and setting the WPEN bit HIGH. VSS Ground SDA Serial Data VCC Power SCL Serial Clock WP Write Protect V2MON Voltage monitor input RESET Low Voltage Detect Output V2FAIL V2 Voltage Fail Output WP VCC V2FAIL SCL VSS V2MON SDA RESET 8L TSSOP

re-writable up to the limit of the EEPROM endurance. around and over-writing previous values. address FFFFh reads or writes the Control Register. passwords to access the control register. watchdog reset does not change the state of the flag bit. WD2, WD1, and WD0. See the following Table. Table 1. Watchdog Time Control Bits

area is re-writable, by issuing the correct password. acknowledge polling sequences are not required. The basic sequence is illustrated in Figure 1. needs a password prior to each read or write to the area. receives the correct password. Figure 1. X46402 Device Operation (Password Table 2. Password Protected Block Size Select

000 None 0000h - 1FFFh

X46402 Preliminary Information VTRIP/V2TRIP Programming Apply 5V to Vcc or V2MON Decrement Vcc RESET goes active? Measured V(2)TRIP - Desired V(2)TRIP DONE Execute Sequence Reset VTRIP/V2TRIP Set Vcc = Vcc applied = Desired VTRIP OR Execute Sequence Set VTRIP, V2TRIP New Vcc or V2MON applied = Old Vcc V2MON applied + Error (<50mV step) Execute Sequence Reset V2TRIP, VTRIP New Vcc/V2MON applied = Old Vcc applied - Error Error < 0 Error = 0 YES NO Error > 0 Set V2MON = V2MON applied = Desired V2TRIP, Vcc>=V2Trip or V2MON or V2FAIL pin Recyle Vcc power

Figure 9. Definition of Start and Stop Conditions receipt of each subsequent eight-bit word. user attempting to enter invalid passwords. Table 3. X46402 Instruction Set Notes: Illegal command codes will be disregarded. The part will respond with a “no-ACK” to the illegal byte and then return to the standby mode.

X46402 Preliminary Information ACK Polling Once a stop condition is issued to indicate the end of the host’s write sequence, the X46402 initiates the internal nonvolatile write cycle. In order to take advantage of the typical 5ms write cycle, ACK polling can begin immedi- ately. This involves issuing the start condition followed by the new command code of 8 bits (1st byte of the protocol.) If the X46402 is still busy with the nonvolatile write opera- tion, it will issue a “no-ACK” in response. If the nonvolatile write operation has completed, an “ACK” will be returned and the host can then proceed with the rest of the proto- col. See Figure 12. After the password sequence, there is always a nonvolatile write cycle. This is done to discourage random guesses of the password if the device is being tampered with. In order to continue the transaction, the X46402 requires the mas- ter to perform an ACK polling with the specific code of F0h. As with regular Acknowledge polling the user can either time out for 10ms, and then issue the ACK polling once, or continuously loop as described in the flow. If the password that was inserted was correct, then an “ACK” will be returned once the nonvolatile cycle is over, in response to the ACK polling cycle immediately following it. If the password that was inserted was incorrect, then a “no ACK” will be returned even if the nonvolatile cycle is over. Therefore, the user cannot be certain that the password is incorrect until the 10ms write cycle time has elapsed. Data ACK Polling Sequence ACK RETURNED ? ISSUE NEW COMMAND CODE WRITE SEQUENCE COMPLETED ENTER ACK POLLING ISSUE START NO YES PROCEED Password ACK Polling Sequence ACK RETURNED ? ISSUE PASSWORD ACK COMMAND PASSWORD LOAD COMPLETED ENTER ACK POLLING ISSUE START NO YES PROCEED

Figure 12. Acknowledge Polling with a different command code. “NACKed” and followed by a repeated start. after reading the byte. Consider the following example. 150h to be read by the host. protected areas are read by a sequential read command. ations but with a different command code. password protected operation. See Figure 15.

X46402 Preliminary Information Note on Read/Write Operations Password Protected (None of the array to all of the array) Non- Password Protected (All of the array to none of the array) 0000h 1FFFh Password Sequential Read Operation No-Password Sequential Read Operation Notes: Using a “password read” or a “password write” to a non-password protected area is acceptable, because the pass- word is received and accepted prior to an address transmission. It is assumed that access to non-password pro- tected areas is uncontrolled, so either method should work. Using a “no-password read” or a “no-password write” on a password protected area would not work. Trying to access a password protected area without the password match causes the device to return a NACK after the address. A password sequential read that starts in the password protected area can continue into and through the non-pass- word protected area. It will not “wrap” back to address ’0’. A no-password sequential read can only start in the non-password protected area and cannot “wrap” back into the protected area. CHANGE PASSWORD COMMAND When changing a password, the Change Password com- mand is sent to the device. The old password follows. When the old password is accepted (as indicated by the ACK Polling Command sequence), the new password is sent to the device twice, following two bytes of zero. A stop bit initiates the store of the new password. To be suc- cessful in the password change operation the first and second transmission of the new password must match and there must be exactly 16 password bytes. If this is not the case, the operation is aborted and the password remains unchanged. PASSWORDS The sequence in Figure 17 shows how to change (pro- gram) the passwords. The programming of passwords is done twice prior to the nonvolatile write cycle in order to verify that the new password is consistent. After the eight bytes are entered in the second pass, a comparison takes place. A mismatch will cause the part to ignore the change command and enter into the standby mode. There are two ways to determine whether the operation was completed successfully. The Data ACK polling method can determine if a password has been loaded correctly, however the data ACK command must be issued less than 2ms after the stop bit. After this time, it cannot be determined if the password has been loaded correctly, without trying the new password. To determine if the new password has been loaded correctly the data ACK polling command is issued immediately following the stop bit. If it returns an ACK, then the two passes of the new password entry do not match. If it returns a “no ACK” then the passwords match and a high voltage cycle is in progress. The high voltage cycle is complete when a sub- sequent data ACK command returns an “ACK”.

X46402 Preliminary Information D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter Limits Units Test ConditionsMin. Max. ICC1 VCC Supply Current (Read) 1m A fSCL = 1MHz, RESET = V2FAIL = VCC w/ pull up resistor V2MON = VCC ICC2 (3) VCC Supply Current (Write) 3m A fSCL = 1MHz, RESET = V2FAIL = VCC w/ pull up resistor RST = VSS ISB1 (1) VCC Supply Current (Standby) 50 µA VIL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 1MHz, fSDA = 400 KHz ISB2 (1) VCC Supply Current (Standby) 1µ A VSDA = VSCL = V2MON = VCC Other = GND or VCC –0.3V ILI Input Leakage Current 10 µA VIN = VSS to VCC ILO Output Leakage Current 10 µA VOUT = VSS to VCC VIL1 (2) Input LOW Voltage –0.5 VCC x 0.3 V VCC = 3.0V VIH1 (2) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VCC = 3.0V VIL2 (2) Input LOW Voltage –0.5 VCC x 0.1 V VCC = 3.0V VIH2 (2) Input HIGH Voltage VCC x 0.9 VCC + 0.5 V VCC = 3.0V VOL Output LOW Voltage 0.4 V IOL = 3mA An easier way to determine that the password has been changed correctly is to read the ACK bit following the second writing of the new password. If the device returns an ACK, the password is good. A No ACK indicates something went wrong. If there was an error, the pass- word remains unchanged. There is no way to read any of the passwords. ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with respect to V *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0°C +70°C Extended –20°C +85°C Device Supply Voltage Limits X46402 2.5V to 3.7V

Table 4. CAPACITANCE (TA = +25°C, f = 1MHz, VCC = 3V) (2) V IL min. and VIH max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested.

X46402 Preliminary Information RESET AC SPECIFICATIONS Nonvolatile Write Cycle Timing Notes: 1. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. TIMING DIAGRAMS Bus Timing Write Cycle Timing Symbol Parameter Min. Typ.(1) Max. Units tWC (1) Write Cycle Time 5 10 mS tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT t F tLOW tBUFtAA tR SCL SDA tWC 8th bit of last byte ACK Stop Condition Start Condition

X46402 Preliminary Information GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS POWER-UP AND POWER-DOWN TIMING RESET Output Timing V2FAIL Output Timing 5040302010 Bus capacitance in pF Pull Up Resistance in KW R MIN R PMAX For VIH = 0.9VCC RMIN VCCMAX 0.4– IOLMIN VIH Vcc 1 e tRMAX– RPMAX CBUS Łł æö RPMAX tR

2.3 CBUS()

tRMAX = maximum allowable SDA rise time 100ns max rise time VCC tPURST tPURST tRV tFV tDVC RESET

0 Volts

X46402 Preliminary Information Notes: (5) This parameter is periodically sampled and not 100% tested. (6) Typical values not tested. Start Bit vs. RESET Timing Symbol Parameter Min. Typ. Max. Units VTRIP RESET Trip Point Voltage 2.4 – 3.5 V V2TRIP V2FAIL Trip Point Voltage 1.7 – 3.5 V VTH VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 40 mV V2TA V2TRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 40 mV tPURST Power-up Reset Timeout 75 150 225 ms tDVC (5) Detect VCC Low Voltage to Reset Output (Vcc = 2.3V) 65 ms tDVB (5) Detect V2MON Low Voltage to Reset Output (Vcc = 2.5-3.7V) 100 ms tFV (5) VCC Fall Time 100 ms tRV (5) VCC Rise Time 100 ms tFB (5) V2MON Fall Time 500 ns tRB (5) V2MON Rise Time 500 ns VRVALID Reset Valid VCC 1V SDA tWDR RESET tWDO tRST tWDO tRST SCL tSU:STA tSU:STO

X46402 Preliminary Information RESET Output Timing Symbol Parameter Min. Typ. Max. Units tWDO Watchdog Timeout Period, WD2 = 0, WD1 = 1, WD0 = 0 WD2 = 0, WD1 = 0, WD0 = 1 WD2 = 0, WD1 = 0, WD0 = 0 WD2 = 1, WD1 = 1, WD0 = 1 WD2 = 1, WD1 = 1, WD0 = 0 WD2 = 1, WD1 = 0, WD0 = 1 WD2 = 1, WD1 = 0, WD0 = 0 225 0.5 2.5 150 450 225 675 1.5 7.5 ms ms sec sec sec sec sec tWDR SDA LOW duration (Reset the Watchdog) 400 ns tRST Reset Timeout 75 150 225 ms

X46402 Preliminary Information NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8-LEAD PLASTIC, TSSOP , PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0¥ – 8¥ .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

X46402 Preliminary Information

ORDERING INFORMATION

Notes: Tolerance for Vtrip and V2trip are +/-5% PART MARK CONVENTION VCC Range V TRIP V2TRIP Package Operating Temperature Range Part Number 2.5–3.7V 3.1 2.6 8L TSSOP 0°C–70°C X46402V8-3.1 -20°C–85°C X46402V8E-3.1 2.5–3.7V 3.1 1.7 8L TSSOP 0°C–70°C X46402V8-3.1A -20°C–85°C X46402V8E-3.1A 2.5–3.7V 2.9 2.3 8L TSSOP 0°C–70°C X46402V8-2.9 -20°C–85°C X46402V8E-2.9 8-Lead TSSOP EYWW XXXX XX

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2.6 2.6 1.7 1.7 2.3 2.3 0 to 70° C -20 to 85°C 0 to 70° C -20 to 85°C 0 to 70° C -20 to 85°C 3.1 3.1 3.1 3.1 2.9 2.9 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.