X4283AL

X4283 XICOR | Alldatasheet

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REV 1.17 11/27/00 Characteristics subject to change without notice. 1 of 22 www.xicor.com Preliminary Information 128K X4283/85 16K x 8 Bit CPU Supervisor with 128K EEPROM

FEATURES

• Selectable watchdog timer
• L o w V CC detection and reset assertion —Four standard reset threshold voltages —Adjust low V CC reset threshold voltage using special programming sequence —Reset signal valid to V CC = 1V
• Low power CMOS —<20µA max standby current, watchdog on —<1µA standby current, watchdog OFF —3mA active current
• 128Kbits of EEPROM —64 byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
• Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512 bytes of EEPROM array with programmable Block Lock protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages —8-lead SOIC —8-lead TSSOP

DESCRIPTION

The X4283/85 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Volt- age Supervision, and Block Lock protect serial EEPROM memory in one package. This combination lowers system cost, reduces board space require- ments, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET /RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the RESET RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when V CC falls below the set minimum V CC trip point. RESET/RESET is asserted until V CC returns to proper operating level and stabilizes. Four industry BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SDA SCL VCC Reset & Watchdog Timebase Power on and Generation VTRIP RESET (X4283) Reset Low Voltage Status Register Protect Logic EEPROM Array Watchdog Transition Detector WP VCC Threshold Reset logic Block Lock Control 8Kb 4Kb 4Kb RESET (X4285)

X4283/85 – Preliminary Information Characteristics subject to change without notice. 2 of 22REV 1.17 11/27/00 www.xicor.com standard Vtrip thresholds are available, however, Xicor’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the thresh- old for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Xicor’s Block Lock protection. The array is internally organized as 64 bytes per page. The device features an 2-wire interface and software proto- col allowing operation on an 2-wire bus. PIN CONFIGURATION VSS VCC SDA SCL3 8S0 WP RST/RST VCC SCL RST/RST VSS3 8WP SDA 8-Pin JEDEC SOIC 8-Pin TSSOP PIN DESCRIPTION Pin (SOIC) Pin (TSSOP) Name Function 13 S Device Select Input 24 S Device Select Input 3 5 RESET / RESET Reset Output RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever V CC falls below the minimum V CC sense level. It will remain active until V CC rises above the minimum V CC sense level for 250ms. RESET/ RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET /RESET goes active on power up and remains active for 250ms after the power supply stabilizes. 46 V SS Ground 5 7 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. 6 8 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

71 W P

Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control register. 82 V CC Supply Voltage

Characteristics subject to change without notice. active. This signal provides several benefits. to operate with insufficient voltage. bilization of the oscillator. tion prior to initialization of the circuit. reducing the likelihood of data corruption on power up. RESET allowing the system to begin operation. signal remains active until the voltage drops below 1V. allowed and no nonvolatile write operation can start. goes active are allowed to finish. memory Block Lock and the Write Protect (WP) pin. These are discussed elsewhere in this document. of a nonvolatile control signal. Figure 1. Set V

Characteristics subject to change without notice. Figure 4. V nonvolatile and do not change when power is removed. data byte is allowed for each register write operation. the Control Register" below.

X4283/85 – Preliminary Information Characteristics subject to change without notice. 6 of 22REV 1.17 11/27/00 www.xicor.com The state of the Control Register can be read at any time by performing a random read at address FFFFh. Only one byte is read by each register read operation. The X4283/85 resets itself after the first byte is read. The master should supply a stop condition to be con- sistent with the bus protocol, but a stop is not required to end this operation. RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to “1” prior to a write to the Control Register. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a vola- tile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. BP2, BP1, BP0: Block Protect Bits (Nonvolatile) The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block pro- tect bits will prevent write operations to one of eight segments of the array. WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below. Write Protect Enable These devices have an advanced Block Lock scheme that protects one of eight blocks of the array when enabled. It provides hardware write protection through the use of a WP pin and a nonvolatile Write Protect Enable (WPEN) bit. Four of the 8 protected blocks match the original Block Lock segments and this pro- tection scheme is fully compatible with the current devices using 2 bits of block lock control (assuming the BP2 bit is set to 0). The Write Protect (WP) pin and the Write Protect Enable (WPEN) bit in the Control Register control the programmable Hardware Write Protect feature. Hard- ware Write Protection is enabled when the WP pin and the WPEN bit are HIGH and disabled when either the WP pin or the WPEN bit is LOW. When the chip is Hard- ware Write Protected, nonvolatile writes as well as to the block protected sections in the memory array cannot be written. Only the sections of the memory array that are not block protected can be written. Note that since the WPEN bit is write protected, it cannot be changed back to a LOW state; so write protection is enabled as long as the WP pin is held HIGH. 76 5 4 321 0 WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2BP2 BP1 BP0 Protected Addresses (Size) Array Lock 0 0 0 None (factory setting) None 0 0 1 3000 h - 3FFFh (4K bytes) Upper 1/4 (Q4) 0 1 0 2000 h - 3FFFh (8K bytes) Upper 1/2 (Q3,Q4) 0 1 1 0000 h - 3FFFh (16K bytes) Full Array (All) 100 0 0 0 h - 03Fh (64 bytes) First Page (P1) 101 0 0 0 h - 07Fh (128 bytes) First 2 pgs (P2) 110 0 0 0 h - 0FFh (256 bytes) First 4 pgs (P4) 111 0 0 0 h - 1FFh (512 bytes) First 8 pgs (P8) WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds (factory setting) 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled

Figure 10. Writing 12 bytes to a 64-byte page starting at location 60.

4 Bytes

8 Bytes

Figure 11. Acknowledge Polling Sequence

Figure 15. X4283/85 Addressing – The device is in the low power standby state. – SDA pin is the input mode. /RESET Signal is active for tPURST. – The WEL bit must be set to allow write operations. HIGH will prevent all writes to the Control Register. communication is terminated. array from write operations.

X4283/85 – Preliminary Information Characteristics subject to change without notice. 14 of 22REV 1.17 11/27/00 www.xicor.com ABSOLUTE MAXIMUM RATINGS Voltage on any pin with respect to V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C Option Supply Voltage Limits –2.7 and –2.7A 2.7V to 5.5V Blank and –4.5A 4.5V to 5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) V IL Min. and VIH Max. are for reference only and are not tested. Symbol Parameter VCC = 2.7 to 5.5V Unit Test ConditionsMin Max ICC1 (1) Active Supply Current Read 1.0 mA V IL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 400kHz, SDA = CommandsICC2 (1) Active Supply Current Write 3.0 mA ISB1 (2) Standby Current DC (WDT off) 1 µA V SDA = VSCL = VSB Others = GND or VSB ISB2 (2) Standby Current DC (WDT on) 20 µA V SDA = VSCL = VSB Others = GND or VSB ILI Input Leakage Current 10 µA V IN = GND to VCC ILO Output Leakage Current 10 µA V SDA = GND to VCC Device is in Standby(2) VIL (3) Input LOW Voltage -0.5 V CC x 0.3 V VIH (3) Input nonvolatile V CC x 0.7 V CC +0.5 V VHYS Schmitt Trigger Input Hysteresis Fixed input level VCC related level 0.2 .05 x VCC V V V OL Output LOW Voltage 0.4 V I OL = 3.0mA (2.7–5.5V)

X4283/85 – Preliminary Information Characteristics subject to change without notice. 15 of 22REV 1.17 11/27/00 www.xicor.com CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V) Note: (4) This parameter is periodically sampled and not 100% tested. Symbol Parameter Max. Unit Test Conditions COUT (4) Output Capacitance (SDA, RST/RST) 8 pF V OUT = 0V CIN (4) Input Capacitance (SCL, WP) 6 pF V IN = 0V EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS SDA or RESET 1533Ω 100pF For VOL = 0.4V and IOL = 3 mA Input pulse levels 0.1 V CC to 0.9 VCC Input rise and fall times 10ns Input and output timing levels 0.5V CC Output load Standard output load A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Notes: (5) Typical values are for TA = 25°C and VCC = 5.0V (6) Cb = total capacitance of one bus line in pF . Symbol Parameter Min. Max. Unit fSCL SCL Clock Frequency 0 400 kHz tIN Pulse width Suppression Time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb (6) 300 ns tF SDA and SCL Fall Time 20 +.1Cb (6) 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0 µs Cb Capacitive load for each bus line 400 pF

X4283/85 – Preliminary Information Characteristics subject to change without notice. 16 of 22REV 1.17 11/27/00 www.xicor.com TIMING DIAGRAMS Bus Timing WP Pin Timing Write Cycle Timing Nonvolatile Write Cycle Timing Note: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Symbol Parameter Min. Typ. (1) Max. Unit tWC (1) Write Cycle Time 5 10 ms tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtAA tR tHD:WP SCL SDA IN WP tSU:WP Clk 1 Clk 9 Slave Address Byte START SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition

X4283/85 – Preliminary Information Characteristics subject to change without notice. 17 of 22REV 1.17 11/27/00 www.xicor.com Power-Up and Power-Down Timing RESET Output Timing Note: (8) This parameter is periodically sampled and not 100% tested. SDA vs. RESET Timing Symbol Parameter Min. Typ. Max. Unit VTRIP Reset Trip Point Voltage, X4283/85-4.5A Reset Trip Point Voltage, X4283/85 Reset Trip Point Voltage, X4283/85-2.7A Reset Trip Point Voltage, X4283/85-2.7 4.5 4.25 2.85 2.55 4.62 4.38 2.92 2.62 4.75 4.5 3.0 2.7 V t PURST Power-up Reset Time out 100 250 400 ms tRPD (8) VCC Detect to Reset/Output 500 ns tF (8) VCC Fall Time 100 µs tR (8) VCC Rise Time 100 µs VRVALID Reset Valid VCC 1V VCC tPURST tR tF tRPD

0 Volts

(X4285) (X4283) tPURST VRVALID tRSP<tWDO tRST RESET SDA tRSP Note: All inputs are ignored during the active reset period (tRST). tRST SCL tRSP>tWDO tRSP>tWDO

X4283/85 – Preliminary Information Characteristics subject to change without notice. 18 of 22REV 1.17 11/27/00 www.xicor.com RESET Output Timing VTRIP Programming Timing Diagram (WEL = 1) VTRIP Programming Parameters Symbol Parameter Min. Typ. Max. Unit tWDO Watchdog Time Out Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 (factory setting) 100 450 250 650 1.5 400 850 ms ms sec t RST Reset Time Out 100 250 400 ms Parameter Description Min. Max. Unit tVPS VTRIP Program Enable Voltage Setup time 1 µs tVPH VTRIP Program Enable Voltage Hold time 1 µs tTSU VTRIP Setup time 1 µs tTHD VTRIP Hold (stable) time 10 ms tWC VTRIP Write Cycle Time 10 ms tVPO VTRIP Program Enable Voltage Off time (Between successive adjustments) 0 µs tRP VTRIP Program Recovery Period (Between successive adjustments) 10 ms VP Programming Voltage 15 18 V VTRAN VTRIP Programmed Voltage Range 2.55 4.75 V Vta1 Initial VTRIP Program Voltage accuracy (VCC applied–VTRIP) (Programmed at 25°C.) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage accuracy [(VCC applied–Vta1)—V TRIP. Programmed at 25°C.) -25 +25 mV Vtr VTRIP Program Voltage repeatability (Successive program operations. Programmed at 25°C.) -25 +25 mV Vtv VTRIP Program variation after programming (0–75°C). (Programmed at 25°C.) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested. VCC (VTRIP) WP tTSU tTHD tVPHtVPS VP VTRIP tVPO SCL SDA A0h 01h or 03h tRP 00h 00h

X4283/85 – Preliminary Information Characteristics subject to change without notice. 19 of 22REV 1.17 11/27/00 www.xicor.com PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"Typical 0.050" Typical 0.030" Typical

8 PlacesFOOTPRINT

X4283/85 – Preliminary Information Characteristics subject to change without notice. 20 of 22REV 1.17 11/27/00 www.xicor.com PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° – 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) (4.16) (7.72) (1.78) (0.42) (0.65) All Measurements Are Typical

X4283/85 – Preliminary Information Characteristics subject to change without notice. 21 of 22REV 1.17 11/27/00 www.xicor.com

Ordering Information

(Active LOW) Part Number RESET (Active HIGH) -40°C–85°C X4283S8I–4.5A X4285S8I–4.5A 8L TSSOP 0°C–70°C X4283V8–4.5A X4285V8–4.5A -40°C–85°C X4283V8I–4.5A X4285V8I–4.5A 4.5-5.5V 4.25-4.5 8L SOIC 0°C–70°C X4283S8 X4285S8 -40°C–85°C X4283S8I X4285S8I 8L TSSOP 0°C–70°C X4283V8 X4285V8 -40°C–85°C X4283V8I X4285V8I -40°C–85°C X4283S8I–2.7A X4285S8I–2.7A 8LTSSOP 0°C–70°C X4283V8–2.7A X4285V8–2.7A -40°C–85°C X4283V8I–2.7A X4285V8I–2.7A -40°C–85°C X4283S8I–2.7 X4285S8I–2.7 8L TSSOP 0°C–70°C X4283V8–2.7 X4285V8–2.7 -40°C–85°C X4283V8I–2.7 X4285V8I–2.7 8-Lead TSSOP EYWW XXXXX 8-Lead SOIC X4283/85 X XX Blank = 8-Lead SOIC ADB/ADK = –4.5A (0 to +70°C) ADD/ADM = No Suffix (0 to +70°C) ADF/ADO = –2.7A (0 to +70°C) ADH/ADQ = –2.7 (0 to +70°C) Blank = No Suffix (0 to +70°C) I = No Suffix (-40 to +85°C) AN = –2.7A (0 to +70°C) AL = –4.5A (0 to +70°C)

X4283/85 – Preliminary Information Characteristics subject to change without notice. 22 of 22 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale onl y. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Xicor, Inc. 2000 Patents Pending REV 1.17 11/27/00 www.xicor.com