X25401 XICOR | Alldatasheet

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SPI Serial AUTOSTORE™ NOVRAM © Xicor, Inc. 1992, 1995, 1996 Patents Pending Characteristics subject to change without notice 2051-1.5 8/1/97 T0/C0/D2 SH

DESCRIPTION

The Xicor X25401 is a serial 256 bit NOVRAM featuring a static RAM configured 16 x 16, overlaid bit-by-bit with a nonvolatile E 2PROM array. The X25401 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is con- trolled through a chip select (CS) input, allowing any number of devices to share the same bus. The Xicor NOVRAM design allows data to be transferred between the two memory arrays by means of software commands or external hardware inputs. A store opera- tion (RAM data to E 2PROM) is completed in 5ms or less and a recall operation (E2PROM data to RAM) is com- pleted in 2µs or less. The X25401 also includes the AUTOSTORE feature, a user selectable feature that automatically performs a store operation when V CC falls below a preset threshold. Xicor NOVRAMs are designed for unlimited write opera- tions to RAM, either from the host or recalls from E2PROM and a minimum 1,000,000 store operations. Inherent data retention is specified to be greater than 100 years.

FEATURES

  • 1MHz Clock Rate
  • AUTOSTORE™ NOVRAM —Automatically Performs a Store Operation Upon Loss of V CC
  • Single 5 Volt Supply
  • Ideal for use with Single Chip Microcomputers —Minimum I/O Interface —SPI Mode (0,0 & 1,1) Serial Port Compatible —Easily Interfaced to Microcontroller Ports
  • Software and Hardware Control of Nonvolatile Functions
  • Auto Recall on Power-Up
  • TTL and CMOS Compatible
  • Low Power Dissipation —Active Current: 10mA —Standby Current: 50 µA
  • 8-Lead PDIP and 8-Lead SOIC Packages
  • High Reliability —Store Cycles: 1,000,000 —Data Retention: 100 Years

256 Bit X25401 16 x 16 Bit

AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc. COPS is a trademark of National Semiconductor Corp. FUNCTIONAL DIAGRAM NONVOLATILE E2PROM CONTROL LOGIC COLUMN DECODE ROW DECODE 4-BIT COUNTER INSTRUCTION DECODE INSTRUCTION REGISTER CS (1) SI (3) SCK (2) SO (4) RECALL (6) AS (7) STATIC RAM 256-BIT RECALL STORE

2051 FHD F01

PIN CONFIGURATIONPIN DESCRIPTIONS Chip Select (CS) The Chip Select input must be LOW to enable all read/ write operations. CS must remain LOW following a Read or Write command until the data transfer is com- plete. CS HIGH places the X25401 in the low power standby mode and resets the instruction register. There- fore, CS must be brought HIGH after the completion of an operation in order to reset the instruction register in preparation for the next command. Serial Clock (SCK) The Serial Clock input is used to clock all data into and out of the device. Serial Data In (SI) SI is the serial data input. Serial Data Out (SO) SO is the serial data output. It is in the high impedance state except during data output cycles in response to a READ instruction. AUTOSTORE Output ( AS) AS is an open drain output which, when asserted indi- cates V CC has fallen below the AUTOSTORE thresh- old (VASTH ). AS may be wire-ORed with multiple open drain outputs and used as an interrupt input to a micro- controller or as an input to a low power reset circuit. RECALL RECALL LOW will initiate an internal transfer of data from E 2PROM to the RAM array. PIN NAMES Symbol Description CS Chip Enable SCK Serial Clock SI Serial Data In SO Serial Data Out RECALL Recall Input AS AUTOSTORE Output VCC +5V VSS Ground

2051 PGM T01

2051 FHD F02

entire data transfer operation. the previous recall latch is not set by this operation. Internally the X25401 contains a “write enable” latch. write enable latch is automatically reset on power-up.

  • STO instruction issued.
  • The internal “write enable” latch must be set (WREN instruction issued).
  • The “previous recall” latch must be set (either a software or hardware recall operation). Once the store cycle is initiated, all other device func- tions are inhibited. Upon completion of the store cycle, the write enable latch is reset. Refer to Figure 4 for a state diagram description of enabling/disabling condi- tions for store operations.

TABLE 1. INSTRUCTION SET

2051 PGM T11

The WRITE instruction contains the 4-bit address of the word to be written. The write instruction is immedi- ately followed by the 16-bit word to be written. CS must remain LOW during the entire operation. CS must go HIGH before the next rising edge of SCK. If CS is brought HIGH prematurely (after the instruction but before 16 bits of data are transferred), the instruction register will be reset and the data that was shifted-in will be written to RAM. If CS is kept LOW for more than 24 SCK clock cycles (8-bit instruction plus 16-bit data), the data already shifted-in will be overwritten. READ The READ instruction contains the 4-bit address of the word to be accessed. Unlike the other six instructions, I 0 of the instruction word is a “don’t care”. This provides two advantages. In a design that ties both SI and SO together, the absence of an eighth bit in the instruction allows the host time to convert an I/O line from an output to an input. Secondly, it allows for valid data output during the ninth SCK clock cycle. All data bits are clocked by the falling edge of SCK (refer to Read Cycle Diagram). LOW POWER MODE When CS is HIGH, non-critical internal devices are powered-down, placing the device in the standby power mode, thereby minimizing power consumption. AUTOSTORE Feature The AUTOSTORE instruction (ENAS) sets the “AUTOSTORE enable” latch, allowing the X25401 to automatically perform a store operation when V CC falls below the AUTOSTORE threshold (VASTH ). WRITE PROTECTION The X25401 provides two software write protection mechanisms to prevent inadvertent stores of unknown data. Power-Up Condition Upon power-up the “write enable” and “AUTOSTORE enable” latches are in the reset state, disabling any store operation. Unknown Data Store The “previous recall” latch must be set after power-up. It may be set only by performing a software or hard- ware recall operation, which assures that data in all RAM locations is valid. SYSTEM CONSIDERATIONS Power-Up Recall The X25401 performs a power-up recall that transfers the E 2PROM contents to the RAM array. Although the data may be read from the RAM array, this recall does not set the “previous recall” latch. During this power-up recall operation, all commands are ignored. Therefore, the host should delay any operations with the X25401 a minimum of t PUR after VCC is stable.

Figure 4. X25401 State Diagram

ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Lead Temperature *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Military –55 °C +125 °C 2051 PGM T02.1 Supply Voltage Limits X25401 5V ±10% 2051 PGM T03.2 Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. ENDURANCE AND DATA RETENTION Parameter Min. Units Endurance 100,000 Data Changes Per Bit Store Cycles 1,000,000 Store Cycles Data Retention 100 Years

2051 PGM T05

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions lCC1 VCC Supply Current 10 mA SCK = 0.4V/2.4V Levels @ 1MHz, (TTL Inputs) SO = Open, All Other Inputs = V IH ICC2 VCC Supply Current 2 mA All Inputs = V IH, CS = VIL (During AUTOSTORE) SO = Open, V CC = 4.3V ISB1 VCC Standby Current 1 mA SO = Open, CS = VIL, (TTL Inputs) All Other Inputs = V IH ISB2 VCC Standby Current 50 µA SO = Open, CS = VSS (CMOS Inputs) All Other Inputs = V CC – 0.3V ILI Input Load Current 10 µAV IN = VSS to VCC ILO Output Leakage Current 10 µAV OUT = VSS to VCC VlL(1) Input LOW Voltage –1 0.8 V VIH(1) Input HIGH Voltage 2 V CC + 1 V VOL Output LOW Voltage 0.4 V I OL = 4.2mA VOH Output HIGH Voltage 2.4 V I OH = –2mA VOL(AS) Output LOW Voltage (AS) 0.4 V I OL (AS) = 1mA 2051 PGM T04.3 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol Parameter Max. Units Test Conditions C OUT (2) Output Capacitance 8 pF V OUT = 0V C IN(2) Input Capacitance 6 pF V IN = 0V 2051 PGM T06.2

A.C. CONDITIONS OF TEST Input Pulse Levels 0V to 3V Input Rise and Fall Times 10ns Input and Output Timing Levels 1.5V 2051 PGM T07.1 EQUIVALENT A.C. LOAD CIRCUIT A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) POWER-UP TIMING Symbol Parameter Max. Units tPUR (4) Power-up to Read Operation 200 µs tPUW (4) Power-up to Write or Store Operation 5 ms

2051 PGM T09

Notes: (3) SCK rise and fall times must be less than 50ns. (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. Read and Write Cycle Limits Symbol Parameter Min. Max. Units FSK (3) SCK Frequency 1 MHz tSCKH SCK Positive Pulse Width 400 ns tSCKL SCK Negative Pulse Width 400 ns tDS Data Setup Time 400 ns tDH Data Hold Time 80 ns tPD1 SCK to Data Bit 0 Valid 375 ns tPD SCK to Data Valid 375 ns tZ Chip Select to Output High Z 1 µs tCSS Chip Select Setup 800 ns tCSH Chip Select Hold 350 ns tCDS Chip Deselect 800 ns 2051 PGM T08.1

2051 FHD F03

919Ω 497Ω OUTPUT 100pF

2051 FHD F04.1 SCK X12n CS SI SCK CYCLE # tCSS tSCKH 1/FSCK tSCKL tCSH tCDS tDHtDS 2051 FHD F05.1 SCK 6789 1 0 n D0 D1 Dn HIGH Z HIGH Z CS SI SO DON’T CARE SK CYCLE # 12 I1 tPD1 tPD tZ

Software Write Enable Recall Latch Operation RECALL Instruction Latch State State Hardware Recall 0 NOP (5) XX Software Recall 1 RCL X X Software Store 1 STO SET SET

2051 PGM T10

Symbol Parameter Min. Max. Units tRCC Recall Cycle Time 2 µs tRCP Recall Pulse Width(6) 500 ns tRCZ Recall to Output in High Z 500 ns SOFTWARE STORE CYCLE LIMITS Symbol Parameter Min. Typ. (7) Max. Units tST Store Time After Clock 8 of STO Command 2 5 ms 2051 PGM T12.1 Notes: (5) NOP designates when the X25401 is not currently executing an instruction. (6) Recall rise time must be <10µs. (7) Typical values are for TA = 25°C and nominal supply voltage.

2051 FHD F06

Symbol Parameter Min. Max. Units VASTO AUTOSTORE Cycle Time 5 ms VASTH AUTOSTORE Threshold Voltage 4.0 4.3 V VASEND AUTOSTORE Cycle End Voltage 3.5 V

2051 PGM T13

AUTOSTORE Cycle Timing Diagrams SYMBOL TABLE

2051 FHD F08

VOLTS (V) TIME (ms) VASTH VASEND AUTOSTORE CYCLE IN PROGRESS tASTO STORE TIME WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

3926 FHD F01

NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.020 (0.51) TYP. 0.010 (0.25) 15° 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62)

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 3926 FHD F22.1 8-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 0.250" 0.050" TYPICAL 0.050" TYPICAL 0.030" TYPICAL

8 PLACESFOOTPRINT

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,883,976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness.

ORDERING INFORMATION

Blank = 5V ±10% Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC