X25256V20G

X25256 ICMIC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 17

Technical content

™ and Block Lock ™ Protection is a trademark of Xicor, Inc. Characteristics subject to change without notice. 1 of 17 www.icmic.com Preliminary Information 256K X25256 32K x 8 Bit 5MHz SPI Serial E 2 PROM with Block Lock ™ Protection

FEATURES

• 5MHz Clock Rate
• Low Power CMOS — <1µA standby current —<5mA active current
• 2.5V To 5.5V Power Supply
• SPI Modes (0,0 & 1,1)
• 32K X 8 Bits —64 byte page mode
• Block Lock ™ Protection —Protect first page, first 2 pages, first 4 pages, first 8 pages, 1/4, 1/2 or all of E 2 PROM array
• Programmable Hardware Write Protection — In -circuit programmable ROM mode
• Built-In Inadvertent Write Protection — Power -up/down protection circuitry —Write enable latch — Write protect pin
• Self-Timed Write Cycle — 5ms write cycle time (typical)
• High Reliability — Endurance: 100,000 cycles —Data Retention: 100 Years — ESD protection: 2000V on a ll pins
• Packages — 8- lead XBGA — 8-lead SOIC (JEDEC, EIAJ) —20-lead TSSOP

DESCRIPTION

The X25256 is a CMOS 256K-bit serial E 2 PROM, inter- nally organized as 32K x 8. The X25256 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25256 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25256 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25256 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering first page, first 2 pages, 4 pages, 8 pages, 0, 1/4, 1/2 or all of the memory. FUNCTIONAL DIAGRAM Command Decode And Control Logic Write Control And Timing Logic Write Protect Logic X-Decode Protect 32K Byte Array

128 X 512

248 X 512

4 X 512

2 X 512

1 X 512

256 X 512

This X25256 device has been acquired by IC MICROSYSTEMS from Xicor; Inc.

X25256 – Preliminary Information Characteristics subject to change without notice. 2 of 17 www.icmic.com The X25256 utilizes Xicor’s proprietary Direct Write ™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION PIN NAMES PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25256 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25256 will be in the standby power mode. CS LOW enables the X25256, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25256 status register are dis- abled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25256 status reg- ister. If the internal write cycle has already been initi- ated, WP going LOW will have no affect on a write. The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to ins tall the X25256 in a system with WP pin grounded and still be able to write to the status register. The WP pin func- tions will be enabled when the WPEN bit is set “1”. Symbol Description CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input V SS Ground V CC Supply Voltage HOLD Hold Input NC No Connect 20 -Lead TSSOP NC X25256 NC NC SO NC NC CS NC NC VCC HOLD SCK WP 8 VSS NC NC NC SI NC NC 8-Lead SOIC VCC HOLD SCK CS X25256 VSS SI 5 SO WP SI WP SCK VCC VSS CS HOLD 8 8-Lead XBGA

Table 1. Instruction Set Notes: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. of many popular microcontroller families. WP inputs must be HIGH during the entire operation. point when HOLD was first asserted. WPEN, BL0 and BL1 are set by the WRSR instruction.

Figure 1. Block Lock Configurations X25256 as a nonvolatile enable bit for the WP pin. trol the Programmable Hardware Write Protect feature. that are not block-protected can be written. tion is enabled as long as the WP pin is held LOW. be ROM, and then programming the WPEN bit HIGH. each combination of WPEN and WP.

X25256 – Preliminary Information Characteristics subject to change without notice. 5 of 17 www.icmic.com can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($7FFF) the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the read E 2 PROM array operation sequence illustrated in Figure 2. To read the status register the CS line is first pulled LOW to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Figure 3 illustrates the read status register sequence. WP WPEN Memory Array Not Block Protected Memory Array Block Protected Block Lock Bits WPEN Bit Protection HIGH X Writable Blocked Writable Writable Software LOW 0 Writable Blocked Writable Writable Software LOW 1 Writable Blocked Writes Blocked Writes Blocked Hardware Write Sequence Prior to any attempt to write data into the X25256, the “write enable” latch must first be set by i ssuing the WREN instruction (See Figure 4). CS is first taken LOW, then the WREN instruction is clocked into the X25256. After all eight bits of the instruction are trans- mitted, CS must then be taken HIGH. If the user con- tinues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the E 2 PROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. This is minimally a thirty- two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 64 bytes of data to the X25256. The only restriction is the 64 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. For the write operation (byte or page write) to be com- pleted, CS can only be brought HIGH after bit 0 of data byte N is clocked in. If it is brought HIGH at any other time the write operation will not be completed. Refer to Figures 5 and 6 below for a detailed illustration of the write sequences and time frames in which CS going HIGH are valid. To write to the status register, the WRSR instruction is followed by the data to be written. Data bits 0, 1, 5, and 6 are “don’t care”. Figure 7 illustrates this sequence. While the write is in progress following a status register or E 2 PROM write sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be HIGH. Hold Operation The HOLD input should be HIGH (at V IH ) under normal operation. If a data transfer is to be interrupted HOLD can be pulled LOW to suspend the transfer until it can be resumed. The only restriction is the SCK input must be LOW when HOLD is first pulled LOW and SCK must also be LOW when HOLD is released. The HOLD input may be tied HIGH either directly to V CC or tied to V CC through a resistor. Operational Notes The X25256 powers-up in the following state: – The device is in the low power standby state. – A HIGH to LOW transition on CS is required to ent er an active state and receive an instruction. – SO pin is high impedance. – The “write enable” latch is reset. Data Protection The following circuitry has been included to prevent inadvertent writes: – The “write enable” latch is reset upon power-up. – A WREN instruction must be issued to set the “wri te enable” latch. – CS must come HIGH at the proper clock count in order to start a write cycle.

Figure 7. Write Status Register Operation Sequence

X25256 – Preliminary Information Characteristics subject to change without notice. 9 of 17 www.icmic.com ABSOLUTE MAXIMUM RATINGS Voltage on any pin with D.C. output current RECOMMENDED OPERATING CONDITIONS COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; and the functional operation of the device (at these or any other conditions above those indicated in the operational sections of this speci- fication) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature Min. Max. Commercial 0 ° C +70 ° C Industrial –40 ° C +85 ° C Supply Voltage Limit X25256-2.5 2.5V to 5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) POWER -UP TIMING CAPACITANCE TA = +25° C, f = 1MHz, V CC = 5V Notes: (1)V IL min. and V IH max. are for reference only and are not tested. (2)This parameter is periodically sampled and not 100% tested. (3)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiat ed. These parameters are periodically sampled and not 100% tested. Symbol Parameter Limits Unit Test Conditions Min. Max. ICC V CC Supply Current (Active) 5 mA SCK = V CC x 0.1/V CC x 0.9 @ 5MHz, SO = Open, CS = VSS ISB V CC Supply Current (Standby) 1 µA CS = V CC , V IN = VSS or V CC – 0.3V, TA = 25° C ILI Input Leakage Current 10 µA VIN = VSS to V CC ILO Output Leakage Current 10 µA VOUT = VSS to V CC V IL (1) Input LOW Voltage –1 VCC x 0.3 V V IH (1) Input HIGH Voltage VCC x 0.7 V CC + 0.5 V VOL1 Output LOW Voltage 0.4 V IOL = 3mA, V CC = 5V VOH1 Output HIGH Voltage VCC –0.8 V IOH = –1.0mA, V CC = 5V VOL2 Output LOW Voltage 0.4 V IOL = 1.0mA, V CC = 3V VOH2 Output HIGH Voltage VCC –0.4 V IOH = –0.4mA, V CC = 3V Symbol Parameter Min. Max. Unit T PUR (3) Power-up to Read Operation 1 ms T PUW (3) Power-up to Write Operation 5 ms Symbol Parameter Max. Unit Test Conditions C I/O (3) Output Capacitance (SO) 8 pF VI/O = 0V C IN (3) Input Capacitance (SCK, SI, CS , WP , HOLD ) 6 pF VIN = 0V

X25256 – Preliminary Information Characteristics subject to change without notice. 10 of 17 www.icmic.com EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST SO 2.06K Ο 3.03K Ο 30pF Input pulse levels VCC x 0.1 to V CC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC X 0.5 A.C. OPERATING CHARACTERISTICS Data Input Timing Data Output Timing Notes: (4)This parameter is periodically sampled and not 100% tested. (5)t WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle Symbol Parameter VCC = 2.5V–5.5V Unit Min. Max. fSCK Clock Frequency 0 5.0 MHz tCYC Cycle Time 200 ns tLEAD CS Lead Time 100 ns tLAG CS Lag Time 100 ns tWH Clock HIGH Time 80 ns tWL Clock LOW Time 80 ns tSU Data Setup Time 20 ns tH Data Hold Time 20 ns t RI (4) Data In Rise Time 2 µs t FI (4) Data In Fall Time 2 µs tHD HOLD Setup Time 40 ns tCD HOLD Hold Time 40 ns tCS CS Deselect Time 100 ns t WC (5) Write Cycle Time 10 ms Symbol Parameter VCC = 2.5V–5.5V Unit Min. Max. fSCK Clock Frequency 0 5.0 MHz tDIS Output Disable Time 100 ns tV Output Valid from Clock LOW 80 ns tHO Output Hold Time 0 ns t RO (4) Output Rise Time 50 ns t FO (4) Output Fall Time 50 ns t LZ (4) HOLD HIGH to Output in Low Z 50 ns t HZ (4) HOLD LOW to Output in High Z 50 ns

X25256 – Preliminary Information Characteristics subject to change without notice. 11 of 17 www.icmic.com Serial Output Timing Serial Input Timing SCK CS SO SI MSB Out MSB–1 Out LSB Out ADDR LSB IN tCYC tV tHO tWL tWH tDIS tLAG SCK CS SI SO MSB IN tSU tRI tLAG tLEAD tH LSB IN tCS tFI High Impedance

X25256 – Preliminary Information Characteristics subject to change without notice. 12 of 17 www.icmic.com Hold Timing SCK CS SI SO tHD tLZ HOLD tHZ tCD tHD tCD

X25256 – Prel iminary Information Characteristics subject to change without notice. 13 of 17 www.icmic.com

PACKAGE INFORMATION

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (.508) 0.012 (.305) .080 (2.03) .070 (1.78) .213 (5.41) .205 (5.21) .330 (8.38) .300 (7.62) .212 (5.38) .203 (5.16) .035 (.889) .020 (.508) .010 (.254) .007 (.178) 0° –8° Ref. Pin 1 ID .050 (1.27) BSC 8-Lead Plastic, 0.200” Wide Small Outline Gullwing Package Typ “A” (EIAJ SOIC) .013 (.330) .004 (.102) NOTES:

X25256 – Preliminary Information Characteristics subject to change without notice. 14 of 17 www.icmic.com PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45 ° 8-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" Typical 0.050" Typical 0.030" Typical

8 Places FOOTPRINT

X25256 – Preliminary Information Characteristics subject to change without notice. 15 of 17 www.icmic.com PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN M ILLIMETERS) 20 -Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

X25256 – Preliminary Information Characteristics subject to change without notice. 16 of 17 www.icmic.com PACKAGING INFORMATION X25256: Bottom View SI WP SCK VCC VSS CS HOLD 8 Complete Part Number Top Mark X25256B -2.5 XAAD X25256BI -2.5 XACR CS VSS WP HOLD VCC SI SCK PIN 1 Dwg Symbol 8-Lead XBGA B Package Min. Max. A 0.445 0.470 A1 0.253 0.293 C 0.360 0.388 D 1.940 2.000 E 3.770 3.830 e 1.0 nominal F 1.2 nominal e D D E C A C NOTE:ALL DIMENSION IN MM ALL DIMENSIONS ARE TYPICAL VALUES E 8-Lead XBGA F 8-Lead XBGA: Top View

X25256 – Preliminary Information LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor’s products are not authorized for use in critical components in life support devices or systems. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in acco rdance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Characteristics subject to change without notice. 17 of 17 www.icmic.com

Ordering Information

2.5 = 2.5V to 5.5V Temperature Range Blank = Commercial = 0° C to +70° C I = Industrial = –40° C to +85° C Package A8 = 8-Lead SOIC (EIAJ) S8 = 8-Lead SOIC (JEDEC) V20 = 20-Lead TSSOP B = 8-Lead XBGA 8-Lead SOIC X5256 X XX Blank = 8-Lead SOIC (JEDEC) J = 2.5 to 5.5V, 0 to +70° C K = 2.5 to 5.5V, -40 to +85° C 8-Lead XBGA Complete Part Number Top Mark X25256B-2.5 XAAK X25256BI-2.5 XAAL A8 = 8-Lead SOIC (EIAJ) 20 -Lead TSSOP X25256 X J = 2.5 to 5.5V, 0 to +70° C K = 2.5 to 5.5V, -40 to +85° C ©Xicor, Inc. 2000 Patents Pending G = RoHS Complaint Lead -Free package Blank = Standard package. Non lead-free X X X -X