X25128SM

X25128 ICMIC | Alldatasheet

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SPI Serial E 2PROM with Block Lock TM Protection 128K 16K x 8 Bit ©Xicor Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice 3091-2.9 5/14/97 T2/C0/D2 SH 1 X25128 This X25128 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. FUNCTIONAL DIAGRAM COMMAND DECODE AND CONTROL LOGIC WRITE CONTROL AND TIMING LOGIC WRITE PROTECT LOGIC X DECODE LOGIC 16K BYTE ARRAY

16 X 256

32 X 256

3091 FM F01

FEATURES

• 2MHz Clock Rate
• SPI Modes (0,0 & 1,1)
• 16K X 8 Bits — 32 Byte Page Mode
• Low Power CMOS —<1 µ A Standby Current —<5mA Active Current
• 2.7V To 5.5V Power Supply
• Block Lock Protection —Protect 1/4, 1/2 or all of E 2PROM Array
• Built-in Inadvertent Write Protection — Power -Up/Power -Down protection circuitry —Write Enable Latch — Write Protect Pin
• Self-Timed Write Cycle — 5ms Write Cycle Time (Typical)
• High Reliability — Endurance: 100,000 cycles —Data Retention: 100 Years — ESD protectio n: 2000V on all pins
• 14-Lead SOIC Package
• 16-Lead SOIC Package
• 8-Lead PDIP Package

DESCRIPTION

The X25128 is a CMOS 131,072-bit serial E 2PROM, internally organized as 16K x 8. The X25128 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25128 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25128 will ignore tran- sitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25128 disabling all write attempts to the status register, thus providing a mech- anism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25128 utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. ICmic IC MICROSYSTEMS TM

Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS ) When CS is high, the X25128 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25128 will be in the standby pow er mode. CS low enables the X25128, placing it in the active pow er mode. It should be noted that after pow er-up, a high to low transition on CS is required prior to the start of any operation. Write Protect (WP ) When WP is low and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25128 status register are disabled, but the part otherwise functions normally. When WP is held high, all functions, including nonvola- tile writes operate normally. WP going low while CS is still low will interrupt a write to the X25128 status register. If the internal write cycle has already been initiated, WP going low will have no effect on a write. The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25128 in a system with WP pin grounded and still be able to write to the status register. The WP pin func- tions will be enabled when the WPEN bit is set “0”. Hold (HOLD ) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought low while SCK is Low. To resume commu- nication, HOLD is brought high, again while SCK is low. If the pause feature is not used, HOLD should be held high at all times. PIN CONFIGURATION PIN NAMES

3091 FM T01

V SS Ground V CC Supply Voltage HOLD Hold Input NC No Connect

3091 FM 02

14 Lead SOIC

.244” .344” NC

8 Lead PDIP

.325” .430” SO WP CS SO WP VCC HOLD SCK SI

16 Lead SOIC

.244” .394” NC NC CS SO WP VCC HOLD SCK SI

WP inputs must be high during the entire operation. The WP input is “Don’t Care” if WPEN is set “0”. point when HOLD was first asserted.

3091 FM T02

in progress. During a write, all other bits are set to “1”. is set, when set to a “0”, the latch is reset.

3091 PGM T03

Table 1. Instruction Set

3091 PGM T04

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

The Wr ite-Protect-Enable (WPEN) is available for the X25128 as a nonvolatile enable bit for the WP pin. 3091 PGM T05.1 The Wr ite Protect (WP ) pin and the nonvolatile Wr ite Protect Enable (WPEN) bit in the Status Register control the programmab le hardware write protect feature. Hardware write protection is enabled when WP pin is low, and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the chip is hardware write protected, nonvolatile writes are disabled to the Status Register, including the Block Protect bits and the WPEN bit itself, as well as the block-protected sections in the memory array. Only the sections of the memor y array that are not block-protected can be written. Note: Since the WPEN bit is write protected, it cannot be changed back to a “0”, as long as the WP pin is held low. Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK. Read Sequence When reading from the E PR OM array, CS is first pulled low to select the device. The 8-bit read instruc- tion is transmitted to the X25128, follow ed by the 16-bit address of which the last 14 are used. After the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($3FFF) the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the read E PR OM array operation sequence illustrated in Figure 1. To read the status register the CS line is first pulled low to select the device follow ed by the 8-bit instruc- tion. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. The read status register sequence is illustrated in Figure 2. Write Sequence Prior to any attempt to write data into the X25128, the “write enable” latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken low, then the WREN instruction is clocked into the X25128. After all eight bits of the instruction are transmitted, CS m ust then be taken high. If the user continues the write operation without taking CS high after issuing the WREN instruction, the write operation will be ignored. To write data to the E PR OM memor y array, the user issues the write instruction, follow ed by the address and then the data to be written. This is minimally a thirty-two clock operation. CS must go low and remain low for the duration of the operation. The host may continue to write up to 32 bytes of data to the X25128. The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. For the write operation (byte or page write) to be completed, CS can only be brought high after bit 0 of data byte N is clocked in. If it is brought high at any other time the write operation will not be completed. Refer to Figures 4 and 5 below for a detailed illustra- tion of the write sequences and time frames in which CS going high are valid. To write to the status register, the WRSR instruction is follow ed by the data to be written. Data bits 0, 1, 4, 5 and 6 must be “0”. This sequence is shown in Figure 6. While the write is in progress, following a status register or E PR OM wr ite sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be high. Hold Operation The HOLD input should be high (at V IH ) under normal operation. If a data transfer is to be interrupted HOLD can be pulled low to suspend the transfer until it can be resumed. The only restriction is the SCK input must WPEN WP WEL Protected Blocks Unprotected Blocks Status Register

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

X High 0 Protected Protected Protected X High 1 Protected Writable Writable

also be low when HOLD is released.

• The device is in the low pow er standby state.
• A high to low transition on CS is required to enter an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset. Data Protection The following circuitry has been included to prevent inadvertent writes:
• The “write enable” latch is reset upon pow er-up.
• A WREN instruction must be issued to set the “write enable” latch.
• CS m ust come high at the proper clock count in order to start a write cycle.

Figure 1. Read E Figure 2. Read Status Register Operation Sequence

3091 FM F03

3091 FM F04

Figure 3. Write Enable Latch Sequence Figure 4. Byte Write Operation Sequence

3091 FM F05

3091 FM F06

Figure 5. Page Write Operation Sequence Figure 6. Write Status Register Operation Sequence

3091 FM F07

3091 FM F08

ABSOLUTE MAXIMUM RATINGS* C to +135 C C to +150 C Voltage on any Pin with Respect to V SS Lead Temperature C D.C. OPERATING CHARACTERISTICS POWER-UP TIMING

3091 FM T09

T A = +25 C, f = 1MHz, V CC = 5V 3091 FM T10.1 Notes: (1) V IL min. and V IH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. (3) t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. Limits Symbol Parameter Min. Max. Units Test Conditions I CC V CC Supply Current (Active) 5 mA SCK = V CC x 0.1/V CC x 0.9 @ 2 MHz, SO = Open, CS = V SS I SB V CC Supply Current (Standby) 1 m A CS = V CC , V IN = V SS or V CC I LI Input Leakage Current 10 mA VIN = VSS to VCC ILO Output Leakage Current 10 mA VOUT = VSS to VCC VlL (1) Input LOW Voltage –1 VCC x 0.3 V VIH (1) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output LOW Voltage 0.4 V VCC = 5V, IOL = 3mA VOH1 Output HIGH Voltage VCC – 0.8 V VCC = 5V, IOH = -1.6mA VOL2 Output LOW Voltage 0.4 V VCC = 3V, IOL = 1.5mA VOH2 Output HIGH Voltage VCC – 0.3 V VCC = 3V, IOH = -0.4mA Symbol Parameter Min. Max. Units tPUR (3) Power-up to Read Operation 1 ms tPUW (3) Power-up to Write Operation 5 ms Symbol Test Max. Units Conditions C OUT (2) Output Capacitance (SO) 8 pF VOUT = 0V C IN (2) Input Capacitance (SCK, SI, CS , WP , HOLD ) 6 pF VIN = 0V RECOMMENDED OPERATING CONDITIONS 3091 FM T06.1 Temperature Min. Max. Commercial 0°C +70°C Industrial –40°C +85°C Military –55°C +125°C 3091 FM T07.2 Supply Voltage Limits X25128 5V –10% X25128-2.7 2.5V to 5.5V *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maxim um rating conditions for extended periods may affect device reliability.

A.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.) Data Input Timing 3091 FM T12.2 Data Output Timing 3091 FM T13.2 Notes:(4) This parameter is periodically sampled and not 100% tested. (5) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Symbol Parameter Min. Max. Units fSCK Clock Frequency 0 2 MHz tCYC Cycle Time 500 ns tLEAD CS Lead Time 250 ns tLAG CS Lag Time 250 ns tWH Clock HIGH Time 200 ns tWL Clock LOW Time 200 ns tSU Data Setup Time 50 ns tH Data Hold Time 50 ns tRI (4) Data In Rise Time 2 ms tFI (4) Data In Fall Time 2 ms tHD HOLD Setup Time 100 ns tCD HOLD Hold Time 100 ns tCS CS Deselect Time 2.0 ms tWC (5) Write Cycle Time 10 ms Symbol Parameter Min. Max. Units fSCK Clock Frequency 0 2 MHz tDIS Output Disable Time 250 ns tV Output Valid from Clock LOW 200 ns tHO Output Hold Time 0 ns tRO (4) Output Rise Time 100 ns tFO (4) Output Fall Time 100 ns tLZ (4) HOLD HIGH to Output in Low Z 100 ns tHZ (4) HOLD LOW to Output in Low Z 100 ns A.C. CONDITIONS OF TEST

3091 FM T11

Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Levels VCC X 0.5 EQUIVALENT A.C. LOAD CIRCUIT OUTPUT 3091 FM F09.1 1.44KW 1.95KW 100pF OUTPUT 1.64KW 4.63KW 100pF

MSB OUT MSB–1 OUT LSB OUT ADDR LSB IN tCYC tV tHO tWL tWH tDIS 3091 FM F10.1 tLAG SCK CS SI SO MSB IN tSU tRI tLAG

3091 FM F11

3091 FM F12.1 tLZ HOLD tCD tHZ tCD tHD Must be steady Will be steady Ma y change from LOW Will change from LOW to HIGH Ma y change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allow ed Changing: State Not Known N/A Center Line is High Impedance W AVEFORM INPUTS OUTPUTS

NO TE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2.PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEA TING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.020 (0.51) TYP .0.010 (0.25) 15° 8-LEAD PLASTIC DU AL IN-LINE PA CKA GE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62)

7040 FM 18

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) PIN 1 PIN 1 INDEX 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 14-LEAD PLASTIC SMALL OUTLINE GULLWING PACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"Typical 0.050"Typical 0.030"Typical

14 PlacesFOO TPRINT

0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45°

16-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) PIN 1 PIN 1 INDEX 0.050 (1.27) 0.386 (9.80) 0.394 (10.01) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" Typical 0.030" Typical

16 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 0.050" Typical

ORDERING INFORMATION

Blank = 5V ±10% 2.7 = 2.7V to 5.5V Temperature Range Blank = Commercial = 0 °C to +70 °C I = Industrial = –40 °C to +85 °C M = Military = –55 °C to +125 °C Package Blank = 5V ±10%, 0 °C to +70 °C F = 2.7V to 5.5V, 0 °C to +70 °C G = 2.7V to 5.5V, –40 °C to +85 °C X25128 XG X LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry emb odied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordanc e with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expecte d to cause the failure of the life support device or system, or to affect its safety or effectiveness. S14 = 14-Lead SOIC S = 16-Lead SOIC P = 8-Lead PDIP G = RoHS compliant lead-free S14 = 14-Lead SOIC S = 16-Lead SOIC P = 8-Lead PDIP G = RoHS Compliant Lead Free package Blank = Standard package. Non lead free